Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.00 99.19 94.49 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1034
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1005 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1423211900 Feb 08 05:51:15 PM UTC 25 Feb 08 05:51:17 PM UTC 25 44692538 ps
T1006 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.722410766 Feb 08 05:51:12 PM UTC 25 Feb 08 05:51:19 PM UTC 25 684319447 ps
T1007 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1562848506 Feb 08 05:51:19 PM UTC 25 Feb 08 05:51:21 PM UTC 25 14294622 ps
T1008 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2310962814 Feb 08 05:51:19 PM UTC 25 Feb 08 05:51:21 PM UTC 25 19854978 ps
T1009 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2064098175 Feb 08 05:50:30 PM UTC 25 Feb 08 05:51:21 PM UTC 25 7386841967 ps
T96 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3899733114 Feb 08 05:50:38 PM UTC 25 Feb 08 05:51:22 PM UTC 25 33633520452 ps
T1010 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.668327961 Feb 08 05:51:16 PM UTC 25 Feb 08 05:51:23 PM UTC 25 360827038 ps
T141 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2304091762 Feb 08 05:51:17 PM UTC 25 Feb 08 05:51:23 PM UTC 25 405735211 ps
T1011 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.771367296 Feb 08 05:51:17 PM UTC 25 Feb 08 05:51:24 PM UTC 25 419732326 ps
T1012 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.895591805 Feb 08 05:49:47 PM UTC 25 Feb 08 05:51:25 PM UTC 25 7148561034 ps
T1013 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3696777065 Feb 08 05:51:22 PM UTC 25 Feb 08 05:51:25 PM UTC 25 39107824 ps
T1014 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4182201323 Feb 08 05:51:23 PM UTC 25 Feb 08 05:51:25 PM UTC 25 28552161 ps
T1015 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3420428491 Feb 08 05:51:23 PM UTC 25 Feb 08 05:51:26 PM UTC 25 144901049 ps
T133 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2681023888 Feb 08 05:51:22 PM UTC 25 Feb 08 05:51:26 PM UTC 25 186158857 ps
T1016 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1625266400 Feb 08 05:51:20 PM UTC 25 Feb 08 05:51:27 PM UTC 25 356958725 ps
T1017 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.480015766 Feb 08 05:51:26 PM UTC 25 Feb 08 05:51:28 PM UTC 25 34895924 ps
T1018 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4415388 Feb 08 05:51:26 PM UTC 25 Feb 08 05:51:28 PM UTC 25 18002628 ps
T1019 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2852411986 Feb 08 05:51:23 PM UTC 25 Feb 08 05:51:29 PM UTC 25 1418066756 ps
T1020 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1119615641 Feb 08 05:51:26 PM UTC 25 Feb 08 05:51:29 PM UTC 25 167203105 ps
T1021 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.248210046 Feb 08 05:51:26 PM UTC 25 Feb 08 05:51:30 PM UTC 25 30737153 ps
T1022 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3446389192 Feb 08 05:51:31 PM UTC 25 Feb 08 05:51:33 PM UTC 25 12147988 ps
T1023 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3565584142 Feb 08 05:51:31 PM UTC 25 Feb 08 05:51:33 PM UTC 25 41586883 ps
T1024 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.700514490 Feb 08 05:51:27 PM UTC 25 Feb 08 05:51:34 PM UTC 25 359152180 ps
T1025 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1205134655 Feb 08 05:51:30 PM UTC 25 Feb 08 05:51:34 PM UTC 25 295638668 ps
T1026 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4163776834 Feb 08 05:50:47 PM UTC 25 Feb 08 05:51:34 PM UTC 25 14272387357 ps
T138 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1887419023 Feb 08 05:51:30 PM UTC 25 Feb 08 05:51:35 PM UTC 25 635596894 ps
T1027 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3023261508 Feb 08 05:51:31 PM UTC 25 Feb 08 05:51:38 PM UTC 25 1389226948 ps
T1028 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3175788529 Feb 08 05:51:08 PM UTC 25 Feb 08 05:51:49 PM UTC 25 7694863411 ps
T1029 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1863185056 Feb 08 05:51:01 PM UTC 25 Feb 08 05:52:02 PM UTC 25 13576275459 ps
T1030 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2740709964 Feb 08 05:51:27 PM UTC 25 Feb 08 05:52:02 PM UTC 25 14227769218 ps
T1031 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2700584102 Feb 08 05:51:17 PM UTC 25 Feb 08 05:52:07 PM UTC 25 8457631372 ps
T1032 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1452049007 Feb 08 05:51:25 PM UTC 25 Feb 08 05:52:08 PM UTC 25 15356849591 ps
T1033 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2497514508 Feb 08 05:51:22 PM UTC 25 Feb 08 05:52:21 PM UTC 25 7416751683 ps
T1034 /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2095396532 Feb 08 05:51:12 PM UTC 25 Feb 08 05:53:00 PM UTC 25 28178395095 ps

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.131444064
Short name T12
Test name
Test status
Simulation time 2477816317 ps
CPU time 101.16 seconds
Started Feb 08 02:49:42 PM UTC 25
Finished Feb 08 02:51:26 PM UTC 25
Peak memory 338644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131444064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.131444064
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.577782588
Short name T5
Test name
Test status
Simulation time 5455460362 ps
CPU time 52.7 seconds
Started Feb 08 02:48:47 PM UTC 25
Finished Feb 08 02:49:41 PM UTC 25
Peak memory 227368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577782588 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.577782588
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.4234288666
Short name T44
Test name
Test status
Simulation time 21337047599 ps
CPU time 402.65 seconds
Started Feb 08 03:00:30 PM UTC 25
Finished Feb 08 03:07:19 PM UTC 25
Peak memory 223220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234288666 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.4234288666
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.1391253482
Short name T27
Test name
Test status
Simulation time 29216651748 ps
CPU time 612.05 seconds
Started Feb 08 02:49:16 PM UTC 25
Finished Feb 08 02:59:36 PM UTC 25
Peak memory 385800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391253482 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1391253482
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3875943523
Short name T58
Test name
Test status
Simulation time 175240101 ps
CPU time 3.85 seconds
Started Feb 08 05:49:00 PM UTC 25
Finished Feb 08 05:49:05 PM UTC 25
Peak memory 221428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875943523 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_intg_err.3875943523
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.235846017
Short name T6
Test name
Test status
Simulation time 1673266143 ps
CPU time 3.13 seconds
Started Feb 08 02:51:17 PM UTC 25
Finished Feb 08 02:51:21 PM UTC 25
Peak memory 248772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235846017 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.235846017
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1998663371
Short name T38
Test name
Test status
Simulation time 18632311371 ps
CPU time 435.64 seconds
Started Feb 08 02:48:46 PM UTC 25
Finished Feb 08 02:56:08 PM UTC 25
Peak memory 212820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998663371 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access_b2b.1998663371
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3807116154
Short name T19
Test name
Test status
Simulation time 65669487517 ps
CPU time 741.02 seconds
Started Feb 08 02:54:42 PM UTC 25
Finished Feb 08 03:07:12 PM UTC 25
Peak memory 369580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807116154 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3807116154
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2647624883
Short name T75
Test name
Test status
Simulation time 26327612683 ps
CPU time 48.48 seconds
Started Feb 08 05:48:38 PM UTC 25
Finished Feb 08 05:49:29 PM UTC 25
Peak memory 221780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647624883 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_e
rr.2647624883
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2225295582
Short name T43
Test name
Test status
Simulation time 11113306948 ps
CPU time 98.87 seconds
Started Feb 08 02:55:50 PM UTC 25
Finished Feb 08 02:57:32 PM UTC 25
Peak memory 222840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225295582 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.2225295582
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.2657751779
Short name T3
Test name
Test status
Simulation time 716601300 ps
CPU time 5.74 seconds
Started Feb 08 02:49:24 PM UTC 25
Finished Feb 08 02:49:31 PM UTC 25
Peak memory 212932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657751779 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.2657751779
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3810260473
Short name T114
Test name
Test status
Simulation time 7279487532 ps
CPU time 60.38 seconds
Started Feb 08 05:11:32 PM UTC 25
Finished Feb 08 05:12:34 PM UTC 25
Peak memory 308032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810260473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3810260473
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1594800708
Short name T140
Test name
Test status
Simulation time 495307688 ps
CPU time 4.12 seconds
Started Feb 08 05:50:40 PM UTC 25
Finished Feb 08 05:50:45 PM UTC 25
Peak memory 221752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594800708 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_intg_err.1594800708
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3423595225
Short name T320
Test name
Test status
Simulation time 168737962209 ps
CPU time 3091.4 seconds
Started Feb 08 03:12:30 PM UTC 25
Finished Feb 08 04:04:35 PM UTC 25
Peak memory 389476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423595225 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.3423595225
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2924235063
Short name T216
Test name
Test status
Simulation time 44073773 ps
CPU time 0.91 seconds
Started Feb 08 03:30:02 PM UTC 25
Finished Feb 08 03:30:04 PM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924235063 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.2924235063
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3541301807
Short name T22
Test name
Test status
Simulation time 46172084667 ps
CPU time 97.35 seconds
Started Feb 08 03:14:37 PM UTC 25
Finished Feb 08 03:16:16 PM UTC 25
Peak memory 223080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541301807 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.3541301807
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2681023888
Short name T133
Test name
Test status
Simulation time 186158857 ps
CPU time 3.04 seconds
Started Feb 08 05:51:22 PM UTC 25
Finished Feb 08 05:51:26 PM UTC 25
Peak memory 221620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681023888 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_intg_err.2681023888
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2708648398
Short name T137
Test name
Test status
Simulation time 325463616 ps
CPU time 3.64 seconds
Started Feb 08 05:50:55 PM UTC 25
Finished Feb 08 05:50:59 PM UTC 25
Peak memory 211428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708648398 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_intg_err.2708648398
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1887419023
Short name T138
Test name
Test status
Simulation time 635596894 ps
CPU time 4.23 seconds
Started Feb 08 05:51:30 PM UTC 25
Finished Feb 08 05:51:35 PM UTC 25
Peak memory 221712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887419023 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_intg_err.1887419023
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.4027976402
Short name T123
Test name
Test status
Simulation time 171606724619 ps
CPU time 3364.09 seconds
Started Feb 08 02:56:46 PM UTC 25
Finished Feb 08 03:53:24 PM UTC 25
Peak memory 393572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027976402 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.4027976402
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.511986542
Short name T69
Test name
Test status
Simulation time 38496377 ps
CPU time 1.18 seconds
Started Feb 08 05:49:06 PM UTC 25
Finished Feb 08 05:49:08 PM UTC 25
Peak memory 210628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511986542 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_aliasing.511986542
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1926564144
Short name T70
Test name
Test status
Simulation time 80111963 ps
CPU time 2.64 seconds
Started Feb 08 05:49:06 PM UTC 25
Finished Feb 08 05:49:10 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926564144 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.1926564144
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1396804040
Short name T63
Test name
Test status
Simulation time 24138533 ps
CPU time 1.1 seconds
Started Feb 08 05:49:00 PM UTC 25
Finished Feb 08 05:49:02 PM UTC 25
Peak memory 210064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396804040 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_reset.1396804040
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3803987788
Short name T948
Test name
Test status
Simulation time 456246305 ps
CPU time 7.63 seconds
Started Feb 08 05:49:11 PM UTC 25
Finished Feb 08 05:49:20 PM UTC 25
Peak memory 221656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3803987788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3803987788
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2278086019
Short name T64
Test name
Test status
Simulation time 35112154 ps
CPU time 0.87 seconds
Started Feb 08 05:49:03 PM UTC 25
Finished Feb 08 05:49:05 PM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278086019 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.2278086019
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.908835872
Short name T98
Test name
Test status
Simulation time 61491068 ps
CPU time 1.12 seconds
Started Feb 08 05:49:09 PM UTC 25
Finished Feb 08 05:49:11 PM UTC 25
Peak memory 210744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908835
872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_same_csr_outstand
ing.908835872
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1339827093
Short name T947
Test name
Test status
Simulation time 84808796 ps
CPU time 6.16 seconds
Started Feb 08 05:48:50 PM UTC 25
Finished Feb 08 05:48:58 PM UTC 25
Peak memory 221992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339827093 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.1339827093
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2760018587
Short name T73
Test name
Test status
Simulation time 19096644 ps
CPU time 0.93 seconds
Started Feb 08 05:49:25 PM UTC 25
Finished Feb 08 05:49:27 PM UTC 25
Peak memory 210800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760018587 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_aliasing.2760018587
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3668971882
Short name T950
Test name
Test status
Simulation time 68361040 ps
CPU time 2.11 seconds
Started Feb 08 05:49:24 PM UTC 25
Finished Feb 08 05:49:28 PM UTC 25
Peak memory 211264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668971882 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.3668971882
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3515718892
Short name T71
Test name
Test status
Simulation time 34012826 ps
CPU time 1.09 seconds
Started Feb 08 05:49:21 PM UTC 25
Finished Feb 08 05:49:24 PM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515718892 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_reset.3515718892
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3145584366
Short name T951
Test name
Test status
Simulation time 359796908 ps
CPU time 5.58 seconds
Started Feb 08 05:49:28 PM UTC 25
Finished Feb 08 05:49:34 PM UTC 25
Peak memory 221588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3145584366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3145584366
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4162278403
Short name T72
Test name
Test status
Simulation time 22670669 ps
CPU time 0.96 seconds
Started Feb 08 05:49:24 PM UTC 25
Finished Feb 08 05:49:27 PM UTC 25
Peak memory 210508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162278403 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.4162278403
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3649140971
Short name T81
Test name
Test status
Simulation time 52770331101 ps
CPU time 54.26 seconds
Started Feb 08 05:49:12 PM UTC 25
Finished Feb 08 05:50:08 PM UTC 25
Peak memory 211336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649140971 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_e
rr.3649140971
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4249414938
Short name T74
Test name
Test status
Simulation time 26588261 ps
CPU time 1.26 seconds
Started Feb 08 05:49:25 PM UTC 25
Finished Feb 08 05:49:27 PM UTC 25
Peak memory 210372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424941
4938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_same_csr_outstan
ding.4249414938
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1181933087
Short name T949
Test name
Test status
Simulation time 273187274 ps
CPU time 4.79 seconds
Started Feb 08 05:49:18 PM UTC 25
Finished Feb 08 05:49:24 PM UTC 25
Peak memory 221756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181933087 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.1181933087
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3004193061
Short name T59
Test name
Test status
Simulation time 203358629 ps
CPU time 2.22 seconds
Started Feb 08 05:49:20 PM UTC 25
Finished Feb 08 05:49:24 PM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004193061 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_intg_err.3004193061
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.59764951
Short name T984
Test name
Test status
Simulation time 373349971 ps
CPU time 5.32 seconds
Started Feb 08 05:50:37 PM UTC 25
Finished Feb 08 05:50:43 PM UTC 25
Peak memory 221508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=59764951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_mem_rw_with_rand_reset.59764951
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4187662777
Short name T979
Test name
Test status
Simulation time 15410905 ps
CPU time 1.09 seconds
Started Feb 08 05:50:33 PM UTC 25
Finished Feb 08 05:50:36 PM UTC 25
Peak memory 210252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187662777 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.4187662777
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2064098175
Short name T1009
Test name
Test status
Simulation time 7386841967 ps
CPU time 49.27 seconds
Started Feb 08 05:50:30 PM UTC 25
Finished Feb 08 05:51:21 PM UTC 25
Peak memory 211476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064098175 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_
err.2064098175
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.344618374
Short name T982
Test name
Test status
Simulation time 15772868 ps
CPU time 1.06 seconds
Started Feb 08 05:50:36 PM UTC 25
Finished Feb 08 05:50:39 PM UTC 25
Peak memory 210368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344618
374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_same_csr_outstan
ding.344618374
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3040727561
Short name T980
Test name
Test status
Simulation time 77987094 ps
CPU time 3.75 seconds
Started Feb 08 05:50:31 PM UTC 25
Finished Feb 08 05:50:36 PM UTC 25
Peak memory 221728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040727561 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.3040727561
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4279034655
Short name T981
Test name
Test status
Simulation time 395491434 ps
CPU time 3.29 seconds
Started Feb 08 05:50:32 PM UTC 25
Finished Feb 08 05:50:37 PM UTC 25
Peak memory 211544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279034655 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_intg_err.4279034655
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2306101128
Short name T989
Test name
Test status
Simulation time 375194303 ps
CPU time 7.43 seconds
Started Feb 08 05:50:46 PM UTC 25
Finished Feb 08 05:50:55 PM UTC 25
Peak memory 221736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2306101128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2306101128
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2150396975
Short name T986
Test name
Test status
Simulation time 15357334 ps
CPU time 1.1 seconds
Started Feb 08 05:50:44 PM UTC 25
Finished Feb 08 05:50:46 PM UTC 25
Peak memory 210252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150396975 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.2150396975
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3899733114
Short name T96
Test name
Test status
Simulation time 33633520452 ps
CPU time 42.78 seconds
Started Feb 08 05:50:38 PM UTC 25
Finished Feb 08 05:51:22 PM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899733114 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_
err.3899733114
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3195721300
Short name T987
Test name
Test status
Simulation time 52411353 ps
CPU time 1.04 seconds
Started Feb 08 05:50:46 PM UTC 25
Finished Feb 08 05:50:48 PM UTC 25
Peak memory 210600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319572
1300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_same_csr_outsta
nding.3195721300
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.223365279
Short name T985
Test name
Test status
Simulation time 92680425 ps
CPU time 4.74 seconds
Started Feb 08 05:50:40 PM UTC 25
Finished Feb 08 05:50:46 PM UTC 25
Peak memory 221732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223365279 -assert nopostpro
c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.223365279
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.910450779
Short name T992
Test name
Test status
Simulation time 374112320 ps
CPU time 4.73 seconds
Started Feb 08 05:51:00 PM UTC 25
Finished Feb 08 05:51:06 PM UTC 25
Peak memory 221680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=910450779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.910450779
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.136575115
Short name T990
Test name
Test status
Simulation time 25351840 ps
CPU time 1.08 seconds
Started Feb 08 05:50:56 PM UTC 25
Finished Feb 08 05:50:58 PM UTC 25
Peak memory 210624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136575115 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.136575115
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4163776834
Short name T1026
Test name
Test status
Simulation time 14272387357 ps
CPU time 45.43 seconds
Started Feb 08 05:50:47 PM UTC 25
Finished Feb 08 05:51:34 PM UTC 25
Peak memory 211340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163776834 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_
err.4163776834
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.592531579
Short name T991
Test name
Test status
Simulation time 18012936 ps
CPU time 1.01 seconds
Started Feb 08 05:50:59 PM UTC 25
Finished Feb 08 05:51:01 PM UTC 25
Peak memory 210548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592531
579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_same_csr_outstan
ding.592531579
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4142826836
Short name T988
Test name
Test status
Simulation time 59856738 ps
CPU time 3.28 seconds
Started Feb 08 05:50:49 PM UTC 25
Finished Feb 08 05:50:54 PM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142826836 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.4142826836
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3059178695
Short name T1003
Test name
Test status
Simulation time 2077850896 ps
CPU time 7.26 seconds
Started Feb 08 05:51:08 PM UTC 25
Finished Feb 08 05:51:16 PM UTC 25
Peak memory 221724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3059178695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.3059178695
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2522114917
Short name T994
Test name
Test status
Simulation time 22287321 ps
CPU time 1 seconds
Started Feb 08 05:51:04 PM UTC 25
Finished Feb 08 05:51:06 PM UTC 25
Peak memory 210252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522114917 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.2522114917
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1863185056
Short name T1029
Test name
Test status
Simulation time 13576275459 ps
CPU time 59.41 seconds
Started Feb 08 05:51:01 PM UTC 25
Finished Feb 08 05:52:02 PM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863185056 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_
err.1863185056
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2721084634
Short name T996
Test name
Test status
Simulation time 19981875 ps
CPU time 0.9 seconds
Started Feb 08 05:51:07 PM UTC 25
Finished Feb 08 05:51:09 PM UTC 25
Peak memory 210636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272108
4634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_same_csr_outsta
nding.2721084634
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3066366662
Short name T995
Test name
Test status
Simulation time 61866903 ps
CPU time 3.28 seconds
Started Feb 08 05:51:02 PM UTC 25
Finished Feb 08 05:51:07 PM UTC 25
Peak memory 221840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066366662 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.3066366662
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.112594984
Short name T993
Test name
Test status
Simulation time 542932441 ps
CPU time 1.96 seconds
Started Feb 08 05:51:03 PM UTC 25
Finished Feb 08 05:51:06 PM UTC 25
Peak memory 210368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112594984 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_intg_err.112594984
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.722410766
Short name T1006
Test name
Test status
Simulation time 684319447 ps
CPU time 6.2 seconds
Started Feb 08 05:51:12 PM UTC 25
Finished Feb 08 05:51:19 PM UTC 25
Peak memory 211260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=722410766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.722410766
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1513941916
Short name T998
Test name
Test status
Simulation time 21863024 ps
CPU time 0.98 seconds
Started Feb 08 05:51:09 PM UTC 25
Finished Feb 08 05:51:11 PM UTC 25
Peak memory 210628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513941916 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.1513941916
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3175788529
Short name T1028
Test name
Test status
Simulation time 7694863411 ps
CPU time 39.59 seconds
Started Feb 08 05:51:08 PM UTC 25
Finished Feb 08 05:51:49 PM UTC 25
Peak memory 211476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175788529 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_
err.3175788529
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1408119047
Short name T999
Test name
Test status
Simulation time 83491279 ps
CPU time 1.18 seconds
Started Feb 08 05:51:10 PM UTC 25
Finished Feb 08 05:51:13 PM UTC 25
Peak memory 210636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140811
9047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_same_csr_outsta
nding.1408119047
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1640121793
Short name T1000
Test name
Test status
Simulation time 31426518 ps
CPU time 5.19 seconds
Started Feb 08 05:51:08 PM UTC 25
Finished Feb 08 05:51:14 PM UTC 25
Peak memory 221732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640121793 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.1640121793
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2168218406
Short name T997
Test name
Test status
Simulation time 84863202 ps
CPU time 1.64 seconds
Started Feb 08 05:51:08 PM UTC 25
Finished Feb 08 05:51:11 PM UTC 25
Peak memory 220840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168218406 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_intg_err.2168218406
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.668327961
Short name T1010
Test name
Test status
Simulation time 360827038 ps
CPU time 5.33 seconds
Started Feb 08 05:51:16 PM UTC 25
Finished Feb 08 05:51:23 PM UTC 25
Peak memory 221572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=668327961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.668327961
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1771996384
Short name T1002
Test name
Test status
Simulation time 13607085 ps
CPU time 0.98 seconds
Started Feb 08 05:51:14 PM UTC 25
Finished Feb 08 05:51:16 PM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771996384 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.1771996384
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2095396532
Short name T1034
Test name
Test status
Simulation time 28178395095 ps
CPU time 106.05 seconds
Started Feb 08 05:51:12 PM UTC 25
Finished Feb 08 05:53:00 PM UTC 25
Peak memory 221724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095396532 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_
err.2095396532
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1423211900
Short name T1005
Test name
Test status
Simulation time 44692538 ps
CPU time 1.05 seconds
Started Feb 08 05:51:15 PM UTC 25
Finished Feb 08 05:51:17 PM UTC 25
Peak memory 210636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142321
1900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_same_csr_outsta
nding.1423211900
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.785044860
Short name T1004
Test name
Test status
Simulation time 97604262 ps
CPU time 3.59 seconds
Started Feb 08 05:51:12 PM UTC 25
Finished Feb 08 05:51:16 PM UTC 25
Peak memory 211612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785044860 -assert nopostpro
c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.785044860
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2598023772
Short name T1001
Test name
Test status
Simulation time 370499403 ps
CPU time 2.66 seconds
Started Feb 08 05:51:12 PM UTC 25
Finished Feb 08 05:51:16 PM UTC 25
Peak memory 221780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598023772 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_intg_err.2598023772
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1625266400
Short name T1016
Test name
Test status
Simulation time 356958725 ps
CPU time 5.72 seconds
Started Feb 08 05:51:20 PM UTC 25
Finished Feb 08 05:51:27 PM UTC 25
Peak memory 211344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1625266400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1625266400
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1562848506
Short name T1007
Test name
Test status
Simulation time 14294622 ps
CPU time 1 seconds
Started Feb 08 05:51:19 PM UTC 25
Finished Feb 08 05:51:21 PM UTC 25
Peak memory 210628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562848506 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.1562848506
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2700584102
Short name T1031
Test name
Test status
Simulation time 8457631372 ps
CPU time 48.22 seconds
Started Feb 08 05:51:17 PM UTC 25
Finished Feb 08 05:52:07 PM UTC 25
Peak memory 211428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700584102 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_
err.2700584102
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2310962814
Short name T1008
Test name
Test status
Simulation time 19854978 ps
CPU time 1.05 seconds
Started Feb 08 05:51:19 PM UTC 25
Finished Feb 08 05:51:21 PM UTC 25
Peak memory 210636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231096
2814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_same_csr_outsta
nding.2310962814
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.771367296
Short name T1011
Test name
Test status
Simulation time 419732326 ps
CPU time 5.15 seconds
Started Feb 08 05:51:17 PM UTC 25
Finished Feb 08 05:51:24 PM UTC 25
Peak memory 221668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771367296 -assert nopostpro
c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.771367296
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2304091762
Short name T141
Test name
Test status
Simulation time 405735211 ps
CPU time 4.47 seconds
Started Feb 08 05:51:17 PM UTC 25
Finished Feb 08 05:51:23 PM UTC 25
Peak memory 221644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304091762 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_intg_err.2304091762
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2852411986
Short name T1019
Test name
Test status
Simulation time 1418066756 ps
CPU time 4.75 seconds
Started Feb 08 05:51:23 PM UTC 25
Finished Feb 08 05:51:29 PM UTC 25
Peak memory 211344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2852411986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.2852411986
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4182201323
Short name T1014
Test name
Test status
Simulation time 28552161 ps
CPU time 0.96 seconds
Started Feb 08 05:51:23 PM UTC 25
Finished Feb 08 05:51:25 PM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182201323 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.4182201323
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2497514508
Short name T1033
Test name
Test status
Simulation time 7416751683 ps
CPU time 57.73 seconds
Started Feb 08 05:51:22 PM UTC 25
Finished Feb 08 05:52:21 PM UTC 25
Peak memory 211620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497514508 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_
err.2497514508
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3420428491
Short name T1015
Test name
Test status
Simulation time 144901049 ps
CPU time 1.02 seconds
Started Feb 08 05:51:23 PM UTC 25
Finished Feb 08 05:51:26 PM UTC 25
Peak memory 209392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342042
8491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_same_csr_outsta
nding.3420428491
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3696777065
Short name T1013
Test name
Test status
Simulation time 39107824 ps
CPU time 2.12 seconds
Started Feb 08 05:51:22 PM UTC 25
Finished Feb 08 05:51:25 PM UTC 25
Peak memory 221724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696777065 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.3696777065
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.700514490
Short name T1024
Test name
Test status
Simulation time 359152180 ps
CPU time 5.16 seconds
Started Feb 08 05:51:27 PM UTC 25
Finished Feb 08 05:51:34 PM UTC 25
Peak memory 221588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=700514490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.700514490
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.480015766
Short name T1017
Test name
Test status
Simulation time 34895924 ps
CPU time 0.98 seconds
Started Feb 08 05:51:26 PM UTC 25
Finished Feb 08 05:51:28 PM UTC 25
Peak memory 210624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480015766 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.480015766
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1452049007
Short name T1032
Test name
Test status
Simulation time 15356849591 ps
CPU time 41.45 seconds
Started Feb 08 05:51:25 PM UTC 25
Finished Feb 08 05:52:08 PM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452049007 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_
err.1452049007
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.4415388
Short name T1018
Test name
Test status
Simulation time 18002628 ps
CPU time 1.15 seconds
Started Feb 08 05:51:26 PM UTC 25
Finished Feb 08 05:51:28 PM UTC 25
Peak memory 210372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441538
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.4415388
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.248210046
Short name T1021
Test name
Test status
Simulation time 30737153 ps
CPU time 2.78 seconds
Started Feb 08 05:51:26 PM UTC 25
Finished Feb 08 05:51:30 PM UTC 25
Peak memory 211508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248210046 -assert nopostpro
c +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.248210046
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1119615641
Short name T1020
Test name
Test status
Simulation time 167203105 ps
CPU time 2.28 seconds
Started Feb 08 05:51:26 PM UTC 25
Finished Feb 08 05:51:29 PM UTC 25
Peak memory 221696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119615641 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_intg_err.1119615641
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3023261508
Short name T1027
Test name
Test status
Simulation time 1389226948 ps
CPU time 5.69 seconds
Started Feb 08 05:51:31 PM UTC 25
Finished Feb 08 05:51:38 PM UTC 25
Peak memory 223556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=3023261508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3023261508
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3446389192
Short name T1022
Test name
Test status
Simulation time 12147988 ps
CPU time 1.02 seconds
Started Feb 08 05:51:31 PM UTC 25
Finished Feb 08 05:51:33 PM UTC 25
Peak memory 210624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446389192 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.3446389192
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2740709964
Short name T1030
Test name
Test status
Simulation time 14227769218 ps
CPU time 33.53 seconds
Started Feb 08 05:51:27 PM UTC 25
Finished Feb 08 05:52:02 PM UTC 25
Peak memory 211328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740709964 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_
err.2740709964
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3565584142
Short name T1023
Test name
Test status
Simulation time 41586883 ps
CPU time 1.1 seconds
Started Feb 08 05:51:31 PM UTC 25
Finished Feb 08 05:51:33 PM UTC 25
Peak memory 210616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356558
4142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_same_csr_outsta
nding.3565584142
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1205134655
Short name T1025
Test name
Test status
Simulation time 295638668 ps
CPU time 3.22 seconds
Started Feb 08 05:51:30 PM UTC 25
Finished Feb 08 05:51:34 PM UTC 25
Peak memory 221728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205134655 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.1205134655
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2672275696
Short name T79
Test name
Test status
Simulation time 55919592 ps
CPU time 0.96 seconds
Started Feb 08 05:49:35 PM UTC 25
Finished Feb 08 05:49:37 PM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672275696 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_aliasing.2672275696
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3070021338
Short name T77
Test name
Test status
Simulation time 110478076 ps
CPU time 1.82 seconds
Started Feb 08 05:49:34 PM UTC 25
Finished Feb 08 05:49:37 PM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070021338 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.3070021338
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1385360010
Short name T76
Test name
Test status
Simulation time 46606171 ps
CPU time 0.91 seconds
Started Feb 08 05:49:30 PM UTC 25
Finished Feb 08 05:49:32 PM UTC 25
Peak memory 210896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385360010 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_reset.1385360010
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4076058444
Short name T954
Test name
Test status
Simulation time 787826176 ps
CPU time 5.25 seconds
Started Feb 08 05:49:36 PM UTC 25
Finished Feb 08 05:49:43 PM UTC 25
Peak memory 221640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=4076058444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.4076058444
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1100451006
Short name T952
Test name
Test status
Simulation time 15403727 ps
CPU time 1.05 seconds
Started Feb 08 05:49:33 PM UTC 25
Finished Feb 08 05:49:35 PM UTC 25
Peak memory 210620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100451006 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.1100451006
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3568126881
Short name T83
Test name
Test status
Simulation time 16304314077 ps
CPU time 54.2 seconds
Started Feb 08 05:49:28 PM UTC 25
Finished Feb 08 05:50:24 PM UTC 25
Peak memory 211472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568126881 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_e
rr.3568126881
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4018065477
Short name T99
Test name
Test status
Simulation time 21378389 ps
CPU time 0.96 seconds
Started Feb 08 05:49:35 PM UTC 25
Finished Feb 08 05:49:37 PM UTC 25
Peak memory 210604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401806
5477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_same_csr_outstan
ding.4018065477
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1333675183
Short name T127
Test name
Test status
Simulation time 511949233 ps
CPU time 4.09 seconds
Started Feb 08 05:49:29 PM UTC 25
Finished Feb 08 05:49:34 PM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333675183 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.1333675183
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1481983889
Short name T60
Test name
Test status
Simulation time 1282609761 ps
CPU time 2.85 seconds
Started Feb 08 05:49:29 PM UTC 25
Finished Feb 08 05:49:33 PM UTC 25
Peak memory 221668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481983889 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_intg_err.1481983889
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3585206945
Short name T955
Test name
Test status
Simulation time 43120088 ps
CPU time 1.08 seconds
Started Feb 08 05:49:44 PM UTC 25
Finished Feb 08 05:49:46 PM UTC 25
Peak memory 210276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585206945 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.3585206945
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2705779020
Short name T956
Test name
Test status
Simulation time 123092150 ps
CPU time 2.86 seconds
Started Feb 08 05:49:43 PM UTC 25
Finished Feb 08 05:49:47 PM UTC 25
Peak memory 211384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705779020 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_bash.2705779020
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1674342743
Short name T953
Test name
Test status
Simulation time 13914963 ps
CPU time 1 seconds
Started Feb 08 05:49:39 PM UTC 25
Finished Feb 08 05:49:41 PM UTC 25
Peak memory 210624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674342743 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.1674342743
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2496768197
Short name T957
Test name
Test status
Simulation time 5741566051 ps
CPU time 6.49 seconds
Started Feb 08 05:49:45 PM UTC 25
Finished Feb 08 05:49:53 PM UTC 25
Peak memory 221648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2496768197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2496768197
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.567981444
Short name T100
Test name
Test status
Simulation time 56815919 ps
CPU time 1.01 seconds
Started Feb 08 05:49:42 PM UTC 25
Finished Feb 08 05:49:44 PM UTC 25
Peak memory 210312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567981444 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.567981444
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.415262454
Short name T84
Test name
Test status
Simulation time 50316382568 ps
CPU time 80.69 seconds
Started Feb 08 05:49:38 PM UTC 25
Finished Feb 08 05:51:00 PM UTC 25
Peak memory 211504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415262454 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.415262454
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4116671992
Short name T101
Test name
Test status
Simulation time 26642066 ps
CPU time 1.05 seconds
Started Feb 08 05:49:44 PM UTC 25
Finished Feb 08 05:49:46 PM UTC 25
Peak memory 210372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411667
1992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_same_csr_outstan
ding.4116671992
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2312213079
Short name T128
Test name
Test status
Simulation time 272405571 ps
CPU time 4.23 seconds
Started Feb 08 05:49:38 PM UTC 25
Finished Feb 08 05:49:43 PM UTC 25
Peak memory 221744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312213079 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.2312213079
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.256940106
Short name T130
Test name
Test status
Simulation time 165847487 ps
CPU time 2.22 seconds
Started Feb 08 05:49:39 PM UTC 25
Finished Feb 08 05:49:42 PM UTC 25
Peak memory 211452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256940106 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_intg_err.256940106
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2799504064
Short name T80
Test name
Test status
Simulation time 39951589 ps
CPU time 1.01 seconds
Started Feb 08 05:49:56 PM UTC 25
Finished Feb 08 05:49:58 PM UTC 25
Peak memory 210624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799504064 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_aliasing.2799504064
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3732704078
Short name T961
Test name
Test status
Simulation time 33242620 ps
CPU time 1.78 seconds
Started Feb 08 05:49:55 PM UTC 25
Finished Feb 08 05:49:58 PM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732704078 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_bash.3732704078
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1459336051
Short name T959
Test name
Test status
Simulation time 42432388 ps
CPU time 1.09 seconds
Started Feb 08 05:49:54 PM UTC 25
Finished Feb 08 05:49:56 PM UTC 25
Peak memory 210312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459336051 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_reset.1459336051
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1548359975
Short name T963
Test name
Test status
Simulation time 1741046969 ps
CPU time 5.2 seconds
Started Feb 08 05:49:58 PM UTC 25
Finished Feb 08 05:50:04 PM UTC 25
Peak memory 221700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1548359975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1548359975
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4041308992
Short name T960
Test name
Test status
Simulation time 49461185 ps
CPU time 1.01 seconds
Started Feb 08 05:49:55 PM UTC 25
Finished Feb 08 05:49:57 PM UTC 25
Peak memory 210252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041308992 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.4041308992
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.895591805
Short name T1012
Test name
Test status
Simulation time 7148561034 ps
CPU time 95.08 seconds
Started Feb 08 05:49:47 PM UTC 25
Finished Feb 08 05:51:25 PM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895591805 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.895591805
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.300325681
Short name T102
Test name
Test status
Simulation time 43384501 ps
CPU time 1.18 seconds
Started Feb 08 05:49:57 PM UTC 25
Finished Feb 08 05:49:59 PM UTC 25
Peak memory 210368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300325
681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_same_csr_outstand
ing.300325681
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1418206608
Short name T958
Test name
Test status
Simulation time 330552988 ps
CPU time 4.95 seconds
Started Feb 08 05:49:47 PM UTC 25
Finished Feb 08 05:49:54 PM UTC 25
Peak memory 221724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418206608 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.1418206608
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3664601474
Short name T131
Test name
Test status
Simulation time 592133636 ps
CPU time 3.69 seconds
Started Feb 08 05:49:48 PM UTC 25
Finished Feb 08 05:49:53 PM UTC 25
Peak memory 221840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664601474 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_intg_err.3664601474
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.471481008
Short name T966
Test name
Test status
Simulation time 368688113 ps
CPU time 6.1 seconds
Started Feb 08 05:50:03 PM UTC 25
Finished Feb 08 05:50:11 PM UTC 25
Peak memory 221580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=471481008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.471481008
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1774328768
Short name T962
Test name
Test status
Simulation time 67688666 ps
CPU time 1.01 seconds
Started Feb 08 05:50:00 PM UTC 25
Finished Feb 08 05:50:02 PM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774328768 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.1774328768
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2021503197
Short name T95
Test name
Test status
Simulation time 7052410887 ps
CPU time 76.93 seconds
Started Feb 08 05:49:58 PM UTC 25
Finished Feb 08 05:51:17 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021503197 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_e
rr.2021503197
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1741197795
Short name T103
Test name
Test status
Simulation time 20931649 ps
CPU time 1.05 seconds
Started Feb 08 05:50:03 PM UTC 25
Finished Feb 08 05:50:06 PM UTC 25
Peak memory 210372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174119
7795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_same_csr_outstan
ding.1741197795
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2372037405
Short name T964
Test name
Test status
Simulation time 530133793 ps
CPU time 7.24 seconds
Started Feb 08 05:49:59 PM UTC 25
Finished Feb 08 05:50:08 PM UTC 25
Peak memory 221732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372037405 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.2372037405
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1207702686
Short name T134
Test name
Test status
Simulation time 240404746 ps
CPU time 1.88 seconds
Started Feb 08 05:50:00 PM UTC 25
Finished Feb 08 05:50:03 PM UTC 25
Peak memory 210368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207702686 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_intg_err.1207702686
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1743913569
Short name T969
Test name
Test status
Simulation time 694842843 ps
CPU time 5.82 seconds
Started Feb 08 05:50:10 PM UTC 25
Finished Feb 08 05:50:17 PM UTC 25
Peak memory 221584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1743913569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.1743913569
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2408795547
Short name T967
Test name
Test status
Simulation time 39135729 ps
CPU time 0.97 seconds
Started Feb 08 05:50:09 PM UTC 25
Finished Feb 08 05:50:11 PM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408795547 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.2408795547
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.903142501
Short name T93
Test name
Test status
Simulation time 18093032714 ps
CPU time 63.4 seconds
Started Feb 08 05:50:05 PM UTC 25
Finished Feb 08 05:51:10 PM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903142501 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.903142501
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.475487432
Short name T104
Test name
Test status
Simulation time 15781243 ps
CPU time 0.94 seconds
Started Feb 08 05:50:09 PM UTC 25
Finished Feb 08 05:50:11 PM UTC 25
Peak memory 210600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475487
432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_same_csr_outstand
ing.475487432
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2618699621
Short name T965
Test name
Test status
Simulation time 28904414 ps
CPU time 2.9 seconds
Started Feb 08 05:50:06 PM UTC 25
Finished Feb 08 05:50:10 PM UTC 25
Peak memory 211560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618699621 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.2618699621
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1170620373
Short name T132
Test name
Test status
Simulation time 625835436 ps
CPU time 3.9 seconds
Started Feb 08 05:50:07 PM UTC 25
Finished Feb 08 05:50:12 PM UTC 25
Peak memory 221836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170620373 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_intg_err.1170620373
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2732414849
Short name T973
Test name
Test status
Simulation time 1421789159 ps
CPU time 5.39 seconds
Started Feb 08 05:50:16 PM UTC 25
Finished Feb 08 05:50:22 PM UTC 25
Peak memory 221516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=2732414849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2732414849
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2244937895
Short name T968
Test name
Test status
Simulation time 32806079 ps
CPU time 0.99 seconds
Started Feb 08 05:50:12 PM UTC 25
Finished Feb 08 05:50:15 PM UTC 25
Peak memory 210620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244937895 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.2244937895
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1582088223
Short name T91
Test name
Test status
Simulation time 13682353986 ps
CPU time 50.9 seconds
Started Feb 08 05:50:11 PM UTC 25
Finished Feb 08 05:51:04 PM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582088223 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_e
rr.1582088223
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.40737799
Short name T970
Test name
Test status
Simulation time 27163121 ps
CPU time 1.22 seconds
Started Feb 08 05:50:16 PM UTC 25
Finished Feb 08 05:50:18 PM UTC 25
Peak memory 210292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407377
99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.40737799
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3248828181
Short name T971
Test name
Test status
Simulation time 75674882 ps
CPU time 6.23 seconds
Started Feb 08 05:50:12 PM UTC 25
Finished Feb 08 05:50:20 PM UTC 25
Peak memory 211528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248828181 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.3248828181
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1979370281
Short name T135
Test name
Test status
Simulation time 376151858 ps
CPU time 2.72 seconds
Started Feb 08 05:50:12 PM UTC 25
Finished Feb 08 05:50:16 PM UTC 25
Peak memory 221664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979370281 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_intg_err.1979370281
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.459514579
Short name T977
Test name
Test status
Simulation time 389342041 ps
CPU time 5.56 seconds
Started Feb 08 05:50:23 PM UTC 25
Finished Feb 08 05:50:30 PM UTC 25
Peak memory 221508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=459514579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.459514579
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.924985085
Short name T82
Test name
Test status
Simulation time 23538044 ps
CPU time 0.92 seconds
Started Feb 08 05:50:21 PM UTC 25
Finished Feb 08 05:50:23 PM UTC 25
Peak memory 210312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924985085 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.924985085
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3733994549
Short name T92
Test name
Test status
Simulation time 28437683358 ps
CPU time 48.12 seconds
Started Feb 08 05:50:17 PM UTC 25
Finished Feb 08 05:51:06 PM UTC 25
Peak memory 221832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733994549 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_e
rr.3733994549
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3650901397
Short name T974
Test name
Test status
Simulation time 17423765 ps
CPU time 1.04 seconds
Started Feb 08 05:50:22 PM UTC 25
Finished Feb 08 05:50:24 PM UTC 25
Peak memory 210252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365090
1397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_same_csr_outstan
ding.3650901397
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1554236520
Short name T972
Test name
Test status
Simulation time 38555325 ps
CPU time 2.78 seconds
Started Feb 08 05:50:18 PM UTC 25
Finished Feb 08 05:50:22 PM UTC 25
Peak memory 221724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554236520 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.1554236520
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.732397922
Short name T136
Test name
Test status
Simulation time 330010830 ps
CPU time 2.49 seconds
Started Feb 08 05:50:19 PM UTC 25
Finished Feb 08 05:50:23 PM UTC 25
Peak memory 221744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732397922 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_intg_err.732397922
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1205283310
Short name T983
Test name
Test status
Simulation time 377638593 ps
CPU time 8.69 seconds
Started Feb 08 05:50:29 PM UTC 25
Finished Feb 08 05:50:39 PM UTC 25
Peak memory 221736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to
ols/sim.tcl +ntb_random_seed=1205283310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1205283310
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3067983513
Short name T975
Test name
Test status
Simulation time 16978517 ps
CPU time 1.06 seconds
Started Feb 08 05:50:26 PM UTC 25
Finished Feb 08 05:50:28 PM UTC 25
Peak memory 210620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067983513 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.3067983513
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3491456037
Short name T94
Test name
Test status
Simulation time 3894286377 ps
CPU time 45.4 seconds
Started Feb 08 05:50:23 PM UTC 25
Finished Feb 08 05:51:10 PM UTC 25
Peak memory 211480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491456037 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_e
rr.3491456037
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2731424230
Short name T978
Test name
Test status
Simulation time 25007294 ps
CPU time 1.12 seconds
Started Feb 08 05:50:29 PM UTC 25
Finished Feb 08 05:50:31 PM UTC 25
Peak memory 210372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273142
4230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_same_csr_outstan
ding.2731424230
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3329377787
Short name T976
Test name
Test status
Simulation time 33534697 ps
CPU time 2.83 seconds
Started Feb 08 05:50:25 PM UTC 25
Finished Feb 08 05:50:28 PM UTC 25
Peak memory 221868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329377787 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.3329377787
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2780599054
Short name T139
Test name
Test status
Simulation time 225225480 ps
CPU time 2.56 seconds
Started Feb 08 05:50:25 PM UTC 25
Finished Feb 08 05:50:28 PM UTC 25
Peak memory 221820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780599054 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_intg_err.2780599054
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2011575188
Short name T39
Test name
Test status
Simulation time 35250072562 ps
CPU time 882.95 seconds
Started Feb 08 02:48:47 PM UTC 25
Finished Feb 08 03:03:39 PM UTC 25
Peak memory 389876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011575188 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_key_req.2011575188
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.546642001
Short name T11
Test name
Test status
Simulation time 73950644 ps
CPU time 0.94 seconds
Started Feb 08 02:51:22 PM UTC 25
Finished Feb 08 02:51:24 PM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546642001 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.546642001
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.2446785400
Short name T159
Test name
Test status
Simulation time 202210482411 ps
CPU time 936.96 seconds
Started Feb 08 02:48:44 PM UTC 25
Finished Feb 08 03:04:32 PM UTC 25
Peak memory 212696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446785400 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.2446785400
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.292257432
Short name T26
Test name
Test status
Simulation time 9488295775 ps
CPU time 262.75 seconds
Started Feb 08 02:49:06 PM UTC 25
Finished Feb 08 02:53:33 PM UTC 25
Peak memory 351168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292257432 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.292257432
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1008507338
Short name T4
Test name
Test status
Simulation time 747073344 ps
CPU time 48.56 seconds
Started Feb 08 02:48:46 PM UTC 25
Finished Feb 08 02:49:37 PM UTC 25
Peak memory 346752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008507338
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max_throughput.1008507338
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1276140775
Short name T10
Test name
Test status
Simulation time 2674983885 ps
CPU time 96.2 seconds
Started Feb 08 02:49:37 PM UTC 25
Finished Feb 08 02:51:16 PM UTC 25
Peak memory 222964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276140775 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.1276140775
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2705580214
Short name T33
Test name
Test status
Simulation time 40687877720 ps
CPU time 196.43 seconds
Started Feb 08 02:49:32 PM UTC 25
Finished Feb 08 02:52:52 PM UTC 25
Peak memory 223252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705580214 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.2705580214
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2569890155
Short name T152
Test name
Test status
Simulation time 61759329570 ps
CPU time 726.97 seconds
Started Feb 08 02:48:44 PM UTC 25
Finished Feb 08 03:01:00 PM UTC 25
Peak memory 383720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569890155 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.2569890155
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1793693299
Short name T1
Test name
Test status
Simulation time 864804323 ps
CPU time 18.5 seconds
Started Feb 08 02:48:44 PM UTC 25
Finished Feb 08 02:49:04 PM UTC 25
Peak memory 254640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793693299 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.1793693299
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.900611871
Short name T2
Test name
Test status
Simulation time 1020694339 ps
CPU time 28.47 seconds
Started Feb 08 02:48:44 PM UTC 25
Finished Feb 08 02:49:14 PM UTC 25
Peak memory 320308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900611871 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.900611871
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.367305916
Short name T557
Test name
Test status
Simulation time 298897572008 ps
CPU time 7827.88 seconds
Started Feb 08 02:49:55 PM UTC 25
Finished Feb 08 05:01:42 PM UTC 25
Peak memory 391528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367305916 -assert n
opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.367305916
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2335789205
Short name T35
Test name
Test status
Simulation time 62136134644 ps
CPU time 301.61 seconds
Started Feb 08 02:48:44 PM UTC 25
Finished Feb 08 02:53:50 PM UTC 25
Peak memory 212768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335789205 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.2335789205
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.4186287287
Short name T9
Test name
Test status
Simulation time 780854432 ps
CPU time 66.43 seconds
Started Feb 08 02:48:46 PM UTC 25
Finished Feb 08 02:49:55 PM UTC 25
Peak memory 371328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186287287
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_throughput_w_partial_w
rite.4186287287
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1218804566
Short name T40
Test name
Test status
Simulation time 15841199976 ps
CPU time 911.4 seconds
Started Feb 08 02:54:12 PM UTC 25
Finished Feb 08 03:09:34 PM UTC 25
Peak memory 385688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218804566 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_key_req.1218804566
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3110682424
Short name T13
Test name
Test status
Simulation time 15134272 ps
CPU time 0.81 seconds
Started Feb 08 02:57:30 PM UTC 25
Finished Feb 08 02:57:32 PM UTC 25
Peak memory 211580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110682424 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.3110682424
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.4227797775
Short name T178
Test name
Test status
Simulation time 73341326162 ps
CPU time 1411.92 seconds
Started Feb 08 02:51:43 PM UTC 25
Finished Feb 08 03:15:31 PM UTC 25
Peak memory 212848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227797775 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.4227797775
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.3771749598
Short name T42
Test name
Test status
Simulation time 66186998875 ps
CPU time 536.28 seconds
Started Feb 08 02:54:34 PM UTC 25
Finished Feb 08 03:03:37 PM UTC 25
Peak memory 389804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771749598 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.3771749598
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1760945746
Short name T7
Test name
Test status
Simulation time 21024008537 ps
CPU time 47.85 seconds
Started Feb 08 02:53:52 PM UTC 25
Finished Feb 08 02:54:41 PM UTC 25
Peak memory 213036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760945746 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.1760945746
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3929819982
Short name T37
Test name
Test status
Simulation time 1575708561 ps
CPU time 67.16 seconds
Started Feb 08 02:53:24 PM UTC 25
Finished Feb 08 02:54:33 PM UTC 25
Peak memory 369276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929819982
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max_throughput.3929819982
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.868505090
Short name T156
Test name
Test status
Simulation time 8047794159 ps
CPU time 312.48 seconds
Started Feb 08 02:54:55 PM UTC 25
Finished Feb 08 03:00:12 PM UTC 25
Peak memory 223144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868505090 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.868505090
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.4050277064
Short name T62
Test name
Test status
Simulation time 8269717697 ps
CPU time 259.07 seconds
Started Feb 08 02:51:27 PM UTC 25
Finished Feb 08 02:55:49 PM UTC 25
Peak memory 383628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050277064 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.4050277064
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2145342115
Short name T34
Test name
Test status
Simulation time 2007138213 ps
CPU time 16.98 seconds
Started Feb 08 02:53:05 PM UTC 25
Finished Feb 08 02:53:24 PM UTC 25
Peak memory 264976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145342115 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.2145342115
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2620005456
Short name T105
Test name
Test status
Simulation time 13198398607 ps
CPU time 311.38 seconds
Started Feb 08 02:53:10 PM UTC 25
Finished Feb 08 02:58:26 PM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620005456 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access_b2b.2620005456
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2499080317
Short name T28
Test name
Test status
Simulation time 351358457 ps
CPU time 4.72 seconds
Started Feb 08 02:54:48 PM UTC 25
Finished Feb 08 02:54:54 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499080317 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2499080317
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.93287499
Short name T16
Test name
Test status
Simulation time 879263548 ps
CPU time 4.61 seconds
Started Feb 08 02:57:23 PM UTC 25
Finished Feb 08 02:57:29 PM UTC 25
Peak memory 248832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93287499 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.93287499
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.307494715
Short name T32
Test name
Test status
Simulation time 842849487 ps
CPU time 15.49 seconds
Started Feb 08 02:51:25 PM UTC 25
Finished Feb 08 02:51:42 PM UTC 25
Peak memory 212624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307494715 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.307494715
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.307271803
Short name T24
Test name
Test status
Simulation time 8604942535 ps
CPU time 34.72 seconds
Started Feb 08 02:56:08 PM UTC 25
Finished Feb 08 02:56:45 PM UTC 25
Peak memory 229436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307271803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.307271803
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3156381863
Short name T61
Test name
Test status
Simulation time 64282689735 ps
CPU time 273.91 seconds
Started Feb 08 02:52:53 PM UTC 25
Finished Feb 08 02:57:31 PM UTC 25
Peak memory 212980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156381863 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.3156381863
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.1761574101
Short name T36
Test name
Test status
Simulation time 3130449007 ps
CPU time 36.22 seconds
Started Feb 08 02:53:34 PM UTC 25
Finished Feb 08 02:54:11 PM UTC 25
Peak memory 336480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761574101
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_throughput_w_partial_w
rite.1761574101
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.4241325211
Short name T253
Test name
Test status
Simulation time 5444193991 ps
CPU time 242.64 seconds
Started Feb 08 03:36:48 PM UTC 25
Finished Feb 08 03:40:54 PM UTC 25
Peak memory 365492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241325211 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during_key_req.4241325211
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3741249655
Short name T248
Test name
Test status
Simulation time 42075257 ps
CPU time 0.87 seconds
Started Feb 08 03:40:28 PM UTC 25
Finished Feb 08 03:40:30 PM UTC 25
Peak memory 212492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741249655 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3741249655
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2441262233
Short name T292
Test name
Test status
Simulation time 94165521373 ps
CPU time 1305.41 seconds
Started Feb 08 03:34:57 PM UTC 25
Finished Feb 08 03:56:58 PM UTC 25
Peak memory 214364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441262233 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.2441262233
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2397985391
Short name T277
Test name
Test status
Simulation time 10666091314 ps
CPU time 832.7 seconds
Started Feb 08 03:36:52 PM UTC 25
Finished Feb 08 03:50:54 PM UTC 25
Peak memory 389544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397985391 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.2397985391
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3605679448
Short name T244
Test name
Test status
Simulation time 14220963580 ps
CPU time 117.91 seconds
Started Feb 08 03:36:44 PM UTC 25
Finished Feb 08 03:38:44 PM UTC 25
Peak memory 212788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605679448 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.3605679448
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1669052789
Short name T241
Test name
Test status
Simulation time 3183755714 ps
CPU time 77.1 seconds
Started Feb 08 03:35:48 PM UTC 25
Finished Feb 08 03:37:07 PM UTC 25
Peak memory 381616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669052789
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_max_throughput.1669052789
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.3085347075
Short name T254
Test name
Test status
Simulation time 1591557819 ps
CPU time 135.01 seconds
Started Feb 08 03:38:44 PM UTC 25
Finished Feb 08 03:41:02 PM UTC 25
Peak memory 230128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085347075 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.3085347075
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2010383916
Short name T252
Test name
Test status
Simulation time 7592674611 ps
CPU time 129.1 seconds
Started Feb 08 03:38:39 PM UTC 25
Finished Feb 08 03:40:51 PM UTC 25
Peak memory 222916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010383916 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.2010383916
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3649889636
Short name T276
Test name
Test status
Simulation time 18576773405 ps
CPU time 937.93 seconds
Started Feb 08 03:34:54 PM UTC 25
Finished Feb 08 03:50:43 PM UTC 25
Peak memory 387288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649889636 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.3649889636
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.4162219877
Short name T236
Test name
Test status
Simulation time 622508626 ps
CPU time 25.41 seconds
Started Feb 08 03:35:21 PM UTC 25
Finished Feb 08 03:35:48 PM UTC 25
Peak memory 212660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162219877 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.4162219877
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.447910863
Short name T249
Test name
Test status
Simulation time 10663188574 ps
CPU time 309.01 seconds
Started Feb 08 03:35:24 PM UTC 25
Finished Feb 08 03:40:37 PM UTC 25
Peak memory 212840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447910863 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access_b2b.447910863
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2856530428
Short name T243
Test name
Test status
Simulation time 1474600045 ps
CPU time 6.19 seconds
Started Feb 08 03:38:30 PM UTC 25
Finished Feb 08 03:38:38 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856530428 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2856530428
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.3064859154
Short name T265
Test name
Test status
Simulation time 2489926648 ps
CPU time 487.78 seconds
Started Feb 08 03:37:08 PM UTC 25
Finished Feb 08 03:45:22 PM UTC 25
Peak memory 381604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064859154 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3064859154
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.2882704394
Short name T232
Test name
Test status
Simulation time 1126671238 ps
CPU time 25.74 seconds
Started Feb 08 03:34:29 PM UTC 25
Finished Feb 08 03:34:56 PM UTC 25
Peak memory 212592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882704394 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2882704394
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.262955438
Short name T527
Test name
Test status
Simulation time 43041181254 ps
CPU time 4543.86 seconds
Started Feb 08 03:40:22 PM UTC 25
Finished Feb 08 04:56:54 PM UTC 25
Peak memory 393516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262955438 -assert n
opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.262955438
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1765814767
Short name T247
Test name
Test status
Simulation time 2292234864 ps
CPU time 41.46 seconds
Started Feb 08 03:39:44 PM UTC 25
Finished Feb 08 03:40:27 PM UTC 25
Peak memory 223132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765814767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1765814767
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3598284804
Short name T258
Test name
Test status
Simulation time 6460754069 ps
CPU time 440.35 seconds
Started Feb 08 03:35:01 PM UTC 25
Finished Feb 08 03:42:27 PM UTC 25
Peak memory 212720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598284804 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.3598284804
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3628177599
Short name T240
Test name
Test status
Simulation time 827671163 ps
CPU time 51.85 seconds
Started Feb 08 03:35:57 PM UTC 25
Finished Feb 08 03:36:51 PM UTC 25
Peak memory 336440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628177599
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_throughput_w_partial_
write.3628177599
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.1732542690
Short name T281
Test name
Test status
Simulation time 64260957241 ps
CPU time 781.29 seconds
Started Feb 08 03:41:56 PM UTC 25
Finished Feb 08 03:55:06 PM UTC 25
Peak memory 387988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732542690 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during_key_req.1732542690
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3178337769
Short name T264
Test name
Test status
Simulation time 15873256 ps
CPU time 0.87 seconds
Started Feb 08 03:45:19 PM UTC 25
Finished Feb 08 03:45:21 PM UTC 25
Peak memory 212492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178337769 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3178337769
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.3904537170
Short name T367
Test name
Test status
Simulation time 193169872121 ps
CPU time 2359.12 seconds
Started Feb 08 03:40:40 PM UTC 25
Finished Feb 08 04:20:25 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904537170 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.3904537170
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2415356466
Short name T118
Test name
Test status
Simulation time 106408933011 ps
CPU time 582.51 seconds
Started Feb 08 03:41:58 PM UTC 25
Finished Feb 08 03:51:48 PM UTC 25
Peak memory 375540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415356466 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.2415356466
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.676883031
Short name T259
Test name
Test status
Simulation time 15155161821 ps
CPU time 120.13 seconds
Started Feb 08 03:41:22 PM UTC 25
Finished Feb 08 03:43:24 PM UTC 25
Peak memory 227344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676883031 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.676883031
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.3262034408
Short name T257
Test name
Test status
Simulation time 5222534174 ps
CPU time 50.76 seconds
Started Feb 08 03:41:02 PM UTC 25
Finished Feb 08 03:41:55 PM UTC 25
Peak memory 320184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262034408
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_max_throughput.3262034408
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2533960184
Short name T263
Test name
Test status
Simulation time 1953526306 ps
CPU time 90.3 seconds
Started Feb 08 03:43:45 PM UTC 25
Finished Feb 08 03:45:18 PM UTC 25
Peak memory 229868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533960184 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.2533960184
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1064023751
Short name T274
Test name
Test status
Simulation time 125753939760 ps
CPU time 408.49 seconds
Started Feb 08 03:43:33 PM UTC 25
Finished Feb 08 03:50:27 PM UTC 25
Peak memory 223280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064023751 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.1064023751
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3519587430
Short name T124
Test name
Test status
Simulation time 7693506776 ps
CPU time 761.3 seconds
Started Feb 08 03:40:38 PM UTC 25
Finished Feb 08 03:53:28 PM UTC 25
Peak memory 390036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519587430 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.3519587430
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4172874775
Short name T255
Test name
Test status
Simulation time 950233286 ps
CPU time 16.12 seconds
Started Feb 08 03:40:51 PM UTC 25
Finished Feb 08 03:41:09 PM UTC 25
Peak memory 212648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172874775 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.4172874775
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.2436097039
Short name T271
Test name
Test status
Simulation time 17258121947 ps
CPU time 463.85 seconds
Started Feb 08 03:40:55 PM UTC 25
Finished Feb 08 03:48:45 PM UTC 25
Peak memory 212768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436097039 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access_b2b.2436097039
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1684034889
Short name T260
Test name
Test status
Simulation time 2238818804 ps
CPU time 5.81 seconds
Started Feb 08 03:43:25 PM UTC 25
Finished Feb 08 03:43:32 PM UTC 25
Peak memory 212872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684034889 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1684034889
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.3276434937
Short name T145
Test name
Test status
Simulation time 4849594566 ps
CPU time 752.92 seconds
Started Feb 08 03:42:28 PM UTC 25
Finished Feb 08 03:55:09 PM UTC 25
Peak memory 381664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276434937 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3276434937
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.1443911650
Short name T251
Test name
Test status
Simulation time 489594732 ps
CPU time 6.89 seconds
Started Feb 08 03:40:31 PM UTC 25
Finished Feb 08 03:40:39 PM UTC 25
Peak memory 212620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443911650 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1443911650
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1194060171
Short name T526
Test name
Test status
Simulation time 280898063347 ps
CPU time 4280.36 seconds
Started Feb 08 03:44:46 PM UTC 25
Finished Feb 08 04:56:51 PM UTC 25
Peak memory 393648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194060171 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.1194060171
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2790505982
Short name T50
Test name
Test status
Simulation time 2022089074 ps
CPU time 52.51 seconds
Started Feb 08 03:43:50 PM UTC 25
Finished Feb 08 03:44:45 PM UTC 25
Peak memory 222904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790505982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2790505982
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1040722074
Short name T268
Test name
Test status
Simulation time 20549519821 ps
CPU time 447.56 seconds
Started Feb 08 03:40:40 PM UTC 25
Finished Feb 08 03:48:14 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040722074 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.1040722074
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2048105317
Short name T256
Test name
Test status
Simulation time 2681690785 ps
CPU time 10.04 seconds
Started Feb 08 03:41:09 PM UTC 25
Finished Feb 08 03:41:21 PM UTC 25
Peak memory 222968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048105317
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_throughput_w_partial_
write.2048105317
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.2335013721
Short name T126
Test name
Test status
Simulation time 6606096323 ps
CPU time 306.87 seconds
Started Feb 08 03:49:10 PM UTC 25
Finished Feb 08 03:54:21 PM UTC 25
Peak memory 388020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335013721 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during_key_req.2335013721
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3156922593
Short name T119
Test name
Test status
Simulation time 13444369 ps
CPU time 0.9 seconds
Started Feb 08 03:51:49 PM UTC 25
Finished Feb 08 03:51:51 PM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156922593 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3156922593
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.1205519510
Short name T376
Test name
Test status
Simulation time 99619469363 ps
CPU time 2300.09 seconds
Started Feb 08 03:45:34 PM UTC 25
Finished Feb 08 04:24:19 PM UTC 25
Peak memory 214468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205519510 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.1205519510
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1864238898
Short name T282
Test name
Test status
Simulation time 9409651605 ps
CPU time 304.88 seconds
Started Feb 08 03:50:04 PM UTC 25
Finished Feb 08 03:55:14 PM UTC 25
Peak memory 379772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864238898 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.1864238898
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.11181887
Short name T273
Test name
Test status
Simulation time 32359930191 ps
CPU time 77.41 seconds
Started Feb 08 03:48:46 PM UTC 25
Finished Feb 08 03:50:05 PM UTC 25
Peak memory 212772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11181887 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.11181887
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3721750724
Short name T270
Test name
Test status
Simulation time 2724894150 ps
CPU time 19.16 seconds
Started Feb 08 03:48:18 PM UTC 25
Finished Feb 08 03:48:38 PM UTC 25
Peak memory 268960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721750724
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_max_throughput.3721750724
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3204338936
Short name T122
Test name
Test status
Simulation time 9770323463 ps
CPU time 147.16 seconds
Started Feb 08 03:50:43 PM UTC 25
Finished Feb 08 03:53:13 PM UTC 25
Peak memory 223252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204338936 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.3204338936
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1264847024
Short name T278
Test name
Test status
Simulation time 25871080198 ps
CPU time 233.4 seconds
Started Feb 08 03:50:35 PM UTC 25
Finished Feb 08 03:54:32 PM UTC 25
Peak memory 222992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264847024 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.1264847024
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.1108207583
Short name T310
Test name
Test status
Simulation time 59238113726 ps
CPU time 1035.91 seconds
Started Feb 08 03:45:23 PM UTC 25
Finished Feb 08 04:02:51 PM UTC 25
Peak memory 381224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108207583 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.1108207583
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3837150910
Short name T269
Test name
Test status
Simulation time 3940966416 ps
CPU time 35.5 seconds
Started Feb 08 03:47:40 PM UTC 25
Finished Feb 08 03:48:17 PM UTC 25
Peak memory 212956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837150910 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.3837150910
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.675010184
Short name T283
Test name
Test status
Simulation time 20565103153 ps
CPU time 414.28 seconds
Started Feb 08 03:48:15 PM UTC 25
Finished Feb 08 03:55:15 PM UTC 25
Peak memory 212764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675010184 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access_b2b.675010184
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1869283783
Short name T275
Test name
Test status
Simulation time 436359043 ps
CPU time 4.68 seconds
Started Feb 08 03:50:28 PM UTC 25
Finished Feb 08 03:50:34 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869283783 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1869283783
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.1891321848
Short name T290
Test name
Test status
Simulation time 5220523236 ps
CPU time 366.03 seconds
Started Feb 08 03:50:06 PM UTC 25
Finished Feb 08 03:56:17 PM UTC 25
Peak memory 379632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891321848 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1891321848
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.3141064256
Short name T266
Test name
Test status
Simulation time 1390895856 ps
CPU time 10.01 seconds
Started Feb 08 03:45:22 PM UTC 25
Finished Feb 08 03:45:33 PM UTC 25
Peak memory 227880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141064256 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3141064256
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.2941794324
Short name T427
Test name
Test status
Simulation time 305292499530 ps
CPU time 2710.73 seconds
Started Feb 08 03:51:08 PM UTC 25
Finished Feb 08 04:36:45 PM UTC 25
Peak memory 391600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941794324 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.2941794324
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1507344276
Short name T110
Test name
Test status
Simulation time 530973011 ps
CPU time 10.05 seconds
Started Feb 08 03:50:56 PM UTC 25
Finished Feb 08 03:51:07 PM UTC 25
Peak memory 222868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507344276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1507344276
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2468323106
Short name T120
Test name
Test status
Simulation time 27009083773 ps
CPU time 341.72 seconds
Started Feb 08 03:46:08 PM UTC 25
Finished Feb 08 03:51:55 PM UTC 25
Peak memory 212952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468323106 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.2468323106
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1643664411
Short name T272
Test name
Test status
Simulation time 713774859 ps
CPU time 28.37 seconds
Started Feb 08 03:48:39 PM UTC 25
Finished Feb 08 03:49:09 PM UTC 25
Peak memory 270900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643664411
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_throughput_w_partial_
write.1643664411
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1619036853
Short name T350
Test name
Test status
Simulation time 14224970599 ps
CPU time 1154.51 seconds
Started Feb 08 03:54:37 PM UTC 25
Finished Feb 08 04:14:04 PM UTC 25
Peak memory 391476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619036853 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during_key_req.1619036853
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.4228314987
Short name T286
Test name
Test status
Simulation time 13697989 ps
CPU time 0.88 seconds
Started Feb 08 03:55:24 PM UTC 25
Finished Feb 08 03:55:26 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228314987 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.4228314987
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3653959149
Short name T317
Test name
Test status
Simulation time 9521266072 ps
CPU time 690.07 seconds
Started Feb 08 03:52:17 PM UTC 25
Finished Feb 08 04:03:56 PM UTC 25
Peak memory 212896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653959149 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.3653959149
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.1747912870
Short name T328
Test name
Test status
Simulation time 21524351444 ps
CPU time 789.01 seconds
Started Feb 08 03:54:40 PM UTC 25
Finished Feb 08 04:07:58 PM UTC 25
Peak memory 387968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747912870 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.1747912870
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2609498217
Short name T285
Test name
Test status
Simulation time 4996470356 ps
CPU time 48.73 seconds
Started Feb 08 03:54:33 PM UTC 25
Finished Feb 08 03:55:23 PM UTC 25
Peak memory 212760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609498217 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.2609498217
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1148721725
Short name T280
Test name
Test status
Simulation time 1024071725 ps
CPU time 57.28 seconds
Started Feb 08 03:53:40 PM UTC 25
Finished Feb 08 03:54:39 PM UTC 25
Peak memory 348968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148721725
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_max_throughput.1148721725
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.3392890394
Short name T295
Test name
Test status
Simulation time 24162979825 ps
CPU time 160.13 seconds
Started Feb 08 03:55:15 PM UTC 25
Finished Feb 08 03:57:58 PM UTC 25
Peak memory 230228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392890394 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.3392890394
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3746990684
Short name T296
Test name
Test status
Simulation time 10449502934 ps
CPU time 180.28 seconds
Started Feb 08 03:55:14 PM UTC 25
Finished Feb 08 03:58:18 PM UTC 25
Peak memory 223048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746990684 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.3746990684
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1396812355
Short name T311
Test name
Test status
Simulation time 49425582892 ps
CPU time 655.47 seconds
Started Feb 08 03:51:56 PM UTC 25
Finished Feb 08 04:02:59 PM UTC 25
Peak memory 390068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396812355 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.1396812355
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.218897594
Short name T125
Test name
Test status
Simulation time 766205451 ps
CPU time 14.23 seconds
Started Feb 08 03:53:24 PM UTC 25
Finished Feb 08 03:53:40 PM UTC 25
Peak memory 212648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218897594 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.218897594
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.1532510381
Short name T302
Test name
Test status
Simulation time 264139608738 ps
CPU time 419.05 seconds
Started Feb 08 03:53:28 PM UTC 25
Finished Feb 08 04:00:33 PM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532510381 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access_b2b.1532510381
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.4245011293
Short name T284
Test name
Test status
Simulation time 345603147 ps
CPU time 4.79 seconds
Started Feb 08 03:55:10 PM UTC 25
Finished Feb 08 03:55:16 PM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245011293 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.4245011293
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.2565169428
Short name T301
Test name
Test status
Simulation time 7535891715 ps
CPU time 318.34 seconds
Started Feb 08 03:55:07 PM UTC 25
Finished Feb 08 04:00:30 PM UTC 25
Peak memory 379636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565169428 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2565169428
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1538646535
Short name T121
Test name
Test status
Simulation time 1153305448 ps
CPU time 22.75 seconds
Started Feb 08 03:51:52 PM UTC 25
Finished Feb 08 03:52:16 PM UTC 25
Peak memory 212648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538646535 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1538646535
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3605240697
Short name T420
Test name
Test status
Simulation time 88337537002 ps
CPU time 2338.79 seconds
Started Feb 08 03:55:17 PM UTC 25
Finished Feb 08 04:34:39 PM UTC 25
Peak memory 393568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605240697 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.3605240697
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2747029766
Short name T288
Test name
Test status
Simulation time 719154356 ps
CPU time 15.02 seconds
Started Feb 08 03:55:16 PM UTC 25
Finished Feb 08 03:55:33 PM UTC 25
Peak memory 222868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747029766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2747029766
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2283364530
Short name T299
Test name
Test status
Simulation time 5468503929 ps
CPU time 409.46 seconds
Started Feb 08 03:53:14 PM UTC 25
Finished Feb 08 04:00:09 PM UTC 25
Peak memory 212776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283364530 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.2283364530
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2684037535
Short name T287
Test name
Test status
Simulation time 5924524341 ps
CPU time 66.46 seconds
Started Feb 08 03:54:22 PM UTC 25
Finished Feb 08 03:55:30 PM UTC 25
Peak memory 367284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684037535
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_throughput_w_partial_
write.2684037535
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2455111593
Short name T326
Test name
Test status
Simulation time 9882478228 ps
CPU time 554.25 seconds
Started Feb 08 03:57:59 PM UTC 25
Finished Feb 08 04:07:20 PM UTC 25
Peak memory 387824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455111593 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during_key_req.2455111593
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3308087874
Short name T303
Test name
Test status
Simulation time 88186546 ps
CPU time 0.86 seconds
Started Feb 08 04:00:34 PM UTC 25
Finished Feb 08 04:00:36 PM UTC 25
Peak memory 211764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308087874 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3308087874
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.4266314492
Short name T419
Test name
Test status
Simulation time 45566368355 ps
CPU time 2311.24 seconds
Started Feb 08 03:55:34 PM UTC 25
Finished Feb 08 04:34:29 PM UTC 25
Peak memory 214492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266314492 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.4266314492
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.3339438342
Short name T357
Test name
Test status
Simulation time 114400100702 ps
CPU time 1087.65 seconds
Started Feb 08 03:58:18 PM UTC 25
Finished Feb 08 04:16:38 PM UTC 25
Peak memory 391416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339438342 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.3339438342
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.2391196225
Short name T297
Test name
Test status
Simulation time 12797817434 ps
CPU time 87.05 seconds
Started Feb 08 03:57:56 PM UTC 25
Finished Feb 08 03:59:25 PM UTC 25
Peak memory 223056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391196225 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.2391196225
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1615977659
Short name T293
Test name
Test status
Simulation time 725532761 ps
CPU time 30.39 seconds
Started Feb 08 03:56:59 PM UTC 25
Finished Feb 08 03:57:31 PM UTC 25
Peak memory 301892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615977659
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_max_throughput.1615977659
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3464395129
Short name T307
Test name
Test status
Simulation time 3029502967 ps
CPU time 118.04 seconds
Started Feb 08 04:00:22 PM UTC 25
Finished Feb 08 04:02:23 PM UTC 25
Peak memory 229968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464395129 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.3464395129
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.242041844
Short name T312
Test name
Test status
Simulation time 19742450088 ps
CPU time 156.59 seconds
Started Feb 08 04:00:22 PM UTC 25
Finished Feb 08 04:03:02 PM UTC 25
Peak memory 225052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242041844 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.242041844
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2518433741
Short name T309
Test name
Test status
Simulation time 18304664378 ps
CPU time 431.5 seconds
Started Feb 08 03:55:31 PM UTC 25
Finished Feb 08 04:02:47 PM UTC 25
Peak memory 369296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518433741 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.2518433741
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1353408454
Short name T291
Test name
Test status
Simulation time 915983814 ps
CPU time 18.36 seconds
Started Feb 08 03:56:18 PM UTC 25
Finished Feb 08 03:56:37 PM UTC 25
Peak memory 212728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353408454 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.1353408454
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2581400067
Short name T314
Test name
Test status
Simulation time 80928816705 ps
CPU time 408.81 seconds
Started Feb 08 03:56:38 PM UTC 25
Finished Feb 08 04:03:32 PM UTC 25
Peak memory 212780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581400067 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access_b2b.2581400067
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1374139825
Short name T300
Test name
Test status
Simulation time 413132957 ps
CPU time 5.28 seconds
Started Feb 08 04:00:02 PM UTC 25
Finished Feb 08 04:00:28 PM UTC 25
Peak memory 213000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374139825 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1374139825
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.1946849061
Short name T340
Test name
Test status
Simulation time 13939482026 ps
CPU time 747.74 seconds
Started Feb 08 03:59:27 PM UTC 25
Finished Feb 08 04:12:03 PM UTC 25
Peak memory 381684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946849061 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1946849061
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.3280556984
Short name T289
Test name
Test status
Simulation time 778782660 ps
CPU time 14.06 seconds
Started Feb 08 03:55:27 PM UTC 25
Finished Feb 08 03:55:43 PM UTC 25
Peak memory 230008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280556984 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3280556984
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2045341381
Short name T304
Test name
Test status
Simulation time 9418125188 ps
CPU time 291.29 seconds
Started Feb 08 03:55:44 PM UTC 25
Finished Feb 08 04:00:39 PM UTC 25
Peak memory 212816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045341381 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.2045341381
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.4171520681
Short name T294
Test name
Test status
Simulation time 2836978352 ps
CPU time 21.9 seconds
Started Feb 08 03:57:32 PM UTC 25
Finished Feb 08 03:57:55 PM UTC 25
Peak memory 279484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171520681
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_throughput_w_partial_
write.4171520681
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3397502713
Short name T341
Test name
Test status
Simulation time 9893960452 ps
CPU time 553.95 seconds
Started Feb 08 04:03:02 PM UTC 25
Finished Feb 08 04:12:23 PM UTC 25
Peak memory 375540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397502713 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during_key_req.3397502713
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2647567853
Short name T319
Test name
Test status
Simulation time 32777197 ps
CPU time 1 seconds
Started Feb 08 04:04:30 PM UTC 25
Finished Feb 08 04:04:32 PM UTC 25
Peak memory 209784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647567853 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.2647567853
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1039017364
Short name T456
Test name
Test status
Simulation time 473393432052 ps
CPU time 2587.58 seconds
Started Feb 08 04:01:02 PM UTC 25
Finished Feb 08 04:44:39 PM UTC 25
Peak memory 214448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039017364 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.1039017364
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.4173575566
Short name T352
Test name
Test status
Simulation time 29140983581 ps
CPU time 725.44 seconds
Started Feb 08 04:03:21 PM UTC 25
Finished Feb 08 04:15:35 PM UTC 25
Peak memory 390040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173575566 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.4173575566
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.4193505116
Short name T318
Test name
Test status
Simulation time 16905746913 ps
CPU time 87.06 seconds
Started Feb 08 04:03:00 PM UTC 25
Finished Feb 08 04:04:29 PM UTC 25
Peak memory 212756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193505116 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.4193505116
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.4210634711
Short name T313
Test name
Test status
Simulation time 1440826935 ps
CPU time 31.55 seconds
Started Feb 08 04:02:48 PM UTC 25
Finished Feb 08 04:03:21 PM UTC 25
Peak memory 299544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210634711
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_max_throughput.4210634711
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2763019866
Short name T324
Test name
Test status
Simulation time 4993916175 ps
CPU time 175.3 seconds
Started Feb 08 04:03:55 PM UTC 25
Finished Feb 08 04:06:53 PM UTC 25
Peak memory 223160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763019866 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.2763019866
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.307723740
Short name T330
Test name
Test status
Simulation time 10714694617 ps
CPU time 287.28 seconds
Started Feb 08 04:03:41 PM UTC 25
Finished Feb 08 04:08:32 PM UTC 25
Peak memory 222924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307723740 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.307723740
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1907590734
Short name T343
Test name
Test status
Simulation time 9508854081 ps
CPU time 701.24 seconds
Started Feb 08 04:00:40 PM UTC 25
Finished Feb 08 04:12:30 PM UTC 25
Peak memory 387760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907590734 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.1907590734
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3473925094
Short name T308
Test name
Test status
Simulation time 17989068411 ps
CPU time 20.04 seconds
Started Feb 08 04:02:23 PM UTC 25
Finished Feb 08 04:02:44 PM UTC 25
Peak memory 212792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473925094 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.3473925094
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.873213847
Short name T338
Test name
Test status
Simulation time 35388827318 ps
CPU time 533.57 seconds
Started Feb 08 04:02:45 PM UTC 25
Finished Feb 08 04:11:45 PM UTC 25
Peak memory 212788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873213847 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access_b2b.873213847
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1380560786
Short name T315
Test name
Test status
Simulation time 362858691 ps
CPU time 4.83 seconds
Started Feb 08 04:03:33 PM UTC 25
Finished Feb 08 04:03:40 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380560786 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1380560786
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.4267815900
Short name T346
Test name
Test status
Simulation time 11421596518 ps
CPU time 563.2 seconds
Started Feb 08 04:03:33 PM UTC 25
Finished Feb 08 04:13:04 PM UTC 25
Peak memory 359224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267815900 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.4267815900
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.426788465
Short name T305
Test name
Test status
Simulation time 1032775726 ps
CPU time 23.18 seconds
Started Feb 08 04:00:37 PM UTC 25
Finished Feb 08 04:01:02 PM UTC 25
Peak memory 212796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426788465 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.426788465
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.4160915733
Short name T384
Test name
Test status
Simulation time 79697919762 ps
CPU time 1356.84 seconds
Started Feb 08 04:04:04 PM UTC 25
Finished Feb 08 04:26:56 PM UTC 25
Peak memory 393900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160915733 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.4160915733
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2930377377
Short name T322
Test name
Test status
Simulation time 3519453354 ps
CPU time 68.28 seconds
Started Feb 08 04:03:57 PM UTC 25
Finished Feb 08 04:05:07 PM UTC 25
Peak memory 223060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930377377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2930377377
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.3764138796
Short name T323
Test name
Test status
Simulation time 13631614562 ps
CPU time 280.07 seconds
Started Feb 08 04:02:07 PM UTC 25
Finished Feb 08 04:06:51 PM UTC 25
Peak memory 212752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764138796 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.3764138796
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2007903272
Short name T316
Test name
Test status
Simulation time 814113196 ps
CPU time 60.92 seconds
Started Feb 08 04:02:51 PM UTC 25
Finished Feb 08 04:03:54 PM UTC 25
Peak memory 369208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007903272
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_throughput_w_partial_
write.2007903272
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3906958347
Short name T372
Test name
Test status
Simulation time 71925595099 ps
CPU time 827.65 seconds
Started Feb 08 04:07:59 PM UTC 25
Finished Feb 08 04:21:57 PM UTC 25
Peak memory 389536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906958347 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during_key_req.3906958347
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3271092877
Short name T336
Test name
Test status
Simulation time 20683747 ps
CPU time 0.93 seconds
Started Feb 08 04:10:55 PM UTC 25
Finished Feb 08 04:10:57 PM UTC 25
Peak memory 212492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271092877 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3271092877
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.4041356965
Short name T390
Test name
Test status
Simulation time 230780375052 ps
CPU time 1417.55 seconds
Started Feb 08 04:05:05 PM UTC 25
Finished Feb 08 04:28:59 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041356965 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.4041356965
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3014977184
Short name T377
Test name
Test status
Simulation time 139251137072 ps
CPU time 991.9 seconds
Started Feb 08 04:08:17 PM UTC 25
Finished Feb 08 04:25:00 PM UTC 25
Peak memory 387384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014977184 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.3014977184
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1669223124
Short name T333
Test name
Test status
Simulation time 9815840227 ps
CPU time 102.15 seconds
Started Feb 08 04:07:47 PM UTC 25
Finished Feb 08 04:09:31 PM UTC 25
Peak memory 213044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669223124 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.1669223124
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1679523955
Short name T329
Test name
Test status
Simulation time 751421213 ps
CPU time 57.88 seconds
Started Feb 08 04:07:17 PM UTC 25
Finished Feb 08 04:08:16 PM UTC 25
Peak memory 350848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679523955
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_max_throughput.1679523955
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.4030276632
Short name T335
Test name
Test status
Simulation time 4805429417 ps
CPU time 88.96 seconds
Started Feb 08 04:09:24 PM UTC 25
Finished Feb 08 04:10:55 PM UTC 25
Peak memory 222968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030276632 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.4030276632
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.314563103
Short name T342
Test name
Test status
Simulation time 14020703161 ps
CPU time 222.39 seconds
Started Feb 08 04:08:39 PM UTC 25
Finished Feb 08 04:12:25 PM UTC 25
Peak memory 214844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314563103 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.314563103
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.670582516
Short name T355
Test name
Test status
Simulation time 18557245733 ps
CPU time 685.81 seconds
Started Feb 08 04:04:36 PM UTC 25
Finished Feb 08 04:16:10 PM UTC 25
Peak memory 387824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670582516 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.670582516
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3029527331
Short name T325
Test name
Test status
Simulation time 2501421152 ps
CPU time 22.77 seconds
Started Feb 08 04:06:52 PM UTC 25
Finished Feb 08 04:07:16 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029527331 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.3029527331
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.475614018
Short name T337
Test name
Test status
Simulation time 3826974895 ps
CPU time 258.07 seconds
Started Feb 08 04:06:54 PM UTC 25
Finished Feb 08 04:11:16 PM UTC 25
Peak memory 212688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475614018 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access_b2b.475614018
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.1957461836
Short name T331
Test name
Test status
Simulation time 354411268 ps
CPU time 4.86 seconds
Started Feb 08 04:08:32 PM UTC 25
Finished Feb 08 04:08:38 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957461836 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1957461836
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.4152493243
Short name T334
Test name
Test status
Simulation time 8259097677 ps
CPU time 143.98 seconds
Started Feb 08 04:08:22 PM UTC 25
Finished Feb 08 04:10:49 PM UTC 25
Peak memory 326316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152493243 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.4152493243
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2203129494
Short name T321
Test name
Test status
Simulation time 3643988393 ps
CPU time 29.97 seconds
Started Feb 08 04:04:33 PM UTC 25
Finished Feb 08 04:05:05 PM UTC 25
Peak memory 212756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203129494 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2203129494
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1759527720
Short name T587
Test name
Test status
Simulation time 718169159406 ps
CPU time 3362.98 seconds
Started Feb 08 04:10:50 PM UTC 25
Finished Feb 08 05:07:30 PM UTC 25
Peak memory 389524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759527720 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.1759527720
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1376068376
Short name T51
Test name
Test status
Simulation time 2258052984 ps
CPU time 81.83 seconds
Started Feb 08 04:09:33 PM UTC 25
Finished Feb 08 04:10:56 PM UTC 25
Peak memory 223060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376068376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1376068376
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2217028620
Short name T332
Test name
Test status
Simulation time 5414571669 ps
CPU time 251.63 seconds
Started Feb 08 04:05:07 PM UTC 25
Finished Feb 08 04:09:23 PM UTC 25
Peak memory 212820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217028620 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.2217028620
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.108175091
Short name T327
Test name
Test status
Simulation time 727457303 ps
CPU time 24.17 seconds
Started Feb 08 04:07:21 PM UTC 25
Finished Feb 08 04:07:47 PM UTC 25
Peak memory 289416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108175091
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_throughput_w_partial_w
rite.108175091
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3346420383
Short name T363
Test name
Test status
Simulation time 26534587567 ps
CPU time 358.57 seconds
Started Feb 08 04:12:38 PM UTC 25
Finished Feb 08 04:18:41 PM UTC 25
Peak memory 377560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346420383 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during_key_req.3346420383
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.3800074078
Short name T353
Test name
Test status
Simulation time 32704405 ps
CPU time 0.85 seconds
Started Feb 08 04:15:36 PM UTC 25
Finished Feb 08 04:15:38 PM UTC 25
Peak memory 211884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800074078 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.3800074078
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.3934612706
Short name T449
Test name
Test status
Simulation time 442537233465 ps
CPU time 1882.91 seconds
Started Feb 08 04:11:16 PM UTC 25
Finished Feb 08 04:42:59 PM UTC 25
Peak memory 214492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934612706 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.3934612706
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2523923232
Short name T356
Test name
Test status
Simulation time 10177340510 ps
CPU time 204.79 seconds
Started Feb 08 04:12:44 PM UTC 25
Finished Feb 08 04:16:12 PM UTC 25
Peak memory 387748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523923232 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.2523923232
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2293946912
Short name T349
Test name
Test status
Simulation time 26976848558 ps
CPU time 90.5 seconds
Started Feb 08 04:12:31 PM UTC 25
Finished Feb 08 04:14:03 PM UTC 25
Peak memory 212820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293946912 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2293946912
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2818437830
Short name T347
Test name
Test status
Simulation time 1598807078 ps
CPU time 79.14 seconds
Started Feb 08 04:12:24 PM UTC 25
Finished Feb 08 04:13:45 PM UTC 25
Peak memory 377392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818437830
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_max_throughput.2818437830
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2430698417
Short name T358
Test name
Test status
Simulation time 3183821058 ps
CPU time 156.61 seconds
Started Feb 08 04:14:04 PM UTC 25
Finished Feb 08 04:16:44 PM UTC 25
Peak memory 223008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430698417 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.2430698417
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.129685938
Short name T371
Test name
Test status
Simulation time 256130793136 ps
CPU time 473.15 seconds
Started Feb 08 04:13:54 PM UTC 25
Finished Feb 08 04:21:54 PM UTC 25
Peak memory 222988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129685938 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.129685938
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3158971501
Short name T378
Test name
Test status
Simulation time 42538981681 ps
CPU time 853.31 seconds
Started Feb 08 04:10:58 PM UTC 25
Finished Feb 08 04:25:22 PM UTC 25
Peak memory 387828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158971501 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.3158971501
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.439782765
Short name T345
Test name
Test status
Simulation time 3716620377 ps
CPU time 41.26 seconds
Started Feb 08 04:12:00 PM UTC 25
Finished Feb 08 04:12:43 PM UTC 25
Peak memory 344800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439782765 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.439782765
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1881032162
Short name T364
Test name
Test status
Simulation time 34734373523 ps
CPU time 472.4 seconds
Started Feb 08 04:12:04 PM UTC 25
Finished Feb 08 04:20:02 PM UTC 25
Peak memory 213072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881032162 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access_b2b.1881032162
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1959421898
Short name T348
Test name
Test status
Simulation time 694240035 ps
CPU time 5.71 seconds
Started Feb 08 04:13:46 PM UTC 25
Finished Feb 08 04:13:53 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959421898 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1959421898
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1459033041
Short name T395
Test name
Test status
Simulation time 18129405148 ps
CPU time 986.41 seconds
Started Feb 08 04:13:05 PM UTC 25
Finished Feb 08 04:29:42 PM UTC 25
Peak memory 393324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459033041 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1459033041
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.4077608749
Short name T339
Test name
Test status
Simulation time 2469463496 ps
CPU time 60.95 seconds
Started Feb 08 04:10:57 PM UTC 25
Finished Feb 08 04:12:00 PM UTC 25
Peak memory 379572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077608749 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.4077608749
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2065303988
Short name T576
Test name
Test status
Simulation time 72310575954 ps
CPU time 3025.73 seconds
Started Feb 08 04:14:35 PM UTC 25
Finished Feb 08 05:05:32 PM UTC 25
Peak memory 401700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065303988 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.2065303988
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1701887998
Short name T351
Test name
Test status
Simulation time 2462350749 ps
CPU time 27.51 seconds
Started Feb 08 04:14:04 PM UTC 25
Finished Feb 08 04:14:33 PM UTC 25
Peak memory 223068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701887998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1701887998
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1695071188
Short name T361
Test name
Test status
Simulation time 18964741243 ps
CPU time 375.75 seconds
Started Feb 08 04:11:46 PM UTC 25
Finished Feb 08 04:18:07 PM UTC 25
Peak memory 212848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695071188 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.1695071188
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1922725622
Short name T344
Test name
Test status
Simulation time 2424325552 ps
CPU time 10.1 seconds
Started Feb 08 04:12:26 PM UTC 25
Finished Feb 08 04:12:37 PM UTC 25
Peak memory 230072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922725622
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_throughput_w_partial_
write.1922725622
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.2389994782
Short name T392
Test name
Test status
Simulation time 13778393804 ps
CPU time 652.99 seconds
Started Feb 08 04:18:25 PM UTC 25
Finished Feb 08 04:29:26 PM UTC 25
Peak memory 385644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389994782 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during_key_req.2389994782
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3536831084
Short name T370
Test name
Test status
Simulation time 20339484 ps
CPU time 0.86 seconds
Started Feb 08 04:21:33 PM UTC 25
Finished Feb 08 04:21:35 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536831084 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3536831084
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.860819515
Short name T464
Test name
Test status
Simulation time 24933300355 ps
CPU time 1792.24 seconds
Started Feb 08 04:16:11 PM UTC 25
Finished Feb 08 04:46:22 PM UTC 25
Peak memory 214500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860819515 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.860819515
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.3078608206
Short name T379
Test name
Test status
Simulation time 60931210065 ps
CPU time 395.61 seconds
Started Feb 08 04:18:42 PM UTC 25
Finished Feb 08 04:25:23 PM UTC 25
Peak memory 387764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078608206 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.3078608206
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2239116765
Short name T365
Test name
Test status
Simulation time 15121830028 ps
CPU time 122.73 seconds
Started Feb 08 04:18:08 PM UTC 25
Finished Feb 08 04:20:13 PM UTC 25
Peak memory 212756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239116765 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.2239116765
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.564257791
Short name T360
Test name
Test status
Simulation time 2458199256 ps
CPU time 26.42 seconds
Started Feb 08 04:16:47 PM UTC 25
Finished Feb 08 04:17:15 PM UTC 25
Peak memory 289460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564257791 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_max_throughput.564257791
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.891281355
Short name T374
Test name
Test status
Simulation time 21886185708 ps
CPU time 203.07 seconds
Started Feb 08 04:20:26 PM UTC 25
Finished Feb 08 04:23:52 PM UTC 25
Peak memory 222924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891281355 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.891281355
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.4225555521
Short name T382
Test name
Test status
Simulation time 55284455447 ps
CPU time 355.61 seconds
Started Feb 08 04:20:20 PM UTC 25
Finished Feb 08 04:26:21 PM UTC 25
Peak memory 222984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225555521 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.4225555521
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2032322638
Short name T387
Test name
Test status
Simulation time 23771306814 ps
CPU time 741.33 seconds
Started Feb 08 04:16:05 PM UTC 25
Finished Feb 08 04:28:34 PM UTC 25
Peak memory 389780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032322638 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.2032322638
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.3983123128
Short name T359
Test name
Test status
Simulation time 1563813108 ps
CPU time 5.68 seconds
Started Feb 08 04:16:39 PM UTC 25
Finished Feb 08 04:16:46 PM UTC 25
Peak memory 212588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983123128 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.3983123128
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.59906225
Short name T389
Test name
Test status
Simulation time 9098407090 ps
CPU time 717.57 seconds
Started Feb 08 04:16:44 PM UTC 25
Finished Feb 08 04:28:51 PM UTC 25
Peak memory 212836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59906225 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access_b2b.59906225
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.871181856
Short name T366
Test name
Test status
Simulation time 2807602205 ps
CPU time 5.32 seconds
Started Feb 08 04:20:13 PM UTC 25
Finished Feb 08 04:20:20 PM UTC 25
Peak memory 212872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871181856 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.871181856
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.3544129916
Short name T406
Test name
Test status
Simulation time 12285033798 ps
CPU time 680.15 seconds
Started Feb 08 04:20:03 PM UTC 25
Finished Feb 08 04:31:30 PM UTC 25
Peak memory 389940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544129916 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3544129916
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.2848360752
Short name T354
Test name
Test status
Simulation time 11741088810 ps
CPU time 23.49 seconds
Started Feb 08 04:15:39 PM UTC 25
Finished Feb 08 04:16:04 PM UTC 25
Peak memory 212868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848360752 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2848360752
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.653016456
Short name T541
Test name
Test status
Simulation time 115453490462 ps
CPU time 2275.81 seconds
Started Feb 08 04:21:03 PM UTC 25
Finished Feb 08 04:59:22 PM UTC 25
Peak memory 391568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653016456 -assert n
opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.653016456
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1659244547
Short name T369
Test name
Test status
Simulation time 3689107306 ps
CPU time 51.82 seconds
Started Feb 08 04:20:39 PM UTC 25
Finished Feb 08 04:21:32 PM UTC 25
Peak memory 332732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659244547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1659244547
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2259464727
Short name T368
Test name
Test status
Simulation time 14276616234 ps
CPU time 285.7 seconds
Started Feb 08 04:16:12 PM UTC 25
Finished Feb 08 04:21:02 PM UTC 25
Peak memory 213052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259464727 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.2259464727
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1490493675
Short name T362
Test name
Test status
Simulation time 1590131962 ps
CPU time 65.8 seconds
Started Feb 08 04:17:17 PM UTC 25
Finished Feb 08 04:18:24 PM UTC 25
Peak memory 351044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490493675
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_throughput_w_partial_
write.1490493675
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1593534526
Short name T409
Test name
Test status
Simulation time 5884780875 ps
CPU time 372.05 seconds
Started Feb 08 04:25:24 PM UTC 25
Finished Feb 08 04:31:41 PM UTC 25
Peak memory 387988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593534526 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during_key_req.1593534526
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.341680567
Short name T388
Test name
Test status
Simulation time 17636035 ps
CPU time 0.9 seconds
Started Feb 08 04:28:35 PM UTC 25
Finished Feb 08 04:28:37 PM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341680567 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.341680567
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.1545063513
Short name T495
Test name
Test status
Simulation time 83947984491 ps
CPU time 1709.29 seconds
Started Feb 08 04:21:57 PM UTC 25
Finished Feb 08 04:50:45 PM UTC 25
Peak memory 214448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545063513 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.1545063513
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.1376258383
Short name T402
Test name
Test status
Simulation time 19267208551 ps
CPU time 305.01 seconds
Started Feb 08 04:25:25 PM UTC 25
Finished Feb 08 04:30:34 PM UTC 25
Peak memory 375544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376258383 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.1376258383
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.702486315
Short name T385
Test name
Test status
Simulation time 50348846268 ps
CPU time 121.24 seconds
Started Feb 08 04:25:23 PM UTC 25
Finished Feb 08 04:27:27 PM UTC 25
Peak memory 223244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702486315 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.702486315
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1505398663
Short name T380
Test name
Test status
Simulation time 1394342338 ps
CPU time 62.02 seconds
Started Feb 08 04:24:19 PM UTC 25
Finished Feb 08 04:25:24 PM UTC 25
Peak memory 363300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505398663
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_max_throughput.1505398663
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3071181467
Short name T399
Test name
Test status
Simulation time 10160956119 ps
CPU time 190 seconds
Started Feb 08 04:26:56 PM UTC 25
Finished Feb 08 04:30:10 PM UTC 25
Peak memory 223244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071181467 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.3071181467
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.4204365202
Short name T415
Test name
Test status
Simulation time 86195414326 ps
CPU time 435.98 seconds
Started Feb 08 04:26:29 PM UTC 25
Finished Feb 08 04:33:51 PM UTC 25
Peak memory 222976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204365202 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.4204365202
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.4106215328
Short name T396
Test name
Test status
Simulation time 19465657101 ps
CPU time 473.77 seconds
Started Feb 08 04:21:55 PM UTC 25
Finished Feb 08 04:29:55 PM UTC 25
Peak memory 377432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106215328 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.4106215328
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.4039622189
Short name T375
Test name
Test status
Simulation time 399095650 ps
CPU time 9.62 seconds
Started Feb 08 04:23:52 PM UTC 25
Finished Feb 08 04:24:03 PM UTC 25
Peak memory 212860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039622189 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.4039622189
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3671545803
Short name T393
Test name
Test status
Simulation time 39945813207 ps
CPU time 323.75 seconds
Started Feb 08 04:24:04 PM UTC 25
Finished Feb 08 04:29:33 PM UTC 25
Peak memory 213036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671545803 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access_b2b.3671545803
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3787019641
Short name T383
Test name
Test status
Simulation time 361198377 ps
CPU time 4.76 seconds
Started Feb 08 04:26:22 PM UTC 25
Finished Feb 08 04:26:28 PM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787019641 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3787019641
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.1644728314
Short name T459
Test name
Test status
Simulation time 183941692635 ps
CPU time 1175.38 seconds
Started Feb 08 04:25:26 PM UTC 25
Finished Feb 08 04:45:14 PM UTC 25
Peak memory 393352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644728314 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1644728314
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.2595455849
Short name T373
Test name
Test status
Simulation time 1973577066 ps
CPU time 38 seconds
Started Feb 08 04:21:36 PM UTC 25
Finished Feb 08 04:22:16 PM UTC 25
Peak memory 295740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595455849 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2595455849
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.4074763917
Short name T892
Test name
Test status
Simulation time 1039865886477 ps
CPU time 4888.46 seconds
Started Feb 08 04:27:45 PM UTC 25
Finished Feb 08 05:50:03 PM UTC 25
Peak memory 399700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074763917 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.4074763917
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3888264033
Short name T391
Test name
Test status
Simulation time 1968579901 ps
CPU time 102.87 seconds
Started Feb 08 04:27:28 PM UTC 25
Finished Feb 08 04:29:13 PM UTC 25
Peak memory 365112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888264033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3888264033
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3241059855
Short name T386
Test name
Test status
Simulation time 5156280867 ps
CPU time 323.31 seconds
Started Feb 08 04:22:16 PM UTC 25
Finished Feb 08 04:27:44 PM UTC 25
Peak memory 212848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241059855 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.3241059855
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.661046712
Short name T381
Test name
Test status
Simulation time 1623152961 ps
CPU time 21.96 seconds
Started Feb 08 04:25:02 PM UTC 25
Finished Feb 08 04:25:25 PM UTC 25
Peak memory 275048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661046712
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_throughput_w_partial_w
rite.661046712
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2809382840
Short name T41
Test name
Test status
Simulation time 14126742330 ps
CPU time 717.88 seconds
Started Feb 08 03:00:02 PM UTC 25
Finished Feb 08 03:12:29 PM UTC 25
Peak memory 387776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809382840 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_key_req.2809382840
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2844171177
Short name T15
Test name
Test status
Simulation time 25182211 ps
CPU time 0.95 seconds
Started Feb 08 03:01:14 PM UTC 25
Finished Feb 08 03:01:16 PM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844171177 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.2844171177
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.2384794354
Short name T189
Test name
Test status
Simulation time 211835370462 ps
CPU time 1506.78 seconds
Started Feb 08 02:57:33 PM UTC 25
Finished Feb 08 03:22:58 PM UTC 25
Peak memory 214300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384794354 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.2384794354
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.1737037129
Short name T142
Test name
Test status
Simulation time 56138271846 ps
CPU time 995.32 seconds
Started Feb 08 03:00:23 PM UTC 25
Finished Feb 08 03:17:10 PM UTC 25
Peak memory 389732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737037129 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.1737037129
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3862613525
Short name T8
Test name
Test status
Simulation time 14414502157 ps
CPU time 66.18 seconds
Started Feb 08 02:59:37 PM UTC 25
Finished Feb 08 03:00:45 PM UTC 25
Peak memory 227104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862613525 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.3862613525
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2923071379
Short name T154
Test name
Test status
Simulation time 2612607364 ps
CPU time 36.43 seconds
Started Feb 08 02:58:27 PM UTC 25
Finished Feb 08 02:59:05 PM UTC 25
Peak memory 320256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923071379
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max_throughput.2923071379
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3475387784
Short name T85
Test name
Test status
Simulation time 4521577452 ps
CPU time 184.25 seconds
Started Feb 08 03:00:36 PM UTC 25
Finished Feb 08 03:03:44 PM UTC 25
Peak memory 223020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475387784 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.3475387784
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1440332469
Short name T170
Test name
Test status
Simulation time 25637645545 ps
CPU time 917.33 seconds
Started Feb 08 02:57:33 PM UTC 25
Finished Feb 08 03:13:01 PM UTC 25
Peak memory 385776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440332469 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.1440332469
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3221970278
Short name T151
Test name
Test status
Simulation time 352519431 ps
CPU time 5.18 seconds
Started Feb 08 02:58:17 PM UTC 25
Finished Feb 08 02:58:24 PM UTC 25
Peak memory 212404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221970278 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.3221970278
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1672857349
Short name T107
Test name
Test status
Simulation time 25365858063 ps
CPU time 535.22 seconds
Started Feb 08 02:58:24 PM UTC 25
Finished Feb 08 03:07:27 PM UTC 25
Peak memory 212984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672857349 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access_b2b.1672857349
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2008791447
Short name T29
Test name
Test status
Simulation time 361078380 ps
CPU time 4.61 seconds
Started Feb 08 03:00:23 PM UTC 25
Finished Feb 08 03:00:29 PM UTC 25
Peak memory 212616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008791447 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2008791447
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1137281902
Short name T18
Test name
Test status
Simulation time 13698286926 ps
CPU time 379.78 seconds
Started Feb 08 03:00:23 PM UTC 25
Finished Feb 08 03:06:48 PM UTC 25
Peak memory 379628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137281902 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1137281902
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2844531714
Short name T17
Test name
Test status
Simulation time 711871618 ps
CPU time 3.81 seconds
Started Feb 08 03:01:09 PM UTC 25
Finished Feb 08 03:01:14 PM UTC 25
Peak memory 248768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844531714 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2844531714
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.4104520392
Short name T78
Test name
Test status
Simulation time 1329567920 ps
CPU time 43.17 seconds
Started Feb 08 02:57:32 PM UTC 25
Finished Feb 08 02:58:17 PM UTC 25
Peak memory 351000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104520392 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.4104520392
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.8091918
Short name T25
Test name
Test status
Simulation time 637554671 ps
CPU time 21.79 seconds
Started Feb 08 03:00:45 PM UTC 25
Finished Feb 08 03:01:08 PM UTC 25
Peak memory 223164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8091918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.8091918
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2415816550
Short name T106
Test name
Test status
Simulation time 4857331431 ps
CPU time 388.48 seconds
Started Feb 08 02:57:34 PM UTC 25
Finished Feb 08 03:04:08 PM UTC 25
Peak memory 212712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415816550 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.2415816550
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4101793508
Short name T155
Test name
Test status
Simulation time 808604265 ps
CPU time 52.43 seconds
Started Feb 08 02:59:07 PM UTC 25
Finished Feb 08 03:00:01 PM UTC 25
Peak memory 352824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101793508
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_throughput_w_partial_w
rite.4101793508
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.1875802251
Short name T461
Test name
Test status
Simulation time 13101622489 ps
CPU time 939.26 seconds
Started Feb 08 04:29:56 PM UTC 25
Finished Feb 08 04:45:45 PM UTC 25
Peak memory 389468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875802251 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during_key_req.1875802251
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.4082437262
Short name T405
Test name
Test status
Simulation time 13875506 ps
CPU time 0.85 seconds
Started Feb 08 04:30:55 PM UTC 25
Finished Feb 08 04:30:57 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082437262 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.4082437262
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.1601764341
Short name T512
Test name
Test status
Simulation time 240118465256 ps
CPU time 1491.31 seconds
Started Feb 08 04:29:00 PM UTC 25
Finished Feb 08 04:54:08 PM UTC 25
Peak memory 214460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601764341 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.1601764341
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.1305852750
Short name T401
Test name
Test status
Simulation time 1717848702 ps
CPU time 24.21 seconds
Started Feb 08 04:29:57 PM UTC 25
Finished Feb 08 04:30:22 PM UTC 25
Peak memory 212888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305852750 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.1305852750
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2659256972
Short name T404
Test name
Test status
Simulation time 37034357439 ps
CPU time 57.64 seconds
Started Feb 08 04:29:56 PM UTC 25
Finished Feb 08 04:30:55 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659256972 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.2659256972
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1047446938
Short name T403
Test name
Test status
Simulation time 2548520023 ps
CPU time 68.86 seconds
Started Feb 08 04:29:38 PM UTC 25
Finished Feb 08 04:30:49 PM UTC 25
Peak memory 383748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047446938
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_max_throughput.1047446938
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3187013094
Short name T414
Test name
Test status
Simulation time 20827784848 ps
CPU time 199.72 seconds
Started Feb 08 04:30:23 PM UTC 25
Finished Feb 08 04:33:46 PM UTC 25
Peak memory 223024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187013094 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.3187013094
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3536855748
Short name T413
Test name
Test status
Simulation time 21110383599 ps
CPU time 190.47 seconds
Started Feb 08 04:30:17 PM UTC 25
Finished Feb 08 04:33:31 PM UTC 25
Peak memory 222920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536855748 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.3536855748
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3598653446
Short name T417
Test name
Test status
Simulation time 16434742928 ps
CPU time 321.32 seconds
Started Feb 08 04:28:52 PM UTC 25
Finished Feb 08 04:34:18 PM UTC 25
Peak memory 390104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598653446 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.3598653446
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.890104721
Short name T394
Test name
Test status
Simulation time 2853003107 ps
CPU time 10.14 seconds
Started Feb 08 04:29:26 PM UTC 25
Finished Feb 08 04:29:38 PM UTC 25
Peak memory 212928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890104721 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.890104721
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1230702389
Short name T411
Test name
Test status
Simulation time 9560461904 ps
CPU time 156.14 seconds
Started Feb 08 04:29:33 PM UTC 25
Finished Feb 08 04:32:12 PM UTC 25
Peak memory 212716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230702389 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access_b2b.1230702389
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.697676401
Short name T400
Test name
Test status
Simulation time 364290977 ps
CPU time 4.72 seconds
Started Feb 08 04:30:10 PM UTC 25
Finished Feb 08 04:30:16 PM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697676401 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.697676401
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.3380108000
Short name T487
Test name
Test status
Simulation time 21937425719 ps
CPU time 1157.51 seconds
Started Feb 08 04:30:09 PM UTC 25
Finished Feb 08 04:49:38 PM UTC 25
Peak memory 391580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380108000 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3380108000
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3926879451
Short name T398
Test name
Test status
Simulation time 2525207185 ps
CPU time 88.08 seconds
Started Feb 08 04:28:38 PM UTC 25
Finished Feb 08 04:30:08 PM UTC 25
Peak memory 371460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926879451 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3926879451
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1316192878
Short name T479
Test name
Test status
Simulation time 193684722245 ps
CPU time 1061.75 seconds
Started Feb 08 04:30:50 PM UTC 25
Finished Feb 08 04:48:43 PM UTC 25
Peak memory 387356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316192878 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.1316192878
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1707716493
Short name T407
Test name
Test status
Simulation time 1805915212 ps
CPU time 55.15 seconds
Started Feb 08 04:30:35 PM UTC 25
Finished Feb 08 04:31:32 PM UTC 25
Peak memory 328284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707716493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1707716493
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2338173463
Short name T425
Test name
Test status
Simulation time 20901298483 ps
CPU time 397.22 seconds
Started Feb 08 04:29:13 PM UTC 25
Finished Feb 08 04:35:56 PM UTC 25
Peak memory 212768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338173463 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.2338173463
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3851454984
Short name T397
Test name
Test status
Simulation time 2827242391 ps
CPU time 11.62 seconds
Started Feb 08 04:29:43 PM UTC 25
Finished Feb 08 04:29:55 PM UTC 25
Peak memory 230056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851454984
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_throughput_w_partial_
write.3851454984
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.4268818553
Short name T436
Test name
Test status
Simulation time 21384765467 ps
CPU time 398.99 seconds
Started Feb 08 04:33:47 PM UTC 25
Finished Feb 08 04:40:31 PM UTC 25
Peak memory 383656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268818553 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during_key_req.4268818553
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.264496142
Short name T423
Test name
Test status
Simulation time 11781374 ps
CPU time 0.85 seconds
Started Feb 08 04:35:29 PM UTC 25
Finished Feb 08 04:35:31 PM UTC 25
Peak memory 211696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264496142 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.264496142
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.1058007079
Short name T458
Test name
Test status
Simulation time 72155484850 ps
CPU time 807.14 seconds
Started Feb 08 04:31:33 PM UTC 25
Finished Feb 08 04:45:09 PM UTC 25
Peak memory 212848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058007079 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.1058007079
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.3993026649
Short name T448
Test name
Test status
Simulation time 41576556202 ps
CPU time 536.4 seconds
Started Feb 08 04:33:52 PM UTC 25
Finished Feb 08 04:42:56 PM UTC 25
Peak memory 389744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993026649 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.3993026649
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1523006655
Short name T422
Test name
Test status
Simulation time 16052851913 ps
CPU time 114.84 seconds
Started Feb 08 04:33:31 PM UTC 25
Finished Feb 08 04:35:28 PM UTC 25
Peak memory 227028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523006655 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.1523006655
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1463003018
Short name T412
Test name
Test status
Simulation time 1418455517 ps
CPU time 13.35 seconds
Started Feb 08 04:32:13 PM UTC 25
Finished Feb 08 04:32:28 PM UTC 25
Peak memory 236228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463003018
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_max_throughput.1463003018
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2074138514
Short name T426
Test name
Test status
Simulation time 2504453382 ps
CPU time 95.78 seconds
Started Feb 08 04:34:30 PM UTC 25
Finished Feb 08 04:36:08 PM UTC 25
Peak memory 223244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074138514 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.2074138514
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1284632688
Short name T428
Test name
Test status
Simulation time 1977677921 ps
CPU time 139.22 seconds
Started Feb 08 04:34:25 PM UTC 25
Finished Feb 08 04:36:47 PM UTC 25
Peak memory 222888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284632688 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.1284632688
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.814259398
Short name T440
Test name
Test status
Simulation time 22067805413 ps
CPU time 579.96 seconds
Started Feb 08 04:31:32 PM UTC 25
Finished Feb 08 04:41:18 PM UTC 25
Peak memory 389704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814259398 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.814259398
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2271289004
Short name T410
Test name
Test status
Simulation time 2043565090 ps
CPU time 17.52 seconds
Started Feb 08 04:31:42 PM UTC 25
Finished Feb 08 04:32:01 PM UTC 25
Peak memory 212588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271289004 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.2271289004
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.1641555260
Short name T439
Test name
Test status
Simulation time 20358382763 ps
CPU time 545.71 seconds
Started Feb 08 04:32:02 PM UTC 25
Finished Feb 08 04:41:14 PM UTC 25
Peak memory 212728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641555260 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access_b2b.1641555260
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.3521850667
Short name T418
Test name
Test status
Simulation time 353913235 ps
CPU time 4.39 seconds
Started Feb 08 04:34:19 PM UTC 25
Finished Feb 08 04:34:24 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521850667 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3521850667
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.773103343
Short name T424
Test name
Test status
Simulation time 2077827192 ps
CPU time 99.98 seconds
Started Feb 08 04:33:57 PM UTC 25
Finished Feb 08 04:35:39 PM UTC 25
Peak memory 367088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773103343 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.773103343
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.202243816
Short name T408
Test name
Test status
Simulation time 774221297 ps
CPU time 33.57 seconds
Started Feb 08 04:30:58 PM UTC 25
Finished Feb 08 04:31:33 PM UTC 25
Peak memory 295516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202243816 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.202243816
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.939010888
Short name T944
Test name
Test status
Simulation time 459448784558 ps
CPU time 8564.29 seconds
Started Feb 08 04:34:56 PM UTC 25
Finished Feb 08 06:59:05 PM UTC 25
Peak memory 389396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939010888 -assert n
opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.939010888
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.180531482
Short name T421
Test name
Test status
Simulation time 3078358875 ps
CPU time 13.85 seconds
Started Feb 08 04:34:40 PM UTC 25
Finished Feb 08 04:34:55 PM UTC 25
Peak memory 223188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180531482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.180531482
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.312658428
Short name T432
Test name
Test status
Simulation time 5060584533 ps
CPU time 358.83 seconds
Started Feb 08 04:31:35 PM UTC 25
Finished Feb 08 04:37:38 PM UTC 25
Peak memory 212980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312658428 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.312658428
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.181049734
Short name T416
Test name
Test status
Simulation time 808674958 ps
CPU time 85.8 seconds
Started Feb 08 04:32:28 PM UTC 25
Finished Feb 08 04:33:56 PM UTC 25
Peak memory 381500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181049734
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_throughput_w_partial_w
rite.181049734
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.924104294
Short name T467
Test name
Test status
Simulation time 20658137558 ps
CPU time 557.28 seconds
Started Feb 08 04:37:29 PM UTC 25
Finished Feb 08 04:46:54 PM UTC 25
Peak memory 383700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924104294 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during_key_req.924104294
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2607246859
Short name T438
Test name
Test status
Simulation time 36183804 ps
CPU time 0.91 seconds
Started Feb 08 04:41:11 PM UTC 25
Finished Feb 08 04:41:13 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607246859 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.2607246859
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.1326010555
Short name T695
Test name
Test status
Simulation time 110300064388 ps
CPU time 2740.89 seconds
Started Feb 08 04:35:57 PM UTC 25
Finished Feb 08 05:22:08 PM UTC 25
Peak memory 214452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326010555 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.1326010555
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.853739645
Short name T441
Test name
Test status
Simulation time 20917095585 ps
CPU time 221.75 seconds
Started Feb 08 04:37:39 PM UTC 25
Finished Feb 08 04:41:25 PM UTC 25
Peak memory 330648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853739645 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.853739645
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.563910557
Short name T434
Test name
Test status
Simulation time 64455245011 ps
CPU time 79.91 seconds
Started Feb 08 04:37:14 PM UTC 25
Finished Feb 08 04:38:36 PM UTC 25
Peak memory 212764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563910557 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.563910557
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1142370098
Short name T433
Test name
Test status
Simulation time 3164581086 ps
CPU time 63.89 seconds
Started Feb 08 04:36:47 PM UTC 25
Finished Feb 08 04:37:53 PM UTC 25
Peak memory 369308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142370098
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_max_throughput.1142370098
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1087795558
Short name T447
Test name
Test status
Simulation time 18724784558 ps
CPU time 173.66 seconds
Started Feb 08 04:39:53 PM UTC 25
Finished Feb 08 04:42:50 PM UTC 25
Peak memory 223024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087795558 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.1087795558
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1893068974
Short name T452
Test name
Test status
Simulation time 30717767678 ps
CPU time 292.22 seconds
Started Feb 08 04:38:45 PM UTC 25
Finished Feb 08 04:43:41 PM UTC 25
Peak memory 223048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893068974 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.1893068974
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.1964065219
Short name T486
Test name
Test status
Simulation time 17492298803 ps
CPU time 821.8 seconds
Started Feb 08 04:35:39 PM UTC 25
Finished Feb 08 04:49:30 PM UTC 25
Peak memory 383636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964065219 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.1964065219
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.807790327
Short name T431
Test name
Test status
Simulation time 793699896 ps
CPU time 41.54 seconds
Started Feb 08 04:36:45 PM UTC 25
Finished Feb 08 04:37:28 PM UTC 25
Peak memory 310044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807790327 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.807790327
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.3258041831
Short name T474
Test name
Test status
Simulation time 24710252052 ps
CPU time 659.32 seconds
Started Feb 08 04:36:46 PM UTC 25
Finished Feb 08 04:47:53 PM UTC 25
Peak memory 212736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258041831 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access_b2b.3258041831
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3214989818
Short name T435
Test name
Test status
Simulation time 353516407 ps
CPU time 5.14 seconds
Started Feb 08 04:38:37 PM UTC 25
Finished Feb 08 04:38:43 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214989818 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3214989818
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.2244390286
Short name T491
Test name
Test status
Simulation time 13354317207 ps
CPU time 730.46 seconds
Started Feb 08 04:37:53 PM UTC 25
Finished Feb 08 04:50:12 PM UTC 25
Peak memory 379828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244390286 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2244390286
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.577587643
Short name T429
Test name
Test status
Simulation time 3935255321 ps
CPU time 85.05 seconds
Started Feb 08 04:35:32 PM UTC 25
Finished Feb 08 04:36:59 PM UTC 25
Peak memory 379876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577587643 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.577587643
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1569971750
Short name T711
Test name
Test status
Simulation time 194805041844 ps
CPU time 2632.48 seconds
Started Feb 08 04:40:32 PM UTC 25
Finished Feb 08 05:24:51 PM UTC 25
Peak memory 393620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569971750 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.1569971750
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.291866210
Short name T442
Test name
Test status
Simulation time 1751375935 ps
CPU time 84.92 seconds
Started Feb 08 04:40:11 PM UTC 25
Finished Feb 08 04:41:38 PM UTC 25
Peak memory 222868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291866210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.291866210
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2726756606
Short name T437
Test name
Test status
Simulation time 4276336610 ps
CPU time 296.58 seconds
Started Feb 08 04:36:09 PM UTC 25
Finished Feb 08 04:41:10 PM UTC 25
Peak memory 212780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726756606 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.2726756606
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3039367223
Short name T430
Test name
Test status
Simulation time 2809733354 ps
CPU time 11.66 seconds
Started Feb 08 04:37:00 PM UTC 25
Finished Feb 08 04:37:13 PM UTC 25
Peak memory 229072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039367223
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_throughput_w_partial_
write.3039367223
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2357544062
Short name T543
Test name
Test status
Simulation time 140619527280 ps
CPU time 1045.3 seconds
Started Feb 08 04:42:05 PM UTC 25
Finished Feb 08 04:59:41 PM UTC 25
Peak memory 387880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357544062 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during_key_req.2357544062
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.4292836537
Short name T454
Test name
Test status
Simulation time 67960855 ps
CPU time 0.93 seconds
Started Feb 08 04:44:18 PM UTC 25
Finished Feb 08 04:44:20 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292836537 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.4292836537
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1960204184
Short name T759
Test name
Test status
Simulation time 317246177459 ps
CPU time 2909.48 seconds
Started Feb 08 04:41:19 PM UTC 25
Finished Feb 08 05:30:19 PM UTC 25
Peak memory 214500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960204184 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.1960204184
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.524446932
Short name T531
Test name
Test status
Simulation time 7757883223 ps
CPU time 862.2 seconds
Started Feb 08 04:42:51 PM UTC 25
Finished Feb 08 04:57:23 PM UTC 25
Peak memory 383728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524446932 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.524446932
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2957923116
Short name T451
Test name
Test status
Simulation time 14353238871 ps
CPU time 94.29 seconds
Started Feb 08 04:42:02 PM UTC 25
Finished Feb 08 04:43:38 PM UTC 25
Peak memory 227352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957923116 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.2957923116
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.558046874
Short name T446
Test name
Test status
Simulation time 738080879 ps
CPU time 15.7 seconds
Started Feb 08 04:41:46 PM UTC 25
Finished Feb 08 04:42:03 PM UTC 25
Peak memory 269116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558046874 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_max_throughput.558046874
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.138140777
Short name T463
Test name
Test status
Simulation time 1597154406 ps
CPU time 134.73 seconds
Started Feb 08 04:43:39 PM UTC 25
Finished Feb 08 04:45:57 PM UTC 25
Peak memory 222792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138140777 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.138140777
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2520144515
Short name T468
Test name
Test status
Simulation time 8967830178 ps
CPU time 222.84 seconds
Started Feb 08 04:43:07 PM UTC 25
Finished Feb 08 04:46:54 PM UTC 25
Peak memory 222940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520144515 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2520144515
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.452450685
Short name T555
Test name
Test status
Simulation time 32703100927 ps
CPU time 1204.11 seconds
Started Feb 08 04:41:15 PM UTC 25
Finished Feb 08 05:01:33 PM UTC 25
Peak memory 389504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452450685 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.452450685
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.36518327
Short name T444
Test name
Test status
Simulation time 1941987434 ps
CPU time 10.76 seconds
Started Feb 08 04:41:38 PM UTC 25
Finished Feb 08 04:41:50 PM UTC 25
Peak memory 212560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36518327 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.36518327
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.777036438
Short name T488
Test name
Test status
Simulation time 296002852333 ps
CPU time 470.67 seconds
Started Feb 08 04:41:43 PM UTC 25
Finished Feb 08 04:49:40 PM UTC 25
Peak memory 212712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777036438 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access_b2b.777036438
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.791231624
Short name T450
Test name
Test status
Simulation time 2413158940 ps
CPU time 5.5 seconds
Started Feb 08 04:43:00 PM UTC 25
Finished Feb 08 04:43:07 PM UTC 25
Peak memory 212788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791231624 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.791231624
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.1981688428
Short name T536
Test name
Test status
Simulation time 26129527534 ps
CPU time 909.72 seconds
Started Feb 08 04:42:56 PM UTC 25
Finished Feb 08 04:58:15 PM UTC 25
Peak memory 389776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981688428 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1981688428
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.364990298
Short name T443
Test name
Test status
Simulation time 6698859404 ps
CPU time 30.81 seconds
Started Feb 08 04:41:14 PM UTC 25
Finished Feb 08 04:41:46 PM UTC 25
Peak memory 212696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364990298 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.364990298
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2971790640
Short name T915
Test name
Test status
Simulation time 144276657480 ps
CPU time 4409.94 seconds
Started Feb 08 04:44:06 PM UTC 25
Finished Feb 08 05:58:21 PM UTC 25
Peak memory 391460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971790640 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.2971790640
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1113781013
Short name T453
Test name
Test status
Simulation time 749729168 ps
CPU time 33.89 seconds
Started Feb 08 04:43:41 PM UTC 25
Finished Feb 08 04:44:17 PM UTC 25
Peak memory 223032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113781013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1113781013
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1702247889
Short name T457
Test name
Test status
Simulation time 3376708271 ps
CPU time 217.66 seconds
Started Feb 08 04:41:25 PM UTC 25
Finished Feb 08 04:45:06 PM UTC 25
Peak memory 212772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702247889 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.1702247889
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.958340150
Short name T445
Test name
Test status
Simulation time 699872563 ps
CPU time 8.97 seconds
Started Feb 08 04:41:51 PM UTC 25
Finished Feb 08 04:42:01 PM UTC 25
Peak memory 223108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958340150
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_throughput_w_partial_w
rite.958340150
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3591746913
Short name T498
Test name
Test status
Simulation time 6354093485 ps
CPU time 335.93 seconds
Started Feb 08 04:45:47 PM UTC 25
Finished Feb 08 04:51:27 PM UTC 25
Peak memory 385692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591746913 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during_key_req.3591746913
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3014014544
Short name T470
Test name
Test status
Simulation time 14240769 ps
CPU time 0.89 seconds
Started Feb 08 04:46:56 PM UTC 25
Finished Feb 08 04:46:58 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014014544 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3014014544
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.2398787092
Short name T710
Test name
Test status
Simulation time 132571202755 ps
CPU time 2389.19 seconds
Started Feb 08 04:44:34 PM UTC 25
Finished Feb 08 05:24:49 PM UTC 25
Peak memory 214432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398787092 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.2398787092
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.1278823189
Short name T492
Test name
Test status
Simulation time 3847824933 ps
CPU time 260.19 seconds
Started Feb 08 04:45:58 PM UTC 25
Finished Feb 08 04:50:21 PM UTC 25
Peak memory 358988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278823189 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.1278823189
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2860937998
Short name T466
Test name
Test status
Simulation time 12826056315 ps
CPU time 59.32 seconds
Started Feb 08 04:45:46 PM UTC 25
Finished Feb 08 04:46:47 PM UTC 25
Peak memory 212692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860937998 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.2860937998
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.4145732755
Short name T462
Test name
Test status
Simulation time 2732083968 ps
CPU time 29.63 seconds
Started Feb 08 04:45:15 PM UTC 25
Finished Feb 08 04:45:46 PM UTC 25
Peak memory 287484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145732755
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_max_throughput.4145732755
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2449435358
Short name T477
Test name
Test status
Simulation time 4019649131 ps
CPU time 79 seconds
Started Feb 08 04:46:48 PM UTC 25
Finished Feb 08 04:48:09 PM UTC 25
Peak memory 223020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449435358 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.2449435358
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1300487822
Short name T482
Test name
Test status
Simulation time 2102204761 ps
CPU time 160.99 seconds
Started Feb 08 04:46:30 PM UTC 25
Finished Feb 08 04:49:14 PM UTC 25
Peak memory 222788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300487822 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.1300487822
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3253975413
Short name T472
Test name
Test status
Simulation time 2193887569 ps
CPU time 186.74 seconds
Started Feb 08 04:44:26 PM UTC 25
Finished Feb 08 04:47:36 PM UTC 25
Peak memory 387740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253975413 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.3253975413
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1300093464
Short name T460
Test name
Test status
Simulation time 1813039724 ps
CPU time 29.64 seconds
Started Feb 08 04:45:07 PM UTC 25
Finished Feb 08 04:45:39 PM UTC 25
Peak memory 212916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300093464 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.1300093464
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.495705192
Short name T490
Test name
Test status
Simulation time 6384168304 ps
CPU time 275.61 seconds
Started Feb 08 04:45:10 PM UTC 25
Finished Feb 08 04:49:50 PM UTC 25
Peak memory 212716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495705192 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access_b2b.495705192
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.3722342876
Short name T465
Test name
Test status
Simulation time 678114088 ps
CPU time 4.69 seconds
Started Feb 08 04:46:23 PM UTC 25
Finished Feb 08 04:46:29 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722342876 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3722342876
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.208891690
Short name T475
Test name
Test status
Simulation time 1565852116 ps
CPU time 107.34 seconds
Started Feb 08 04:46:10 PM UTC 25
Finished Feb 08 04:48:00 PM UTC 25
Peak memory 342552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208891690 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.208891690
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.2270397679
Short name T455
Test name
Test status
Simulation time 1092334076 ps
CPU time 11.59 seconds
Started Feb 08 04:44:21 PM UTC 25
Finished Feb 08 04:44:34 PM UTC 25
Peak memory 219640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270397679 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2270397679
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.1855412940
Short name T874
Test name
Test status
Simulation time 1005887542450 ps
CPU time 3606.97 seconds
Started Feb 08 04:46:55 PM UTC 25
Finished Feb 08 05:47:39 PM UTC 25
Peak memory 402092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855412940 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.1855412940
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3502624170
Short name T471
Test name
Test status
Simulation time 2168499437 ps
CPU time 25.73 seconds
Started Feb 08 04:46:55 PM UTC 25
Finished Feb 08 04:47:22 PM UTC 25
Peak memory 222940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502624170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3502624170
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3223928689
Short name T484
Test name
Test status
Simulation time 3193504527 ps
CPU time 280.61 seconds
Started Feb 08 04:44:39 PM UTC 25
Finished Feb 08 04:49:24 PM UTC 25
Peak memory 212720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223928689 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.3223928689
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1098038898
Short name T469
Test name
Test status
Simulation time 825876122 ps
CPU time 73.39 seconds
Started Feb 08 04:45:40 PM UTC 25
Finished Feb 08 04:46:55 PM UTC 25
Peak memory 381820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098038898
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_throughput_w_partial_
write.1098038898
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1037691012
Short name T621
Test name
Test status
Simulation time 113636896969 ps
CPU time 1369.61 seconds
Started Feb 08 04:48:09 PM UTC 25
Finished Feb 08 05:11:12 PM UTC 25
Peak memory 391504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037691012 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during_key_req.1037691012
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1613638518
Short name T485
Test name
Test status
Simulation time 27495672 ps
CPU time 0.93 seconds
Started Feb 08 04:49:25 PM UTC 25
Finished Feb 08 04:49:27 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613638518 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1613638518
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.533557792
Short name T579
Test name
Test status
Simulation time 173297740084 ps
CPU time 1109.6 seconds
Started Feb 08 04:47:22 PM UTC 25
Finished Feb 08 05:06:05 PM UTC 25
Peak memory 213172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533557792 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.533557792
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.3188748754
Short name T559
Test name
Test status
Simulation time 12090552703 ps
CPU time 825.41 seconds
Started Feb 08 04:48:23 PM UTC 25
Finished Feb 08 05:02:18 PM UTC 25
Peak memory 375516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188748754 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.3188748754
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.1830923504
Short name T478
Test name
Test status
Simulation time 8659204076 ps
CPU time 21.12 seconds
Started Feb 08 04:48:01 PM UTC 25
Finished Feb 08 04:48:23 PM UTC 25
Peak memory 227096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830923504 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.1830923504
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.234319723
Short name T481
Test name
Test status
Simulation time 1077881766 ps
CPU time 64.34 seconds
Started Feb 08 04:47:54 PM UTC 25
Finished Feb 08 04:49:00 PM UTC 25
Peak memory 356908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234319723 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_max_throughput.234319723
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1778324584
Short name T503
Test name
Test status
Simulation time 10058674682 ps
CPU time 180.01 seconds
Started Feb 08 04:49:01 PM UTC 25
Finished Feb 08 04:52:04 PM UTC 25
Peak memory 223008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778324584 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.1778324584
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1653090270
Short name T499
Test name
Test status
Simulation time 27733640360 ps
CPU time 172.36 seconds
Started Feb 08 04:48:51 PM UTC 25
Finished Feb 08 04:51:46 PM UTC 25
Peak memory 223048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653090270 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.1653090270
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3451171966
Short name T560
Test name
Test status
Simulation time 6471449364 ps
CPU time 910.09 seconds
Started Feb 08 04:47:03 PM UTC 25
Finished Feb 08 05:02:24 PM UTC 25
Peak memory 387724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451171966 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.3451171966
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.896632962
Short name T473
Test name
Test status
Simulation time 989626136 ps
CPU time 9.99 seconds
Started Feb 08 04:47:37 PM UTC 25
Finished Feb 08 04:47:48 PM UTC 25
Peak memory 212620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896632962 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.896632962
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1326940537
Short name T514
Test name
Test status
Simulation time 6299286226 ps
CPU time 402.61 seconds
Started Feb 08 04:47:49 PM UTC 25
Finished Feb 08 04:54:37 PM UTC 25
Peak memory 212660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326940537 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access_b2b.1326940537
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3409506414
Short name T480
Test name
Test status
Simulation time 1400127608 ps
CPU time 5.39 seconds
Started Feb 08 04:48:44 PM UTC 25
Finished Feb 08 04:48:50 PM UTC 25
Peak memory 212996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409506414 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3409506414
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.1567261925
Short name T524
Test name
Test status
Simulation time 4974948418 ps
CPU time 475.02 seconds
Started Feb 08 04:48:24 PM UTC 25
Finished Feb 08 04:56:25 PM UTC 25
Peak memory 385752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567261925 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1567261925
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1656335315
Short name T476
Test name
Test status
Simulation time 4851920073 ps
CPU time 59.87 seconds
Started Feb 08 04:46:59 PM UTC 25
Finished Feb 08 04:48:00 PM UTC 25
Peak memory 369596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656335315 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1656335315
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.2894331568
Short name T745
Test name
Test status
Simulation time 147594423227 ps
CPU time 2315.81 seconds
Started Feb 08 04:49:22 PM UTC 25
Finished Feb 08 05:28:22 PM UTC 25
Peak memory 391404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894331568 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.2894331568
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3679478540
Short name T111
Test name
Test status
Simulation time 1586402803 ps
CPU time 38.02 seconds
Started Feb 08 04:49:15 PM UTC 25
Finished Feb 08 04:49:55 PM UTC 25
Peak memory 222872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679478540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3679478540
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.556560092
Short name T509
Test name
Test status
Simulation time 10024991483 ps
CPU time 345.76 seconds
Started Feb 08 04:47:34 PM UTC 25
Finished Feb 08 04:53:24 PM UTC 25
Peak memory 212756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556560092 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.556560092
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2728015103
Short name T483
Test name
Test status
Simulation time 795923938 ps
CPU time 78.68 seconds
Started Feb 08 04:48:01 PM UTC 25
Finished Feb 08 04:49:21 PM UTC 25
Peak memory 355136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728015103
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_throughput_w_partial_
write.2728015103
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.761724013
Short name T515
Test name
Test status
Simulation time 16493783454 ps
CPU time 254.35 seconds
Started Feb 08 04:50:25 PM UTC 25
Finished Feb 08 04:54:44 PM UTC 25
Peak memory 377556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761724013 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during_key_req.761724013
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.1394574662
Short name T500
Test name
Test status
Simulation time 32385754 ps
CPU time 1.02 seconds
Started Feb 08 04:51:47 PM UTC 25
Finished Feb 08 04:51:49 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394574662 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.1394574662
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.492043251
Short name T640
Test name
Test status
Simulation time 57678144122 ps
CPU time 1447.04 seconds
Started Feb 08 04:49:39 PM UTC 25
Finished Feb 08 05:14:03 PM UTC 25
Peak memory 214452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492043251 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.492043251
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.4161796252
Short name T591
Test name
Test status
Simulation time 85843734887 ps
CPU time 1027.52 seconds
Started Feb 08 04:50:29 PM UTC 25
Finished Feb 08 05:07:48 PM UTC 25
Peak memory 387832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161796252 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.4161796252
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.4282159634
Short name T502
Test name
Test status
Simulation time 8056911576 ps
CPU time 98.08 seconds
Started Feb 08 04:50:22 PM UTC 25
Finished Feb 08 04:52:02 PM UTC 25
Peak memory 212776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282159634 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.4282159634
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.4002127719
Short name T494
Test name
Test status
Simulation time 2954006834 ps
CPU time 31.46 seconds
Started Feb 08 04:49:56 PM UTC 25
Finished Feb 08 04:50:28 PM UTC 25
Peak memory 287388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002127719
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_max_throughput.4002127719
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2939108110
Short name T504
Test name
Test status
Simulation time 1386798360 ps
CPU time 81.26 seconds
Started Feb 08 04:50:55 PM UTC 25
Finished Feb 08 04:52:19 PM UTC 25
Peak memory 222952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939108110 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.2939108110
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.2284241009
Short name T537
Test name
Test status
Simulation time 82827302497 ps
CPU time 448.52 seconds
Started Feb 08 04:50:49 PM UTC 25
Finished Feb 08 04:58:24 PM UTC 25
Peak memory 222920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284241009 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.2284241009
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3962519157
Short name T546
Test name
Test status
Simulation time 143817696716 ps
CPU time 617.17 seconds
Started Feb 08 04:49:31 PM UTC 25
Finished Feb 08 04:59:55 PM UTC 25
Peak memory 381604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962519157 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3962519157
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.78994632
Short name T493
Test name
Test status
Simulation time 1711532389 ps
CPU time 32.92 seconds
Started Feb 08 04:49:49 PM UTC 25
Finished Feb 08 04:50:24 PM UTC 25
Peak memory 212724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78994632 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.78994632
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1590175637
Short name T508
Test name
Test status
Simulation time 15936714359 ps
CPU time 203.6 seconds
Started Feb 08 04:49:51 PM UTC 25
Finished Feb 08 04:53:18 PM UTC 25
Peak memory 212920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590175637 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access_b2b.1590175637
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3229624080
Short name T497
Test name
Test status
Simulation time 364141326 ps
CPU time 4.74 seconds
Started Feb 08 04:50:48 PM UTC 25
Finished Feb 08 04:50:54 PM UTC 25
Peak memory 212996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229624080 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3229624080
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.1896658241
Short name T611
Test name
Test status
Simulation time 124740157813 ps
CPU time 1100.91 seconds
Started Feb 08 04:50:46 PM UTC 25
Finished Feb 08 05:09:19 PM UTC 25
Peak memory 389804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896658241 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1896658241
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.1108686583
Short name T489
Test name
Test status
Simulation time 880604273 ps
CPU time 19.15 seconds
Started Feb 08 04:49:28 PM UTC 25
Finished Feb 08 04:49:49 PM UTC 25
Peak memory 212924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108686583 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1108686583
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3313313972
Short name T930
Test name
Test status
Simulation time 79539010441 ps
CPU time 4786.52 seconds
Started Feb 08 04:51:28 PM UTC 25
Finished Feb 08 06:12:02 PM UTC 25
Peak memory 393520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313313972 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.3313313972
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.70583060
Short name T501
Test name
Test status
Simulation time 7196435765 ps
CPU time 55.05 seconds
Started Feb 08 04:51:03 PM UTC 25
Finished Feb 08 04:51:59 PM UTC 25
Peak memory 223056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70583060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.70583060
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.560936259
Short name T521
Test name
Test status
Simulation time 4349258163 ps
CPU time 364.73 seconds
Started Feb 08 04:49:41 PM UTC 25
Finished Feb 08 04:55:51 PM UTC 25
Peak memory 212984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560936259 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.560936259
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1075463549
Short name T496
Test name
Test status
Simulation time 1557493840 ps
CPU time 32.59 seconds
Started Feb 08 04:50:14 PM UTC 25
Finished Feb 08 04:50:48 PM UTC 25
Peak memory 303936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075463549
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_throughput_w_partial_
write.1075463549
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.4043194976
Short name T540
Test name
Test status
Simulation time 25516478787 ps
CPU time 352.82 seconds
Started Feb 08 04:53:19 PM UTC 25
Finished Feb 08 04:59:17 PM UTC 25
Peak memory 381608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043194976 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during_key_req.4043194976
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.4166956930
Short name T516
Test name
Test status
Simulation time 34944128 ps
CPU time 0.88 seconds
Started Feb 08 04:54:49 PM UTC 25
Finished Feb 08 04:54:51 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166956930 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.4166956930
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.3791809796
Short name T683
Test name
Test status
Simulation time 40830637417 ps
CPU time 1683.15 seconds
Started Feb 08 04:52:03 PM UTC 25
Finished Feb 08 05:20:26 PM UTC 25
Peak memory 214504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791809796 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.3791809796
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.2326335271
Short name T586
Test name
Test status
Simulation time 16331884246 ps
CPU time 834.48 seconds
Started Feb 08 04:53:25 PM UTC 25
Finished Feb 08 05:07:29 PM UTC 25
Peak memory 387732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326335271 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.2326335271
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.938725075
Short name T511
Test name
Test status
Simulation time 5569424264 ps
CPU time 44.22 seconds
Started Feb 08 04:53:16 PM UTC 25
Finished Feb 08 04:54:02 PM UTC 25
Peak memory 222996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938725075 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.938725075
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2003222633
Short name T507
Test name
Test status
Simulation time 7105873484 ps
CPU time 27.71 seconds
Started Feb 08 04:52:47 PM UTC 25
Finished Feb 08 04:53:16 PM UTC 25
Peak memory 287384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003222633
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_max_throughput.2003222633
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.397970082
Short name T520
Test name
Test status
Simulation time 9681459139 ps
CPU time 98.07 seconds
Started Feb 08 04:54:10 PM UTC 25
Finished Feb 08 04:55:50 PM UTC 25
Peak memory 230088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397970082 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.397970082
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2330491553
Short name T542
Test name
Test status
Simulation time 16421640939 ps
CPU time 317.32 seconds
Started Feb 08 04:54:08 PM UTC 25
Finished Feb 08 04:59:31 PM UTC 25
Peak memory 222928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330491553 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.2330491553
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.3413068769
Short name T519
Test name
Test status
Simulation time 5699882009 ps
CPU time 219.79 seconds
Started Feb 08 04:52:00 PM UTC 25
Finished Feb 08 04:55:43 PM UTC 25
Peak memory 338796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413068769 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.3413068769
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3182463622
Short name T506
Test name
Test status
Simulation time 11636910984 ps
CPU time 24.83 seconds
Started Feb 08 04:52:19 PM UTC 25
Finished Feb 08 04:52:46 PM UTC 25
Peak memory 212952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182463622 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.3182463622
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2281068556
Short name T562
Test name
Test status
Simulation time 43995949463 ps
CPU time 589.58 seconds
Started Feb 08 04:52:35 PM UTC 25
Finished Feb 08 05:02:32 PM UTC 25
Peak memory 212816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281068556 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access_b2b.2281068556
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.693324603
Short name T513
Test name
Test status
Simulation time 356999046 ps
CPU time 5.02 seconds
Started Feb 08 04:54:02 PM UTC 25
Finished Feb 08 04:54:09 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693324603 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.693324603
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.499536893
Short name T545
Test name
Test status
Simulation time 4867031504 ps
CPU time 380.14 seconds
Started Feb 08 04:53:30 PM UTC 25
Finished Feb 08 04:59:55 PM UTC 25
Peak memory 383932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499536893 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.499536893
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.3460436818
Short name T505
Test name
Test status
Simulation time 796198533 ps
CPU time 43.34 seconds
Started Feb 08 04:51:50 PM UTC 25
Finished Feb 08 04:52:35 PM UTC 25
Peak memory 305792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460436818 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3460436818
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.585558825
Short name T934
Test name
Test status
Simulation time 508873378390 ps
CPU time 4997.84 seconds
Started Feb 08 04:54:45 PM UTC 25
Finished Feb 08 06:18:54 PM UTC 25
Peak memory 391460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585558825 -assert n
opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.585558825
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1234350339
Short name T517
Test name
Test status
Simulation time 1110066735 ps
CPU time 44.1 seconds
Started Feb 08 04:54:38 PM UTC 25
Finished Feb 08 04:55:24 PM UTC 25
Peak memory 223032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234350339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.1234350339
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2243986551
Short name T528
Test name
Test status
Simulation time 10246416558 ps
CPU time 287.66 seconds
Started Feb 08 04:52:04 PM UTC 25
Finished Feb 08 04:56:56 PM UTC 25
Peak memory 213008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243986551 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2243986551
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3982799406
Short name T510
Test name
Test status
Simulation time 2970315492 ps
CPU time 34.71 seconds
Started Feb 08 04:52:53 PM UTC 25
Finished Feb 08 04:53:29 PM UTC 25
Peak memory 312036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982799406
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_throughput_w_partial_
write.3982799406
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2603254766
Short name T554
Test name
Test status
Simulation time 7867242168 ps
CPU time 287.65 seconds
Started Feb 08 04:56:25 PM UTC 25
Finished Feb 08 05:01:17 PM UTC 25
Peak memory 387756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603254766 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during_key_req.2603254766
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3820249638
Short name T532
Test name
Test status
Simulation time 15893844 ps
CPU time 0.99 seconds
Started Feb 08 04:57:24 PM UTC 25
Finished Feb 08 04:57:27 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820249638 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3820249638
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.1636770435
Short name T707
Test name
Test status
Simulation time 23999418812 ps
CPU time 1730.62 seconds
Started Feb 08 04:55:30 PM UTC 25
Finished Feb 08 05:24:39 PM UTC 25
Peak memory 214504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636770435 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.1636770435
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.3661923815
Short name T596
Test name
Test status
Simulation time 28727961001 ps
CPU time 676.82 seconds
Started Feb 08 04:56:41 PM UTC 25
Finished Feb 08 05:08:06 PM UTC 25
Peak memory 387720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661923815 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.3661923815
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3828143348
Short name T530
Test name
Test status
Simulation time 5449270888 ps
CPU time 49.28 seconds
Started Feb 08 04:56:18 PM UTC 25
Finished Feb 08 04:57:09 PM UTC 25
Peak memory 222996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828143348 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.3828143348
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2171204607
Short name T525
Test name
Test status
Simulation time 745331609 ps
CPU time 46.67 seconds
Started Feb 08 04:55:52 PM UTC 25
Finished Feb 08 04:56:40 PM UTC 25
Peak memory 313916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171204607
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_max_throughput.2171204607
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2577716793
Short name T535
Test name
Test status
Simulation time 3676962135 ps
CPU time 66.62 seconds
Started Feb 08 04:57:02 PM UTC 25
Finished Feb 08 04:58:10 PM UTC 25
Peak memory 230288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577716793 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.2577716793
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.928424194
Short name T551
Test name
Test status
Simulation time 28830106752 ps
CPU time 205.56 seconds
Started Feb 08 04:56:57 PM UTC 25
Finished Feb 08 05:00:26 PM UTC 25
Peak memory 223056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928424194 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.928424194
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.732656468
Short name T533
Test name
Test status
Simulation time 15197451926 ps
CPU time 141.09 seconds
Started Feb 08 04:55:24 PM UTC 25
Finished Feb 08 04:57:48 PM UTC 25
Peak memory 336468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732656468 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.732656468
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.4100261914
Short name T522
Test name
Test status
Simulation time 729806596 ps
CPU time 10.58 seconds
Started Feb 08 04:55:44 PM UTC 25
Finished Feb 08 04:55:56 PM UTC 25
Peak memory 229844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100261914 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.4100261914
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.994195098
Short name T564
Test name
Test status
Simulation time 5408553586 ps
CPU time 420.41 seconds
Started Feb 08 04:55:51 PM UTC 25
Finished Feb 08 05:02:57 PM UTC 25
Peak memory 212788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994195098 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access_b2b.994195098
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2008616960
Short name T529
Test name
Test status
Simulation time 360298870 ps
CPU time 4.74 seconds
Started Feb 08 04:56:55 PM UTC 25
Finished Feb 08 04:57:01 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008616960 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2008616960
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.1459198173
Short name T588
Test name
Test status
Simulation time 69555707917 ps
CPU time 632.33 seconds
Started Feb 08 04:56:52 PM UTC 25
Finished Feb 08 05:07:31 PM UTC 25
Peak memory 387828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459198173 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1459198173
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.1528514125
Short name T518
Test name
Test status
Simulation time 2992312510 ps
CPU time 42.9 seconds
Started Feb 08 04:54:52 PM UTC 25
Finished Feb 08 04:55:37 PM UTC 25
Peak memory 324240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528514125 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1528514125
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3422987559
Short name T943
Test name
Test status
Simulation time 273782064889 ps
CPU time 6921.21 seconds
Started Feb 08 04:57:23 PM UTC 25
Finished Feb 08 06:53:56 PM UTC 25
Peak memory 391516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422987559 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.3422987559
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3980835419
Short name T112
Test name
Test status
Simulation time 286081775 ps
CPU time 13.52 seconds
Started Feb 08 04:57:11 PM UTC 25
Finished Feb 08 04:57:26 PM UTC 25
Peak memory 222884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980835419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.3980835419
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1735100084
Short name T553
Test name
Test status
Simulation time 4816956222 ps
CPU time 326.61 seconds
Started Feb 08 04:55:38 PM UTC 25
Finished Feb 08 05:01:10 PM UTC 25
Peak memory 213044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735100084 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.1735100084
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.755350555
Short name T523
Test name
Test status
Simulation time 725220676 ps
CPU time 19.14 seconds
Started Feb 08 04:55:57 PM UTC 25
Finished Feb 08 04:56:18 PM UTC 25
Peak memory 281220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755350555
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_throughput_w_partial_w
rite.755350555
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.685609704
Short name T550
Test name
Test status
Simulation time 4608770815 ps
CPU time 65.2 seconds
Started Feb 08 04:59:17 PM UTC 25
Finished Feb 08 05:00:24 PM UTC 25
Peak memory 216884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685609704 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during_key_req.685609704
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2360063814
Short name T549
Test name
Test status
Simulation time 17666258 ps
CPU time 0.98 seconds
Started Feb 08 05:00:22 PM UTC 25
Finished Feb 08 05:00:24 PM UTC 25
Peak memory 212492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360063814 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.2360063814
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.9428254
Short name T682
Test name
Test status
Simulation time 131837281097 ps
CPU time 1317.84 seconds
Started Feb 08 04:57:49 PM UTC 25
Finished Feb 08 05:20:01 PM UTC 25
Peak memory 214456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9428254 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.9428254
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.2585475259
Short name T662
Test name
Test status
Simulation time 22366722153 ps
CPU time 1071.96 seconds
Started Feb 08 04:59:23 PM UTC 25
Finished Feb 08 05:17:27 PM UTC 25
Peak memory 389756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585475259 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.2585475259
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.3064493123
Short name T548
Test name
Test status
Simulation time 24404093021 ps
CPU time 89.94 seconds
Started Feb 08 04:58:49 PM UTC 25
Finished Feb 08 05:00:21 PM UTC 25
Peak memory 212764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064493123 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.3064493123
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.849413580
Short name T538
Test name
Test status
Simulation time 704065763 ps
CPU time 14.73 seconds
Started Feb 08 04:58:25 PM UTC 25
Finished Feb 08 04:58:41 PM UTC 25
Peak memory 246588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849413580 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_max_throughput.849413580
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1272160605
Short name T565
Test name
Test status
Simulation time 19080635068 ps
CPU time 178.61 seconds
Started Feb 08 04:59:56 PM UTC 25
Finished Feb 08 05:02:57 PM UTC 25
Peak memory 230012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272160605 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.1272160605
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3813979114
Short name T573
Test name
Test status
Simulation time 5253796951 ps
CPU time 312.19 seconds
Started Feb 08 04:59:50 PM UTC 25
Finished Feb 08 05:05:06 PM UTC 25
Peak memory 223180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813979114 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.3813979114
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.3450107102
Short name T605
Test name
Test status
Simulation time 63330448555 ps
CPU time 680.93 seconds
Started Feb 08 04:57:28 PM UTC 25
Finished Feb 08 05:08:57 PM UTC 25
Peak memory 375700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450107102 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.3450107102
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.490328937
Short name T539
Test name
Test status
Simulation time 3716909086 ps
CPU time 35.53 seconds
Started Feb 08 04:58:11 PM UTC 25
Finished Feb 08 04:58:48 PM UTC 25
Peak memory 283544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490328937 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.490328937
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.3487596975
Short name T580
Test name
Test status
Simulation time 68461787738 ps
CPU time 466.36 seconds
Started Feb 08 04:58:15 PM UTC 25
Finished Feb 08 05:06:07 PM UTC 25
Peak memory 213012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487596975 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access_b2b.3487596975
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.335770303
Short name T544
Test name
Test status
Simulation time 690165729 ps
CPU time 4.66 seconds
Started Feb 08 04:59:43 PM UTC 25
Finished Feb 08 04:59:48 PM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335770303 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.335770303
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1827266472
Short name T602
Test name
Test status
Simulation time 9749597202 ps
CPU time 549.01 seconds
Started Feb 08 04:59:31 PM UTC 25
Finished Feb 08 05:08:47 PM UTC 25
Peak memory 365200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827266472 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1827266472
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.1458359028
Short name T534
Test name
Test status
Simulation time 1693983948 ps
CPU time 28.04 seconds
Started Feb 08 04:57:27 PM UTC 25
Finished Feb 08 04:57:56 PM UTC 25
Peak memory 212884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458359028 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1458359028
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.782383128
Short name T940
Test name
Test status
Simulation time 1022390745251 ps
CPU time 5815.9 seconds
Started Feb 08 04:59:57 PM UTC 25
Finished Feb 08 06:37:53 PM UTC 25
Peak memory 389544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782383128 -assert n
opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.782383128
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2725514250
Short name T113
Test name
Test status
Simulation time 8618310231 ps
CPU time 132.98 seconds
Started Feb 08 04:59:57 PM UTC 25
Finished Feb 08 05:02:12 PM UTC 25
Peak memory 383732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725514250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.2725514250
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.266071518
Short name T572
Test name
Test status
Simulation time 10938985045 ps
CPU time 416.01 seconds
Started Feb 08 04:57:57 PM UTC 25
Finished Feb 08 05:04:59 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266071518 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.266071518
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3715391250
Short name T547
Test name
Test status
Simulation time 1536576357 ps
CPU time 71.71 seconds
Started Feb 08 04:58:42 PM UTC 25
Finished Feb 08 04:59:56 PM UTC 25
Peak memory 361064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715391250
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_throughput_w_partial_
write.3715391250
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1795308926
Short name T88
Test name
Test status
Simulation time 22402116679 ps
CPU time 604.38 seconds
Started Feb 08 03:04:55 PM UTC 25
Finished Feb 08 03:15:06 PM UTC 25
Peak memory 383664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795308926 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_key_req.1795308926
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1646222515
Short name T14
Test name
Test status
Simulation time 27752108 ps
CPU time 0.84 seconds
Started Feb 08 03:08:00 PM UTC 25
Finished Feb 08 03:08:02 PM UTC 25
Peak memory 211452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646222515 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1646222515
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.3533840492
Short name T169
Test name
Test status
Simulation time 34462803135 ps
CPU time 608.48 seconds
Started Feb 08 03:02:42 PM UTC 25
Finished Feb 08 03:12:58 PM UTC 25
Peak memory 212720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533840492 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.3533840492
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.921533528
Short name T147
Test name
Test status
Simulation time 6258098561 ps
CPU time 148.09 seconds
Started Feb 08 03:05:28 PM UTC 25
Finished Feb 08 03:07:59 PM UTC 25
Peak memory 365304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921533528 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.921533528
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.3014100162
Short name T68
Test name
Test status
Simulation time 11009095606 ps
CPU time 104.6 seconds
Started Feb 08 03:04:33 PM UTC 25
Finished Feb 08 03:06:19 PM UTC 25
Peak memory 222980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014100162 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.3014100162
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.390645435
Short name T161
Test name
Test status
Simulation time 1560253436 ps
CPU time 76.15 seconds
Started Feb 08 03:04:09 PM UTC 25
Finished Feb 08 03:05:27 PM UTC 25
Peak memory 377404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390645435 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max_throughput.390645435
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2336088044
Short name T48
Test name
Test status
Simulation time 38605572325 ps
CPU time 194.94 seconds
Started Feb 08 03:07:12 PM UTC 25
Finished Feb 08 03:10:31 PM UTC 25
Peak memory 222904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336088044 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.2336088044
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3522816825
Short name T52
Test name
Test status
Simulation time 81140720612 ps
CPU time 428.91 seconds
Started Feb 08 03:06:55 PM UTC 25
Finished Feb 08 03:14:10 PM UTC 25
Peak memory 223248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522816825 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.3522816825
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.829238794
Short name T168
Test name
Test status
Simulation time 8256451357 ps
CPU time 646.23 seconds
Started Feb 08 03:01:17 PM UTC 25
Finished Feb 08 03:12:12 PM UTC 25
Peak memory 389872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829238794 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.829238794
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3579049007
Short name T158
Test name
Test status
Simulation time 472983258 ps
CPU time 31.27 seconds
Started Feb 08 03:03:40 PM UTC 25
Finished Feb 08 03:04:13 PM UTC 25
Peak memory 305672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579049007 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.3579049007
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.678577854
Short name T173
Test name
Test status
Simulation time 93500006604 ps
CPU time 631.73 seconds
Started Feb 08 03:03:44 PM UTC 25
Finished Feb 08 03:14:24 PM UTC 25
Peak memory 212760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678577854 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access_b2b.678577854
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1959387393
Short name T162
Test name
Test status
Simulation time 1408135868 ps
CPU time 4.61 seconds
Started Feb 08 03:06:48 PM UTC 25
Finished Feb 08 03:06:54 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959387393 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1959387393
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.1045875067
Short name T153
Test name
Test status
Simulation time 15255023185 ps
CPU time 772.72 seconds
Started Feb 08 03:06:20 PM UTC 25
Finished Feb 08 03:19:22 PM UTC 25
Peak memory 373416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045875067 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1045875067
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1888681643
Short name T30
Test name
Test status
Simulation time 232674420 ps
CPU time 4.11 seconds
Started Feb 08 03:07:54 PM UTC 25
Finished Feb 08 03:07:59 PM UTC 25
Peak memory 248704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888681643 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.1888681643
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1403553932
Short name T157
Test name
Test status
Simulation time 5965461431 ps
CPU time 83.57 seconds
Started Feb 08 03:01:15 PM UTC 25
Finished Feb 08 03:02:41 PM UTC 25
Peak memory 377516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403553932 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1403553932
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1036154470
Short name T129
Test name
Test status
Simulation time 466682728725 ps
CPU time 2835.56 seconds
Started Feb 08 03:07:28 PM UTC 25
Finished Feb 08 03:55:16 PM UTC 25
Peak memory 393544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036154470 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.1036154470
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.209070357
Short name T47
Test name
Test status
Simulation time 8363714498 ps
CPU time 174.7 seconds
Started Feb 08 03:07:20 PM UTC 25
Finished Feb 08 03:10:17 PM UTC 25
Peak memory 393972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209070357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.209070357
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1008569609
Short name T108
Test name
Test status
Simulation time 19506037211 ps
CPU time 422.54 seconds
Started Feb 08 03:03:37 PM UTC 25
Finished Feb 08 03:10:46 PM UTC 25
Peak memory 212716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008569609 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.1008569609
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3079371808
Short name T160
Test name
Test status
Simulation time 3043143839 ps
CPU time 37.27 seconds
Started Feb 08 03:04:14 PM UTC 25
Finished Feb 08 03:04:53 PM UTC 25
Peak memory 304060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079371808
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_throughput_w_partial_w
rite.3079371808
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1970172228
Short name T652
Test name
Test status
Simulation time 25576191953 ps
CPU time 839.42 seconds
Started Feb 08 05:02:13 PM UTC 25
Finished Feb 08 05:16:21 PM UTC 25
Peak memory 387764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970172228 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during_key_req.1970172228
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.1241831900
Short name T566
Test name
Test status
Simulation time 30337925 ps
CPU time 0.86 seconds
Started Feb 08 05:02:58 PM UTC 25
Finished Feb 08 05:03:01 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241831900 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.1241831900
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.2572974964
Short name T859
Test name
Test status
Simulation time 110426871151 ps
CPU time 2657.11 seconds
Started Feb 08 05:00:26 PM UTC 25
Finished Feb 08 05:45:10 PM UTC 25
Peak memory 214456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572974964 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.2572974964
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.3565636728
Short name T569
Test name
Test status
Simulation time 2477779480 ps
CPU time 130.23 seconds
Started Feb 08 05:02:16 PM UTC 25
Finished Feb 08 05:04:28 PM UTC 25
Peak memory 357040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565636728 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.3565636728
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3152667040
Short name T568
Test name
Test status
Simulation time 23039246748 ps
CPU time 124.05 seconds
Started Feb 08 05:01:44 PM UTC 25
Finished Feb 08 05:03:50 PM UTC 25
Peak memory 212688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152667040 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.3152667040
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.847050172
Short name T563
Test name
Test status
Simulation time 3154090438 ps
CPU time 80.71 seconds
Started Feb 08 05:01:34 PM UTC 25
Finished Feb 08 05:02:56 PM UTC 25
Peak memory 371352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847050172 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_max_throughput.847050172
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.525931218
Short name T89
Test name
Test status
Simulation time 5522028044 ps
CPU time 195.71 seconds
Started Feb 08 05:02:33 PM UTC 25
Finished Feb 08 05:05:52 PM UTC 25
Peak memory 223212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525931218 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.525931218
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.302070295
Short name T582
Test name
Test status
Simulation time 15731126752 ps
CPU time 219.49 seconds
Started Feb 08 05:02:32 PM UTC 25
Finished Feb 08 05:06:15 PM UTC 25
Peak memory 222956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302070295 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.302070295
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3811427630
Short name T730
Test name
Test status
Simulation time 102445298735 ps
CPU time 1589.08 seconds
Started Feb 08 05:00:25 PM UTC 25
Finished Feb 08 05:27:10 PM UTC 25
Peak memory 391588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811427630 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.3811427630
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3815627097
Short name T556
Test name
Test status
Simulation time 1892155634 ps
CPU time 23.15 seconds
Started Feb 08 05:01:10 PM UTC 25
Finished Feb 08 05:01:35 PM UTC 25
Peak memory 266840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815627097 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.3815627097
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.569516554
Short name T618
Test name
Test status
Simulation time 66339386295 ps
CPU time 542.81 seconds
Started Feb 08 05:01:18 PM UTC 25
Finished Feb 08 05:10:28 PM UTC 25
Peak memory 213008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569516554 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access_b2b.569516554
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2398336533
Short name T561
Test name
Test status
Simulation time 721214143 ps
CPU time 4.63 seconds
Started Feb 08 05:02:25 PM UTC 25
Finished Feb 08 05:02:31 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398336533 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2398336533
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.430390327
Short name T692
Test name
Test status
Simulation time 105620927978 ps
CPU time 1173.09 seconds
Started Feb 08 05:02:19 PM UTC 25
Finished Feb 08 05:22:04 PM UTC 25
Peak memory 385724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430390327 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.430390327
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.4020756833
Short name T552
Test name
Test status
Simulation time 3314499653 ps
CPU time 9.53 seconds
Started Feb 08 05:00:25 PM UTC 25
Finished Feb 08 05:00:36 PM UTC 25
Peak memory 240376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020756833 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.4020756833
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1840648154
Short name T904
Test name
Test status
Simulation time 21442087742 ps
CPU time 3116.39 seconds
Started Feb 08 05:02:57 PM UTC 25
Finished Feb 08 05:55:26 PM UTC 25
Peak memory 399784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840648154 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.1840648154
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1758272123
Short name T571
Test name
Test status
Simulation time 2770169404 ps
CPU time 115.29 seconds
Started Feb 08 05:02:57 PM UTC 25
Finished Feb 08 05:04:55 PM UTC 25
Peak memory 265124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758272123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1758272123
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1741613127
Short name T592
Test name
Test status
Simulation time 19201618068 ps
CPU time 427.52 seconds
Started Feb 08 05:00:36 PM UTC 25
Finished Feb 08 05:07:49 PM UTC 25
Peak memory 213012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741613127 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.1741613127
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1945014237
Short name T558
Test name
Test status
Simulation time 742201239 ps
CPU time 38.32 seconds
Started Feb 08 05:01:36 PM UTC 25
Finished Feb 08 05:02:15 PM UTC 25
Peak memory 311868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945014237
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_throughput_w_partial_
write.1945014237
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.794966831
Short name T624
Test name
Test status
Simulation time 29364833713 ps
CPU time 379.67 seconds
Started Feb 08 05:05:07 PM UTC 25
Finished Feb 08 05:11:32 PM UTC 25
Peak memory 373420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794966831 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during_key_req.794966831
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3888098813
Short name T581
Test name
Test status
Simulation time 38925051 ps
CPU time 0.87 seconds
Started Feb 08 05:06:08 PM UTC 25
Finished Feb 08 05:06:10 PM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888098813 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3888098813
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.3596496926
Short name T827
Test name
Test status
Simulation time 90141122848 ps
CPU time 2210.12 seconds
Started Feb 08 05:03:51 PM UTC 25
Finished Feb 08 05:41:05 PM UTC 25
Peak memory 214396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596496926 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.3596496926
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2090758480
Short name T613
Test name
Test status
Simulation time 5285773409 ps
CPU time 254.06 seconds
Started Feb 08 05:05:15 PM UTC 25
Finished Feb 08 05:09:32 PM UTC 25
Peak memory 387760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090758480 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.2090758480
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.385824297
Short name T578
Test name
Test status
Simulation time 4577732776 ps
CPU time 47.14 seconds
Started Feb 08 05:05:04 PM UTC 25
Finished Feb 08 05:05:52 PM UTC 25
Peak memory 222916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385824297 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.385824297
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2605016530
Short name T574
Test name
Test status
Simulation time 3107903354 ps
CPU time 16.43 seconds
Started Feb 08 05:04:56 PM UTC 25
Finished Feb 08 05:05:14 PM UTC 25
Peak memory 246500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605016530
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_max_throughput.2605016530
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.592190465
Short name T603
Test name
Test status
Simulation time 3155004887 ps
CPU time 173.72 seconds
Started Feb 08 05:05:53 PM UTC 25
Finished Feb 08 05:08:50 PM UTC 25
Peak memory 222952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592190465 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.592190465
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2178885780
Short name T598
Test name
Test status
Simulation time 28755142168 ps
CPU time 153.64 seconds
Started Feb 08 05:05:40 PM UTC 25
Finished Feb 08 05:08:16 PM UTC 25
Peak memory 223048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178885780 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.2178885780
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.3159700147
Short name T619
Test name
Test status
Simulation time 23436430908 ps
CPU time 441.03 seconds
Started Feb 08 05:03:18 PM UTC 25
Finished Feb 08 05:10:45 PM UTC 25
Peak memory 385684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159700147 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.3159700147
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.458377452
Short name T570
Test name
Test status
Simulation time 458083187 ps
CPU time 14.4 seconds
Started Feb 08 05:04:39 PM UTC 25
Finished Feb 08 05:04:55 PM UTC 25
Peak memory 212564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458377452 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.458377452
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.2209640090
Short name T622
Test name
Test status
Simulation time 19620386964 ps
CPU time 375.86 seconds
Started Feb 08 05:04:55 PM UTC 25
Finished Feb 08 05:11:16 PM UTC 25
Peak memory 212708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209640090 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access_b2b.2209640090
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2646031634
Short name T577
Test name
Test status
Simulation time 1246971557 ps
CPU time 5.46 seconds
Started Feb 08 05:05:33 PM UTC 25
Finished Feb 08 05:05:40 PM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646031634 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2646031634
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.486335684
Short name T657
Test name
Test status
Simulation time 43979990149 ps
CPU time 665.17 seconds
Started Feb 08 05:05:27 PM UTC 25
Finished Feb 08 05:16:40 PM UTC 25
Peak memory 385776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486335684 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.486335684
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.3244123162
Short name T567
Test name
Test status
Simulation time 10007786228 ps
CPU time 13.7 seconds
Started Feb 08 05:03:01 PM UTC 25
Finished Feb 08 05:03:16 PM UTC 25
Peak memory 212988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244123162 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3244123162
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3545655813
Short name T584
Test name
Test status
Simulation time 2759961832 ps
CPU time 42.04 seconds
Started Feb 08 05:05:53 PM UTC 25
Finished Feb 08 05:06:37 PM UTC 25
Peak memory 223268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545655813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3545655813
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.2772546291
Short name T601
Test name
Test status
Simulation time 3119268384 ps
CPU time 252.02 seconds
Started Feb 08 05:04:29 PM UTC 25
Finished Feb 08 05:08:45 PM UTC 25
Peak memory 212816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772546291 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.2772546291
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3418907417
Short name T575
Test name
Test status
Simulation time 1496408125 ps
CPU time 25.66 seconds
Started Feb 08 05:04:59 PM UTC 25
Finished Feb 08 05:05:26 PM UTC 25
Peak memory 301620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418907417
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_throughput_w_partial_
write.3418907417
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2518005371
Short name T647
Test name
Test status
Simulation time 18379780512 ps
CPU time 482.8 seconds
Started Feb 08 05:07:26 PM UTC 25
Finished Feb 08 05:15:35 PM UTC 25
Peak memory 385688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518005371 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during_key_req.2518005371
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.3132299644
Short name T594
Test name
Test status
Simulation time 12608912 ps
CPU time 1.05 seconds
Started Feb 08 05:07:52 PM UTC 25
Finished Feb 08 05:07:54 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132299644 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.3132299644
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.3782335976
Short name T658
Test name
Test status
Simulation time 39059409214 ps
CPU time 632.15 seconds
Started Feb 08 05:06:22 PM UTC 25
Finished Feb 08 05:17:02 PM UTC 25
Peak memory 213048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782335976 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.3782335976
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2023978036
Short name T716
Test name
Test status
Simulation time 31634321710 ps
CPU time 1095.66 seconds
Started Feb 08 05:07:30 PM UTC 25
Finished Feb 08 05:25:56 PM UTC 25
Peak memory 367348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023978036 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.2023978036
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3510299043
Short name T608
Test name
Test status
Simulation time 24767254557 ps
CPU time 110.65 seconds
Started Feb 08 05:07:15 PM UTC 25
Finished Feb 08 05:09:08 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510299043 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.3510299043
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3117405472
Short name T585
Test name
Test status
Simulation time 11111481866 ps
CPU time 16.96 seconds
Started Feb 08 05:06:51 PM UTC 25
Finished Feb 08 05:07:10 PM UTC 25
Peak memory 223012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117405472
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_max_throughput.3117405472
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2168497300
Short name T607
Test name
Test status
Simulation time 962322568 ps
CPU time 77.61 seconds
Started Feb 08 05:07:44 PM UTC 25
Finished Feb 08 05:09:04 PM UTC 25
Peak memory 222840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168497300 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.2168497300
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1720414598
Short name T641
Test name
Test status
Simulation time 108823622379 ps
CPU time 384.84 seconds
Started Feb 08 05:07:39 PM UTC 25
Finished Feb 08 05:14:09 PM UTC 25
Peak memory 222984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720414598 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.1720414598
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2588710866
Short name T626
Test name
Test status
Simulation time 43195113570 ps
CPU time 320.18 seconds
Started Feb 08 05:06:17 PM UTC 25
Finished Feb 08 05:11:41 PM UTC 25
Peak memory 346800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588710866 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.2588710866
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.596123315
Short name T593
Test name
Test status
Simulation time 504101125 ps
CPU time 77.35 seconds
Started Feb 08 05:06:31 PM UTC 25
Finished Feb 08 05:07:50 PM UTC 25
Peak memory 359224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596123315 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.596123315
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2046490097
Short name T638
Test name
Test status
Simulation time 58794305260 ps
CPU time 418.99 seconds
Started Feb 08 05:06:38 PM UTC 25
Finished Feb 08 05:13:42 PM UTC 25
Peak memory 212732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046490097 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access_b2b.2046490097
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.292433439
Short name T589
Test name
Test status
Simulation time 1463227052 ps
CPU time 4.78 seconds
Started Feb 08 05:07:32 PM UTC 25
Finished Feb 08 05:07:38 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292433439 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.292433439
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.1988067183
Short name T599
Test name
Test status
Simulation time 4310912822 ps
CPU time 45.04 seconds
Started Feb 08 05:07:31 PM UTC 25
Finished Feb 08 05:08:18 PM UTC 25
Peak memory 291504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988067183 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1988067183
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.1365711411
Short name T583
Test name
Test status
Simulation time 1688396715 ps
CPU time 11.34 seconds
Started Feb 08 05:06:11 PM UTC 25
Finished Feb 08 05:06:24 PM UTC 25
Peak memory 212572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365711411 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1365711411
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3764825576
Short name T942
Test name
Test status
Simulation time 70007659108 ps
CPU time 5995.36 seconds
Started Feb 08 05:07:51 PM UTC 25
Finished Feb 08 06:48:43 PM UTC 25
Peak memory 401740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764825576 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.3764825576
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1142706362
Short name T595
Test name
Test status
Simulation time 1217368767 ps
CPU time 13.19 seconds
Started Feb 08 05:07:48 PM UTC 25
Finished Feb 08 05:08:03 PM UTC 25
Peak memory 222868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142706362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1142706362
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2889864545
Short name T628
Test name
Test status
Simulation time 8013569101 ps
CPU time 316.55 seconds
Started Feb 08 05:06:25 PM UTC 25
Finished Feb 08 05:11:46 PM UTC 25
Peak memory 212720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889864545 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.2889864545
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.70745834
Short name T590
Test name
Test status
Simulation time 1485366018 ps
CPU time 32.1 seconds
Started Feb 08 05:07:10 PM UTC 25
Finished Feb 08 05:07:44 PM UTC 25
Peak memory 318076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70745834 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.70745834
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.452164484
Short name T686
Test name
Test status
Simulation time 57128127546 ps
CPU time 723.73 seconds
Started Feb 08 05:08:48 PM UTC 25
Finished Feb 08 05:21:00 PM UTC 25
Peak memory 387804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452164484 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during_key_req.452164484
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2273928048
Short name T609
Test name
Test status
Simulation time 44263788 ps
CPU time 0.96 seconds
Started Feb 08 05:09:09 PM UTC 25
Finished Feb 08 05:09:11 PM UTC 25
Peak memory 212492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273928048 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.2273928048
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.812271425
Short name T735
Test name
Test status
Simulation time 230767428392 ps
CPU time 1163.05 seconds
Started Feb 08 05:08:04 PM UTC 25
Finished Feb 08 05:27:41 PM UTC 25
Peak memory 212764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812271425 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.812271425
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.3002502729
Short name T677
Test name
Test status
Simulation time 44069108226 ps
CPU time 643.28 seconds
Started Feb 08 05:08:51 PM UTC 25
Finished Feb 08 05:19:42 PM UTC 25
Peak memory 371376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002502729 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.3002502729
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3484313562
Short name T610
Test name
Test status
Simulation time 15025664386 ps
CPU time 30.48 seconds
Started Feb 08 05:08:45 PM UTC 25
Finished Feb 08 05:09:17 PM UTC 25
Peak memory 212956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484313562 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.3484313562
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2152398267
Short name T604
Test name
Test status
Simulation time 2974442043 ps
CPU time 30.95 seconds
Started Feb 08 05:08:18 PM UTC 25
Finished Feb 08 05:08:51 PM UTC 25
Peak memory 287464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152398267
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_max_throughput.2152398267
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1779907604
Short name T625
Test name
Test status
Simulation time 7346900917 ps
CPU time 151.63 seconds
Started Feb 08 05:08:59 PM UTC 25
Finished Feb 08 05:11:33 PM UTC 25
Peak memory 223024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779907604 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.1779907604
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.2545229415
Short name T631
Test name
Test status
Simulation time 54440430160 ps
CPU time 223.24 seconds
Started Feb 08 05:08:58 PM UTC 25
Finished Feb 08 05:12:45 PM UTC 25
Peak memory 222996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545229415 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.2545229415
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3274190905
Short name T644
Test name
Test status
Simulation time 7011951068 ps
CPU time 382.67 seconds
Started Feb 08 05:07:57 PM UTC 25
Finished Feb 08 05:14:24 PM UTC 25
Peak memory 383700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274190905 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.3274190905
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1602124322
Short name T600
Test name
Test status
Simulation time 963240534 ps
CPU time 22 seconds
Started Feb 08 05:08:15 PM UTC 25
Finished Feb 08 05:08:39 PM UTC 25
Peak memory 212584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602124322 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.1602124322
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2780689820
Short name T688
Test name
Test status
Simulation time 226998881190 ps
CPU time 772.48 seconds
Started Feb 08 05:08:17 PM UTC 25
Finished Feb 08 05:21:19 PM UTC 25
Peak memory 212688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780689820 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access_b2b.2780689820
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.4241188779
Short name T606
Test name
Test status
Simulation time 1399607495 ps
CPU time 4.75 seconds
Started Feb 08 05:08:52 PM UTC 25
Finished Feb 08 05:08:58 PM UTC 25
Peak memory 212936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241188779 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.4241188779
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1649281133
Short name T728
Test name
Test status
Simulation time 20813924201 ps
CPU time 1082.97 seconds
Started Feb 08 05:08:51 PM UTC 25
Finished Feb 08 05:27:05 PM UTC 25
Peak memory 391772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649281133 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1649281133
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.590626209
Short name T597
Test name
Test status
Simulation time 2048748003 ps
CPU time 18.73 seconds
Started Feb 08 05:07:55 PM UTC 25
Finished Feb 08 05:08:15 PM UTC 25
Peak memory 212656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590626209 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.590626209
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1996484321
Short name T938
Test name
Test status
Simulation time 466944105332 ps
CPU time 4840.22 seconds
Started Feb 08 05:09:06 PM UTC 25
Finished Feb 08 06:30:34 PM UTC 25
Peak memory 391512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996484321 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.1996484321
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2526242542
Short name T616
Test name
Test status
Simulation time 4653015234 ps
CPU time 50.68 seconds
Started Feb 08 05:09:04 PM UTC 25
Finished Feb 08 05:09:57 PM UTC 25
Peak memory 223068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526242542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2526242542
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.3510910921
Short name T633
Test name
Test status
Simulation time 4113518154 ps
CPU time 288 seconds
Started Feb 08 05:08:07 PM UTC 25
Finished Feb 08 05:12:59 PM UTC 25
Peak memory 212792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510910921 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.3510910921
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.620903150
Short name T615
Test name
Test status
Simulation time 765970294 ps
CPU time 75.25 seconds
Started Feb 08 05:08:39 PM UTC 25
Finished Feb 08 05:09:57 PM UTC 25
Peak memory 349064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620903150
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_throughput_w_partial_w
rite.620903150
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2321283782
Short name T742
Test name
Test status
Simulation time 55373353127 ps
CPU time 1050.51 seconds
Started Feb 08 05:10:29 PM UTC 25
Finished Feb 08 05:28:12 PM UTC 25
Peak memory 387796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321283782 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during_key_req.2321283782
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.4232158922
Short name T627
Test name
Test status
Simulation time 23029715 ps
CPU time 1.06 seconds
Started Feb 08 05:11:42 PM UTC 25
Finished Feb 08 05:11:44 PM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232158922 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.4232158922
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.697814124
Short name T875
Test name
Test status
Simulation time 103205906437 ps
CPU time 2282.28 seconds
Started Feb 08 05:09:20 PM UTC 25
Finished Feb 08 05:47:47 PM UTC 25
Peak memory 214416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697814124 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.697814124
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1355735859
Short name T718
Test name
Test status
Simulation time 73362275304 ps
CPU time 915.37 seconds
Started Feb 08 05:10:46 PM UTC 25
Finished Feb 08 05:26:11 PM UTC 25
Peak memory 385972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355735859 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.1355735859
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2256000713
Short name T629
Test name
Test status
Simulation time 36584066545 ps
CPU time 92.37 seconds
Started Feb 08 05:10:17 PM UTC 25
Finished Feb 08 05:11:52 PM UTC 25
Peak memory 212836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256000713 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.2256000713
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1990582048
Short name T620
Test name
Test status
Simulation time 1508377915 ps
CPU time 46.49 seconds
Started Feb 08 05:09:57 PM UTC 25
Finished Feb 08 05:10:45 PM UTC 25
Peak memory 312132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990582048
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_max_throughput.1990582048
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.595286511
Short name T90
Test name
Test status
Simulation time 1401836465 ps
CPU time 93.33 seconds
Started Feb 08 05:11:20 PM UTC 25
Finished Feb 08 05:12:55 PM UTC 25
Peak memory 222824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595286511 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.595286511
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1907641406
Short name T663
Test name
Test status
Simulation time 53088016508 ps
CPU time 373.45 seconds
Started Feb 08 05:11:17 PM UTC 25
Finished Feb 08 05:17:35 PM UTC 25
Peak memory 223052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907641406 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.1907641406
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.668499924
Short name T659
Test name
Test status
Simulation time 6411915912 ps
CPU time 466.92 seconds
Started Feb 08 05:09:18 PM UTC 25
Finished Feb 08 05:17:11 PM UTC 25
Peak memory 367532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668499924 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.668499924
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.4087148816
Short name T614
Test name
Test status
Simulation time 809041312 ps
CPU time 20.99 seconds
Started Feb 08 05:09:33 PM UTC 25
Finished Feb 08 05:09:55 PM UTC 25
Peak memory 212852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087148816 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.4087148816
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2662217397
Short name T669
Test name
Test status
Simulation time 18437181603 ps
CPU time 504.28 seconds
Started Feb 08 05:09:56 PM UTC 25
Finished Feb 08 05:18:27 PM UTC 25
Peak memory 212712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662217397 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access_b2b.2662217397
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.109154071
Short name T623
Test name
Test status
Simulation time 378468221 ps
CPU time 5.32 seconds
Started Feb 08 05:11:13 PM UTC 25
Finished Feb 08 05:11:19 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109154071 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.109154071
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.1600298483
Short name T634
Test name
Test status
Simulation time 6020038383 ps
CPU time 146.75 seconds
Started Feb 08 05:10:47 PM UTC 25
Finished Feb 08 05:13:16 PM UTC 25
Peak memory 357008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600298483 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1600298483
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.3769369953
Short name T612
Test name
Test status
Simulation time 2860580881 ps
CPU time 17.28 seconds
Started Feb 08 05:09:12 PM UTC 25
Finished Feb 08 05:09:30 PM UTC 25
Peak memory 212688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769369953 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3769369953
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3908498954
Short name T927
Test name
Test status
Simulation time 34854966723 ps
CPU time 3521.47 seconds
Started Feb 08 05:11:34 PM UTC 25
Finished Feb 08 06:10:49 PM UTC 25
Peak memory 397968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908498954 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.3908498954
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.3248041659
Short name T648
Test name
Test status
Simulation time 17495104439 ps
CPU time 361.59 seconds
Started Feb 08 05:09:31 PM UTC 25
Finished Feb 08 05:15:38 PM UTC 25
Peak memory 212760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248041659 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.3248041659
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.61523668
Short name T617
Test name
Test status
Simulation time 1622839728 ps
CPU time 18.01 seconds
Started Feb 08 05:09:57 PM UTC 25
Finished Feb 08 05:10:17 PM UTC 25
Peak memory 262676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61523668 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.61523668
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.58224222
Short name T649
Test name
Test status
Simulation time 4067661334 ps
CPU time 183.76 seconds
Started Feb 08 05:12:59 PM UTC 25
Finished Feb 08 05:16:06 PM UTC 25
Peak memory 361176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58224222 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during_key_req.58224222
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.550640186
Short name T642
Test name
Test status
Simulation time 16048415 ps
CPU time 0.86 seconds
Started Feb 08 05:14:10 PM UTC 25
Finished Feb 08 05:14:12 PM UTC 25
Peak memory 211584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550640186 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.550640186
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.3298179839
Short name T739
Test name
Test status
Simulation time 14010736255 ps
CPU time 959.55 seconds
Started Feb 08 05:11:52 PM UTC 25
Finished Feb 08 05:28:03 PM UTC 25
Peak memory 212776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298179839 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.3298179839
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.3496722616
Short name T819
Test name
Test status
Simulation time 26393094710 ps
CPU time 1591.69 seconds
Started Feb 08 05:13:17 PM UTC 25
Finished Feb 08 05:40:05 PM UTC 25
Peak memory 391784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496722616 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.3496722616
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.463350512
Short name T639
Test name
Test status
Simulation time 31404449933 ps
CPU time 62.06 seconds
Started Feb 08 05:12:56 PM UTC 25
Finished Feb 08 05:14:00 PM UTC 25
Peak memory 212680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463350512 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.463350512
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1330957635
Short name T636
Test name
Test status
Simulation time 1216994756 ps
CPU time 43.26 seconds
Started Feb 08 05:12:48 PM UTC 25
Finished Feb 08 05:13:33 PM UTC 25
Peak memory 311856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330957635
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_max_throughput.1330957635
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.491225153
Short name T646
Test name
Test status
Simulation time 4831043938 ps
CPU time 107.62 seconds
Started Feb 08 05:13:43 PM UTC 25
Finished Feb 08 05:15:33 PM UTC 25
Peak memory 223280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491225153 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.491225153
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.4179791571
Short name T653
Test name
Test status
Simulation time 25625430947 ps
CPU time 160.8 seconds
Started Feb 08 05:13:43 PM UTC 25
Finished Feb 08 05:16:26 PM UTC 25
Peak memory 222924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179791571 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.4179791571
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3633864464
Short name T684
Test name
Test status
Simulation time 99001419887 ps
CPU time 533.68 seconds
Started Feb 08 05:11:47 PM UTC 25
Finished Feb 08 05:20:48 PM UTC 25
Peak memory 383708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633864464 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.3633864464
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2128771857
Short name T632
Test name
Test status
Simulation time 1813309378 ps
CPU time 18.14 seconds
Started Feb 08 05:12:35 PM UTC 25
Finished Feb 08 05:12:54 PM UTC 25
Peak memory 212564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128771857 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.2128771857
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.2827200562
Short name T698
Test name
Test status
Simulation time 52280223252 ps
CPU time 585.1 seconds
Started Feb 08 05:12:46 PM UTC 25
Finished Feb 08 05:22:37 PM UTC 25
Peak memory 212696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827200562 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access_b2b.2827200562
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1889211611
Short name T637
Test name
Test status
Simulation time 1341009911 ps
CPU time 6.57 seconds
Started Feb 08 05:13:34 PM UTC 25
Finished Feb 08 05:13:41 PM UTC 25
Peak memory 213000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889211611 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.1889211611
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.974636246
Short name T722
Test name
Test status
Simulation time 80154100477 ps
CPU time 780.81 seconds
Started Feb 08 05:13:30 PM UTC 25
Finished Feb 08 05:26:39 PM UTC 25
Peak memory 381664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974636246 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.974636246
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.106490851
Short name T630
Test name
Test status
Simulation time 392510498 ps
CPU time 22.33 seconds
Started Feb 08 05:11:45 PM UTC 25
Finished Feb 08 05:12:09 PM UTC 25
Peak memory 283252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106490851 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.106490851
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.59386042
Short name T926
Test name
Test status
Simulation time 303620335793 ps
CPU time 3363.27 seconds
Started Feb 08 05:14:04 PM UTC 25
Finished Feb 08 06:10:42 PM UTC 25
Peak memory 397668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59386042 -assert no
postproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.59386042
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1320414001
Short name T643
Test name
Test status
Simulation time 446342773 ps
CPU time 14.67 seconds
Started Feb 08 05:14:01 PM UTC 25
Finished Feb 08 05:14:17 PM UTC 25
Peak memory 222812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320414001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.1320414001
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.501265240
Short name T664
Test name
Test status
Simulation time 18664275900 ps
CPU time 339.15 seconds
Started Feb 08 05:12:10 PM UTC 25
Finished Feb 08 05:17:53 PM UTC 25
Peak memory 212684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501265240 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.501265240
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1472238107
Short name T635
Test name
Test status
Simulation time 2582774706 ps
CPU time 32.23 seconds
Started Feb 08 05:12:55 PM UTC 25
Finished Feb 08 05:13:29 PM UTC 25
Peak memory 295576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472238107
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_throughput_w_partial_
write.1472238107
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.4224954770
Short name T671
Test name
Test status
Simulation time 10594240706 ps
CPU time 152.71 seconds
Started Feb 08 05:16:10 PM UTC 25
Finished Feb 08 05:18:46 PM UTC 25
Peak memory 336620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224954770 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during_key_req.4224954770
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.690847996
Short name T660
Test name
Test status
Simulation time 55400030 ps
CPU time 0.95 seconds
Started Feb 08 05:17:11 PM UTC 25
Finished Feb 08 05:17:13 PM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690847996 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.690847996
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.3784341514
Short name T866
Test name
Test status
Simulation time 106472323706 ps
CPU time 1879.75 seconds
Started Feb 08 05:14:25 PM UTC 25
Finished Feb 08 05:46:05 PM UTC 25
Peak memory 214372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784341514 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.3784341514
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.4259589548
Short name T741
Test name
Test status
Simulation time 38211288030 ps
CPU time 703.54 seconds
Started Feb 08 05:16:15 PM UTC 25
Finished Feb 08 05:28:05 PM UTC 25
Peak memory 381556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259589548 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.4259589548
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2615540409
Short name T665
Test name
Test status
Simulation time 57050812218 ps
CPU time 119.79 seconds
Started Feb 08 05:16:06 PM UTC 25
Finished Feb 08 05:18:09 PM UTC 25
Peak memory 227292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615540409 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.2615540409
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3909786472
Short name T651
Test name
Test status
Simulation time 729883384 ps
CPU time 35.5 seconds
Started Feb 08 05:15:36 PM UTC 25
Finished Feb 08 05:16:13 PM UTC 25
Peak memory 299652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909786472
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_max_throughput.3909786472
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2290145228
Short name T676
Test name
Test status
Simulation time 4881755042 ps
CPU time 170.45 seconds
Started Feb 08 05:16:38 PM UTC 25
Finished Feb 08 05:19:31 PM UTC 25
Peak memory 229972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290145228 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.2290145228
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3397674910
Short name T672
Test name
Test status
Simulation time 7358579339 ps
CPU time 152.75 seconds
Started Feb 08 05:16:34 PM UTC 25
Finished Feb 08 05:19:09 PM UTC 25
Peak memory 223176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397674910 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.3397674910
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.1656626369
Short name T666
Test name
Test status
Simulation time 13010525838 ps
CPU time 228.18 seconds
Started Feb 08 05:14:18 PM UTC 25
Finished Feb 08 05:18:10 PM UTC 25
Peak memory 346836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656626369 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.1656626369
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.3860704674
Short name T650
Test name
Test status
Simulation time 821209283 ps
CPU time 37.99 seconds
Started Feb 08 05:15:30 PM UTC 25
Finished Feb 08 05:16:10 PM UTC 25
Peak memory 287508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860704674 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.3860704674
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1305577182
Short name T720
Test name
Test status
Simulation time 19692935485 ps
CPU time 650.74 seconds
Started Feb 08 05:15:34 PM UTC 25
Finished Feb 08 05:26:33 PM UTC 25
Peak memory 212956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305577182 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access_b2b.1305577182
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1255100844
Short name T654
Test name
Test status
Simulation time 400453901 ps
CPU time 5.62 seconds
Started Feb 08 05:16:27 PM UTC 25
Finished Feb 08 05:16:33 PM UTC 25
Peak memory 213000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255100844 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1255100844
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.43224243
Short name T680
Test name
Test status
Simulation time 5266711172 ps
CPU time 205.97 seconds
Started Feb 08 05:16:22 PM UTC 25
Finished Feb 08 05:19:51 PM UTC 25
Peak memory 350968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43224243 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.43224243
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.2845884664
Short name T645
Test name
Test status
Simulation time 4117693578 ps
CPU time 73.94 seconds
Started Feb 08 05:14:13 PM UTC 25
Finished Feb 08 05:15:29 PM UTC 25
Peak memory 342788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845884664 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2845884664
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.687057231
Short name T945
Test name
Test status
Simulation time 3052393918398 ps
CPU time 7281.27 seconds
Started Feb 08 05:17:02 PM UTC 25
Finished Feb 08 07:19:37 PM UTC 25
Peak memory 393648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687057231 -assert n
opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.687057231
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3954819256
Short name T661
Test name
Test status
Simulation time 750234789 ps
CPU time 36.01 seconds
Started Feb 08 05:16:41 PM UTC 25
Finished Feb 08 05:17:19 PM UTC 25
Peak memory 222856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954819256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3954819256
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.824799505
Short name T700
Test name
Test status
Simulation time 22874644109 ps
CPU time 487.29 seconds
Started Feb 08 05:14:42 PM UTC 25
Finished Feb 08 05:22:55 PM UTC 25
Peak memory 212792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824799505 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.824799505
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3973621289
Short name T656
Test name
Test status
Simulation time 8400934921 ps
CPU time 56.97 seconds
Started Feb 08 05:15:38 PM UTC 25
Finished Feb 08 05:16:37 PM UTC 25
Peak memory 348932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973621289
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_throughput_w_partial_
write.3973621289
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2068114591
Short name T746
Test name
Test status
Simulation time 6386702557 ps
CPU time 591.82 seconds
Started Feb 08 05:18:28 PM UTC 25
Finished Feb 08 05:28:27 PM UTC 25
Peak memory 386036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068114591 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_key_req.2068114591
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1749177529
Short name T679
Test name
Test status
Simulation time 34652539 ps
CPU time 0.89 seconds
Started Feb 08 05:19:43 PM UTC 25
Finished Feb 08 05:19:45 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749177529 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1749177529
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.2705154660
Short name T922
Test name
Test status
Simulation time 690351734170 ps
CPU time 2868.26 seconds
Started Feb 08 05:17:28 PM UTC 25
Finished Feb 08 06:05:46 PM UTC 25
Peak memory 214456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705154660 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.2705154660
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.3057307379
Short name T712
Test name
Test status
Simulation time 21424736341 ps
CPU time 383.66 seconds
Started Feb 08 05:18:45 PM UTC 25
Finished Feb 08 05:25:14 PM UTC 25
Peak memory 373688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057307379 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.3057307379
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.337421497
Short name T673
Test name
Test status
Simulation time 8930988179 ps
CPU time 44.37 seconds
Started Feb 08 05:18:26 PM UTC 25
Finished Feb 08 05:19:12 PM UTC 25
Peak memory 223004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337421497 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.337421497
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.2508229328
Short name T668
Test name
Test status
Simulation time 2734594048 ps
CPU time 13.09 seconds
Started Feb 08 05:18:11 PM UTC 25
Finished Feb 08 05:18:25 PM UTC 25
Peak memory 246788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508229328
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max_throughput.2508229328
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2906036675
Short name T687
Test name
Test status
Simulation time 37408900187 ps
CPU time 108.05 seconds
Started Feb 08 05:19:17 PM UTC 25
Finished Feb 08 05:21:08 PM UTC 25
Peak memory 225252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906036675 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.2906036675
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1682512383
Short name T721
Test name
Test status
Simulation time 82828423309 ps
CPU time 439 seconds
Started Feb 08 05:19:12 PM UTC 25
Finished Feb 08 05:26:37 PM UTC 25
Peak memory 223192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682512383 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.1682512383
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.97596604
Short name T717
Test name
Test status
Simulation time 57090847152 ps
CPU time 515.98 seconds
Started Feb 08 05:17:19 PM UTC 25
Finished Feb 08 05:26:01 PM UTC 25
Peak memory 390072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97596604 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.97596604
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1196983926
Short name T667
Test name
Test status
Simulation time 4372636162 ps
CPU time 29.98 seconds
Started Feb 08 05:17:54 PM UTC 25
Finished Feb 08 05:18:25 PM UTC 25
Peak memory 212712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196983926 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.1196983926
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3757356071
Short name T733
Test name
Test status
Simulation time 90403069141 ps
CPU time 562 seconds
Started Feb 08 05:18:10 PM UTC 25
Finished Feb 08 05:27:39 PM UTC 25
Peak memory 212788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757356071 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access_b2b.3757356071
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.3920174286
Short name T675
Test name
Test status
Simulation time 350066411 ps
CPU time 5.47 seconds
Started Feb 08 05:19:10 PM UTC 25
Finished Feb 08 05:19:17 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920174286 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3920174286
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1232858908
Short name T703
Test name
Test status
Simulation time 15717468258 ps
CPU time 280.21 seconds
Started Feb 08 05:18:46 PM UTC 25
Finished Feb 08 05:23:30 PM UTC 25
Peak memory 369368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232858908 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1232858908
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.3787674678
Short name T670
Test name
Test status
Simulation time 781043359 ps
CPU time 87.87 seconds
Started Feb 08 05:17:14 PM UTC 25
Finished Feb 08 05:18:44 PM UTC 25
Peak memory 379688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787674678 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3787674678
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1146591783
Short name T921
Test name
Test status
Simulation time 24308071384 ps
CPU time 2720.35 seconds
Started Feb 08 05:19:33 PM UTC 25
Finished Feb 08 06:05:21 PM UTC 25
Peak memory 391572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146591783 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.1146591783
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1760572458
Short name T678
Test name
Test status
Simulation time 667604628 ps
CPU time 23.93 seconds
Started Feb 08 05:19:17 PM UTC 25
Finished Feb 08 05:19:43 PM UTC 25
Peak memory 222876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760572458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1760572458
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.837204287
Short name T689
Test name
Test status
Simulation time 11826680747 ps
CPU time 239.28 seconds
Started Feb 08 05:17:37 PM UTC 25
Finished Feb 08 05:21:39 PM UTC 25
Peak memory 212816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837204287 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.837204287
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3043825410
Short name T674
Test name
Test status
Simulation time 3108075085 ps
CPU time 49.02 seconds
Started Feb 08 05:18:26 PM UTC 25
Finished Feb 08 05:19:17 PM UTC 25
Peak memory 326324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043825410
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_throughput_w_partial_
write.3043825410
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2187085721
Short name T708
Test name
Test status
Simulation time 19006268273 ps
CPU time 221.47 seconds
Started Feb 08 05:21:01 PM UTC 25
Finished Feb 08 05:24:45 PM UTC 25
Peak memory 342952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187085721 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during_key_req.2187085721
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3324246471
Short name T696
Test name
Test status
Simulation time 12724705 ps
CPU time 0.85 seconds
Started Feb 08 05:22:07 PM UTC 25
Finished Feb 08 05:22:09 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324246471 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3324246471
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.4276122073
Short name T918
Test name
Test status
Simulation time 459786059191 ps
CPU time 2432.9 seconds
Started Feb 08 05:19:52 PM UTC 25
Finished Feb 08 06:00:53 PM UTC 25
Peak memory 214404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276122073 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.4276122073
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.4032812357
Short name T816
Test name
Test status
Simulation time 31739957956 ps
CPU time 1114.58 seconds
Started Feb 08 05:21:09 PM UTC 25
Finished Feb 08 05:39:55 PM UTC 25
Peak memory 390108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032812357 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.4032812357
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2248901454
Short name T697
Test name
Test status
Simulation time 35138435423 ps
CPU time 76.85 seconds
Started Feb 08 05:21:01 PM UTC 25
Finished Feb 08 05:22:19 PM UTC 25
Peak memory 222952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248901454 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.2248901454
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.2968142046
Short name T694
Test name
Test status
Simulation time 3127151264 ps
CPU time 78.76 seconds
Started Feb 08 05:20:46 PM UTC 25
Finished Feb 08 05:22:06 PM UTC 25
Peak memory 359360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968142046
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_max_throughput.2968142046
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3779815081
Short name T714
Test name
Test status
Simulation time 21846772694 ps
CPU time 201.09 seconds
Started Feb 08 05:21:57 PM UTC 25
Finished Feb 08 05:25:22 PM UTC 25
Peak memory 230204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779815081 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.3779815081
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2321003411
Short name T737
Test name
Test status
Simulation time 10718853218 ps
CPU time 364.24 seconds
Started Feb 08 05:21:48 PM UTC 25
Finished Feb 08 05:27:58 PM UTC 25
Peak memory 222920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321003411 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.2321003411
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.4035543170
Short name T824
Test name
Test status
Simulation time 50904719225 ps
CPU time 1237.88 seconds
Started Feb 08 05:19:46 PM UTC 25
Finished Feb 08 05:40:36 PM UTC 25
Peak memory 390068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035543170 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.4035543170
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1866959479
Short name T685
Test name
Test status
Simulation time 8624529414 ps
CPU time 55.79 seconds
Started Feb 08 05:20:02 PM UTC 25
Finished Feb 08 05:21:00 PM UTC 25
Peak memory 308144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866959479 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.1866959479
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.20700681
Short name T767
Test name
Test status
Simulation time 24389334774 ps
CPU time 643.65 seconds
Started Feb 08 05:20:27 PM UTC 25
Finished Feb 08 05:31:19 PM UTC 25
Peak memory 212724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20700681 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access_b2b.20700681
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4277099106
Short name T690
Test name
Test status
Simulation time 1351791607 ps
CPU time 6.14 seconds
Started Feb 08 05:21:40 PM UTC 25
Finished Feb 08 05:21:47 PM UTC 25
Peak memory 213000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277099106 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.4277099106
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.979764683
Short name T756
Test name
Test status
Simulation time 4221667613 ps
CPU time 507.51 seconds
Started Feb 08 05:21:20 PM UTC 25
Finished Feb 08 05:29:53 PM UTC 25
Peak memory 385852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979764683 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.979764683
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2873295244
Short name T681
Test name
Test status
Simulation time 1900681417 ps
CPU time 14.65 seconds
Started Feb 08 05:19:44 PM UTC 25
Finished Feb 08 05:20:00 PM UTC 25
Peak memory 240176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873295244 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2873295244
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1098870315
Short name T935
Test name
Test status
Simulation time 44652398718 ps
CPU time 3420.84 seconds
Started Feb 08 05:22:06 PM UTC 25
Finished Feb 08 06:19:43 PM UTC 25
Peak memory 391460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098870315 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.1098870315
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2896714024
Short name T115
Test name
Test status
Simulation time 4105081697 ps
CPU time 39.44 seconds
Started Feb 08 05:22:04 PM UTC 25
Finished Feb 08 05:22:45 PM UTC 25
Peak memory 223260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896714024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2896714024
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2941537022
Short name T691
Test name
Test status
Simulation time 8919918625 ps
CPU time 112.84 seconds
Started Feb 08 05:20:01 PM UTC 25
Finished Feb 08 05:21:56 PM UTC 25
Peak memory 212764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941537022 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.2941537022
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.3435540692
Short name T693
Test name
Test status
Simulation time 8375329577 ps
CPU time 75.17 seconds
Started Feb 08 05:20:49 PM UTC 25
Finished Feb 08 05:22:06 PM UTC 25
Peak memory 344756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435540692
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_throughput_w_partial_
write.3435540692
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2300670571
Short name T829
Test name
Test status
Simulation time 65380537507 ps
CPU time 1066.83 seconds
Started Feb 08 05:23:20 PM UTC 25
Finished Feb 08 05:41:18 PM UTC 25
Peak memory 383664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300670571 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during_key_req.2300670571
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.324967769
Short name T709
Test name
Test status
Simulation time 30157392 ps
CPU time 0.83 seconds
Started Feb 08 05:24:46 PM UTC 25
Finished Feb 08 05:24:48 PM UTC 25
Peak memory 212560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324967769 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.324967769
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.2475308231
Short name T910
Test name
Test status
Simulation time 59792877958 ps
CPU time 2048.74 seconds
Started Feb 08 05:22:12 PM UTC 25
Finished Feb 08 05:56:42 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475308231 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.2475308231
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.1646220061
Short name T775
Test name
Test status
Simulation time 10045838213 ps
CPU time 521.81 seconds
Started Feb 08 05:23:32 PM UTC 25
Finished Feb 08 05:32:20 PM UTC 25
Peak memory 385628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646220061 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.1646220061
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3094485921
Short name T702
Test name
Test status
Simulation time 1724868758 ps
CPU time 19.47 seconds
Started Feb 08 05:22:58 PM UTC 25
Finished Feb 08 05:23:19 PM UTC 25
Peak memory 222836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094485921 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.3094485921
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2246930682
Short name T704
Test name
Test status
Simulation time 1508214337 ps
CPU time 45.11 seconds
Started Feb 08 05:22:48 PM UTC 25
Finished Feb 08 05:23:35 PM UTC 25
Peak memory 336436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246930682
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_max_throughput.2246930682
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2963691836
Short name T719
Test name
Test status
Simulation time 6371743273 ps
CPU time 140.1 seconds
Started Feb 08 05:24:04 PM UTC 25
Finished Feb 08 05:26:27 PM UTC 25
Peak memory 223160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963691836 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.2963691836
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1330805200
Short name T724
Test name
Test status
Simulation time 2634286745 ps
CPU time 176.73 seconds
Started Feb 08 05:23:44 PM UTC 25
Finished Feb 08 05:26:44 PM UTC 25
Peak memory 223184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330805200 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.1330805200
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4072734971
Short name T738
Test name
Test status
Simulation time 35480804260 ps
CPU time 343.43 seconds
Started Feb 08 05:22:11 PM UTC 25
Finished Feb 08 05:27:59 PM UTC 25
Peak memory 387828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072734971 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.4072734971
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3555722361
Short name T701
Test name
Test status
Simulation time 5804397125 ps
CPU time 17.71 seconds
Started Feb 08 05:22:38 PM UTC 25
Finished Feb 08 05:22:57 PM UTC 25
Peak memory 212816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555722361 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.3555722361
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.567045045
Short name T749
Test name
Test status
Simulation time 37372478497 ps
CPU time 344.8 seconds
Started Feb 08 05:22:46 PM UTC 25
Finished Feb 08 05:28:36 PM UTC 25
Peak memory 212696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567045045 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access_b2b.567045045
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1811167548
Short name T705
Test name
Test status
Simulation time 929353106 ps
CPU time 6.35 seconds
Started Feb 08 05:23:36 PM UTC 25
Finished Feb 08 05:23:44 PM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811167548 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1811167548
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.758683074
Short name T753
Test name
Test status
Simulation time 31147905171 ps
CPU time 345.64 seconds
Started Feb 08 05:23:36 PM UTC 25
Finished Feb 08 05:29:26 PM UTC 25
Peak memory 387832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758683074 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.758683074
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.3339384413
Short name T699
Test name
Test status
Simulation time 2011366573 ps
CPU time 37.58 seconds
Started Feb 08 05:22:09 PM UTC 25
Finished Feb 08 05:22:48 PM UTC 25
Peak memory 287336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339384413 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3339384413
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.8082640
Short name T905
Test name
Test status
Simulation time 86951781926 ps
CPU time 1832.73 seconds
Started Feb 08 05:24:40 PM UTC 25
Finished Feb 08 05:55:32 PM UTC 25
Peak memory 381252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8082640 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.8082640
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2257381576
Short name T736
Test name
Test status
Simulation time 1728988987 ps
CPU time 213.4 seconds
Started Feb 08 05:24:21 PM UTC 25
Finished Feb 08 05:27:57 PM UTC 25
Peak memory 387672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257381576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2257381576
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.447194331
Short name T727
Test name
Test status
Simulation time 3793941051 ps
CPU time 279.25 seconds
Started Feb 08 05:22:20 PM UTC 25
Finished Feb 08 05:27:03 PM UTC 25
Peak memory 212844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447194331 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.447194331
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.4220086175
Short name T706
Test name
Test status
Simulation time 1580523060 ps
CPU time 65.16 seconds
Started Feb 08 05:22:56 PM UTC 25
Finished Feb 08 05:24:03 PM UTC 25
Peak memory 338464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220086175
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_throughput_w_partial_
write.4220086175
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.554477052
Short name T86
Test name
Test status
Simulation time 10387158627 ps
CPU time 138.11 seconds
Started Feb 08 03:10:45 PM UTC 25
Finished Feb 08 03:13:06 PM UTC 25
Peak memory 377508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554477052 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_key_req.554477052
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3807686632
Short name T171
Test name
Test status
Simulation time 15378837 ps
CPU time 0.97 seconds
Started Feb 08 03:13:02 PM UTC 25
Finished Feb 08 03:13:04 PM UTC 25
Peak memory 211584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807686632 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.3807686632
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.226693707
Short name T238
Test name
Test status
Simulation time 68684066387 ps
CPU time 1700.01 seconds
Started Feb 08 03:08:03 PM UTC 25
Finished Feb 08 03:36:43 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226693707 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.226693707
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.1945110393
Short name T143
Test name
Test status
Simulation time 43192922168 ps
CPU time 358.17 seconds
Started Feb 08 03:10:47 PM UTC 25
Finished Feb 08 03:16:50 PM UTC 25
Peak memory 385700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945110393 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.1945110393
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1118553772
Short name T21
Test name
Test status
Simulation time 30372607698 ps
CPU time 57.09 seconds
Started Feb 08 03:10:37 PM UTC 25
Finished Feb 08 03:11:36 PM UTC 25
Peak memory 212708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118553772 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.1118553772
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2170019896
Short name T166
Test name
Test status
Simulation time 801234107 ps
CPU time 83.99 seconds
Started Feb 08 03:10:18 PM UTC 25
Finished Feb 08 03:11:44 PM UTC 25
Peak memory 381760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170019896
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max_throughput.2170019896
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3422001622
Short name T87
Test name
Test status
Simulation time 10552706879 ps
CPU time 102.38 seconds
Started Feb 08 03:12:13 PM UTC 25
Finished Feb 08 03:13:57 PM UTC 25
Peak memory 223072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422001622 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.3422001622
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3258083509
Short name T45
Test name
Test status
Simulation time 64072115857 ps
CPU time 370.19 seconds
Started Feb 08 03:11:49 PM UTC 25
Finished Feb 08 03:18:05 PM UTC 25
Peak memory 223028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258083509 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.3258083509
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.628266168
Short name T186
Test name
Test status
Simulation time 15328767252 ps
CPU time 686.62 seconds
Started Feb 08 03:08:00 PM UTC 25
Finished Feb 08 03:19:34 PM UTC 25
Peak memory 387744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628266168 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.628266168
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.2502302477
Short name T164
Test name
Test status
Simulation time 3369680575 ps
CPU time 16.04 seconds
Started Feb 08 03:09:34 PM UTC 25
Finished Feb 08 03:09:52 PM UTC 25
Peak memory 242308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502302477 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.2502302477
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2084169183
Short name T182
Test name
Test status
Simulation time 71529902842 ps
CPU time 477.09 seconds
Started Feb 08 03:09:52 PM UTC 25
Finished Feb 08 03:17:56 PM UTC 25
Peak memory 212788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084169183 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access_b2b.2084169183
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.555676831
Short name T167
Test name
Test status
Simulation time 361632840 ps
CPU time 3.58 seconds
Started Feb 08 03:11:44 PM UTC 25
Finished Feb 08 03:11:49 PM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555676831 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.555676831
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.3447763778
Short name T20
Test name
Test status
Simulation time 57752143976 ps
CPU time 787.73 seconds
Started Feb 08 03:11:36 PM UTC 25
Finished Feb 08 03:24:53 PM UTC 25
Peak memory 390056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447763778 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3447763778
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.540382995
Short name T31
Test name
Test status
Simulation time 1743465993 ps
CPU time 3.36 seconds
Started Feb 08 03:12:59 PM UTC 25
Finished Feb 08 03:13:03 PM UTC 25
Peak memory 248828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540382995 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.540382995
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.4034202269
Short name T163
Test name
Test status
Simulation time 3278880771 ps
CPU time 21.92 seconds
Started Feb 08 03:08:00 PM UTC 25
Finished Feb 08 03:08:23 PM UTC 25
Peak memory 212712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034202269 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.4034202269
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.653581968
Short name T65
Test name
Test status
Simulation time 7299001493 ps
CPU time 167.26 seconds
Started Feb 08 03:12:28 PM UTC 25
Finished Feb 08 03:15:18 PM UTC 25
Peak memory 371412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653581968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.653581968
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.68079887
Short name T109
Test name
Test status
Simulation time 4486214628 ps
CPU time 282.82 seconds
Started Feb 08 03:08:24 PM UTC 25
Finished Feb 08 03:13:11 PM UTC 25
Peak memory 212688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68079887 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.68079887
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3555007013
Short name T165
Test name
Test status
Simulation time 696062010 ps
CPU time 10.99 seconds
Started Feb 08 03:10:32 PM UTC 25
Finished Feb 08 03:10:44 PM UTC 25
Peak memory 230268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555007013
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_throughput_w_partial_w
rite.3555007013
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3568756099
Short name T801
Test name
Test status
Simulation time 6788110561 ps
CPU time 621.49 seconds
Started Feb 08 05:26:02 PM UTC 25
Finished Feb 08 05:36:31 PM UTC 25
Peak memory 390028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568756099 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during_key_req.3568756099
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.4263616474
Short name T726
Test name
Test status
Simulation time 12566766 ps
CPU time 0.98 seconds
Started Feb 08 05:26:52 PM UTC 25
Finished Feb 08 05:26:54 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263616474 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.4263616474
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.1787306152
Short name T902
Test name
Test status
Simulation time 97543489376 ps
CPU time 1752.64 seconds
Started Feb 08 05:24:52 PM UTC 25
Finished Feb 08 05:54:24 PM UTC 25
Peak memory 214476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787306152 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.1787306152
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.2662091638
Short name T806
Test name
Test status
Simulation time 7280863414 ps
CPU time 672.84 seconds
Started Feb 08 05:26:11 PM UTC 25
Finished Feb 08 05:37:31 PM UTC 25
Peak memory 377784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662091638 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.2662091638
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.861463485
Short name T655
Test name
Test status
Simulation time 11400956871 ps
CPU time 72.51 seconds
Started Feb 08 05:25:57 PM UTC 25
Finished Feb 08 05:27:11 PM UTC 25
Peak memory 222980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861463485 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.861463485
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2578076309
Short name T731
Test name
Test status
Simulation time 3039447912 ps
CPU time 91.28 seconds
Started Feb 08 05:25:44 PM UTC 25
Finished Feb 08 05:27:17 PM UTC 25
Peak memory 377520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578076309
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_max_throughput.2578076309
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.956405529
Short name T744
Test name
Test status
Simulation time 2781644881 ps
CPU time 93.01 seconds
Started Feb 08 05:26:40 PM UTC 25
Finished Feb 08 05:28:15 PM UTC 25
Peak memory 223228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956405529 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.956405529
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.211655286
Short name T764
Test name
Test status
Simulation time 43162234654 ps
CPU time 261.9 seconds
Started Feb 08 05:26:37 PM UTC 25
Finished Feb 08 05:31:04 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211655286 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.211655286
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.107753657
Short name T794
Test name
Test status
Simulation time 13797403414 ps
CPU time 621.13 seconds
Started Feb 08 05:24:50 PM UTC 25
Finished Feb 08 05:35:18 PM UTC 25
Peak memory 388012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107753657 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.107753657
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1114244800
Short name T715
Test name
Test status
Simulation time 933559774 ps
CPU time 23.69 seconds
Started Feb 08 05:25:17 PM UTC 25
Finished Feb 08 05:25:42 PM UTC 25
Peak memory 212664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114244800 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.1114244800
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.795340815
Short name T770
Test name
Test status
Simulation time 6630733018 ps
CPU time 366.97 seconds
Started Feb 08 05:25:22 PM UTC 25
Finished Feb 08 05:31:34 PM UTC 25
Peak memory 212788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795340815 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access_b2b.795340815
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2485242935
Short name T723
Test name
Test status
Simulation time 693740142 ps
CPU time 5.72 seconds
Started Feb 08 05:26:34 PM UTC 25
Finished Feb 08 05:26:41 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485242935 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2485242935
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.4213706628
Short name T772
Test name
Test status
Simulation time 7988103339 ps
CPU time 334.15 seconds
Started Feb 08 05:26:28 PM UTC 25
Finished Feb 08 05:32:07 PM UTC 25
Peak memory 387820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213706628 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.4213706628
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.241686907
Short name T713
Test name
Test status
Simulation time 849217929 ps
CPU time 26.41 seconds
Started Feb 08 05:24:49 PM UTC 25
Finished Feb 08 05:25:17 PM UTC 25
Peak memory 212600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241686907 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.241686907
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.412953305
Short name T932
Test name
Test status
Simulation time 781271861069 ps
CPU time 2944.3 seconds
Started Feb 08 05:26:45 PM UTC 25
Finished Feb 08 06:16:19 PM UTC 25
Peak memory 395624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412953305 -assert n
opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.412953305
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3125980654
Short name T734
Test name
Test status
Simulation time 4541420888 ps
CPU time 57.27 seconds
Started Feb 08 05:26:42 PM UTC 25
Finished Feb 08 05:27:41 PM UTC 25
Peak memory 223352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125980654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.3125980654
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2887477482
Short name T763
Test name
Test status
Simulation time 17617444994 ps
CPU time 329.45 seconds
Started Feb 08 05:25:14 PM UTC 25
Finished Feb 08 05:30:48 PM UTC 25
Peak memory 212844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887477482 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.2887477482
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1619502799
Short name T725
Test name
Test status
Simulation time 1602003375 ps
CPU time 62.15 seconds
Started Feb 08 05:25:47 PM UTC 25
Finished Feb 08 05:26:51 PM UTC 25
Peak memory 363036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619502799
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_throughput_w_partial_
write.1619502799
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1187234790
Short name T894
Test name
Test status
Simulation time 91192371387 ps
CPU time 1356.01 seconds
Started Feb 08 05:27:42 PM UTC 25
Finished Feb 08 05:50:33 PM UTC 25
Peak memory 389868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187234790 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during_key_req.1187234790
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3068627180
Short name T743
Test name
Test status
Simulation time 22964234 ps
CPU time 0.93 seconds
Started Feb 08 05:28:12 PM UTC 25
Finished Feb 08 05:28:14 PM UTC 25
Peak memory 212556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068627180 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.3068627180
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.873544076
Short name T891
Test name
Test status
Simulation time 263646347606 ps
CPU time 1358.11 seconds
Started Feb 08 05:27:06 PM UTC 25
Finished Feb 08 05:49:59 PM UTC 25
Peak memory 212692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873544076 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.873544076
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.2252734274
Short name T840
Test name
Test status
Simulation time 82199617560 ps
CPU time 882 seconds
Started Feb 08 05:27:42 PM UTC 25
Finished Feb 08 05:42:33 PM UTC 25
Peak memory 381612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252734274 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.2252734274
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.241396646
Short name T755
Test name
Test status
Simulation time 13566945271 ps
CPU time 129.37 seconds
Started Feb 08 05:27:39 PM UTC 25
Finished Feb 08 05:29:52 PM UTC 25
Peak memory 222944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241396646 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.241396646
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.3768634898
Short name T750
Test name
Test status
Simulation time 1178414494 ps
CPU time 85.14 seconds
Started Feb 08 05:27:18 PM UTC 25
Finished Feb 08 05:28:46 PM UTC 25
Peak memory 365380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768634898
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_max_throughput.3768634898
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.210758384
Short name T758
Test name
Test status
Simulation time 3203237498 ps
CPU time 123.95 seconds
Started Feb 08 05:28:04 PM UTC 25
Finished Feb 08 05:30:10 PM UTC 25
Peak memory 223052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210758384 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.210758384
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1684196047
Short name T784
Test name
Test status
Simulation time 25003503931 ps
CPU time 316.78 seconds
Started Feb 08 05:28:00 PM UTC 25
Finished Feb 08 05:33:21 PM UTC 25
Peak memory 222988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684196047 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.1684196047
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1477786621
Short name T856
Test name
Test status
Simulation time 13203638189 ps
CPU time 1061.18 seconds
Started Feb 08 05:27:04 PM UTC 25
Finished Feb 08 05:44:56 PM UTC 25
Peak memory 392176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477786621 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.1477786621
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.4188767451
Short name T732
Test name
Test status
Simulation time 2730483576 ps
CPU time 11.2 seconds
Started Feb 08 05:27:11 PM UTC 25
Finished Feb 08 05:27:24 PM UTC 25
Peak memory 212548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188767451 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.4188767451
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2466210165
Short name T768
Test name
Test status
Simulation time 3193436632 ps
CPU time 243.49 seconds
Started Feb 08 05:27:12 PM UTC 25
Finished Feb 08 05:31:20 PM UTC 25
Peak memory 212788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466210165 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access_b2b.2466210165
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1849877263
Short name T740
Test name
Test status
Simulation time 2143402457 ps
CPU time 4.79 seconds
Started Feb 08 05:27:59 PM UTC 25
Finished Feb 08 05:28:05 PM UTC 25
Peak memory 213000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849877263 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1849877263
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.4218587692
Short name T833
Test name
Test status
Simulation time 3387685449 ps
CPU time 813.38 seconds
Started Feb 08 05:27:58 PM UTC 25
Finished Feb 08 05:41:40 PM UTC 25
Peak memory 377560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218587692 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.4218587692
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.3874089272
Short name T729
Test name
Test status
Simulation time 2427919908 ps
CPU time 12.77 seconds
Started Feb 08 05:26:55 PM UTC 25
Finished Feb 08 05:27:09 PM UTC 25
Peak memory 212804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874089272 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3874089272
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.3975324910
Short name T929
Test name
Test status
Simulation time 343329584284 ps
CPU time 2594.93 seconds
Started Feb 08 05:28:06 PM UTC 25
Finished Feb 08 06:11:48 PM UTC 25
Peak memory 391572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975324910 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.3975324910
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1945342413
Short name T116
Test name
Test status
Simulation time 260168337 ps
CPU time 14.39 seconds
Started Feb 08 05:28:06 PM UTC 25
Finished Feb 08 05:28:22 PM UTC 25
Peak memory 222940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945342413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1945342413
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.4199879703
Short name T774
Test name
Test status
Simulation time 3616214089 ps
CPU time 303.98 seconds
Started Feb 08 05:27:10 PM UTC 25
Finished Feb 08 05:32:19 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199879703 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.4199879703
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2560365652
Short name T748
Test name
Test status
Simulation time 1576926093 ps
CPU time 66.43 seconds
Started Feb 08 05:27:24 PM UTC 25
Finished Feb 08 05:28:33 PM UTC 25
Peak memory 336436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560365652
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_throughput_w_partial_
write.2560365652
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.342279111
Short name T771
Test name
Test status
Simulation time 4351585468 ps
CPU time 161.88 seconds
Started Feb 08 05:28:51 PM UTC 25
Finished Feb 08 05:31:36 PM UTC 25
Peak memory 379576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342279111 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during_key_req.342279111
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1787515500
Short name T760
Test name
Test status
Simulation time 60974136 ps
CPU time 0.97 seconds
Started Feb 08 05:30:20 PM UTC 25
Finished Feb 08 05:30:22 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787515500 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.1787515500
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.3569646352
Short name T864
Test name
Test status
Simulation time 63478233476 ps
CPU time 1041.9 seconds
Started Feb 08 05:28:22 PM UTC 25
Finished Feb 08 05:45:56 PM UTC 25
Peak memory 212800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569646352 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.3569646352
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.264442527
Short name T812
Test name
Test status
Simulation time 13121287185 ps
CPU time 544.17 seconds
Started Feb 08 05:29:08 PM UTC 25
Finished Feb 08 05:38:19 PM UTC 25
Peak memory 385720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264442527 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.264442527
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3612863547
Short name T765
Test name
Test status
Simulation time 13527064739 ps
CPU time 137.33 seconds
Started Feb 08 05:28:47 PM UTC 25
Finished Feb 08 05:31:07 PM UTC 25
Peak memory 222984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612863547 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.3612863547
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.174326193
Short name T754
Test name
Test status
Simulation time 753518531 ps
CPU time 73.89 seconds
Started Feb 08 05:28:34 PM UTC 25
Finished Feb 08 05:29:50 PM UTC 25
Peak memory 355132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174326193 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_max_throughput.174326193
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3357863436
Short name T769
Test name
Test status
Simulation time 3424812359 ps
CPU time 86 seconds
Started Feb 08 05:29:54 PM UTC 25
Finished Feb 08 05:31:23 PM UTC 25
Peak memory 223008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357863436 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.3357863436
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.505127119
Short name T781
Test name
Test status
Simulation time 34521300326 ps
CPU time 175.01 seconds
Started Feb 08 05:29:52 PM UTC 25
Finished Feb 08 05:32:50 PM UTC 25
Peak memory 212716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505127119 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.505127119
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1781321639
Short name T805
Test name
Test status
Simulation time 56477957692 ps
CPU time 546.33 seconds
Started Feb 08 05:28:15 PM UTC 25
Finished Feb 08 05:37:28 PM UTC 25
Peak memory 375536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781321639 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.1781321639
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3303780364
Short name T751
Test name
Test status
Simulation time 1029393647 ps
CPU time 21.21 seconds
Started Feb 08 05:28:28 PM UTC 25
Finished Feb 08 05:28:50 PM UTC 25
Peak memory 254452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303780364 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.3303780364
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2696714033
Short name T841
Test name
Test status
Simulation time 81729255041 ps
CPU time 840.09 seconds
Started Feb 08 05:28:28 PM UTC 25
Finished Feb 08 05:42:38 PM UTC 25
Peak memory 212984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696714033 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access_b2b.2696714033
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2641049261
Short name T757
Test name
Test status
Simulation time 364607953 ps
CPU time 4.09 seconds
Started Feb 08 05:29:50 PM UTC 25
Finished Feb 08 05:29:56 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641049261 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2641049261
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.3988722797
Short name T783
Test name
Test status
Simulation time 4224325568 ps
CPU time 221.15 seconds
Started Feb 08 05:29:27 PM UTC 25
Finished Feb 08 05:33:11 PM UTC 25
Peak memory 387792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988722797 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3988722797
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.4013700580
Short name T747
Test name
Test status
Simulation time 682729304 ps
CPU time 10.59 seconds
Started Feb 08 05:28:15 PM UTC 25
Finished Feb 08 05:28:27 PM UTC 25
Peak memory 212720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013700580 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.4013700580
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.629759665
Short name T937
Test name
Test status
Simulation time 518691683188 ps
CPU time 3403.93 seconds
Started Feb 08 05:30:12 PM UTC 25
Finished Feb 08 06:27:31 PM UTC 25
Peak memory 391464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629759665 -assert n
opostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.629759665
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3413208623
Short name T761
Test name
Test status
Simulation time 1276663346 ps
CPU time 28.08 seconds
Started Feb 08 05:29:57 PM UTC 25
Finished Feb 08 05:30:26 PM UTC 25
Peak memory 222884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413208623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3413208623
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.153127884
Short name T785
Test name
Test status
Simulation time 7158994822 ps
CPU time 305.07 seconds
Started Feb 08 05:28:23 PM UTC 25
Finished Feb 08 05:33:33 PM UTC 25
Peak memory 212980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153127884 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.153127884
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.2771846010
Short name T752
Test name
Test status
Simulation time 1498369001 ps
CPU time 28.55 seconds
Started Feb 08 05:28:37 PM UTC 25
Finished Feb 08 05:29:07 PM UTC 25
Peak memory 285312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771846010
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_throughput_w_partial_
write.2771846010
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2246756217
Short name T818
Test name
Test status
Simulation time 11918935593 ps
CPU time 508.28 seconds
Started Feb 08 05:31:24 PM UTC 25
Finished Feb 08 05:39:58 PM UTC 25
Peak memory 387832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246756217 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during_key_req.2246756217
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2210429646
Short name T778
Test name
Test status
Simulation time 16412892 ps
CPU time 0.93 seconds
Started Feb 08 05:32:25 PM UTC 25
Finished Feb 08 05:32:27 PM UTC 25
Peak memory 212672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210429646 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2210429646
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.3209519563
Short name T928
Test name
Test status
Simulation time 33128968319 ps
CPU time 2436.48 seconds
Started Feb 08 05:30:31 PM UTC 25
Finished Feb 08 06:11:35 PM UTC 25
Peak memory 214816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209519563 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.3209519563
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.4229152239
Short name T817
Test name
Test status
Simulation time 8524672291 ps
CPU time 493.95 seconds
Started Feb 08 05:31:36 PM UTC 25
Finished Feb 08 05:39:55 PM UTC 25
Peak memory 375380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229152239 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.4229152239
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.472821441
Short name T779
Test name
Test status
Simulation time 31845239836 ps
CPU time 75.6 seconds
Started Feb 08 05:31:20 PM UTC 25
Finished Feb 08 05:32:38 PM UTC 25
Peak memory 212684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472821441 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.472821441
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1108788179
Short name T780
Test name
Test status
Simulation time 1573778810 ps
CPU time 80.18 seconds
Started Feb 08 05:31:18 PM UTC 25
Finished Feb 08 05:32:40 PM UTC 25
Peak memory 363112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108788179
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_max_throughput.1108788179
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3230837417
Short name T788
Test name
Test status
Simulation time 47147894082 ps
CPU time 111.59 seconds
Started Feb 08 05:32:19 PM UTC 25
Finished Feb 08 05:34:13 PM UTC 25
Peak memory 225024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230837417 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.3230837417
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3705176802
Short name T809
Test name
Test status
Simulation time 42003242833 ps
CPU time 338.57 seconds
Started Feb 08 05:32:15 PM UTC 25
Finished Feb 08 05:37:58 PM UTC 25
Peak memory 222956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705176802 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.3705176802
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1460807263
Short name T776
Test name
Test status
Simulation time 5952674551 ps
CPU time 114.76 seconds
Started Feb 08 05:30:27 PM UTC 25
Finished Feb 08 05:32:24 PM UTC 25
Peak memory 350876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460807263 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.1460807263
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.4293614642
Short name T766
Test name
Test status
Simulation time 1496469604 ps
CPU time 12 seconds
Started Feb 08 05:31:04 PM UTC 25
Finished Feb 08 05:31:17 PM UTC 25
Peak memory 223704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293614642 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.4293614642
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1368874189
Short name T798
Test name
Test status
Simulation time 16830294607 ps
CPU time 268.49 seconds
Started Feb 08 05:31:08 PM UTC 25
Finished Feb 08 05:35:41 PM UTC 25
Peak memory 212716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368874189 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access_b2b.1368874189
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1313786426
Short name T773
Test name
Test status
Simulation time 674798535 ps
CPU time 4.81 seconds
Started Feb 08 05:32:08 PM UTC 25
Finished Feb 08 05:32:14 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313786426 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1313786426
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.1067083476
Short name T901
Test name
Test status
Simulation time 97899376152 ps
CPU time 1328.99 seconds
Started Feb 08 05:31:37 PM UTC 25
Finished Feb 08 05:54:00 PM UTC 25
Peak memory 391928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067083476 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1067083476
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.3494371395
Short name T762
Test name
Test status
Simulation time 356358703 ps
CPU time 6.01 seconds
Started Feb 08 05:30:23 PM UTC 25
Finished Feb 08 05:30:30 PM UTC 25
Peak memory 212692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494371395 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3494371395
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1137945876
Short name T925
Test name
Test status
Simulation time 144467143592 ps
CPU time 2208.68 seconds
Started Feb 08 05:32:24 PM UTC 25
Finished Feb 08 06:09:36 PM UTC 25
Peak memory 399712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137945876 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.1137945876
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2713510077
Short name T792
Test name
Test status
Simulation time 4286699299 ps
CPU time 131.28 seconds
Started Feb 08 05:32:21 PM UTC 25
Finished Feb 08 05:34:35 PM UTC 25
Peak memory 279284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713510077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.2713510077
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3635212812
Short name T789
Test name
Test status
Simulation time 12812751749 ps
CPU time 203.37 seconds
Started Feb 08 05:30:49 PM UTC 25
Finished Feb 08 05:34:16 PM UTC 25
Peak memory 212984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635212812 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.3635212812
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.1521494914
Short name T777
Test name
Test status
Simulation time 784887881 ps
CPU time 63.56 seconds
Started Feb 08 05:31:19 PM UTC 25
Finished Feb 08 05:32:25 PM UTC 25
Peak memory 320128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521494914
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_throughput_w_partial_
write.1521494914
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1044890828
Short name T880
Test name
Test status
Simulation time 38742390359 ps
CPU time 829.3 seconds
Started Feb 08 05:34:12 PM UTC 25
Finished Feb 08 05:48:10 PM UTC 25
Peak memory 387720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044890828 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during_key_req.1044890828
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1601070459
Short name T795
Test name
Test status
Simulation time 49254504 ps
CPU time 0.98 seconds
Started Feb 08 05:35:19 PM UTC 25
Finished Feb 08 05:35:21 PM UTC 25
Peak memory 212004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601070459 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1601070459
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.985295288
Short name T870
Test name
Test status
Simulation time 12267285644 ps
CPU time 866.6 seconds
Started Feb 08 05:32:42 PM UTC 25
Finished Feb 08 05:47:18 PM UTC 25
Peak memory 212660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985295288 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.985295288
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.505152126
Short name T799
Test name
Test status
Simulation time 2031884243 ps
CPU time 96.41 seconds
Started Feb 08 05:34:13 PM UTC 25
Finished Feb 08 05:35:51 PM UTC 25
Peak memory 336424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505152126 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.505152126
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.444696707
Short name T796
Test name
Test status
Simulation time 15745010678 ps
CPU time 77.1 seconds
Started Feb 08 05:34:03 PM UTC 25
Finished Feb 08 05:35:22 PM UTC 25
Peak memory 212764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444696707 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.444696707
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.92449221
Short name T786
Test name
Test status
Simulation time 742152722 ps
CPU time 47.37 seconds
Started Feb 08 05:33:22 PM UTC 25
Finished Feb 08 05:34:11 PM UTC 25
Peak memory 320124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92449221 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_max_throughput.92449221
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2123968825
Short name T800
Test name
Test status
Simulation time 1646475136 ps
CPU time 119.51 seconds
Started Feb 08 05:34:28 PM UTC 25
Finished Feb 08 05:36:30 PM UTC 25
Peak memory 222824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123968825 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.2123968825
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3609372525
Short name T803
Test name
Test status
Simulation time 11619761436 ps
CPU time 166.81 seconds
Started Feb 08 05:34:25 PM UTC 25
Finished Feb 08 05:37:15 PM UTC 25
Peak memory 223000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609372525 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.3609372525
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.271993900
Short name T873
Test name
Test status
Simulation time 32851169926 ps
CPU time 888.07 seconds
Started Feb 08 05:32:38 PM UTC 25
Finished Feb 08 05:47:36 PM UTC 25
Peak memory 390096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271993900 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.271993900
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3756826247
Short name T791
Test name
Test status
Simulation time 1025414489 ps
CPU time 86.27 seconds
Started Feb 08 05:32:59 PM UTC 25
Finished Feb 08 05:34:27 PM UTC 25
Peak memory 358960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756826247 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.3756826247
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.37475447
Short name T831
Test name
Test status
Simulation time 62751697757 ps
CPU time 492.91 seconds
Started Feb 08 05:33:12 PM UTC 25
Finished Feb 08 05:41:31 PM UTC 25
Peak memory 212916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37475447 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access_b2b.37475447
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3138798101
Short name T790
Test name
Test status
Simulation time 1403936570 ps
CPU time 6.43 seconds
Started Feb 08 05:34:17 PM UTC 25
Finished Feb 08 05:34:24 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138798101 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3138798101
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.3753667041
Short name T823
Test name
Test status
Simulation time 1784245126 ps
CPU time 372.37 seconds
Started Feb 08 05:34:14 PM UTC 25
Finished Feb 08 05:40:31 PM UTC 25
Peak memory 383576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753667041 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3753667041
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.718756921
Short name T782
Test name
Test status
Simulation time 3246277161 ps
CPU time 27.65 seconds
Started Feb 08 05:32:28 PM UTC 25
Finished Feb 08 05:32:58 PM UTC 25
Peak memory 212696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718756921 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.718756921
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1390219209
Short name T931
Test name
Test status
Simulation time 36121090337 ps
CPU time 2320.26 seconds
Started Feb 08 05:35:02 PM UTC 25
Finished Feb 08 06:14:08 PM UTC 25
Peak memory 393484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390219209 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.1390219209
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3696348235
Short name T793
Test name
Test status
Simulation time 2562461754 ps
CPU time 23.41 seconds
Started Feb 08 05:34:36 PM UTC 25
Finished Feb 08 05:35:01 PM UTC 25
Peak memory 222992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696348235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3696348235
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.3418037582
Short name T810
Test name
Test status
Simulation time 14572469087 ps
CPU time 304.59 seconds
Started Feb 08 05:32:51 PM UTC 25
Finished Feb 08 05:38:00 PM UTC 25
Peak memory 212792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418037582 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.3418037582
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.355125606
Short name T787
Test name
Test status
Simulation time 724185880 ps
CPU time 36.29 seconds
Started Feb 08 05:33:34 PM UTC 25
Finished Feb 08 05:34:12 PM UTC 25
Peak memory 289412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355125606
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_throughput_w_partial_w
rite.355125606
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3793918428
Short name T876
Test name
Test status
Simulation time 15699474932 ps
CPU time 627.04 seconds
Started Feb 08 05:37:17 PM UTC 25
Finished Feb 08 05:47:52 PM UTC 25
Peak memory 385752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793918428 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during_key_req.3793918428
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3151907030
Short name T813
Test name
Test status
Simulation time 16583484 ps
CPU time 1.01 seconds
Started Feb 08 05:38:18 PM UTC 25
Finished Feb 08 05:38:20 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151907030 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.3151907030
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.255540168
Short name T914
Test name
Test status
Simulation time 158483245614 ps
CPU time 1346.01 seconds
Started Feb 08 05:35:39 PM UTC 25
Finished Feb 08 05:58:19 PM UTC 25
Peak memory 212712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255540168 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.255540168
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.4293971452
Short name T903
Test name
Test status
Simulation time 27452456799 ps
CPU time 1035.25 seconds
Started Feb 08 05:37:30 PM UTC 25
Finished Feb 08 05:54:55 PM UTC 25
Peak memory 388020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293971452 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.4293971452
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3802374007
Short name T822
Test name
Test status
Simulation time 18313671386 ps
CPU time 190.03 seconds
Started Feb 08 05:37:15 PM UTC 25
Finished Feb 08 05:40:29 PM UTC 25
Peak memory 222932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802374007 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.3802374007
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2575739446
Short name T804
Test name
Test status
Simulation time 3026881336 ps
CPU time 42.59 seconds
Started Feb 08 05:36:32 PM UTC 25
Finished Feb 08 05:37:16 PM UTC 25
Peak memory 312068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575739446
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_max_throughput.2575739446
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.111659869
Short name T826
Test name
Test status
Simulation time 5263959849 ps
CPU time 189.44 seconds
Started Feb 08 05:37:51 PM UTC 25
Finished Feb 08 05:41:04 PM UTC 25
Peak memory 223216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111659869 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.111659869
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2824372064
Short name T839
Test name
Test status
Simulation time 17134678063 ps
CPU time 266.06 seconds
Started Feb 08 05:37:51 PM UTC 25
Finished Feb 08 05:42:21 PM UTC 25
Peak memory 223000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824372064 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.2824372064
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3726490491
Short name T832
Test name
Test status
Simulation time 9111507755 ps
CPU time 370.86 seconds
Started Feb 08 05:35:22 PM UTC 25
Finished Feb 08 05:41:38 PM UTC 25
Peak memory 375436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726490491 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.3726490491
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1599989705
Short name T802
Test name
Test status
Simulation time 763169018 ps
CPU time 45.14 seconds
Started Feb 08 05:35:52 PM UTC 25
Finished Feb 08 05:36:39 PM UTC 25
Peak memory 312120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599989705 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.1599989705
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1383611399
Short name T834
Test name
Test status
Simulation time 11538334433 ps
CPU time 318.39 seconds
Started Feb 08 05:36:31 PM UTC 25
Finished Feb 08 05:41:54 PM UTC 25
Peak memory 212848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383611399 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access_b2b.1383611399
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3451627254
Short name T808
Test name
Test status
Simulation time 361595061 ps
CPU time 5.87 seconds
Started Feb 08 05:37:43 PM UTC 25
Finished Feb 08 05:37:50 PM UTC 25
Peak memory 212660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451627254 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3451627254
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.154333725
Short name T815
Test name
Test status
Simulation time 13957617620 ps
CPU time 93.87 seconds
Started Feb 08 05:37:33 PM UTC 25
Finished Feb 08 05:39:09 PM UTC 25
Peak memory 320228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154333725 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.154333725
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.4080701635
Short name T797
Test name
Test status
Simulation time 943047747 ps
CPU time 13.79 seconds
Started Feb 08 05:35:22 PM UTC 25
Finished Feb 08 05:35:37 PM UTC 25
Peak memory 212924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080701635 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.4080701635
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2545878829
Short name T893
Test name
Test status
Simulation time 340634335613 ps
CPU time 726.63 seconds
Started Feb 08 05:38:01 PM UTC 25
Finished Feb 08 05:50:15 PM UTC 25
Peak memory 383712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545878829 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.2545878829
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1038167007
Short name T811
Test name
Test status
Simulation time 369249528 ps
CPU time 16.57 seconds
Started Feb 08 05:37:58 PM UTC 25
Finished Feb 08 05:38:16 PM UTC 25
Peak memory 222896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038167007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1038167007
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.3741411413
Short name T836
Test name
Test status
Simulation time 4759105327 ps
CPU time 377.01 seconds
Started Feb 08 05:35:42 PM UTC 25
Finished Feb 08 05:42:04 PM UTC 25
Peak memory 213036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741411413 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.3741411413
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.453454359
Short name T807
Test name
Test status
Simulation time 7595268236 ps
CPU time 60.43 seconds
Started Feb 08 05:36:39 PM UTC 25
Finished Feb 08 05:37:41 PM UTC 25
Peak memory 349192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453454359
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_throughput_w_partial_w
rite.453454359
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1404546478
Short name T911
Test name
Test status
Simulation time 129569137130 ps
CPU time 1026.64 seconds
Started Feb 08 05:40:23 PM UTC 25
Finished Feb 08 05:57:41 PM UTC 25
Peak memory 387840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404546478 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during_key_req.1404546478
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2363648994
Short name T830
Test name
Test status
Simulation time 60281224 ps
CPU time 0.91 seconds
Started Feb 08 05:41:18 PM UTC 25
Finished Feb 08 05:41:20 PM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363648994 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2363648994
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.30175984
Short name T906
Test name
Test status
Simulation time 240996790591 ps
CPU time 998.94 seconds
Started Feb 08 05:38:52 PM UTC 25
Finished Feb 08 05:55:42 PM UTC 25
Peak memory 212736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30175984 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.30175984
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.2009909976
Short name T912
Test name
Test status
Simulation time 45786855723 ps
CPU time 1024.84 seconds
Started Feb 08 05:40:30 PM UTC 25
Finished Feb 08 05:57:46 PM UTC 25
Peak memory 387728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009909976 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.2009909976
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1211543013
Short name T835
Test name
Test status
Simulation time 38364351939 ps
CPU time 109.86 seconds
Started Feb 08 05:40:10 PM UTC 25
Finished Feb 08 05:42:02 PM UTC 25
Peak memory 222924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211543013 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.1211543013
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.756096604
Short name T820
Test name
Test status
Simulation time 1361374935 ps
CPU time 8.83 seconds
Started Feb 08 05:39:59 PM UTC 25
Finished Feb 08 05:40:09 PM UTC 25
Peak memory 212416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756096604 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_max_throughput.756096604
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1331540932
Short name T844
Test name
Test status
Simulation time 2900434404 ps
CPU time 103.76 seconds
Started Feb 08 05:41:05 PM UTC 25
Finished Feb 08 05:42:51 PM UTC 25
Peak memory 222952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331540932 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.1331540932
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.622197649
Short name T847
Test name
Test status
Simulation time 2061803865 ps
CPU time 141.65 seconds
Started Feb 08 05:40:45 PM UTC 25
Finished Feb 08 05:43:09 PM UTC 25
Peak memory 222824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622197649 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.622197649
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3942846843
Short name T860
Test name
Test status
Simulation time 3705074200 ps
CPU time 405.11 seconds
Started Feb 08 05:38:21 PM UTC 25
Finished Feb 08 05:45:11 PM UTC 25
Peak memory 381680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942846843 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.3942846843
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.302326658
Short name T828
Test name
Test status
Simulation time 4750778578 ps
CPU time 76.41 seconds
Started Feb 08 05:39:56 PM UTC 25
Finished Feb 08 05:41:15 PM UTC 25
Peak memory 340716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302326658 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.302326658
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.4027164869
Short name T868
Test name
Test status
Simulation time 83369521086 ps
CPU time 377.89 seconds
Started Feb 08 05:39:56 PM UTC 25
Finished Feb 08 05:46:20 PM UTC 25
Peak memory 212740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027164869 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access_b2b.4027164869
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3782340316
Short name T825
Test name
Test status
Simulation time 354228337 ps
CPU time 6.01 seconds
Started Feb 08 05:40:37 PM UTC 25
Finished Feb 08 05:40:44 PM UTC 25
Peak memory 212936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782340316 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3782340316
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.1998707743
Short name T854
Test name
Test status
Simulation time 19039381142 ps
CPU time 248.09 seconds
Started Feb 08 05:40:32 PM UTC 25
Finished Feb 08 05:44:44 PM UTC 25
Peak memory 386040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998707743 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1998707743
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1661930724
Short name T814
Test name
Test status
Simulation time 5558831312 ps
CPU time 29.7 seconds
Started Feb 08 05:38:20 PM UTC 25
Finished Feb 08 05:38:51 PM UTC 25
Peak memory 212736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661930724 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1661930724
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3317996495
Short name T941
Test name
Test status
Simulation time 194002144965 ps
CPU time 3617.67 seconds
Started Feb 08 05:41:15 PM UTC 25
Finished Feb 08 06:42:12 PM UTC 25
Peak memory 391456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317996495 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.3317996495
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.506175738
Short name T846
Test name
Test status
Simulation time 7088549301 ps
CPU time 118.87 seconds
Started Feb 08 05:41:05 PM UTC 25
Finished Feb 08 05:43:06 PM UTC 25
Peak memory 299828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506175738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.506175738
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2041793281
Short name T855
Test name
Test status
Simulation time 15554523379 ps
CPU time 329.94 seconds
Started Feb 08 05:39:10 PM UTC 25
Finished Feb 08 05:44:45 PM UTC 25
Peak memory 213012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041793281 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.2041793281
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.180815797
Short name T821
Test name
Test status
Simulation time 710076918 ps
CPU time 13.96 seconds
Started Feb 08 05:40:07 PM UTC 25
Finished Feb 08 05:40:22 PM UTC 25
Peak memory 230020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180815797
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_throughput_w_partial_w
rite.180815797
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.1851146707
Short name T857
Test name
Test status
Simulation time 3516266242 ps
CPU time 152.57 seconds
Started Feb 08 05:42:22 PM UTC 25
Finished Feb 08 05:44:57 PM UTC 25
Peak memory 350868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851146707 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during_key_req.1851146707
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1128775276
Short name T849
Test name
Test status
Simulation time 47025469 ps
CPU time 0.97 seconds
Started Feb 08 05:43:10 PM UTC 25
Finished Feb 08 05:43:12 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128775276 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1128775276
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.1979042227
Short name T924
Test name
Test status
Simulation time 83876872990 ps
CPU time 1652.58 seconds
Started Feb 08 05:41:39 PM UTC 25
Finished Feb 08 06:09:29 PM UTC 25
Peak memory 214424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979042227 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.1979042227
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.4206788123
Short name T919
Test name
Test status
Simulation time 95876489432 ps
CPU time 1157.75 seconds
Started Feb 08 05:42:34 PM UTC 25
Finished Feb 08 06:02:04 PM UTC 25
Peak memory 381620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206788123 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.4206788123
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3192380434
Short name T842
Test name
Test status
Simulation time 9472825924 ps
CPU time 23.2 seconds
Started Feb 08 05:42:16 PM UTC 25
Finished Feb 08 05:42:41 PM UTC 25
Peak memory 227156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192380434 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.3192380434
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.3597571863
Short name T838
Test name
Test status
Simulation time 842859587 ps
CPU time 10.62 seconds
Started Feb 08 05:42:04 PM UTC 25
Finished Feb 08 05:42:16 PM UTC 25
Peak memory 230184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597571863
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_max_throughput.3597571863
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2466200707
Short name T851
Test name
Test status
Simulation time 10924788944 ps
CPU time 80.35 seconds
Started Feb 08 05:42:52 PM UTC 25
Finished Feb 08 05:44:14 PM UTC 25
Peak memory 222968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466200707 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.2466200707
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.548795772
Short name T886
Test name
Test status
Simulation time 20665105674 ps
CPU time 382.2 seconds
Started Feb 08 05:42:50 PM UTC 25
Finished Feb 08 05:49:17 PM UTC 25
Peak memory 212744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548795772 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.548795772
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.2690589723
Short name T848
Test name
Test status
Simulation time 2204004391 ps
CPU time 97.71 seconds
Started Feb 08 05:41:32 PM UTC 25
Finished Feb 08 05:43:11 PM UTC 25
Peak memory 314096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690589723 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.2690589723
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.4016982739
Short name T837
Test name
Test status
Simulation time 3184391550 ps
CPU time 17.38 seconds
Started Feb 08 05:41:55 PM UTC 25
Finished Feb 08 05:42:14 PM UTC 25
Peak memory 242592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016982739 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.4016982739
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.702828145
Short name T888
Test name
Test status
Simulation time 7134049906 ps
CPU time 434.53 seconds
Started Feb 08 05:42:03 PM UTC 25
Finished Feb 08 05:49:23 PM UTC 25
Peak memory 212852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702828145 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access_b2b.702828145
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.441617613
Short name T843
Test name
Test status
Simulation time 1464608683 ps
CPU time 6.05 seconds
Started Feb 08 05:42:42 PM UTC 25
Finished Feb 08 05:42:49 PM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441617613 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.441617613
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.1538363604
Short name T897
Test name
Test status
Simulation time 19089083031 ps
CPU time 551.35 seconds
Started Feb 08 05:42:39 PM UTC 25
Finished Feb 08 05:51:57 PM UTC 25
Peak memory 385972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538363604 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.1538363604
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.3396941818
Short name T845
Test name
Test status
Simulation time 2694637346 ps
CPU time 97.06 seconds
Started Feb 08 05:41:22 PM UTC 25
Finished Feb 08 05:43:01 PM UTC 25
Peak memory 379584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396941818 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3396941818
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1584412074
Short name T936
Test name
Test status
Simulation time 444905292247 ps
CPU time 2415.72 seconds
Started Feb 08 05:43:07 PM UTC 25
Finished Feb 08 06:23:47 PM UTC 25
Peak memory 393568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584412074 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.1584412074
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.182614542
Short name T117
Test name
Test status
Simulation time 1992898472 ps
CPU time 76.25 seconds
Started Feb 08 05:43:02 PM UTC 25
Finished Feb 08 05:44:20 PM UTC 25
Peak memory 222956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182614542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.182614542
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.208870932
Short name T877
Test name
Test status
Simulation time 4225316682 ps
CPU time 372.04 seconds
Started Feb 08 05:41:41 PM UTC 25
Finished Feb 08 05:47:58 PM UTC 25
Peak memory 212816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208870932 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.208870932
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1011722155
Short name T850
Test name
Test status
Simulation time 1705285527 ps
CPU time 115.25 seconds
Started Feb 08 05:42:14 PM UTC 25
Finished Feb 08 05:44:12 PM UTC 25
Peak memory 383616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011722155
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_throughput_w_partial_
write.1011722155
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.2812785480
Short name T913
Test name
Test status
Simulation time 12678332592 ps
CPU time 775.03 seconds
Started Feb 08 05:44:57 PM UTC 25
Finished Feb 08 05:58:01 PM UTC 25
Peak memory 389872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812785480 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during_key_req.2812785480
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3512721272
Short name T865
Test name
Test status
Simulation time 39394107 ps
CPU time 0.93 seconds
Started Feb 08 05:45:57 PM UTC 25
Finished Feb 08 05:45:59 PM UTC 25
Peak memory 212556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512721272 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3512721272
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.2152133002
Short name T916
Test name
Test status
Simulation time 11280615176 ps
CPU time 843.08 seconds
Started Feb 08 05:44:12 PM UTC 25
Finished Feb 08 05:58:26 PM UTC 25
Peak memory 212792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152133002 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.2152133002
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.1771174233
Short name T899
Test name
Test status
Simulation time 17517390374 ps
CPU time 535.04 seconds
Started Feb 08 05:44:58 PM UTC 25
Finished Feb 08 05:53:59 PM UTC 25
Peak memory 385684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771174233 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.1771174233
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.4133319610
Short name T862
Test name
Test status
Simulation time 14560069715 ps
CPU time 30.85 seconds
Started Feb 08 05:44:46 PM UTC 25
Finished Feb 08 05:45:18 PM UTC 25
Peak memory 223260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133319610 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.4133319610
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.740603944
Short name T858
Test name
Test status
Simulation time 1801250925 ps
CPU time 19.25 seconds
Started Feb 08 05:44:38 PM UTC 25
Finished Feb 08 05:44:58 PM UTC 25
Peak memory 270968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740603944 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_max_throughput.740603944
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.601128391
Short name T885
Test name
Test status
Simulation time 10213701013 ps
CPU time 216.54 seconds
Started Feb 08 05:45:18 PM UTC 25
Finished Feb 08 05:48:59 PM UTC 25
Peak memory 223052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601128391 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.601128391
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3044881590
Short name T872
Test name
Test status
Simulation time 6584791537 ps
CPU time 132.33 seconds
Started Feb 08 05:45:11 PM UTC 25
Finished Feb 08 05:47:26 PM UTC 25
Peak memory 223000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044881590 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.3044881590
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.1258632785
Short name T907
Test name
Test status
Simulation time 42205675758 ps
CPU time 763.73 seconds
Started Feb 08 05:43:13 PM UTC 25
Finished Feb 08 05:56:04 PM UTC 25
Peak memory 389796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258632785 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.1258632785
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.251742338
Short name T853
Test name
Test status
Simulation time 3011313317 ps
CPU time 14.79 seconds
Started Feb 08 05:44:21 PM UTC 25
Finished Feb 08 05:44:37 PM UTC 25
Peak memory 212776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251742338 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.251742338
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2908196476
Short name T895
Test name
Test status
Simulation time 29833001663 ps
CPU time 386.21 seconds
Started Feb 08 05:44:31 PM UTC 25
Finished Feb 08 05:51:02 PM UTC 25
Peak memory 212772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908196476 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access_b2b.2908196476
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.580653163
Short name T861
Test name
Test status
Simulation time 345228724 ps
CPU time 5.45 seconds
Started Feb 08 05:45:11 PM UTC 25
Finished Feb 08 05:45:18 PM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580653163 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.580653163
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.2466554341
Short name T908
Test name
Test status
Simulation time 19361218572 ps
CPU time 680.02 seconds
Started Feb 08 05:44:59 PM UTC 25
Finished Feb 08 05:56:27 PM UTC 25
Peak memory 387828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466554341 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2466554341
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.321692260
Short name T852
Test name
Test status
Simulation time 4671294717 ps
CPU time 76.21 seconds
Started Feb 08 05:43:12 PM UTC 25
Finished Feb 08 05:44:30 PM UTC 25
Peak memory 332444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321692260 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.321692260
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2125563302
Short name T946
Test name
Test status
Simulation time 262118639322 ps
CPU time 7622.59 seconds
Started Feb 08 05:45:54 PM UTC 25
Finished Feb 08 07:54:16 PM UTC 25
Peak memory 399624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125563302 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.2125563302
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2572837678
Short name T863
Test name
Test status
Simulation time 629365082 ps
CPU time 31.93 seconds
Started Feb 08 05:45:19 PM UTC 25
Finished Feb 08 05:45:53 PM UTC 25
Peak memory 222836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572837678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2572837678
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1900664619
Short name T887
Test name
Test status
Simulation time 3886913671 ps
CPU time 301.03 seconds
Started Feb 08 05:44:14 PM UTC 25
Finished Feb 08 05:49:20 PM UTC 25
Peak memory 212720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900664619 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.1900664619
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3100852421
Short name T867
Test name
Test status
Simulation time 1558618347 ps
CPU time 82.65 seconds
Started Feb 08 05:44:45 PM UTC 25
Finished Feb 08 05:46:09 PM UTC 25
Peak memory 377572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100852421
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_throughput_w_partial_
write.3100852421
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.2929706391
Short name T917
Test name
Test status
Simulation time 11349675751 ps
CPU time 655.86 seconds
Started Feb 08 05:47:40 PM UTC 25
Finished Feb 08 05:58:43 PM UTC 25
Peak memory 383884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929706391 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during_key_req.2929706391
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3230702244
Short name T883
Test name
Test status
Simulation time 86676284 ps
CPU time 0.94 seconds
Started Feb 08 05:48:35 PM UTC 25
Finished Feb 08 05:48:37 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230702244 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.3230702244
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.278465397
Short name T939
Test name
Test status
Simulation time 136345745162 ps
CPU time 2704.52 seconds
Started Feb 08 05:46:10 PM UTC 25
Finished Feb 08 06:31:44 PM UTC 25
Peak memory 214424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278465397 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.278465397
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.591623534
Short name T909
Test name
Test status
Simulation time 52628648667 ps
CPU time 527.02 seconds
Started Feb 08 05:47:48 PM UTC 25
Finished Feb 08 05:56:41 PM UTC 25
Peak memory 385684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591623534 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.591623534
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.2571620003
Short name T881
Test name
Test status
Simulation time 19667790234 ps
CPU time 35.73 seconds
Started Feb 08 05:47:37 PM UTC 25
Finished Feb 08 05:48:14 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571620003 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.2571620003
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3061716755
Short name T884
Test name
Test status
Simulation time 791767675 ps
CPU time 88.58 seconds
Started Feb 08 05:47:19 PM UTC 25
Finished Feb 08 05:48:50 PM UTC 25
Peak memory 350780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061716755
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_max_throughput.3061716755
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.88374453
Short name T889
Test name
Test status
Simulation time 2750550919 ps
CPU time 89.08 seconds
Started Feb 08 05:48:07 PM UTC 25
Finished Feb 08 05:49:38 PM UTC 25
Peak memory 222992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88374453 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.88374453
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.482324562
Short name T900
Test name
Test status
Simulation time 39513744842 ps
CPU time 351.77 seconds
Started Feb 08 05:48:03 PM UTC 25
Finished Feb 08 05:53:59 PM UTC 25
Peak memory 223056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482324562 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.482324562
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.719355488
Short name T920
Test name
Test status
Simulation time 48994821714 ps
CPU time 1076.29 seconds
Started Feb 08 05:46:06 PM UTC 25
Finished Feb 08 06:04:13 PM UTC 25
Peak memory 387744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719355488 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.719355488
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.773214511
Short name T871
Test name
Test status
Simulation time 11119081744 ps
CPU time 27.38 seconds
Started Feb 08 05:46:50 PM UTC 25
Finished Feb 08 05:47:19 PM UTC 25
Peak memory 212776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773214511 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.773214511
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.522717493
Short name T896
Test name
Test status
Simulation time 36534612031 ps
CPU time 229.21 seconds
Started Feb 08 05:47:18 PM UTC 25
Finished Feb 08 05:51:11 PM UTC 25
Peak memory 212728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522717493 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access_b2b.522717493
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.4147313010
Short name T879
Test name
Test status
Simulation time 2405006041 ps
CPU time 5.8 seconds
Started Feb 08 05:47:59 PM UTC 25
Finished Feb 08 05:48:06 PM UTC 25
Peak memory 212792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147313010 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.4147313010
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2160347672
Short name T923
Test name
Test status
Simulation time 5948992348 ps
CPU time 1136.86 seconds
Started Feb 08 05:47:53 PM UTC 25
Finished Feb 08 06:07:01 PM UTC 25
Peak memory 390136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160347672 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2160347672
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.952994661
Short name T869
Test name
Test status
Simulation time 788218255 ps
CPU time 47.56 seconds
Started Feb 08 05:46:00 PM UTC 25
Finished Feb 08 05:46:49 PM UTC 25
Peak memory 307760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952994661 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.952994661
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.4050398031
Short name T933
Test name
Test status
Simulation time 14261210253 ps
CPU time 1720.22 seconds
Started Feb 08 05:48:14 PM UTC 25
Finished Feb 08 06:17:12 PM UTC 25
Peak memory 393572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050398031 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.4050398031
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.783278463
Short name T882
Test name
Test status
Simulation time 986329379 ps
CPU time 21.72 seconds
Started Feb 08 05:48:11 PM UTC 25
Finished Feb 08 05:48:34 PM UTC 25
Peak memory 222996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783278463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.783278463
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2631251957
Short name T890
Test name
Test status
Simulation time 2831099684 ps
CPU time 210.28 seconds
Started Feb 08 05:46:21 PM UTC 25
Finished Feb 08 05:49:55 PM UTC 25
Peak memory 212716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631251957 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.2631251957
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.829821043
Short name T878
Test name
Test status
Simulation time 5584054932 ps
CPU time 33.51 seconds
Started Feb 08 05:47:27 PM UTC 25
Finished Feb 08 05:48:02 PM UTC 25
Peak memory 295556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829821043
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_throughput_w_partial_w
rite.829821043
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.18574473
Short name T211
Test name
Test status
Simulation time 16720754342 ps
CPU time 873.72 seconds
Started Feb 08 03:14:41 PM UTC 25
Finished Feb 08 03:29:24 PM UTC 25
Peak memory 388004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18574473 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_key_req.18574473
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3004946803
Short name T180
Test name
Test status
Simulation time 18111051 ps
CPU time 0.85 seconds
Started Feb 08 03:16:50 PM UTC 25
Finished Feb 08 03:16:52 PM UTC 25
Peak memory 211452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004946803 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3004946803
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.1054893089
Short name T199
Test name
Test status
Simulation time 66480817927 ps
CPU time 789.62 seconds
Started Feb 08 03:13:07 PM UTC 25
Finished Feb 08 03:26:26 PM UTC 25
Peak memory 212788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054893089 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.1054893089
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2453125048
Short name T148
Test name
Test status
Simulation time 10342237604 ps
CPU time 559.55 seconds
Started Feb 08 03:15:04 PM UTC 25
Finished Feb 08 03:24:30 PM UTC 25
Peak memory 379572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453125048 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.2453125048
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2881153038
Short name T176
Test name
Test status
Simulation time 784494110 ps
CPU time 49.49 seconds
Started Feb 08 03:14:11 PM UTC 25
Finished Feb 08 03:15:02 PM UTC 25
Peak memory 344960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881153038
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max_throughput.2881153038
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1980142624
Short name T97
Test name
Test status
Simulation time 18286444659 ps
CPU time 190.69 seconds
Started Feb 08 03:15:32 PM UTC 25
Finished Feb 08 03:18:46 PM UTC 25
Peak memory 230028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980142624 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.1980142624
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1271596236
Short name T46
Test name
Test status
Simulation time 121825600557 ps
CPU time 425.35 seconds
Started Feb 08 03:15:26 PM UTC 25
Finished Feb 08 03:22:37 PM UTC 25
Peak memory 223004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271596236 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.1271596236
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3553066791
Short name T201
Test name
Test status
Simulation time 133820579901 ps
CPU time 858.13 seconds
Started Feb 08 03:13:05 PM UTC 25
Finished Feb 08 03:27:32 PM UTC 25
Peak memory 389892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553066791 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.3553066791
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.4006996191
Short name T175
Test name
Test status
Simulation time 6511319057 ps
CPU time 46.09 seconds
Started Feb 08 03:13:52 PM UTC 25
Finished Feb 08 03:14:40 PM UTC 25
Peak memory 212724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006996191 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.4006996191
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3725511662
Short name T190
Test name
Test status
Simulation time 79427984711 ps
CPU time 535 seconds
Started Feb 08 03:13:58 PM UTC 25
Finished Feb 08 03:23:00 PM UTC 25
Peak memory 212844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725511662 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access_b2b.3725511662
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.4256584908
Short name T177
Test name
Test status
Simulation time 345143120 ps
CPU time 4.82 seconds
Started Feb 08 03:15:19 PM UTC 25
Finished Feb 08 03:15:25 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256584908 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.4256584908
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3237231028
Short name T149
Test name
Test status
Simulation time 12339225256 ps
CPU time 580.79 seconds
Started Feb 08 03:15:07 PM UTC 25
Finished Feb 08 03:24:56 PM UTC 25
Peak memory 391868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237231028 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3237231028
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.385060415
Short name T172
Test name
Test status
Simulation time 502830140 ps
CPU time 45.91 seconds
Started Feb 08 03:13:04 PM UTC 25
Finished Feb 08 03:13:51 PM UTC 25
Peak memory 365084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385060415 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.385060415
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3380341776
Short name T898
Test name
Test status
Simulation time 333839095809 ps
CPU time 9220.46 seconds
Started Feb 08 03:16:47 PM UTC 25
Finished Feb 08 05:52:05 PM UTC 25
Peak memory 391764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380341776 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.3380341776
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3526405756
Short name T53
Test name
Test status
Simulation time 17188610184 ps
CPU time 157.5 seconds
Started Feb 08 03:16:17 PM UTC 25
Finished Feb 08 03:18:58 PM UTC 25
Peak memory 322548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526405756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3526405756
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.2681485788
Short name T179
Test name
Test status
Simulation time 6929230764 ps
CPU time 210.64 seconds
Started Feb 08 03:13:12 PM UTC 25
Finished Feb 08 03:16:46 PM UTC 25
Peak memory 212732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681485788 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.2681485788
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.792766370
Short name T174
Test name
Test status
Simulation time 681371925 ps
CPU time 9.91 seconds
Started Feb 08 03:14:24 PM UTC 25
Finished Feb 08 03:14:36 PM UTC 25
Peak memory 223132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792766370
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_throughput_w_partial_wr
ite.792766370
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2046866713
Short name T214
Test name
Test status
Simulation time 11178075878 ps
CPU time 610.54 seconds
Started Feb 08 03:19:18 PM UTC 25
Finished Feb 08 03:29:36 PM UTC 25
Peak memory 391872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046866713 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_key_req.2046866713
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3851468364
Short name T191
Test name
Test status
Simulation time 18843627 ps
CPU time 0.88 seconds
Started Feb 08 03:22:59 PM UTC 25
Finished Feb 08 03:23:01 PM UTC 25
Peak memory 211700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851468364 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3851468364
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.3419850107
Short name T262
Test name
Test status
Simulation time 316633696413 ps
CPU time 1580.56 seconds
Started Feb 08 03:17:12 PM UTC 25
Finished Feb 08 03:43:50 PM UTC 25
Peak memory 214504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419850107 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.3419850107
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3414171828
Short name T207
Test name
Test status
Simulation time 31475187551 ps
CPU time 566.68 seconds
Started Feb 08 03:19:23 PM UTC 25
Finished Feb 08 03:28:57 PM UTC 25
Peak memory 361100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414171828 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.3414171828
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.4267876514
Short name T23
Test name
Test status
Simulation time 13711256000 ps
CPU time 114.51 seconds
Started Feb 08 03:19:08 PM UTC 25
Finished Feb 08 03:21:05 PM UTC 25
Peak memory 229140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267876514 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.4267876514
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1328185196
Short name T184
Test name
Test status
Simulation time 9815708394 ps
CPU time 19.32 seconds
Started Feb 08 03:18:47 PM UTC 25
Finished Feb 08 03:19:08 PM UTC 25
Peak memory 248464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328185196
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max_throughput.1328185196
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3378928380
Short name T54
Test name
Test status
Simulation time 2452750453 ps
CPU time 171.42 seconds
Started Feb 08 03:21:47 PM UTC 25
Finished Feb 08 03:24:42 PM UTC 25
Peak memory 223020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378928380 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.3378928380
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1792634667
Short name T203
Test name
Test status
Simulation time 21884422610 ps
CPU time 397.72 seconds
Started Feb 08 03:21:14 PM UTC 25
Finished Feb 08 03:27:57 PM UTC 25
Peak memory 222924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792634667 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.1792634667
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2137322495
Short name T194
Test name
Test status
Simulation time 8600784638 ps
CPU time 465.33 seconds
Started Feb 08 03:17:10 PM UTC 25
Finished Feb 08 03:25:02 PM UTC 25
Peak memory 387744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137322495 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.2137322495
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1612876798
Short name T183
Test name
Test status
Simulation time 1060732786 ps
CPU time 18.66 seconds
Started Feb 08 03:18:06 PM UTC 25
Finished Feb 08 03:18:26 PM UTC 25
Peak memory 212652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612876798 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.1612876798
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2644952200
Short name T192
Test name
Test status
Simulation time 41480915739 ps
CPU time 324.54 seconds
Started Feb 08 03:18:27 PM UTC 25
Finished Feb 08 03:23:56 PM UTC 25
Peak memory 212760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644952200 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access_b2b.2644952200
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.4069823300
Short name T187
Test name
Test status
Simulation time 360617669 ps
CPU time 5.25 seconds
Started Feb 08 03:21:07 PM UTC 25
Finished Feb 08 03:21:13 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069823300 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.4069823300
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.3125975154
Short name T146
Test name
Test status
Simulation time 2256267436 ps
CPU time 402.45 seconds
Started Feb 08 03:19:36 PM UTC 25
Finished Feb 08 03:26:23 PM UTC 25
Peak memory 387728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125975154 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3125975154
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.2523597639
Short name T181
Test name
Test status
Simulation time 3054391231 ps
CPU time 16.18 seconds
Started Feb 08 03:16:53 PM UTC 25
Finished Feb 08 03:17:11 PM UTC 25
Peak memory 213032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523597639 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.2523597639
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2338477573
Short name T298
Test name
Test status
Simulation time 63943194315 ps
CPU time 2201.69 seconds
Started Feb 08 03:22:56 PM UTC 25
Finished Feb 08 04:00:01 PM UTC 25
Peak memory 391480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338477573 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.2338477573
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.296442239
Short name T66
Test name
Test status
Simulation time 305735036 ps
CPU time 14.6 seconds
Started Feb 08 03:22:38 PM UTC 25
Finished Feb 08 03:22:54 PM UTC 25
Peak memory 222892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296442239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.296442239
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.118857928
Short name T188
Test name
Test status
Simulation time 9178655099 ps
CPU time 225.75 seconds
Started Feb 08 03:17:57 PM UTC 25
Finished Feb 08 03:21:46 PM UTC 25
Peak memory 212984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118857928 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.118857928
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.118246542
Short name T185
Test name
Test status
Simulation time 732647785 ps
CPU time 17.43 seconds
Started Feb 08 03:18:58 PM UTC 25
Finished Feb 08 03:19:17 PM UTC 25
Peak memory 262780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118246542
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_throughput_w_partial_wr
ite.118246542
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.726246039
Short name T208
Test name
Test status
Simulation time 8419164447 ps
CPU time 231.95 seconds
Started Feb 08 03:25:03 PM UTC 25
Finished Feb 08 03:28:58 PM UTC 25
Peak memory 387788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726246039 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_key_req.726246039
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.481873582
Short name T202
Test name
Test status
Simulation time 14545613 ps
CPU time 0.86 seconds
Started Feb 08 03:27:33 PM UTC 25
Finished Feb 08 03:27:35 PM UTC 25
Peak memory 211584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481873582 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.481873582
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1366213695
Short name T267
Test name
Test status
Simulation time 16470232383 ps
CPU time 1314.85 seconds
Started Feb 08 03:23:57 PM UTC 25
Finished Feb 08 03:46:07 PM UTC 25
Peak memory 214308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366213695 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.1366213695
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.828657066
Short name T225
Test name
Test status
Simulation time 14010955051 ps
CPU time 462.86 seconds
Started Feb 08 03:25:10 PM UTC 25
Finished Feb 08 03:32:58 PM UTC 25
Peak memory 375396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828657066 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.828657066
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3907296773
Short name T200
Test name
Test status
Simulation time 12710514714 ps
CPU time 150.18 seconds
Started Feb 08 03:24:57 PM UTC 25
Finished Feb 08 03:27:30 PM UTC 25
Peak memory 212736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907296773 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.3907296773
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1052674047
Short name T196
Test name
Test status
Simulation time 2833526883 ps
CPU time 24.84 seconds
Started Feb 08 03:24:54 PM UTC 25
Finished Feb 08 03:25:21 PM UTC 25
Peak memory 281260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052674047
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max_throughput.1052674047
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3092620512
Short name T55
Test name
Test status
Simulation time 10642763482 ps
CPU time 84.42 seconds
Started Feb 08 03:26:24 PM UTC 25
Finished Feb 08 03:27:50 PM UTC 25
Peak memory 223092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092620512 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.3092620512
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.735931739
Short name T224
Test name
Test status
Simulation time 41399080181 ps
CPU time 397.92 seconds
Started Feb 08 03:26:12 PM UTC 25
Finished Feb 08 03:32:55 PM UTC 25
Peak memory 222976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735931739 -assert nopostproc +UVM_
TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.735931739
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3284472789
Short name T212
Test name
Test status
Simulation time 32698169273 ps
CPU time 380.93 seconds
Started Feb 08 03:23:02 PM UTC 25
Finished Feb 08 03:29:28 PM UTC 25
Peak memory 371280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284472789 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.3284472789
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.59643205
Short name T197
Test name
Test status
Simulation time 2874156958 ps
CPU time 79.64 seconds
Started Feb 08 03:24:42 PM UTC 25
Finished Feb 08 03:26:04 PM UTC 25
Peak memory 371640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59643205 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.59643205
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1864383891
Short name T221
Test name
Test status
Simulation time 19138947031 ps
CPU time 447.18 seconds
Started Feb 08 03:24:42 PM UTC 25
Finished Feb 08 03:32:16 PM UTC 25
Peak memory 212816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864383891 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access_b2b.1864383891
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1506358747
Short name T198
Test name
Test status
Simulation time 691943545 ps
CPU time 4.76 seconds
Started Feb 08 03:26:05 PM UTC 25
Finished Feb 08 03:26:11 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506358747 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1506358747
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3680415262
Short name T242
Test name
Test status
Simulation time 65208091261 ps
CPU time 777.93 seconds
Started Feb 08 03:25:22 PM UTC 25
Finished Feb 08 03:38:29 PM UTC 25
Peak memory 393564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680415262 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3680415262
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.2359321682
Short name T193
Test name
Test status
Simulation time 1549644789 ps
CPU time 98.09 seconds
Started Feb 08 03:23:01 PM UTC 25
Finished Feb 08 03:24:41 PM UTC 25
Peak memory 379692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359321682 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2359321682
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1457172166
Short name T56
Test name
Test status
Simulation time 7671943296 ps
CPU time 136.41 seconds
Started Feb 08 03:26:27 PM UTC 25
Finished Feb 08 03:28:46 PM UTC 25
Peak memory 330444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457172166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1457172166
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1773264428
Short name T205
Test name
Test status
Simulation time 4295255214 ps
CPU time 258.75 seconds
Started Feb 08 03:24:31 PM UTC 25
Finished Feb 08 03:28:54 PM UTC 25
Peak memory 212848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773264428 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.1773264428
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2534398808
Short name T195
Test name
Test status
Simulation time 1394369229 ps
CPU time 10.99 seconds
Started Feb 08 03:24:56 PM UTC 25
Finished Feb 08 03:25:09 PM UTC 25
Peak memory 230064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534398808
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_throughput_w_partial_w
rite.2534398808
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1845346929
Short name T220
Test name
Test status
Simulation time 5559461590 ps
CPU time 189.25 seconds
Started Feb 08 03:28:59 PM UTC 25
Finished Feb 08 03:32:12 PM UTC 25
Peak memory 377820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845346929 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_key_req.1845346929
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3730613271
Short name T279
Test name
Test status
Simulation time 38086997058 ps
CPU time 1579.04 seconds
Started Feb 08 03:27:59 PM UTC 25
Finished Feb 08 03:54:36 PM UTC 25
Peak memory 214480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730613271 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.3730613271
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.184034167
Short name T150
Test name
Test status
Simulation time 12537489501 ps
CPU time 98.11 seconds
Started Feb 08 03:29:06 PM UTC 25
Finished Feb 08 03:30:47 PM UTC 25
Peak memory 385948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184034167 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.184034167
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4243601165
Short name T215
Test name
Test status
Simulation time 8853033958 ps
CPU time 48.28 seconds
Started Feb 08 03:28:58 PM UTC 25
Finished Feb 08 03:29:48 PM UTC 25
Peak memory 223212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243601165 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.4243601165
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.19463090
Short name T210
Test name
Test status
Simulation time 703231821 ps
CPU time 22.49 seconds
Started Feb 08 03:28:54 PM UTC 25
Finished Feb 08 03:29:18 PM UTC 25
Peak memory 262708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19463090 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max_throughput.19463090
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3026711449
Short name T57
Test name
Test status
Simulation time 13796498540 ps
CPU time 88.55 seconds
Started Feb 08 03:29:32 PM UTC 25
Finished Feb 08 03:31:02 PM UTC 25
Peak memory 223236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026711449 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.3026711449
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2258132708
Short name T237
Test name
Test status
Simulation time 43118935281 ps
CPU time 382.37 seconds
Started Feb 08 03:29:29 PM UTC 25
Finished Feb 08 03:35:56 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258132708 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.2258132708
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3687623703
Short name T218
Test name
Test status
Simulation time 25541337061 ps
CPU time 217.94 seconds
Started Feb 08 03:27:52 PM UTC 25
Finished Feb 08 03:31:33 PM UTC 25
Peak memory 386032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687623703 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.3687623703
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.4109622897
Short name T206
Test name
Test status
Simulation time 3696119048 ps
CPU time 43.56 seconds
Started Feb 08 03:28:11 PM UTC 25
Finished Feb 08 03:28:56 PM UTC 25
Peak memory 212716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109622897 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.4109622897
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2592158910
Short name T250
Test name
Test status
Simulation time 97767935670 ps
CPU time 703.09 seconds
Started Feb 08 03:28:47 PM UTC 25
Finished Feb 08 03:40:39 PM UTC 25
Peak memory 214568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592158910 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access_b2b.2592158910
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.578021252
Short name T213
Test name
Test status
Simulation time 1354932365 ps
CPU time 4.92 seconds
Started Feb 08 03:29:25 PM UTC 25
Finished Feb 08 03:29:31 PM UTC 25
Peak memory 212668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578021252 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.578021252
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2065363612
Short name T239
Test name
Test status
Simulation time 2696642713 ps
CPU time 442.57 seconds
Started Feb 08 03:29:19 PM UTC 25
Finished Feb 08 03:36:47 PM UTC 25
Peak memory 385804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065363612 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2065363612
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.425951711
Short name T204
Test name
Test status
Simulation time 556569075 ps
CPU time 20.89 seconds
Started Feb 08 03:27:36 PM UTC 25
Finished Feb 08 03:27:59 PM UTC 25
Peak memory 212604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425951711 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sra
m_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.425951711
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1177433447
Short name T261
Test name
Test status
Simulation time 44759630592 ps
CPU time 826.19 seconds
Started Feb 08 03:29:49 PM UTC 25
Finished Feb 08 03:43:45 PM UTC 25
Peak memory 385448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177433447 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.1177433447
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3116900410
Short name T67
Test name
Test status
Simulation time 862997779 ps
CPU time 23.25 seconds
Started Feb 08 03:29:37 PM UTC 25
Finished Feb 08 03:30:01 PM UTC 25
Peak memory 222888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116900410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3116900410
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.340005709
Short name T226
Test name
Test status
Simulation time 5486020518 ps
CPU time 301.3 seconds
Started Feb 08 03:28:00 PM UTC 25
Finished Feb 08 03:33:05 PM UTC 25
Peak memory 212764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340005709 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.340005709
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2799346807
Short name T209
Test name
Test status
Simulation time 1390763358 ps
CPU time 7.03 seconds
Started Feb 08 03:28:57 PM UTC 25
Finished Feb 08 03:29:06 PM UTC 25
Peak memory 224984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799346807
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_throughput_w_partial_w
rite.2799346807
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.841117055
Short name T229
Test name
Test status
Simulation time 9350774899 ps
CPU time 71.88 seconds
Started Feb 08 03:32:46 PM UTC 25
Finished Feb 08 03:34:00 PM UTC 25
Peak memory 310196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841117055 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_key_req.841117055
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.711037656
Short name T231
Test name
Test status
Simulation time 42620123 ps
CPU time 0.86 seconds
Started Feb 08 03:34:26 PM UTC 25
Finished Feb 08 03:34:28 PM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711037656 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.711037656
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2132134185
Short name T245
Test name
Test status
Simulation time 5798033448 ps
CPU time 402.03 seconds
Started Feb 08 03:32:56 PM UTC 25
Finished Feb 08 03:39:43 PM UTC 25
Peak memory 387720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132134185 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.2132134185
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3650285326
Short name T227
Test name
Test status
Simulation time 33185570319 ps
CPU time 36.27 seconds
Started Feb 08 03:32:30 PM UTC 25
Finished Feb 08 03:33:08 PM UTC 25
Peak memory 223240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650285326 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.3650285326
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1662457659
Short name T222
Test name
Test status
Simulation time 1446051046 ps
CPU time 15.21 seconds
Started Feb 08 03:32:13 PM UTC 25
Finished Feb 08 03:32:29 PM UTC 25
Peak memory 250684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662457659
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max_throughput.1662457659
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.590250329
Short name T233
Test name
Test status
Simulation time 30617231361 ps
CPU time 105.71 seconds
Started Feb 08 03:33:12 PM UTC 25
Finished Feb 08 03:35:00 PM UTC 25
Peak memory 223000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590250329 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.590250329
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.4292011985
Short name T234
Test name
Test status
Simulation time 2040641410 ps
CPU time 129.29 seconds
Started Feb 08 03:33:08 PM UTC 25
Finished Feb 08 03:35:20 PM UTC 25
Peak memory 222840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292011985 -assert nopostproc +UVM
_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.4292011985
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.260818569
Short name T235
Test name
Test status
Simulation time 21355078331 ps
CPU time 296.76 seconds
Started Feb 08 03:30:22 PM UTC 25
Finished Feb 08 03:35:23 PM UTC 25
Peak memory 387696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260818569 -assert nopostproc +UVM_TESTNAME=sram_
ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.260818569
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1749707749
Short name T219
Test name
Test status
Simulation time 426615352 ps
CPU time 7 seconds
Started Feb 08 03:31:34 PM UTC 25
Finished Feb 08 03:31:42 PM UTC 25
Peak memory 219028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749707749 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.1749707749
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.422907832
Short name T246
Test name
Test status
Simulation time 29341453336 ps
CPU time 512.34 seconds
Started Feb 08 03:31:43 PM UTC 25
Finished Feb 08 03:40:21 PM UTC 25
Peak memory 212976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422907832 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access_b2b.422907832
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.1767270239
Short name T228
Test name
Test status
Simulation time 360854555 ps
CPU time 4.62 seconds
Started Feb 08 03:33:06 PM UTC 25
Finished Feb 08 03:33:12 PM UTC 25
Peak memory 212748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767270239 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.1767270239
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2908543077
Short name T144
Test name
Test status
Simulation time 11719227503 ps
CPU time 531.77 seconds
Started Feb 08 03:32:59 PM UTC 25
Finished Feb 08 03:41:57 PM UTC 25
Peak memory 385884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908543077 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/s
ram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2908543077
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.3734705637
Short name T217
Test name
Test status
Simulation time 2648039914 ps
CPU time 15.07 seconds
Started Feb 08 03:30:05 PM UTC 25
Finished Feb 08 03:30:21 PM UTC 25
Peak memory 212792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734705637 -assert nopostproc +UVM_TESTNAME=sram
_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sr
am_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3734705637
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3964573118
Short name T306
Test name
Test status
Simulation time 44084627609 ps
CPU time 1649.79 seconds
Started Feb 08 03:34:18 PM UTC 25
Finished Feb 08 04:02:06 PM UTC 25
Peak memory 383336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentati
on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964573118 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.3964573118
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1321163608
Short name T49
Test name
Test status
Simulation time 15347665782 ps
CPU time 51.33 seconds
Started Feb 08 03:34:01 PM UTC 25
Finished Feb 08 03:34:54 PM UTC 25
Peak memory 225128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sr
am_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321163608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1321163608
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2383894034
Short name T230
Test name
Test status
Simulation time 8489275438 ps
CPU time 190.05 seconds
Started Feb 08 03:31:03 PM UTC 25
Finished Feb 08 03:34:17 PM UTC 25
Peak memory 212712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383894034 -assert nopostproc +UV
M_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.2383894034
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3951692130
Short name T223
Test name
Test status
Simulation time 4229792045 ps
CPU time 26.88 seconds
Started Feb 08 03:32:17 PM UTC 25
Finished Feb 08 03:32:45 PM UTC 25
Peak memory 289724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951692130
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_throughput_w_partial_w
rite.3951692130
Directory /workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%