| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 98.64 | 99.50 | 96.05 | 99.72 | 100.00 | 97.34 | 99.13 | 98.72 |
| T1023 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.22816702 | Oct 15 03:00:08 AM UTC 24 | Oct 15 03:00:10 AM UTC 24 | 21242248 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2337707813 | Oct 15 02:59:34 AM UTC 24 | Oct 15 03:00:11 AM UTC 24 | 14804104318 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3878811764 | Oct 15 03:00:06 AM UTC 24 | Oct 15 03:00:12 AM UTC 24 | 732660404 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4284602468 | Oct 15 03:00:13 AM UTC 24 | Oct 15 03:00:15 AM UTC 24 | 25216742 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1526261310 | Oct 15 03:00:09 AM UTC 24 | Oct 15 03:00:16 AM UTC 24 | 1426113883 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1510236169 | Oct 15 03:00:13 AM UTC 24 | Oct 15 03:00:17 AM UTC 24 | 392322879 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2589590247 | Oct 15 03:00:13 AM UTC 24 | Oct 15 03:00:18 AM UTC 24 | 299705098 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1221314377 | Oct 15 03:00:16 AM UTC 24 | Oct 15 03:00:18 AM UTC 24 | 38910988 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3662188228 | Oct 15 03:00:20 AM UTC 24 | Oct 15 03:00:21 AM UTC 24 | 14507554 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.635820032 | Oct 15 03:00:18 AM UTC 24 | Oct 15 03:00:22 AM UTC 24 | 257528138 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.674373767 | Oct 15 03:00:18 AM UTC 24 | Oct 15 03:00:23 AM UTC 24 | 371715245 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2229629196 | Oct 15 03:00:17 AM UTC 24 | Oct 15 03:00:24 AM UTC 24 | 1223052320 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1438277752 | Oct 15 03:00:23 AM UTC 24 | Oct 15 03:00:25 AM UTC 24 | 37136836 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.513788318 | Oct 15 02:58:53 AM UTC 24 | Oct 15 03:00:29 AM UTC 24 | 22774358933 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.575143327 | Oct 15 03:00:26 AM UTC 24 | Oct 15 03:00:31 AM UTC 24 | 368500232 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1902517012 | Oct 15 03:00:29 AM UTC 24 | Oct 15 03:00:31 AM UTC 24 | 11597680 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1478212527 | Oct 15 03:00:25 AM UTC 24 | Oct 15 03:00:33 AM UTC 24 | 1950044688 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2510711058 | Oct 15 03:00:23 AM UTC 24 | Oct 15 03:00:34 AM UTC 24 | 6870454544 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3986339280 | Oct 15 03:00:32 AM UTC 24 | Oct 15 03:00:35 AM UTC 24 | 22566436 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2432394749 | Oct 15 02:59:16 AM UTC 24 | Oct 15 03:00:36 AM UTC 24 | 7041220469 ps | ||
| T94 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4017986900 | Oct 15 02:59:03 AM UTC 24 | Oct 15 03:00:36 AM UTC 24 | 28126828616 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3036274387 | Oct 15 03:00:36 AM UTC 24 | Oct 15 03:00:38 AM UTC 24 | 329476259 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2797885502 | Oct 15 03:00:37 AM UTC 24 | Oct 15 03:00:39 AM UTC 24 | 28074399 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2364542882 | Oct 15 03:00:32 AM UTC 24 | Oct 15 03:00:39 AM UTC 24 | 690066446 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2716968063 | Oct 15 03:00:37 AM UTC 24 | Oct 15 03:00:39 AM UTC 24 | 137171560 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.92605218 | Oct 15 03:00:40 AM UTC 24 | Oct 15 03:00:42 AM UTC 24 | 47412111 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2844825835 | Oct 15 03:00:40 AM UTC 24 | Oct 15 03:00:44 AM UTC 24 | 125767214 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3500529987 | Oct 15 03:00:39 AM UTC 24 | Oct 15 03:00:45 AM UTC 24 | 370523023 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1454873047 | Oct 15 03:00:38 AM UTC 24 | Oct 15 03:00:45 AM UTC 24 | 719333347 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.210491530 | Oct 15 03:00:43 AM UTC 24 | Oct 15 03:00:46 AM UTC 24 | 114924534 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.928346622 | Oct 15 03:00:46 AM UTC 24 | Oct 15 03:00:48 AM UTC 24 | 69967724 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.513016501 | Oct 15 03:00:47 AM UTC 24 | Oct 15 03:00:49 AM UTC 24 | 32370955 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2188881805 | Oct 15 03:00:46 AM UTC 24 | Oct 15 03:00:49 AM UTC 24 | 197377784 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.564210901 | Oct 15 03:00:46 AM UTC 24 | Oct 15 03:00:50 AM UTC 24 | 30111049 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4167380166 | Oct 15 03:00:45 AM UTC 24 | Oct 15 03:00:51 AM UTC 24 | 364806532 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2164178212 | Oct 15 03:00:11 AM UTC 24 | Oct 15 03:00:53 AM UTC 24 | 3734762939 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3350504573 | Oct 15 03:00:53 AM UTC 24 | Oct 15 03:00:55 AM UTC 24 | 13538575 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1681216774 | Oct 15 03:00:50 AM UTC 24 | Oct 15 03:00:55 AM UTC 24 | 93591310 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.588943026 | Oct 15 03:00:54 AM UTC 24 | Oct 15 03:00:56 AM UTC 24 | 23277825 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1119054415 | Oct 15 03:00:52 AM UTC 24 | Oct 15 03:00:56 AM UTC 24 | 154657707 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1324869362 | Oct 15 03:00:49 AM UTC 24 | Oct 15 03:00:56 AM UTC 24 | 1384255536 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1153438245 | Oct 15 03:00:24 AM UTC 24 | Oct 15 03:00:57 AM UTC 24 | 15664719025 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4027465319 | Oct 15 03:00:57 AM UTC 24 | Oct 15 03:00:59 AM UTC 24 | 106920661 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1568414766 | Oct 15 03:00:57 AM UTC 24 | Oct 15 03:01:00 AM UTC 24 | 124961595 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3636359053 | Oct 15 03:00:58 AM UTC 24 | Oct 15 03:01:01 AM UTC 24 | 42065909 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3918218913 | Oct 15 03:00:17 AM UTC 24 | Oct 15 03:01:02 AM UTC 24 | 3761513893 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1261618367 | Oct 15 03:00:33 AM UTC 24 | Oct 15 03:01:03 AM UTC 24 | 3737099956 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4021640482 | Oct 15 03:00:56 AM UTC 24 | Oct 15 03:01:04 AM UTC 24 | 741409649 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.139893037 | Oct 15 03:00:57 AM UTC 24 | Oct 15 03:01:04 AM UTC 24 | 108043740 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3479917450 | Oct 15 03:01:04 AM UTC 24 | Oct 15 03:01:06 AM UTC 24 | 50797029 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.49245614 | Oct 15 03:01:04 AM UTC 24 | Oct 15 03:01:06 AM UTC 24 | 26964931 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1879822756 | Oct 15 03:01:02 AM UTC 24 | Oct 15 03:01:07 AM UTC 24 | 104514356 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.896223956 | Oct 15 03:01:03 AM UTC 24 | Oct 15 03:01:08 AM UTC 24 | 479216615 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3428238204 | Oct 15 03:01:06 AM UTC 24 | Oct 15 03:01:08 AM UTC 24 | 36765541 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.497762244 | Oct 15 03:01:01 AM UTC 24 | Oct 15 03:01:09 AM UTC 24 | 1455772953 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2773958076 | Oct 15 02:59:46 AM UTC 24 | Oct 15 03:01:09 AM UTC 24 | 28482602556 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.996960694 | Oct 15 03:01:08 AM UTC 24 | Oct 15 03:01:10 AM UTC 24 | 47186016 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2664612311 | Oct 15 03:01:06 AM UTC 24 | Oct 15 03:01:10 AM UTC 24 | 319565493 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.128801436 | Oct 15 03:01:10 AM UTC 24 | Oct 15 03:01:12 AM UTC 24 | 18923367 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2916978221 | Oct 15 03:01:06 AM UTC 24 | Oct 15 03:01:13 AM UTC 24 | 157579322 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1007916994 | Oct 15 03:01:10 AM UTC 24 | Oct 15 03:01:13 AM UTC 24 | 126788840 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2943685469 | Oct 15 03:01:11 AM UTC 24 | Oct 15 03:01:13 AM UTC 24 | 51718516 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.990331901 | Oct 15 03:01:08 AM UTC 24 | Oct 15 03:01:14 AM UTC 24 | 720485699 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.428787611 | Oct 15 03:01:10 AM UTC 24 | Oct 15 03:01:16 AM UTC 24 | 103172830 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.326677908 | Oct 15 03:01:05 AM UTC 24 | Oct 15 03:01:17 AM UTC 24 | 6914991523 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3311366279 | Oct 15 03:01:15 AM UTC 24 | Oct 15 03:01:17 AM UTC 24 | 14317892 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1142827656 | Oct 15 03:01:16 AM UTC 24 | Oct 15 03:01:18 AM UTC 24 | 17040026 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1840448618 | Oct 15 03:01:11 AM UTC 24 | Oct 15 03:01:19 AM UTC 24 | 2832177265 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3818248147 | Oct 15 03:01:13 AM UTC 24 | Oct 15 03:01:20 AM UTC 24 | 691530111 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2088045779 | Oct 15 02:59:59 AM UTC 24 | Oct 15 03:01:20 AM UTC 24 | 8587166507 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.135151338 | Oct 15 03:01:19 AM UTC 24 | Oct 15 03:01:22 AM UTC 24 | 50538452 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1587001164 | Oct 15 03:01:17 AM UTC 24 | Oct 15 03:01:23 AM UTC 24 | 1371723495 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.960702548 | Oct 15 03:01:20 AM UTC 24 | Oct 15 03:01:23 AM UTC 24 | 27519837 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1969723078 | Oct 15 03:01:19 AM UTC 24 | Oct 15 03:01:23 AM UTC 24 | 328012898 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2429120029 | Oct 15 03:01:18 AM UTC 24 | Oct 15 03:01:24 AM UTC 24 | 134799572 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1106872229 | Oct 15 03:01:20 AM UTC 24 | Oct 15 03:01:30 AM UTC 24 | 2467329204 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2329366543 | Oct 15 03:00:56 AM UTC 24 | Oct 15 03:01:30 AM UTC 24 | 7565484669 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.190525145 | Oct 15 03:01:18 AM UTC 24 | Oct 15 03:01:50 AM UTC 24 | 3737508168 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.551311628 | Oct 15 03:00:45 AM UTC 24 | Oct 15 03:01:54 AM UTC 24 | 73650816397 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.271201088 | Oct 15 03:00:39 AM UTC 24 | Oct 15 03:01:56 AM UTC 24 | 29309051289 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2487079916 | Oct 15 03:01:12 AM UTC 24 | Oct 15 03:02:12 AM UTC 24 | 7398418310 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2092567173 | Oct 15 03:01:05 AM UTC 24 | Oct 15 03:02:16 AM UTC 24 | 15013723918 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.606412488 | Oct 15 03:01:09 AM UTC 24 | Oct 15 03:02:17 AM UTC 24 | 13853423629 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.958860221 | Oct 15 03:00:50 AM UTC 24 | Oct 15 03:02:20 AM UTC 24 | 22065392761 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3921176476 | Oct 15 03:01:02 AM UTC 24 | Oct 15 03:02:29 AM UTC 24 | 10208263573 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1871598553 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 203882473 ps |
| CPU time | 7.29 seconds |
| Started | Oct 15 01:11:50 AM UTC 24 |
| Finished | Oct 15 01:11:59 AM UTC 24 |
| Peak memory | 221544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871598553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1871598553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.1351326285 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6015341702 ps |
| CPU time | 111.97 seconds |
| Started | Oct 15 01:12:00 AM UTC 24 |
| Finished | Oct 15 01:13:54 AM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351326285 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.1351326285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.3847464745 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1871280556 ps |
| CPU time | 13.45 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:12:07 AM UTC 24 |
| Peak memory | 248828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847464745 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3847464745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1122332131 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 15369687468 ps |
| CPU time | 50.75 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:12:44 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122332131 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.1122332131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.758248133 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2555341864 ps |
| CPU time | 250.66 seconds |
| Started | Oct 15 01:12:45 AM UTC 24 |
| Finished | Oct 15 01:16:59 AM UTC 24 |
| Peak memory | 361156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758248133 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.758248133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2747028838 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 285988068 ps |
| CPU time | 2.31 seconds |
| Started | Oct 15 01:12:02 AM UTC 24 |
| Finished | Oct 15 01:12:23 AM UTC 24 |
| Peak memory | 247512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747028838 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2747028838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2714408037 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 990897347 ps |
| CPU time | 3.24 seconds |
| Started | Oct 15 02:58:47 AM UTC 24 |
| Finished | Oct 15 02:58:51 AM UTC 24 |
| Peak memory | 224384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714 408037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_ intg_err.2714408037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.38897520 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1332352893 ps |
| CPU time | 33.96 seconds |
| Started | Oct 15 01:19:51 AM UTC 24 |
| Finished | Oct 15 01:20:26 AM UTC 24 |
| Peak memory | 221676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38897520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.38897520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2725222936 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 60730857835 ps |
| CPU time | 353.07 seconds |
| Started | Oct 15 01:12:29 AM UTC 24 |
| Finished | Oct 15 01:18:26 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725222936 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_ac cess_b2b.2725222936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_readback_err.2560649329 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1323699039 ps |
| CPU time | 10.45 seconds |
| Started | Oct 15 01:13:54 AM UTC 24 |
| Finished | Oct 15 01:14:06 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560649329 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_readback_err.2560649329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.4085521484 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6130855529 ps |
| CPU time | 620.06 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:22:19 AM UTC 24 |
| Peak memory | 369536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085521484 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.4085521484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2590759523 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1142768127 ps |
| CPU time | 35.3 seconds |
| Started | Oct 15 01:11:43 AM UTC 24 |
| Finished | Oct 15 01:12:21 AM UTC 24 |
| Peak memory | 303928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590759523 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.2590759523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.1373144802 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1023370174 ps |
| CPU time | 5.32 seconds |
| Started | Oct 15 01:11:45 AM UTC 24 |
| Finished | Oct 15 01:11:59 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373144802 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1373144802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.513788318 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 22774358933 ps |
| CPU time | 94 seconds |
| Started | Oct 15 02:58:53 AM UTC 24 |
| Finished | Oct 15 03:00:29 AM UTC 24 |
| Peak memory | 214144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 13788318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_p assthru_mem_tl_intg_err.513788318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3878811764 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 732660404 ps |
| CPU time | 4.83 seconds |
| Started | Oct 15 03:00:06 AM UTC 24 |
| Finished | Oct 15 03:00:12 AM UTC 24 |
| Peak memory | 224180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878 811764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_ intg_err.3878811764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3358390995 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 24791995179 ps |
| CPU time | 2273.8 seconds |
| Started | Oct 15 01:12:22 AM UTC 24 |
| Finished | Oct 15 01:50:43 AM UTC 24 |
| Peak memory | 388040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33583909 95 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.3358390995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1065006648 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 29788500 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 01:11:54 AM UTC 24 |
| Finished | Oct 15 01:11:56 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065006648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1065006648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2738925833 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 148770286263 ps |
| CPU time | 145.71 seconds |
| Started | Oct 15 01:13:32 AM UTC 24 |
| Finished | Oct 15 01:16:00 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738925833 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.2738925833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.731423568 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4325097809 ps |
| CPU time | 316.98 seconds |
| Started | Oct 15 01:26:25 AM UTC 24 |
| Finished | Oct 15 01:31:46 AM UTC 24 |
| Peak memory | 377848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731423568 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.731423568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2760407636 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 32166938 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 02:58:48 AM UTC 24 |
| Finished | Oct 15 02:58:50 AM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760407636 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.2760407636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2844825835 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 125767214 ps |
| CPU time | 2.44 seconds |
| Started | Oct 15 03:00:40 AM UTC 24 |
| Finished | Oct 15 03:00:44 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844 825835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl _intg_err.2844825835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2188881805 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 197377784 ps |
| CPU time | 2.56 seconds |
| Started | Oct 15 03:00:46 AM UTC 24 |
| Finished | Oct 15 03:00:49 AM UTC 24 |
| Peak memory | 224320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188 881805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl _intg_err.2188881805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2664612311 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 319565493 ps |
| CPU time | 2.69 seconds |
| Started | Oct 15 03:01:06 AM UTC 24 |
| Finished | Oct 15 03:01:10 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664 612311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl _intg_err.2664612311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2358952874 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3068262191 ps |
| CPU time | 111.98 seconds |
| Started | Oct 15 01:49:57 AM UTC 24 |
| Finished | Oct 15 01:51:51 AM UTC 24 |
| Peak memory | 361476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358952874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2358952874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3100958806 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 23453504961 ps |
| CPU time | 41.07 seconds |
| Started | Oct 15 01:23:08 AM UTC 24 |
| Finished | Oct 15 01:23:50 AM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100958806 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.3100958806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1357163134 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 56367026 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 02:58:51 AM UTC 24 |
| Finished | Oct 15 02:58:53 AM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357163 134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_al iasing.1357163134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1050342668 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 349148874 ps |
| CPU time | 3.87 seconds |
| Started | Oct 15 02:58:51 AM UTC 24 |
| Finished | Oct 15 02:58:56 AM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050342 668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bi t_bash.1050342668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.243899518 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 37265045 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 02:58:48 AM UTC 24 |
| Finished | Oct 15 02:58:50 AM UTC 24 |
| Peak memory | 212440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438995 18 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_ reset.243899518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1388364218 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 4338754248 ps |
| CPU time | 7.95 seconds |
| Started | Oct 15 02:58:51 AM UTC 24 |
| Finished | Oct 15 02:59:00 AM UTC 24 |
| Peak memory | 224228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1388364218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1388364218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2994785783 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 7148600737 ps |
| CPU time | 53.69 seconds |
| Started | Oct 15 02:58:38 AM UTC 24 |
| Finished | Oct 15 02:59:33 AM UTC 24 |
| Peak memory | 214048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 994785783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ passthru_mem_tl_intg_err.2994785783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3699000948 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 32147359 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 02:58:51 AM UTC 24 |
| Finished | Oct 15 02:58:54 AM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3699000948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram _ctrl_same_csr_outstanding.3699000948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1717964335 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 130083141 ps |
| CPU time | 6.15 seconds |
| Started | Oct 15 02:58:40 AM UTC 24 |
| Finished | Oct 15 02:58:47 AM UTC 24 |
| Peak memory | 214264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717964335 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.1717964335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2900033711 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 20522963 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 02:59:00 AM UTC 24 |
| Finished | Oct 15 02:59:02 AM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900033 711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_al iasing.2900033711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3151927024 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 96504159 ps |
| CPU time | 1.73 seconds |
| Started | Oct 15 02:59:00 AM UTC 24 |
| Finished | Oct 15 02:59:03 AM UTC 24 |
| Peak memory | 213400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151927 024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bi t_bash.3151927024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2918053945 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 51961971 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 02:58:57 AM UTC 24 |
| Finished | Oct 15 02:58:59 AM UTC 24 |
| Peak memory | 212684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918053 945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw _reset.2918053945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3361252583 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 1328783302 ps |
| CPU time | 5.59 seconds |
| Started | Oct 15 02:59:02 AM UTC 24 |
| Finished | Oct 15 02:59:09 AM UTC 24 |
| Peak memory | 224172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3361252583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.3361252583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3410882639 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 79338706 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 02:59:00 AM UTC 24 |
| Finished | Oct 15 02:59:02 AM UTC 24 |
| Peak memory | 212224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410882639 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.3410882639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3697974352 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 23398327 ps |
| CPU time | 1 seconds |
| Started | Oct 15 02:59:01 AM UTC 24 |
| Finished | Oct 15 02:59:03 AM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3697974352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram _ctrl_same_csr_outstanding.3697974352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4125515659 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 92875954 ps |
| CPU time | 4.61 seconds |
| Started | Oct 15 02:58:54 AM UTC 24 |
| Finished | Oct 15 02:58:59 AM UTC 24 |
| Peak memory | 213948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125515659 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.4125515659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1170866586 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 348046874 ps |
| CPU time | 2.81 seconds |
| Started | Oct 15 02:58:55 AM UTC 24 |
| Finished | Oct 15 02:58:59 AM UTC 24 |
| Peak memory | 224376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170 866586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_ intg_err.1170866586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1454873047 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 719333347 ps |
| CPU time | 5.88 seconds |
| Started | Oct 15 03:00:38 AM UTC 24 |
| Finished | Oct 15 03:00:45 AM UTC 24 |
| Peak memory | 213664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1454873047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1454873047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2797885502 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 28074399 ps |
| CPU time | 0.93 seconds |
| Started | Oct 15 03:00:37 AM UTC 24 |
| Finished | Oct 15 03:00:39 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797885502 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.2797885502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1261618367 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3737099956 ps |
| CPU time | 28.47 seconds |
| Started | Oct 15 03:00:33 AM UTC 24 |
| Finished | Oct 15 03:01:03 AM UTC 24 |
| Peak memory | 224220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 261618367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _passthru_mem_tl_intg_err.1261618367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2716968063 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 137171560 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 03:00:37 AM UTC 24 |
| Finished | Oct 15 03:00:39 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2716968063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sra m_ctrl_same_csr_outstanding.2716968063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1766106610 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 141855339 ps |
| CPU time | 7.5 seconds |
| Started | Oct 15 03:00:36 AM UTC 24 |
| Finished | Oct 15 03:00:44 AM UTC 24 |
| Peak memory | 213952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766106610 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.1766106610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3036274387 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 329476259 ps |
| CPU time | 1.61 seconds |
| Started | Oct 15 03:00:36 AM UTC 24 |
| Finished | Oct 15 03:00:38 AM UTC 24 |
| Peak memory | 223140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036 274387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl _intg_err.3036274387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4167380166 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 364806532 ps |
| CPU time | 5.69 seconds |
| Started | Oct 15 03:00:45 AM UTC 24 |
| Finished | Oct 15 03:00:51 AM UTC 24 |
| Peak memory | 228000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=4167380166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.4167380166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.92605218 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 47412111 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 03:00:40 AM UTC 24 |
| Finished | Oct 15 03:00:42 AM UTC 24 |
| Peak memory | 212440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92605218 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.92605218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.271201088 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 29309051289 ps |
| CPU time | 74.97 seconds |
| Started | Oct 15 03:00:39 AM UTC 24 |
| Finished | Oct 15 03:01:56 AM UTC 24 |
| Peak memory | 214052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 71201088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ passthru_mem_tl_intg_err.271201088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.210491530 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 114924534 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 03:00:43 AM UTC 24 |
| Finished | Oct 15 03:00:46 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=210491530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram _ctrl_same_csr_outstanding.210491530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3500529987 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 370523023 ps |
| CPU time | 4.56 seconds |
| Started | Oct 15 03:00:39 AM UTC 24 |
| Finished | Oct 15 03:00:45 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500529987 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.3500529987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1324869362 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 1384255536 ps |
| CPU time | 6.2 seconds |
| Started | Oct 15 03:00:49 AM UTC 24 |
| Finished | Oct 15 03:00:56 AM UTC 24 |
| Peak memory | 223900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1324869362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1324869362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.928346622 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 69967724 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 03:00:46 AM UTC 24 |
| Finished | Oct 15 03:00:48 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928346622 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.928346622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.551311628 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 73650816397 ps |
| CPU time | 67.25 seconds |
| Started | Oct 15 03:00:45 AM UTC 24 |
| Finished | Oct 15 03:01:54 AM UTC 24 |
| Peak memory | 214068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5 51311628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ passthru_mem_tl_intg_err.551311628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.513016501 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 32370955 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 03:00:47 AM UTC 24 |
| Finished | Oct 15 03:00:49 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=513016501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram _ctrl_same_csr_outstanding.513016501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.564210901 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 30111049 ps |
| CPU time | 3.64 seconds |
| Started | Oct 15 03:00:46 AM UTC 24 |
| Finished | Oct 15 03:00:50 AM UTC 24 |
| Peak memory | 214044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564210901 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.564210901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4021640482 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 741409649 ps |
| CPU time | 6.64 seconds |
| Started | Oct 15 03:00:56 AM UTC 24 |
| Finished | Oct 15 03:01:04 AM UTC 24 |
| Peak memory | 226204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=4021640482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.4021640482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3350504573 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 13538575 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 03:00:53 AM UTC 24 |
| Finished | Oct 15 03:00:55 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350504573 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.3350504573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.958860221 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 22065392761 ps |
| CPU time | 87.65 seconds |
| Started | Oct 15 03:00:50 AM UTC 24 |
| Finished | Oct 15 03:02:20 AM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 58860221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ passthru_mem_tl_intg_err.958860221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.588943026 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 23277825 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 03:00:54 AM UTC 24 |
| Finished | Oct 15 03:00:56 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=588943026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram _ctrl_same_csr_outstanding.588943026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1681216774 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 93591310 ps |
| CPU time | 3.59 seconds |
| Started | Oct 15 03:00:50 AM UTC 24 |
| Finished | Oct 15 03:00:55 AM UTC 24 |
| Peak memory | 213944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681216774 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.1681216774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1119054415 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 154657707 ps |
| CPU time | 3.76 seconds |
| Started | Oct 15 03:00:52 AM UTC 24 |
| Finished | Oct 15 03:00:56 AM UTC 24 |
| Peak memory | 224052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119 054415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl _intg_err.1119054415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.497762244 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 1455772953 ps |
| CPU time | 6.96 seconds |
| Started | Oct 15 03:01:01 AM UTC 24 |
| Finished | Oct 15 03:01:09 AM UTC 24 |
| Peak memory | 224164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=497762244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.497762244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4027465319 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 106920661 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 03:00:57 AM UTC 24 |
| Finished | Oct 15 03:00:59 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027465319 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.4027465319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2329366543 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 7565484669 ps |
| CPU time | 32.72 seconds |
| Started | Oct 15 03:00:56 AM UTC 24 |
| Finished | Oct 15 03:01:30 AM UTC 24 |
| Peak memory | 213780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 329366543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _passthru_mem_tl_intg_err.2329366543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3636359053 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 42065909 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 03:00:58 AM UTC 24 |
| Finished | Oct 15 03:01:01 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3636359053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sra m_ctrl_same_csr_outstanding.3636359053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.139893037 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 108043740 ps |
| CPU time | 5.52 seconds |
| Started | Oct 15 03:00:57 AM UTC 24 |
| Finished | Oct 15 03:01:04 AM UTC 24 |
| Peak memory | 214196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139893037 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.139893037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1568414766 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 124961595 ps |
| CPU time | 2.16 seconds |
| Started | Oct 15 03:00:57 AM UTC 24 |
| Finished | Oct 15 03:01:00 AM UTC 24 |
| Peak memory | 224316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568 414766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl _intg_err.1568414766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.326677908 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 6914991523 ps |
| CPU time | 10.6 seconds |
| Started | Oct 15 03:01:05 AM UTC 24 |
| Finished | Oct 15 03:01:17 AM UTC 24 |
| Peak memory | 224228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=326677908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.326677908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3479917450 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 50797029 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 03:01:04 AM UTC 24 |
| Finished | Oct 15 03:01:06 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479917450 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.3479917450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3921176476 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 10208263573 ps |
| CPU time | 85.35 seconds |
| Started | Oct 15 03:01:02 AM UTC 24 |
| Finished | Oct 15 03:02:29 AM UTC 24 |
| Peak memory | 214356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 921176476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _passthru_mem_tl_intg_err.3921176476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.49245614 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 26964931 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 03:01:04 AM UTC 24 |
| Finished | Oct 15 03:01:06 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=49245614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ ctrl_same_csr_outstanding.49245614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1879822756 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 104514356 ps |
| CPU time | 4.22 seconds |
| Started | Oct 15 03:01:02 AM UTC 24 |
| Finished | Oct 15 03:01:07 AM UTC 24 |
| Peak memory | 224252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879822756 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.1879822756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.896223956 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 479216615 ps |
| CPU time | 3.79 seconds |
| Started | Oct 15 03:01:03 AM UTC 24 |
| Finished | Oct 15 03:01:08 AM UTC 24 |
| Peak memory | 224324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8962 23956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_ intg_err.896223956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.990331901 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 720485699 ps |
| CPU time | 5.57 seconds |
| Started | Oct 15 03:01:08 AM UTC 24 |
| Finished | Oct 15 03:01:14 AM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=990331901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.990331901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3428238204 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 36765541 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 03:01:06 AM UTC 24 |
| Finished | Oct 15 03:01:08 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428238204 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.3428238204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2092567173 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 15013723918 ps |
| CPU time | 68.97 seconds |
| Started | Oct 15 03:01:05 AM UTC 24 |
| Finished | Oct 15 03:02:16 AM UTC 24 |
| Peak memory | 214048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 092567173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _passthru_mem_tl_intg_err.2092567173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.996960694 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 47186016 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 03:01:08 AM UTC 24 |
| Finished | Oct 15 03:01:10 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=996960694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram _ctrl_same_csr_outstanding.996960694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2916978221 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 157579322 ps |
| CPU time | 5.39 seconds |
| Started | Oct 15 03:01:06 AM UTC 24 |
| Finished | Oct 15 03:01:13 AM UTC 24 |
| Peak memory | 214052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916978221 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.2916978221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1840448618 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 2832177265 ps |
| CPU time | 6.38 seconds |
| Started | Oct 15 03:01:11 AM UTC 24 |
| Finished | Oct 15 03:01:19 AM UTC 24 |
| Peak memory | 224232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1840448618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1840448618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.128801436 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 18923367 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 03:01:10 AM UTC 24 |
| Finished | Oct 15 03:01:12 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128801436 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.128801436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.606412488 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 13853423629 ps |
| CPU time | 66.92 seconds |
| Started | Oct 15 03:01:09 AM UTC 24 |
| Finished | Oct 15 03:02:17 AM UTC 24 |
| Peak memory | 214296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 06412488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ passthru_mem_tl_intg_err.606412488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2943685469 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 51718516 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 03:01:11 AM UTC 24 |
| Finished | Oct 15 03:01:13 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2943685469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sra m_ctrl_same_csr_outstanding.2943685469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.428787611 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 103172830 ps |
| CPU time | 5.37 seconds |
| Started | Oct 15 03:01:10 AM UTC 24 |
| Finished | Oct 15 03:01:16 AM UTC 24 |
| Peak memory | 224408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428787611 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.428787611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1007916994 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 126788840 ps |
| CPU time | 2.33 seconds |
| Started | Oct 15 03:01:10 AM UTC 24 |
| Finished | Oct 15 03:01:13 AM UTC 24 |
| Peak memory | 224252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007 916994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl _intg_err.1007916994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1587001164 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 1371723495 ps |
| CPU time | 5.02 seconds |
| Started | Oct 15 03:01:17 AM UTC 24 |
| Finished | Oct 15 03:01:23 AM UTC 24 |
| Peak memory | 223900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1587001164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1587001164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3311366279 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 14317892 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 03:01:15 AM UTC 24 |
| Finished | Oct 15 03:01:17 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311366279 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.3311366279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2487079916 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 7398418310 ps |
| CPU time | 58.39 seconds |
| Started | Oct 15 03:01:12 AM UTC 24 |
| Finished | Oct 15 03:02:12 AM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 487079916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl _passthru_mem_tl_intg_err.2487079916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1142827656 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 17040026 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 03:01:16 AM UTC 24 |
| Finished | Oct 15 03:01:18 AM UTC 24 |
| Peak memory | 212884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1142827656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sra m_ctrl_same_csr_outstanding.1142827656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3818248147 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 691530111 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 03:01:13 AM UTC 24 |
| Finished | Oct 15 03:01:20 AM UTC 24 |
| Peak memory | 224288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818248147 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.3818248147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1106872229 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 2467329204 ps |
| CPU time | 8.08 seconds |
| Started | Oct 15 03:01:20 AM UTC 24 |
| Finished | Oct 15 03:01:30 AM UTC 24 |
| Peak memory | 224504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1106872229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1106872229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.135151338 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 50538452 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 03:01:19 AM UTC 24 |
| Finished | Oct 15 03:01:22 AM UTC 24 |
| Peak memory | 212672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135151338 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.135151338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.190525145 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 3737508168 ps |
| CPU time | 30.86 seconds |
| Started | Oct 15 03:01:18 AM UTC 24 |
| Finished | Oct 15 03:01:50 AM UTC 24 |
| Peak memory | 214048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 90525145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ passthru_mem_tl_intg_err.190525145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.960702548 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 27519837 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 03:01:20 AM UTC 24 |
| Finished | Oct 15 03:01:23 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=960702548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram _ctrl_same_csr_outstanding.960702548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2429120029 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 134799572 ps |
| CPU time | 4.87 seconds |
| Started | Oct 15 03:01:18 AM UTC 24 |
| Finished | Oct 15 03:01:24 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429120029 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.2429120029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1969723078 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 328012898 ps |
| CPU time | 2.23 seconds |
| Started | Oct 15 03:01:19 AM UTC 24 |
| Finished | Oct 15 03:01:23 AM UTC 24 |
| Peak memory | 224212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969 723078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl _intg_err.1969723078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3070382139 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 16858605 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 02:59:13 AM UTC 24 |
| Finished | Oct 15 02:59:15 AM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070382 139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_al iasing.3070382139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3589969846 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 44179435 ps |
| CPU time | 2.54 seconds |
| Started | Oct 15 02:59:12 AM UTC 24 |
| Finished | Oct 15 02:59:15 AM UTC 24 |
| Peak memory | 213956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589969 846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bi t_bash.3589969846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1186994339 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 27179356 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 02:59:10 AM UTC 24 |
| Finished | Oct 15 02:59:12 AM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186994 339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw _reset.1186994339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.261587619 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 1372991197 ps |
| CPU time | 7.87 seconds |
| Started | Oct 15 02:59:16 AM UTC 24 |
| Finished | Oct 15 02:59:25 AM UTC 24 |
| Peak memory | 226116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=261587619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.261587619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1608061353 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 14646387 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 02:59:11 AM UTC 24 |
| Finished | Oct 15 02:59:13 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608061353 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.1608061353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4017986900 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 28126828616 ps |
| CPU time | 90.91 seconds |
| Started | Oct 15 02:59:03 AM UTC 24 |
| Finished | Oct 15 03:00:36 AM UTC 24 |
| Peak memory | 214072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 017986900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ passthru_mem_tl_intg_err.4017986900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1369646382 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 35494204 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 02:59:14 AM UTC 24 |
| Finished | Oct 15 02:59:16 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1369646382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram _ctrl_same_csr_outstanding.1369646382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.922076775 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 47350545 ps |
| CPU time | 6.74 seconds |
| Started | Oct 15 02:59:03 AM UTC 24 |
| Finished | Oct 15 02:59:11 AM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922076775 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.922076775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.81111660 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1766073732 ps |
| CPU time | 4.22 seconds |
| Started | Oct 15 02:59:05 AM UTC 24 |
| Finished | Oct 15 02:59:10 AM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8111 1660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_in tg_err.81111660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4105613984 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 34944983 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 02:59:31 AM UTC 24 |
| Finished | Oct 15 02:59:33 AM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105613 984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_al iasing.4105613984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2064867187 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 27006667 ps |
| CPU time | 1.86 seconds |
| Started | Oct 15 02:59:30 AM UTC 24 |
| Finished | Oct 15 02:59:33 AM UTC 24 |
| Peak memory | 212684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064867 187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bi t_bash.2064867187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1432752329 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 25206289 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 02:59:27 AM UTC 24 |
| Finished | Oct 15 02:59:29 AM UTC 24 |
| Peak memory | 212444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432752 329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw _reset.1432752329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.647165143 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 352211505 ps |
| CPU time | 5.79 seconds |
| Started | Oct 15 02:59:34 AM UTC 24 |
| Finished | Oct 15 02:59:42 AM UTC 24 |
| Peak memory | 224236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=647165143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.647165143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.415145083 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 49479967 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 02:59:28 AM UTC 24 |
| Finished | Oct 15 02:59:30 AM UTC 24 |
| Peak memory | 212828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415145083 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.415145083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2432394749 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 7041220469 ps |
| CPU time | 77.96 seconds |
| Started | Oct 15 02:59:16 AM UTC 24 |
| Finished | Oct 15 03:00:36 AM UTC 24 |
| Peak memory | 214148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 432394749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ passthru_mem_tl_intg_err.2432394749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.130768082 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 24058704 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 02:59:31 AM UTC 24 |
| Finished | Oct 15 02:59:33 AM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=130768082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ ctrl_same_csr_outstanding.130768082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.804406947 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 144109550 ps |
| CPU time | 6.24 seconds |
| Started | Oct 15 02:59:17 AM UTC 24 |
| Finished | Oct 15 02:59:25 AM UTC 24 |
| Peak memory | 214008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804406947 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.804406947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2501112119 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 398634342 ps |
| CPU time | 3.18 seconds |
| Started | Oct 15 02:59:25 AM UTC 24 |
| Finished | Oct 15 02:59:30 AM UTC 24 |
| Peak memory | 224124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501 112119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_ intg_err.2501112119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4146237747 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 26427961 ps |
| CPU time | 1.03 seconds |
| Started | Oct 15 02:59:43 AM UTC 24 |
| Finished | Oct 15 02:59:45 AM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146237 747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_al iasing.4146237747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3896007712 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 70385419 ps |
| CPU time | 1.68 seconds |
| Started | Oct 15 02:59:43 AM UTC 24 |
| Finished | Oct 15 02:59:45 AM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896007 712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bi t_bash.3896007712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1244489289 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 38075099 ps |
| CPU time | 1 seconds |
| Started | Oct 15 02:59:39 AM UTC 24 |
| Finished | Oct 15 02:59:42 AM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244489 289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw _reset.1244489289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2374798222 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 1451597518 ps |
| CPU time | 7.47 seconds |
| Started | Oct 15 02:59:46 AM UTC 24 |
| Finished | Oct 15 02:59:55 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2374798222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2374798222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3850412235 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 40969416 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 02:59:43 AM UTC 24 |
| Finished | Oct 15 02:59:45 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850412235 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.3850412235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2337707813 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 14804104318 ps |
| CPU time | 35.38 seconds |
| Started | Oct 15 02:59:34 AM UTC 24 |
| Finished | Oct 15 03:00:11 AM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 337707813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ passthru_mem_tl_intg_err.2337707813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1343126098 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 61948997 ps |
| CPU time | 1.21 seconds |
| Started | Oct 15 02:59:46 AM UTC 24 |
| Finished | Oct 15 02:59:48 AM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1343126098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram _ctrl_same_csr_outstanding.1343126098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2404302661 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 235498291 ps |
| CPU time | 6.07 seconds |
| Started | Oct 15 02:59:34 AM UTC 24 |
| Finished | Oct 15 02:59:42 AM UTC 24 |
| Peak memory | 224248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404302661 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.2404302661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1746849973 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 425334463 ps |
| CPU time | 2.45 seconds |
| Started | Oct 15 02:59:34 AM UTC 24 |
| Finished | Oct 15 02:59:38 AM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746 849973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_ intg_err.1746849973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1763176591 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 1111559942 ps |
| CPU time | 5.78 seconds |
| Started | Oct 15 02:59:59 AM UTC 24 |
| Finished | Oct 15 03:00:06 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1763176591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1763176591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1945028346 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 13208583 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 02:59:56 AM UTC 24 |
| Finished | Oct 15 02:59:57 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945028346 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.1945028346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2773958076 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 28482602556 ps |
| CPU time | 80.67 seconds |
| Started | Oct 15 02:59:46 AM UTC 24 |
| Finished | Oct 15 03:01:09 AM UTC 24 |
| Peak memory | 214320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 773958076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ passthru_mem_tl_intg_err.2773958076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.954498542 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 75584110 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 02:59:56 AM UTC 24 |
| Finished | Oct 15 02:59:58 AM UTC 24 |
| Peak memory | 212948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=954498542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ ctrl_same_csr_outstanding.954498542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3996962897 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 62273022 ps |
| CPU time | 3.84 seconds |
| Started | Oct 15 02:59:49 AM UTC 24 |
| Finished | Oct 15 02:59:54 AM UTC 24 |
| Peak memory | 224284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996962897 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.3996962897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.58935617 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 91127020 ps |
| CPU time | 2.47 seconds |
| Started | Oct 15 02:59:55 AM UTC 24 |
| Finished | Oct 15 02:59:59 AM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5893 5617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_in tg_err.58935617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1526261310 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 1426113883 ps |
| CPU time | 5.75 seconds |
| Started | Oct 15 03:00:09 AM UTC 24 |
| Finished | Oct 15 03:00:16 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1526261310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.1526261310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1488284237 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 18393942 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 03:00:06 AM UTC 24 |
| Finished | Oct 15 03:00:08 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488284237 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.1488284237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2088045779 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 8587166507 ps |
| CPU time | 79.6 seconds |
| Started | Oct 15 02:59:59 AM UTC 24 |
| Finished | Oct 15 03:01:20 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 088045779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ passthru_mem_tl_intg_err.2088045779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.22816702 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 21242248 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 03:00:08 AM UTC 24 |
| Finished | Oct 15 03:00:10 AM UTC 24 |
| Peak memory | 212948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=22816702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c trl_same_csr_outstanding.22816702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1363821113 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 118986680 ps |
| CPU time | 3.7 seconds |
| Started | Oct 15 03:00:00 AM UTC 24 |
| Finished | Oct 15 03:00:05 AM UTC 24 |
| Peak memory | 224188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363821113 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.1363821113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2229629196 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1223052320 ps |
| CPU time | 5.48 seconds |
| Started | Oct 15 03:00:17 AM UTC 24 |
| Finished | Oct 15 03:00:24 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2229629196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2229629196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4284602468 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 25216742 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 03:00:13 AM UTC 24 |
| Finished | Oct 15 03:00:15 AM UTC 24 |
| Peak memory | 212676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284602468 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.4284602468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2164178212 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 3734762939 ps |
| CPU time | 40.17 seconds |
| Started | Oct 15 03:00:11 AM UTC 24 |
| Finished | Oct 15 03:00:53 AM UTC 24 |
| Peak memory | 213784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 164178212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ passthru_mem_tl_intg_err.2164178212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1221314377 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 38910988 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 03:00:16 AM UTC 24 |
| Finished | Oct 15 03:00:18 AM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1221314377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram _ctrl_same_csr_outstanding.1221314377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2589590247 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 299705098 ps |
| CPU time | 4.2 seconds |
| Started | Oct 15 03:00:13 AM UTC 24 |
| Finished | Oct 15 03:00:18 AM UTC 24 |
| Peak memory | 224244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589590247 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.2589590247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1510236169 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 392322879 ps |
| CPU time | 3.5 seconds |
| Started | Oct 15 03:00:13 AM UTC 24 |
| Finished | Oct 15 03:00:17 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510 236169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_ intg_err.1510236169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2510711058 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 6870454544 ps |
| CPU time | 10.63 seconds |
| Started | Oct 15 03:00:23 AM UTC 24 |
| Finished | Oct 15 03:00:34 AM UTC 24 |
| Peak memory | 224348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2510711058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2510711058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3662188228 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 14507554 ps |
| CPU time | 0.93 seconds |
| Started | Oct 15 03:00:20 AM UTC 24 |
| Finished | Oct 15 03:00:21 AM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662188228 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.3662188228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3918218913 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 3761513893 ps |
| CPU time | 43.23 seconds |
| Started | Oct 15 03:00:17 AM UTC 24 |
| Finished | Oct 15 03:01:02 AM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 918218913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ passthru_mem_tl_intg_err.3918218913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1438277752 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 37136836 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 03:00:23 AM UTC 24 |
| Finished | Oct 15 03:00:25 AM UTC 24 |
| Peak memory | 212436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1438277752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram _ctrl_same_csr_outstanding.1438277752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.674373767 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 371715245 ps |
| CPU time | 3.35 seconds |
| Started | Oct 15 03:00:18 AM UTC 24 |
| Finished | Oct 15 03:00:23 AM UTC 24 |
| Peak memory | 224248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674373767 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.674373767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.635820032 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 257528138 ps |
| CPU time | 2.3 seconds |
| Started | Oct 15 03:00:18 AM UTC 24 |
| Finished | Oct 15 03:00:22 AM UTC 24 |
| Peak memory | 224180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6358 20032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_i ntg_err.635820032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2364542882 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 690066446 ps |
| CPU time | 5.4 seconds |
| Started | Oct 15 03:00:32 AM UTC 24 |
| Finished | Oct 15 03:00:39 AM UTC 24 |
| Peak memory | 224108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2364542882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2364542882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1902517012 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 11597680 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 03:00:29 AM UTC 24 |
| Finished | Oct 15 03:00:31 AM UTC 24 |
| Peak memory | 212880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902517012 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.1902517012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1153438245 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 15664719025 ps |
| CPU time | 32.21 seconds |
| Started | Oct 15 03:00:24 AM UTC 24 |
| Finished | Oct 15 03:00:57 AM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 153438245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ passthru_mem_tl_intg_err.1153438245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3986339280 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 22566436 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 03:00:32 AM UTC 24 |
| Finished | Oct 15 03:00:35 AM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3986339280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram _ctrl_same_csr_outstanding.3986339280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1478212527 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 1950044688 ps |
| CPU time | 6.89 seconds |
| Started | Oct 15 03:00:25 AM UTC 24 |
| Finished | Oct 15 03:00:33 AM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478212527 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.1478212527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.575143327 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 368500232 ps |
| CPU time | 4.1 seconds |
| Started | Oct 15 03:00:26 AM UTC 24 |
| Finished | Oct 15 03:00:31 AM UTC 24 |
| Peak memory | 224212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5751 43327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_i ntg_err.575143327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.4088212996 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 30716188839 ps |
| CPU time | 909.09 seconds |
| Started | Oct 15 01:11:45 AM UTC 24 |
| Finished | Oct 15 01:27:04 AM UTC 24 |
| Peak memory | 388092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088212996 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_durin g_key_req.4088212996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1814398726 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 24588406 ps |
| CPU time | 0.65 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:11:53 AM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814398726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1814398726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3759994909 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 46251709862 ps |
| CPU time | 1093.08 seconds |
| Started | Oct 15 01:11:43 AM UTC 24 |
| Finished | Oct 15 01:30:16 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759994909 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.3759994909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2783512227 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 6196656453 ps |
| CPU time | 674.69 seconds |
| Started | Oct 15 01:11:45 AM UTC 24 |
| Finished | Oct 15 01:23:07 AM UTC 24 |
| Peak memory | 383868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783512227 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.2783512227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1654670019 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10138693447 ps |
| CPU time | 64.74 seconds |
| Started | Oct 15 01:11:44 AM UTC 24 |
| Finished | Oct 15 01:12:51 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654670019 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.1654670019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3218639505 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10060081588 ps |
| CPU time | 23.51 seconds |
| Started | Oct 15 01:11:44 AM UTC 24 |
| Finished | Oct 15 01:12:10 AM UTC 24 |
| Peak memory | 277372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3218639505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m ax_throughput.3218639505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2121529453 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 23578606202 ps |
| CPU time | 196.23 seconds |
| Started | Oct 15 01:11:45 AM UTC 24 |
| Finished | Oct 15 01:15:12 AM UTC 24 |
| Peak memory | 228348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121529453 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.2121529453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.980967399 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4697465273 ps |
| CPU time | 246.85 seconds |
| Started | Oct 15 01:11:45 AM UTC 24 |
| Finished | Oct 15 01:16:03 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980967399 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.980967399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2324084903 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 16483044409 ps |
| CPU time | 414.13 seconds |
| Started | Oct 15 01:11:43 AM UTC 24 |
| Finished | Oct 15 01:18:50 AM UTC 24 |
| Peak memory | 379840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324084903 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.2324084903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.201593297 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 22094816875 ps |
| CPU time | 496.08 seconds |
| Started | Oct 15 01:11:43 AM UTC 24 |
| Finished | Oct 15 01:20:07 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201593297 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acc ess_b2b.201593297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_readback_err.307005227 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 754448422 ps |
| CPU time | 6.24 seconds |
| Started | Oct 15 01:11:50 AM UTC 24 |
| Finished | Oct 15 01:11:58 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307005227 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_readback_err.307005227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2681180647 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14642665504 ps |
| CPU time | 646.8 seconds |
| Started | Oct 15 01:11:45 AM UTC 24 |
| Finished | Oct 15 01:22:39 AM UTC 24 |
| Peak memory | 388032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681180647 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2681180647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1476168517 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 655430991 ps |
| CPU time | 2.6 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:11:55 AM UTC 24 |
| Peak memory | 247504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476168517 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1476168517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.121395246 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3087955014 ps |
| CPU time | 12.64 seconds |
| Started | Oct 15 01:11:43 AM UTC 24 |
| Finished | Oct 15 01:12:04 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121395246 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.121395246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2162273414 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 66439220347 ps |
| CPU time | 2316.24 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:50:52 AM UTC 24 |
| Peak memory | 392188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21622734 14 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.2162273414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.4284345601 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3467199345 ps |
| CPU time | 266.65 seconds |
| Started | Oct 15 01:11:43 AM UTC 24 |
| Finished | Oct 15 01:16:21 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284345601 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.4284345601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2883728368 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7374570520 ps |
| CPU time | 5.95 seconds |
| Started | Oct 15 01:11:44 AM UTC 24 |
| Finished | Oct 15 01:11:52 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2883728368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ throughput_w_partial_write.2883728368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1992705440 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 50904638444 ps |
| CPU time | 463.93 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:19:42 AM UTC 24 |
| Peak memory | 383904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992705440 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_durin g_key_req.1992705440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.1054608922 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 86367840622 ps |
| CPU time | 2087.85 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:47:03 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054608922 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.1054608922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.182885471 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 25717746352 ps |
| CPU time | 741.02 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:24:21 AM UTC 24 |
| Peak memory | 386048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182885471 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.182885471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3547952880 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2688070185 ps |
| CPU time | 8.36 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:12:02 AM UTC 24 |
| Peak memory | 221404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3547952880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_m ax_throughput.3547952880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2589637744 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2782047266 ps |
| CPU time | 79.6 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:13:14 AM UTC 24 |
| Peak memory | 221324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589637744 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.2589637744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1324613228 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 20694678951 ps |
| CPU time | 204.06 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:15:20 AM UTC 24 |
| Peak memory | 221484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324613228 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.1324613228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2109275698 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 34275581530 ps |
| CPU time | 851.89 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:26:14 AM UTC 24 |
| Peak memory | 379980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109275698 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.2109275698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2069533390 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1038534491 ps |
| CPU time | 14.05 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:12:07 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069533390 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.2069533390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3998402977 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 28620869390 ps |
| CPU time | 520.43 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:20:39 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998402977 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_ac cess_b2b.3998402977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3497805589 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 375459473 ps |
| CPU time | 5.73 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:11:59 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497805589 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3497805589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_readback_err.196533936 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1833491766 ps |
| CPU time | 9.51 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:12:03 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196533936 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_readback_err.196533936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.173207742 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 905816897 ps |
| CPU time | 5.08 seconds |
| Started | Oct 15 01:11:54 AM UTC 24 |
| Finished | Oct 15 01:12:00 AM UTC 24 |
| Peak memory | 247624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173207742 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.173207742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2471397117 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 863783071784 ps |
| CPU time | 7294.76 seconds |
| Started | Oct 15 01:11:54 AM UTC 24 |
| Finished | Oct 15 03:14:44 AM UTC 24 |
| Peak memory | 399672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24713971 17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.2471397117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2616295767 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2349065555 ps |
| CPU time | 33.68 seconds |
| Started | Oct 15 01:11:54 AM UTC 24 |
| Finished | Oct 15 01:12:29 AM UTC 24 |
| Peak memory | 221612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616295767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2616295767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2690184580 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 4304578772 ps |
| CPU time | 398.46 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:18:36 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690184580 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.2690184580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3229013382 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 751188442 ps |
| CPU time | 42.41 seconds |
| Started | Oct 15 01:11:52 AM UTC 24 |
| Finished | Oct 15 01:12:36 AM UTC 24 |
| Peak memory | 320400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3229013382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ throughput_w_partial_write.3229013382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2524264472 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 61945112765 ps |
| CPU time | 960.07 seconds |
| Started | Oct 15 01:23:13 AM UTC 24 |
| Finished | Oct 15 01:39:24 AM UTC 24 |
| Peak memory | 384076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524264472 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_duri ng_key_req.2524264472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2399897116 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 23856172 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 01:23:57 AM UTC 24 |
| Finished | Oct 15 01:23:59 AM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399897116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.2399897116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2528581009 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 159869004248 ps |
| CPU time | 2081.48 seconds |
| Started | Oct 15 01:22:46 AM UTC 24 |
| Finished | Oct 15 01:57:52 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528581009 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.2528581009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2453289353 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 32782498893 ps |
| CPU time | 1050.57 seconds |
| Started | Oct 15 01:23:16 AM UTC 24 |
| Finished | Oct 15 01:40:57 AM UTC 24 |
| Peak memory | 388040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453289353 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.2453289353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.569353572 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 813979816 ps |
| CPU time | 95.26 seconds |
| Started | Oct 15 01:22:54 AM UTC 24 |
| Finished | Oct 15 01:24:31 AM UTC 24 |
| Peak memory | 373632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 569353572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_m ax_throughput.569353572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.3881177330 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3248937756 ps |
| CPU time | 175.79 seconds |
| Started | Oct 15 01:23:30 AM UTC 24 |
| Finished | Oct 15 01:26:29 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881177330 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.3881177330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.4043712856 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 14284914649 ps |
| CPU time | 415.88 seconds |
| Started | Oct 15 01:23:28 AM UTC 24 |
| Finished | Oct 15 01:30:30 AM UTC 24 |
| Peak memory | 221432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043712856 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.4043712856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2040966401 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 11892011036 ps |
| CPU time | 899.15 seconds |
| Started | Oct 15 01:22:40 AM UTC 24 |
| Finished | Oct 15 01:37:49 AM UTC 24 |
| Peak memory | 388036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040966401 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.2040966401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1334556790 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 7235343863 ps |
| CPU time | 20.47 seconds |
| Started | Oct 15 01:22:51 AM UTC 24 |
| Finished | Oct 15 01:23:12 AM UTC 24 |
| Peak memory | 261192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334556790 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.1334556790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1082736453 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 89293667542 ps |
| CPU time | 652.03 seconds |
| Started | Oct 15 01:22:51 AM UTC 24 |
| Finished | Oct 15 01:33:51 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082736453 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_a ccess_b2b.1082736453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2036627446 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2809855215 ps |
| CPU time | 5.37 seconds |
| Started | Oct 15 01:23:23 AM UTC 24 |
| Finished | Oct 15 01:23:30 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036627446 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2036627446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_readback_err.1165973902 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 700239859 ps |
| CPU time | 9.41 seconds |
| Started | Oct 15 01:23:41 AM UTC 24 |
| Finished | Oct 15 01:23:52 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165973902 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_readback_err.1165973902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.4281310494 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3846163180 ps |
| CPU time | 1278.59 seconds |
| Started | Oct 15 01:23:18 AM UTC 24 |
| Finished | Oct 15 01:44:51 AM UTC 24 |
| Peak memory | 385988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281310494 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.4281310494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.514876565 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4990529045 ps |
| CPU time | 25.93 seconds |
| Started | Oct 15 01:22:30 AM UTC 24 |
| Finished | Oct 15 01:22:58 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514876565 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.514876565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1111207329 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 35845111339 ps |
| CPU time | 1989.93 seconds |
| Started | Oct 15 01:23:53 AM UTC 24 |
| Finished | Oct 15 01:57:25 AM UTC 24 |
| Peak memory | 385996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11112073 29 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_a ll.1111207329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1207332326 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 634138065 ps |
| CPU time | 11.1 seconds |
| Started | Oct 15 01:23:52 AM UTC 24 |
| Finished | Oct 15 01:24:04 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207332326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1207332326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.1252867443 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4438912244 ps |
| CPU time | 318.09 seconds |
| Started | Oct 15 01:22:49 AM UTC 24 |
| Finished | Oct 15 01:28:12 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252867443 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.1252867443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1566483187 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2846286724 ps |
| CPU time | 15.47 seconds |
| Started | Oct 15 01:22:59 AM UTC 24 |
| Finished | Oct 15 01:23:16 AM UTC 24 |
| Peak memory | 234436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1566483187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _throughput_w_partial_write.1566483187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3026319957 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 25985782316 ps |
| CPU time | 667.25 seconds |
| Started | Oct 15 01:24:36 AM UTC 24 |
| Finished | Oct 15 01:35:51 AM UTC 24 |
| Peak memory | 371664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026319957 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_duri ng_key_req.3026319957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1399361382 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 11715559 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 01:25:49 AM UTC 24 |
| Finished | Oct 15 01:25:51 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399361382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1399361382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.4247966045 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 122161601017 ps |
| CPU time | 2105.36 seconds |
| Started | Oct 15 01:24:06 AM UTC 24 |
| Finished | Oct 15 01:59:35 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247966045 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.4247966045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2874971941 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 39376283486 ps |
| CPU time | 769.56 seconds |
| Started | Oct 15 01:24:45 AM UTC 24 |
| Finished | Oct 15 01:37:43 AM UTC 24 |
| Peak memory | 383948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874971941 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.2874971941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1230635548 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 33440381257 ps |
| CPU time | 70.13 seconds |
| Started | Oct 15 01:24:36 AM UTC 24 |
| Finished | Oct 15 01:25:48 AM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230635548 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.1230635548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2011310631 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1549574358 ps |
| CPU time | 76.55 seconds |
| Started | Oct 15 01:24:29 AM UTC 24 |
| Finished | Oct 15 01:25:48 AM UTC 24 |
| Peak memory | 371512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2011310631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ max_throughput.2011310631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2641052285 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 75241669710 ps |
| CPU time | 203.14 seconds |
| Started | Oct 15 01:25:04 AM UTC 24 |
| Finished | Oct 15 01:28:31 AM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641052285 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.2641052285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1376810117 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 86156380962 ps |
| CPU time | 369.19 seconds |
| Started | Oct 15 01:25:02 AM UTC 24 |
| Finished | Oct 15 01:31:16 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376810117 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.1376810117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2336543985 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3771631127 ps |
| CPU time | 125.91 seconds |
| Started | Oct 15 01:24:05 AM UTC 24 |
| Finished | Oct 15 01:26:13 AM UTC 24 |
| Peak memory | 328572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336543985 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.2336543985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.904592717 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 6398690216 ps |
| CPU time | 17.86 seconds |
| Started | Oct 15 01:24:15 AM UTC 24 |
| Finished | Oct 15 01:24:35 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904592717 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.904592717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1414654889 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 16571777990 ps |
| CPU time | 645.64 seconds |
| Started | Oct 15 01:24:22 AM UTC 24 |
| Finished | Oct 15 01:35:16 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414654889 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_a ccess_b2b.1414654889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.988676135 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 678616873 ps |
| CPU time | 4.71 seconds |
| Started | Oct 15 01:24:55 AM UTC 24 |
| Finished | Oct 15 01:25:01 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988676135 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.988676135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_readback_err.1323449460 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 817093249 ps |
| CPU time | 9.9 seconds |
| Started | Oct 15 01:25:23 AM UTC 24 |
| Finished | Oct 15 01:25:34 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323449460 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_readback_err.1323449460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.59656923 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 8441136348 ps |
| CPU time | 749.11 seconds |
| Started | Oct 15 01:24:54 AM UTC 24 |
| Finished | Oct 15 01:37:32 AM UTC 24 |
| Peak memory | 363376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59656923 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.59656923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.2333751071 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1964184037 ps |
| CPU time | 27.18 seconds |
| Started | Oct 15 01:24:00 AM UTC 24 |
| Finished | Oct 15 01:24:28 AM UTC 24 |
| Peak memory | 283520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333751071 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2333751071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.528786775 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 86127244835 ps |
| CPU time | 6167.57 seconds |
| Started | Oct 15 01:25:36 AM UTC 24 |
| Finished | Oct 15 03:09:24 AM UTC 24 |
| Peak memory | 399748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52878677 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.528786775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.662033047 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 728305773 ps |
| CPU time | 26.85 seconds |
| Started | Oct 15 01:25:27 AM UTC 24 |
| Finished | Oct 15 01:25:56 AM UTC 24 |
| Peak memory | 221612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662033047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.662033047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.723674338 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 5040638327 ps |
| CPU time | 313.13 seconds |
| Started | Oct 15 01:24:08 AM UTC 24 |
| Finished | Oct 15 01:29:26 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723674338 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.723674338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2329396447 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2683656414 ps |
| CPU time | 11.59 seconds |
| Started | Oct 15 01:24:32 AM UTC 24 |
| Finished | Oct 15 01:24:44 AM UTC 24 |
| Peak memory | 223460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2329396447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl _throughput_w_partial_write.2329396447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3729748325 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 15632222700 ps |
| CPU time | 1015.61 seconds |
| Started | Oct 15 01:26:14 AM UTC 24 |
| Finished | Oct 15 01:43:21 AM UTC 24 |
| Peak memory | 386060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729748325 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_duri ng_key_req.3729748325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3885542461 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 49478928 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 01:26:50 AM UTC 24 |
| Finished | Oct 15 01:26:52 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885542461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3885542461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.4264595573 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 245710930887 ps |
| CPU time | 1824.66 seconds |
| Started | Oct 15 01:25:52 AM UTC 24 |
| Finished | Oct 15 01:56:39 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264595573 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.4264595573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.2363972419 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 7401482874 ps |
| CPU time | 307.5 seconds |
| Started | Oct 15 01:26:25 AM UTC 24 |
| Finished | Oct 15 01:31:36 AM UTC 24 |
| Peak memory | 361340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363972419 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.2363972419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3279072302 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 51675976684 ps |
| CPU time | 99.87 seconds |
| Started | Oct 15 01:26:14 AM UTC 24 |
| Finished | Oct 15 01:27:56 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279072302 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.3279072302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.94950855 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2692559288 ps |
| CPU time | 25.8 seconds |
| Started | Oct 15 01:26:08 AM UTC 24 |
| Finished | Oct 15 01:26:35 AM UTC 24 |
| Peak memory | 265352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 94950855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma x_throughput.94950855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1195471780 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 7035686066 ps |
| CPU time | 78.58 seconds |
| Started | Oct 15 01:26:36 AM UTC 24 |
| Finished | Oct 15 01:27:56 AM UTC 24 |
| Peak memory | 221444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195471780 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.1195471780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.959771577 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 28764862744 ps |
| CPU time | 146.89 seconds |
| Started | Oct 15 01:26:35 AM UTC 24 |
| Finished | Oct 15 01:29:04 AM UTC 24 |
| Peak memory | 221588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959771577 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.959771577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.1791931095 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 18438476181 ps |
| CPU time | 206.98 seconds |
| Started | Oct 15 01:25:49 AM UTC 24 |
| Finished | Oct 15 01:29:19 AM UTC 24 |
| Peak memory | 371648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791931095 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.1791931095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.867954380 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3101623534 ps |
| CPU time | 33.81 seconds |
| Started | Oct 15 01:25:59 AM UTC 24 |
| Finished | Oct 15 01:26:34 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867954380 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.867954380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.3127870039 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 10244855605 ps |
| CPU time | 408.14 seconds |
| Started | Oct 15 01:26:06 AM UTC 24 |
| Finished | Oct 15 01:33:00 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127870039 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_a ccess_b2b.3127870039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.41139118 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 710175711 ps |
| CPU time | 5.83 seconds |
| Started | Oct 15 01:26:30 AM UTC 24 |
| Finished | Oct 15 01:26:37 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41139118 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.41139118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_readback_err.1935608650 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1328637828 ps |
| CPU time | 9.36 seconds |
| Started | Oct 15 01:26:38 AM UTC 24 |
| Finished | Oct 15 01:26:49 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935608650 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_readback_err.1935608650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.3343527426 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5407663779 ps |
| CPU time | 16.98 seconds |
| Started | Oct 15 01:25:49 AM UTC 24 |
| Finished | Oct 15 01:26:07 AM UTC 24 |
| Peak memory | 273404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343527426 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3343527426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3848208461 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 97483453691 ps |
| CPU time | 2014.69 seconds |
| Started | Oct 15 01:26:49 AM UTC 24 |
| Finished | Oct 15 02:00:45 AM UTC 24 |
| Peak memory | 396360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38482084 61 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_a ll.3848208461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.527784426 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3195088397 ps |
| CPU time | 79.92 seconds |
| Started | Oct 15 01:26:41 AM UTC 24 |
| Finished | Oct 15 01:28:03 AM UTC 24 |
| Peak memory | 221612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527784426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.527784426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3538766611 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3893582456 ps |
| CPU time | 272.24 seconds |
| Started | Oct 15 01:25:57 AM UTC 24 |
| Finished | Oct 15 01:30:33 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538766611 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.3538766611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.2479397181 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1456084687 ps |
| CPU time | 37.89 seconds |
| Started | Oct 15 01:26:14 AM UTC 24 |
| Finished | Oct 15 01:26:54 AM UTC 24 |
| Peak memory | 297860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2479397181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _throughput_w_partial_write.2479397181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2687879121 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 21937140148 ps |
| CPU time | 929.03 seconds |
| Started | Oct 15 01:28:03 AM UTC 24 |
| Finished | Oct 15 01:43:43 AM UTC 24 |
| Peak memory | 388172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687879121 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_duri ng_key_req.2687879121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.415558512 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 31457968 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 01:29:15 AM UTC 24 |
| Finished | Oct 15 01:29:17 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415558512 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.415558512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.1358101080 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 423721223337 ps |
| CPU time | 2666.71 seconds |
| Started | Oct 15 01:26:55 AM UTC 24 |
| Finished | Oct 15 02:11:50 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358101080 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.1358101080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.2486208545 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 11917461925 ps |
| CPU time | 594.86 seconds |
| Started | Oct 15 01:28:12 AM UTC 24 |
| Finished | Oct 15 01:38:14 AM UTC 24 |
| Peak memory | 388040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486208545 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.2486208545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.3124235997 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 49605876467 ps |
| CPU time | 87.88 seconds |
| Started | Oct 15 01:27:57 AM UTC 24 |
| Finished | Oct 15 01:29:27 AM UTC 24 |
| Peak memory | 221424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124235997 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.3124235997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1719154304 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3303550728 ps |
| CPU time | 74.68 seconds |
| Started | Oct 15 01:27:40 AM UTC 24 |
| Finished | Oct 15 01:28:57 AM UTC 24 |
| Peak memory | 371660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1719154304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ max_throughput.1719154304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.4267319910 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2707935579 ps |
| CPU time | 88.22 seconds |
| Started | Oct 15 01:28:41 AM UTC 24 |
| Finished | Oct 15 01:30:11 AM UTC 24 |
| Peak memory | 221484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267319910 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.4267319910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3647671161 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 114999341583 ps |
| CPU time | 265.28 seconds |
| Started | Oct 15 01:28:38 AM UTC 24 |
| Finished | Oct 15 01:33:07 AM UTC 24 |
| Peak memory | 221424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647671161 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.3647671161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1146158841 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 8543235848 ps |
| CPU time | 909.69 seconds |
| Started | Oct 15 01:26:55 AM UTC 24 |
| Finished | Oct 15 01:42:14 AM UTC 24 |
| Peak memory | 381876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146158841 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.1146158841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.2610684650 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 823100332 ps |
| CPU time | 21.64 seconds |
| Started | Oct 15 01:27:16 AM UTC 24 |
| Finished | Oct 15 01:27:39 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610684650 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.2610684650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3542684613 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 23375178212 ps |
| CPU time | 281.03 seconds |
| Started | Oct 15 01:27:18 AM UTC 24 |
| Finished | Oct 15 01:32:03 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542684613 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_a ccess_b2b.3542684613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.4286865578 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2279579641 ps |
| CPU time | 5.44 seconds |
| Started | Oct 15 01:28:34 AM UTC 24 |
| Finished | Oct 15 01:28:40 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286865578 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.4286865578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_readback_err.2415610783 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1346017123 ps |
| CPU time | 8.59 seconds |
| Started | Oct 15 01:28:58 AM UTC 24 |
| Finished | Oct 15 01:29:08 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415610783 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_readback_err.2415610783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.781971283 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 61759833486 ps |
| CPU time | 543.48 seconds |
| Started | Oct 15 01:28:32 AM UTC 24 |
| Finished | Oct 15 01:37:42 AM UTC 24 |
| Peak memory | 373820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781971283 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.781971283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.3673394498 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3137662674 ps |
| CPU time | 20.38 seconds |
| Started | Oct 15 01:26:53 AM UTC 24 |
| Finished | Oct 15 01:27:15 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673394498 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3673394498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3799658017 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 42208031348 ps |
| CPU time | 975.11 seconds |
| Started | Oct 15 01:29:09 AM UTC 24 |
| Finished | Oct 15 01:45:34 AM UTC 24 |
| Peak memory | 398200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37996580 17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_a ll.3799658017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.372506429 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3949349892 ps |
| CPU time | 131.4 seconds |
| Started | Oct 15 01:29:05 AM UTC 24 |
| Finished | Oct 15 01:31:19 AM UTC 24 |
| Peak memory | 394232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372506429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.372506429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2102493649 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 11175239495 ps |
| CPU time | 389.95 seconds |
| Started | Oct 15 01:27:05 AM UTC 24 |
| Finished | Oct 15 01:33:40 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102493649 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.2102493649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3211154615 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2995108532 ps |
| CPU time | 75.44 seconds |
| Started | Oct 15 01:27:57 AM UTC 24 |
| Finished | Oct 15 01:29:14 AM UTC 24 |
| Peak memory | 373592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3211154615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _throughput_w_partial_write.3211154615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.200952798 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 27765277029 ps |
| CPU time | 910.13 seconds |
| Started | Oct 15 01:30:34 AM UTC 24 |
| Finished | Oct 15 01:45:56 AM UTC 24 |
| Peak memory | 381880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200952798 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_durin g_key_req.200952798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3359631405 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 25292941 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 01:31:55 AM UTC 24 |
| Finished | Oct 15 01:31:58 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359631405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.3359631405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.2549433150 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 85250352942 ps |
| CPU time | 1509.27 seconds |
| Started | Oct 15 01:29:26 AM UTC 24 |
| Finished | Oct 15 01:54:52 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549433150 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.2549433150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.1857387613 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 136067392983 ps |
| CPU time | 1416.31 seconds |
| Started | Oct 15 01:31:09 AM UTC 24 |
| Finished | Oct 15 01:55:01 AM UTC 24 |
| Peak memory | 387968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857387613 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.1857387613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1444037653 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 24352944643 ps |
| CPU time | 37.41 seconds |
| Started | Oct 15 01:30:31 AM UTC 24 |
| Finished | Oct 15 01:31:10 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444037653 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.1444037653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.740966370 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 778218553 ps |
| CPU time | 49.07 seconds |
| Started | Oct 15 01:30:17 AM UTC 24 |
| Finished | Oct 15 01:31:08 AM UTC 24 |
| Peak memory | 322568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 740966370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_m ax_throughput.740966370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.768497300 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5264949986 ps |
| CPU time | 165.86 seconds |
| Started | Oct 15 01:31:26 AM UTC 24 |
| Finished | Oct 15 01:34:15 AM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768497300 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.768497300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.75951746 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 22822634446 ps |
| CPU time | 311.6 seconds |
| Started | Oct 15 01:31:20 AM UTC 24 |
| Finished | Oct 15 01:36:36 AM UTC 24 |
| Peak memory | 221428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75951746 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.75951746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3729693704 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5201427664 ps |
| CPU time | 468.32 seconds |
| Started | Oct 15 01:29:19 AM UTC 24 |
| Finished | Oct 15 01:37:14 AM UTC 24 |
| Peak memory | 388032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729693704 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.3729693704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.348185266 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1850255008 ps |
| CPU time | 33.09 seconds |
| Started | Oct 15 01:29:54 AM UTC 24 |
| Finished | Oct 15 01:30:28 AM UTC 24 |
| Peak memory | 304012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348185266 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.348185266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.3634495003 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 10210516640 ps |
| CPU time | 275.27 seconds |
| Started | Oct 15 01:30:12 AM UTC 24 |
| Finished | Oct 15 01:34:51 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634495003 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_a ccess_b2b.3634495003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2252131929 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2576993853 ps |
| CPU time | 7.22 seconds |
| Started | Oct 15 01:31:17 AM UTC 24 |
| Finished | Oct 15 01:31:25 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252131929 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2252131929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_readback_err.3104936601 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1389421541 ps |
| CPU time | 7.61 seconds |
| Started | Oct 15 01:31:37 AM UTC 24 |
| Finished | Oct 15 01:31:46 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104936601 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_readback_err.3104936601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.3550486893 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 21390131968 ps |
| CPU time | 1363.46 seconds |
| Started | Oct 15 01:31:11 AM UTC 24 |
| Finished | Oct 15 01:54:09 AM UTC 24 |
| Peak memory | 387968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550486893 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3550486893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1515078031 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1450208708 ps |
| CPU time | 32.96 seconds |
| Started | Oct 15 01:29:18 AM UTC 24 |
| Finished | Oct 15 01:29:53 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515078031 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1515078031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3057849020 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 477280886370 ps |
| CPU time | 6616.65 seconds |
| Started | Oct 15 01:31:46 AM UTC 24 |
| Finished | Oct 15 03:23:13 AM UTC 24 |
| Peak memory | 389444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30578490 20 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_a ll.3057849020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.888575364 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 10237029995 ps |
| CPU time | 69.71 seconds |
| Started | Oct 15 01:31:46 AM UTC 24 |
| Finished | Oct 15 01:32:58 AM UTC 24 |
| Peak memory | 225836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888575364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.888575364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3028884775 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 20846772194 ps |
| CPU time | 338.53 seconds |
| Started | Oct 15 01:29:27 AM UTC 24 |
| Finished | Oct 15 01:35:11 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028884775 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.3028884775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1536775640 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 787002145 ps |
| CPU time | 89.02 seconds |
| Started | Oct 15 01:30:29 AM UTC 24 |
| Finished | Oct 15 01:32:00 AM UTC 24 |
| Peak memory | 375684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1536775640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _throughput_w_partial_write.1536775640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.139963316 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 59856872164 ps |
| CPU time | 374.78 seconds |
| Started | Oct 15 01:33:06 AM UTC 24 |
| Finished | Oct 15 01:39:25 AM UTC 24 |
| Peak memory | 384012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139963316 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_durin g_key_req.139963316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.586673244 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 43964393 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 01:34:31 AM UTC 24 |
| Finished | Oct 15 01:34:33 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586673244 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.586673244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.195551298 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 14919202698 ps |
| CPU time | 1063.73 seconds |
| Started | Oct 15 01:32:04 AM UTC 24 |
| Finished | Oct 15 01:50:00 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195551298 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.195551298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.187468054 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 14297957266 ps |
| CPU time | 703.45 seconds |
| Started | Oct 15 01:33:08 AM UTC 24 |
| Finished | Oct 15 01:44:59 AM UTC 24 |
| Peak memory | 375872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187468054 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.187468054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3783354174 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 7214540080 ps |
| CPU time | 66 seconds |
| Started | Oct 15 01:33:01 AM UTC 24 |
| Finished | Oct 15 01:34:08 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783354174 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.3783354174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.717992861 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 714056246 ps |
| CPU time | 20.25 seconds |
| Started | Oct 15 01:32:43 AM UTC 24 |
| Finished | Oct 15 01:33:05 AM UTC 24 |
| Peak memory | 261128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 717992861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_m ax_throughput.717992861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1845755699 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4164873737 ps |
| CPU time | 90.49 seconds |
| Started | Oct 15 01:34:02 AM UTC 24 |
| Finished | Oct 15 01:35:35 AM UTC 24 |
| Peak memory | 228292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845755699 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.1845755699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1192042017 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 149485621658 ps |
| CPU time | 247.56 seconds |
| Started | Oct 15 01:33:59 AM UTC 24 |
| Finished | Oct 15 01:38:11 AM UTC 24 |
| Peak memory | 221468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192042017 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.1192042017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.4075372821 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 43418293454 ps |
| CPU time | 543.75 seconds |
| Started | Oct 15 01:32:01 AM UTC 24 |
| Finished | Oct 15 01:41:11 AM UTC 24 |
| Peak memory | 377684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075372821 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.4075372821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.4155770571 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5977431811 ps |
| CPU time | 29.98 seconds |
| Started | Oct 15 01:32:11 AM UTC 24 |
| Finished | Oct 15 01:32:43 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155770571 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.4155770571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.357159942 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5425122995 ps |
| CPU time | 329.36 seconds |
| Started | Oct 15 01:32:11 AM UTC 24 |
| Finished | Oct 15 01:37:45 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357159942 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_ac cess_b2b.357159942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.2643237286 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1768417285 ps |
| CPU time | 4.9 seconds |
| Started | Oct 15 01:33:52 AM UTC 24 |
| Finished | Oct 15 01:33:58 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643237286 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2643237286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_readback_err.3995710817 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 6007473934 ps |
| CPU time | 14.27 seconds |
| Started | Oct 15 01:34:10 AM UTC 24 |
| Finished | Oct 15 01:34:25 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995710817 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_readback_err.3995710817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.3460828479 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 7138486153 ps |
| CPU time | 389.45 seconds |
| Started | Oct 15 01:33:41 AM UTC 24 |
| Finished | Oct 15 01:40:16 AM UTC 24 |
| Peak memory | 383944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460828479 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3460828479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.155248949 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2869366203 ps |
| CPU time | 10.47 seconds |
| Started | Oct 15 01:31:59 AM UTC 24 |
| Finished | Oct 15 01:32:10 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155248949 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.155248949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1663035286 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 123894594642 ps |
| CPU time | 3138.34 seconds |
| Started | Oct 15 01:34:26 AM UTC 24 |
| Finished | Oct 15 02:27:16 AM UTC 24 |
| Peak memory | 390012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16630352 86 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_a ll.1663035286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.835466997 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 573003314 ps |
| CPU time | 13.44 seconds |
| Started | Oct 15 01:34:16 AM UTC 24 |
| Finished | Oct 15 01:34:30 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835466997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.835466997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1705826516 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 6711339804 ps |
| CPU time | 509.04 seconds |
| Started | Oct 15 01:32:11 AM UTC 24 |
| Finished | Oct 15 01:40:47 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705826516 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.1705826516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.827169114 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 11186658469 ps |
| CPU time | 106.27 seconds |
| Started | Oct 15 01:32:59 AM UTC 24 |
| Finished | Oct 15 01:34:47 AM UTC 24 |
| Peak memory | 379852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =827169114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ throughput_w_partial_write.827169114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3072774743 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 13280590037 ps |
| CPU time | 414.66 seconds |
| Started | Oct 15 01:35:42 AM UTC 24 |
| Finished | Oct 15 01:42:42 AM UTC 24 |
| Peak memory | 382032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072774743 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_duri ng_key_req.3072774743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3949479923 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 39647463 ps |
| CPU time | 1 seconds |
| Started | Oct 15 01:37:15 AM UTC 24 |
| Finished | Oct 15 01:37:17 AM UTC 24 |
| Peak memory | 210460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949479923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3949479923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.835719355 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 18111247509 ps |
| CPU time | 1268.79 seconds |
| Started | Oct 15 01:34:52 AM UTC 24 |
| Finished | Oct 15 01:56:16 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835719355 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.835719355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.1348743337 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 17861242876 ps |
| CPU time | 445.07 seconds |
| Started | Oct 15 01:35:51 AM UTC 24 |
| Finished | Oct 15 01:43:22 AM UTC 24 |
| Peak memory | 375744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348743337 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.1348743337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.2889635811 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 9151531459 ps |
| CPU time | 48.38 seconds |
| Started | Oct 15 01:35:36 AM UTC 24 |
| Finished | Oct 15 01:36:26 AM UTC 24 |
| Peak memory | 221484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889635811 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.2889635811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.857272117 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1510790891 ps |
| CPU time | 60.21 seconds |
| Started | Oct 15 01:35:24 AM UTC 24 |
| Finished | Oct 15 01:36:26 AM UTC 24 |
| Peak memory | 340864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 857272117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_m ax_throughput.857272117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.20152743 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 10053069583 ps |
| CPU time | 195.56 seconds |
| Started | Oct 15 01:36:27 AM UTC 24 |
| Finished | Oct 15 01:39:46 AM UTC 24 |
| Peak memory | 221580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20152743 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.20152743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.2911766268 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 20998792314 ps |
| CPU time | 322.59 seconds |
| Started | Oct 15 01:36:23 AM UTC 24 |
| Finished | Oct 15 01:41:50 AM UTC 24 |
| Peak memory | 221352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911766268 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.2911766268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3705057220 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 23749254753 ps |
| CPU time | 529.54 seconds |
| Started | Oct 15 01:34:48 AM UTC 24 |
| Finished | Oct 15 01:43:44 AM UTC 24 |
| Peak memory | 373616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705057220 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3705057220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2893405684 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1180937358 ps |
| CPU time | 18.28 seconds |
| Started | Oct 15 01:35:12 AM UTC 24 |
| Finished | Oct 15 01:35:31 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893405684 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.2893405684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1055705323 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5810853302 ps |
| CPU time | 318.29 seconds |
| Started | Oct 15 01:35:18 AM UTC 24 |
| Finished | Oct 15 01:40:40 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055705323 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_a ccess_b2b.1055705323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.1572072658 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1359044858 ps |
| CPU time | 6.72 seconds |
| Started | Oct 15 01:36:14 AM UTC 24 |
| Finished | Oct 15 01:36:21 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572072658 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1572072658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_readback_err.563205423 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2637280528 ps |
| CPU time | 7.04 seconds |
| Started | Oct 15 01:36:27 AM UTC 24 |
| Finished | Oct 15 01:36:35 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563205423 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_readback_err.563205423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.1611713916 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 16616391567 ps |
| CPU time | 437.82 seconds |
| Started | Oct 15 01:36:13 AM UTC 24 |
| Finished | Oct 15 01:43:36 AM UTC 24 |
| Peak memory | 371836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611713916 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1611713916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.3813287956 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1543923572 ps |
| CPU time | 96.75 seconds |
| Started | Oct 15 01:34:34 AM UTC 24 |
| Finished | Oct 15 01:36:13 AM UTC 24 |
| Peak memory | 371512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813287956 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3813287956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1383489260 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 171402817255 ps |
| CPU time | 5188.73 seconds |
| Started | Oct 15 01:36:37 AM UTC 24 |
| Finished | Oct 15 03:04:01 AM UTC 24 |
| Peak memory | 398404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13834892 60 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_a ll.1383489260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1481770640 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 938524127 ps |
| CPU time | 50.1 seconds |
| Started | Oct 15 01:36:36 AM UTC 24 |
| Finished | Oct 15 01:37:28 AM UTC 24 |
| Peak memory | 221492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481770640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1481770640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1735274840 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4727533398 ps |
| CPU time | 346.06 seconds |
| Started | Oct 15 01:34:58 AM UTC 24 |
| Finished | Oct 15 01:40:50 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735274840 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.1735274840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3439062066 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 712506782 ps |
| CPU time | 8.63 seconds |
| Started | Oct 15 01:35:32 AM UTC 24 |
| Finished | Oct 15 01:35:42 AM UTC 24 |
| Peak memory | 230280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3439062066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _throughput_w_partial_write.3439062066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.794385393 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 51960404349 ps |
| CPU time | 626.32 seconds |
| Started | Oct 15 01:38:08 AM UTC 24 |
| Finished | Oct 15 01:48:41 AM UTC 24 |
| Peak memory | 373824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794385393 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_durin g_key_req.794385393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1747612625 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 62309478 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 01:39:02 AM UTC 24 |
| Finished | Oct 15 01:39:04 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747612625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1747612625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.3494474509 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 122345286367 ps |
| CPU time | 1479.8 seconds |
| Started | Oct 15 01:37:33 AM UTC 24 |
| Finished | Oct 15 02:02:31 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494474509 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.3494474509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2149477770 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 53407680217 ps |
| CPU time | 419.54 seconds |
| Started | Oct 15 01:38:12 AM UTC 24 |
| Finished | Oct 15 01:45:17 AM UTC 24 |
| Peak memory | 385996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149477770 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.2149477770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2331952492 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 5601599747 ps |
| CPU time | 59.85 seconds |
| Started | Oct 15 01:37:50 AM UTC 24 |
| Finished | Oct 15 01:38:52 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331952492 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2331952492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.441368905 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 758192051 ps |
| CPU time | 60.52 seconds |
| Started | Oct 15 01:37:46 AM UTC 24 |
| Finished | Oct 15 01:38:48 AM UTC 24 |
| Peak memory | 351112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 441368905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_m ax_throughput.441368905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3469754374 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2946921731 ps |
| CPU time | 97.83 seconds |
| Started | Oct 15 01:38:43 AM UTC 24 |
| Finished | Oct 15 01:40:23 AM UTC 24 |
| Peak memory | 221412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469754374 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.3469754374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1423315811 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 24682931746 ps |
| CPU time | 162.3 seconds |
| Started | Oct 15 01:38:27 AM UTC 24 |
| Finished | Oct 15 01:41:12 AM UTC 24 |
| Peak memory | 221428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423315811 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.1423315811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2405607376 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 5622559741 ps |
| CPU time | 89.8 seconds |
| Started | Oct 15 01:37:29 AM UTC 24 |
| Finished | Oct 15 01:39:01 AM UTC 24 |
| Peak memory | 339004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405607376 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.2405607376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1605312581 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1526310174 ps |
| CPU time | 33.56 seconds |
| Started | Oct 15 01:37:43 AM UTC 24 |
| Finished | Oct 15 01:38:18 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605312581 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.1605312581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.3912385648 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 21112261298 ps |
| CPU time | 374.69 seconds |
| Started | Oct 15 01:37:43 AM UTC 24 |
| Finished | Oct 15 01:44:03 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912385648 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_a ccess_b2b.3912385648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3124195800 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1355921667 ps |
| CPU time | 6.02 seconds |
| Started | Oct 15 01:38:19 AM UTC 24 |
| Finished | Oct 15 01:38:26 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124195800 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3124195800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_readback_err.3612040358 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 702783885 ps |
| CPU time | 10.52 seconds |
| Started | Oct 15 01:38:49 AM UTC 24 |
| Finished | Oct 15 01:39:01 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612040358 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_readback_err.3612040358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.2873527948 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 12940885697 ps |
| CPU time | 665.74 seconds |
| Started | Oct 15 01:38:15 AM UTC 24 |
| Finished | Oct 15 01:49:28 AM UTC 24 |
| Peak memory | 379840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873527948 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2873527948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.1819098182 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2021154144 ps |
| CPU time | 26.24 seconds |
| Started | Oct 15 01:37:18 AM UTC 24 |
| Finished | Oct 15 01:37:45 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819098182 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1819098182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3150956767 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 573637511011 ps |
| CPU time | 2394.85 seconds |
| Started | Oct 15 01:39:02 AM UTC 24 |
| Finished | Oct 15 02:19:21 AM UTC 24 |
| Peak memory | 387972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31509567 67 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_a ll.3150956767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.194253084 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 608285918 ps |
| CPU time | 33.45 seconds |
| Started | Oct 15 01:38:52 AM UTC 24 |
| Finished | Oct 15 01:39:27 AM UTC 24 |
| Peak memory | 221548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194253084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.194253084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3249277790 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2641792857 ps |
| CPU time | 209.25 seconds |
| Started | Oct 15 01:37:40 AM UTC 24 |
| Finished | Oct 15 01:41:12 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249277790 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.3249277790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.4132723100 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 7651538994 ps |
| CPU time | 18.82 seconds |
| Started | Oct 15 01:37:46 AM UTC 24 |
| Finished | Oct 15 01:38:06 AM UTC 24 |
| Peak memory | 244604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4132723100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _throughput_w_partial_write.4132723100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.367379962 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 42930663092 ps |
| CPU time | 727.25 seconds |
| Started | Oct 15 01:40:17 AM UTC 24 |
| Finished | Oct 15 01:52:32 AM UTC 24 |
| Peak memory | 375752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367379962 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_durin g_key_req.367379962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2729441166 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 36491591 ps |
| CPU time | 0.82 seconds |
| Started | Oct 15 01:41:00 AM UTC 24 |
| Finished | Oct 15 01:41:02 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729441166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2729441166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.2065434432 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 179433320046 ps |
| CPU time | 1635.68 seconds |
| Started | Oct 15 01:39:26 AM UTC 24 |
| Finished | Oct 15 02:07:01 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065434432 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.2065434432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.2656647505 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 13959896649 ps |
| CPU time | 826.54 seconds |
| Started | Oct 15 01:40:19 AM UTC 24 |
| Finished | Oct 15 01:54:15 AM UTC 24 |
| Peak memory | 388044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656647505 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.2656647505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.887800913 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 246698804948 ps |
| CPU time | 202.75 seconds |
| Started | Oct 15 01:40:16 AM UTC 24 |
| Finished | Oct 15 01:43:41 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887800913 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.887800913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.3758432182 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2937921840 ps |
| CPU time | 26.86 seconds |
| Started | Oct 15 01:39:46 AM UTC 24 |
| Finished | Oct 15 01:40:15 AM UTC 24 |
| Peak memory | 277436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3758432182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ max_throughput.3758432182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1492306669 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4377641003 ps |
| CPU time | 93.31 seconds |
| Started | Oct 15 01:40:41 AM UTC 24 |
| Finished | Oct 15 01:42:17 AM UTC 24 |
| Peak memory | 221644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492306669 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.1492306669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3374077748 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 13812078758 ps |
| CPU time | 325.52 seconds |
| Started | Oct 15 01:40:38 AM UTC 24 |
| Finished | Oct 15 01:46:08 AM UTC 24 |
| Peak memory | 221428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374077748 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.3374077748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3936245433 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 51837813973 ps |
| CPU time | 993.96 seconds |
| Started | Oct 15 01:39:25 AM UTC 24 |
| Finished | Oct 15 01:56:10 AM UTC 24 |
| Peak memory | 383936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936245433 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.3936245433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.80867725 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1116745286 ps |
| CPU time | 27.13 seconds |
| Started | Oct 15 01:39:28 AM UTC 24 |
| Finished | Oct 15 01:39:57 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80867725 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.80867725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.185899613 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 14453140902 ps |
| CPU time | 350.94 seconds |
| Started | Oct 15 01:39:35 AM UTC 24 |
| Finished | Oct 15 01:45:31 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185899613 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_ac cess_b2b.185899613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.629361354 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1342278728 ps |
| CPU time | 6.86 seconds |
| Started | Oct 15 01:40:29 AM UTC 24 |
| Finished | Oct 15 01:40:37 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629361354 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.629361354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_readback_err.2476651315 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1074138592 ps |
| CPU time | 10.68 seconds |
| Started | Oct 15 01:40:47 AM UTC 24 |
| Finished | Oct 15 01:40:59 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476651315 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_readback_err.2476651315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.3012015792 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 55838239558 ps |
| CPU time | 543.94 seconds |
| Started | Oct 15 01:40:24 AM UTC 24 |
| Finished | Oct 15 01:49:34 AM UTC 24 |
| Peak memory | 385916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012015792 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3012015792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3228550835 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 907348078 ps |
| CPU time | 18.82 seconds |
| Started | Oct 15 01:39:05 AM UTC 24 |
| Finished | Oct 15 01:39:25 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228550835 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3228550835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3554535322 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 1527721300776 ps |
| CPU time | 5781.73 seconds |
| Started | Oct 15 01:40:58 AM UTC 24 |
| Finished | Oct 15 03:18:20 AM UTC 24 |
| Peak memory | 387464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35545353 22 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_a ll.3554535322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1933920742 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1353597378 ps |
| CPU time | 31.47 seconds |
| Started | Oct 15 01:40:50 AM UTC 24 |
| Finished | Oct 15 01:41:23 AM UTC 24 |
| Peak memory | 221684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933920742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1933920742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.118066687 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 24946929336 ps |
| CPU time | 329.9 seconds |
| Started | Oct 15 01:39:26 AM UTC 24 |
| Finished | Oct 15 01:45:01 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118066687 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.118066687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3811648055 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2801525237 ps |
| CPU time | 19.27 seconds |
| Started | Oct 15 01:39:58 AM UTC 24 |
| Finished | Oct 15 01:40:18 AM UTC 24 |
| Peak memory | 261060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3811648055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl _throughput_w_partial_write.3811648055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.2374338846 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 12094628788 ps |
| CPU time | 101.1 seconds |
| Started | Oct 15 01:42:18 AM UTC 24 |
| Finished | Oct 15 01:44:01 AM UTC 24 |
| Peak memory | 269260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374338846 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_duri ng_key_req.2374338846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1541060634 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 11155379 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 01:43:23 AM UTC 24 |
| Finished | Oct 15 01:43:25 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541060634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1541060634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.2432260228 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 122225863542 ps |
| CPU time | 2010.25 seconds |
| Started | Oct 15 01:41:13 AM UTC 24 |
| Finished | Oct 15 02:15:05 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432260228 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.2432260228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.3673186874 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 20954569569 ps |
| CPU time | 547.86 seconds |
| Started | Oct 15 01:42:22 AM UTC 24 |
| Finished | Oct 15 01:51:36 AM UTC 24 |
| Peak memory | 377716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673186874 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.3673186874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.300317507 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3373445826 ps |
| CPU time | 32.54 seconds |
| Started | Oct 15 01:42:15 AM UTC 24 |
| Finished | Oct 15 01:42:49 AM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300317507 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.300317507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3542282621 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 731432169 ps |
| CPU time | 18.58 seconds |
| Started | Oct 15 01:41:51 AM UTC 24 |
| Finished | Oct 15 01:42:10 AM UTC 24 |
| Peak memory | 248704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3542282621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ max_throughput.3542282621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1926455776 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 20362593813 ps |
| CPU time | 176.16 seconds |
| Started | Oct 15 01:42:47 AM UTC 24 |
| Finished | Oct 15 01:45:47 AM UTC 24 |
| Peak memory | 221516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926455776 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.1926455776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3535785230 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 34544839085 ps |
| CPU time | 224.73 seconds |
| Started | Oct 15 01:42:42 AM UTC 24 |
| Finished | Oct 15 01:46:31 AM UTC 24 |
| Peak memory | 221364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535785230 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.3535785230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1645200923 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 22201875483 ps |
| CPU time | 679.05 seconds |
| Started | Oct 15 01:41:12 AM UTC 24 |
| Finished | Oct 15 01:52:39 AM UTC 24 |
| Peak memory | 384068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645200923 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.1645200923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.4189155663 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 6172446469 ps |
| CPU time | 55.05 seconds |
| Started | Oct 15 01:41:24 AM UTC 24 |
| Finished | Oct 15 01:42:21 AM UTC 24 |
| Peak memory | 349052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189155663 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.4189155663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.958855172 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 16513008407 ps |
| CPU time | 247.92 seconds |
| Started | Oct 15 01:41:28 AM UTC 24 |
| Finished | Oct 15 01:45:40 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958855172 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_ac cess_b2b.958855172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.130732588 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 701442804 ps |
| CPU time | 5.98 seconds |
| Started | Oct 15 01:42:39 AM UTC 24 |
| Finished | Oct 15 01:42:46 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130732588 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.130732588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_readback_err.457799053 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2659049303 ps |
| CPU time | 10.68 seconds |
| Started | Oct 15 01:42:50 AM UTC 24 |
| Finished | Oct 15 01:43:01 AM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457799053 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_readback_err.457799053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.3365302573 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 24840835979 ps |
| CPU time | 346.28 seconds |
| Started | Oct 15 01:42:28 AM UTC 24 |
| Finished | Oct 15 01:48:20 AM UTC 24 |
| Peak memory | 365508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365302573 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3365302573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.3935900938 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4672154774 ps |
| CPU time | 23.71 seconds |
| Started | Oct 15 01:41:03 AM UTC 24 |
| Finished | Oct 15 01:41:28 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935900938 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3935900938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.4140310889 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 193327502247 ps |
| CPU time | 4354.43 seconds |
| Started | Oct 15 01:43:22 AM UTC 24 |
| Finished | Oct 15 02:56:41 AM UTC 24 |
| Peak memory | 388044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41403108 89 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_a ll.4140310889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2517726004 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 436408159 ps |
| CPU time | 22.54 seconds |
| Started | Oct 15 01:43:03 AM UTC 24 |
| Finished | Oct 15 01:43:26 AM UTC 24 |
| Peak memory | 221476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517726004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2517726004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2755580926 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 7727993666 ps |
| CPU time | 243.03 seconds |
| Started | Oct 15 01:41:13 AM UTC 24 |
| Finished | Oct 15 01:45:20 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755580926 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.2755580926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1281675051 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 728735048 ps |
| CPU time | 14.27 seconds |
| Started | Oct 15 01:42:12 AM UTC 24 |
| Finished | Oct 15 01:42:27 AM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1281675051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _throughput_w_partial_write.1281675051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.372997616 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 22140804622 ps |
| CPU time | 611.76 seconds |
| Started | Oct 15 01:11:57 AM UTC 24 |
| Finished | Oct 15 01:22:17 AM UTC 24 |
| Peak memory | 381816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372997616 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during _key_req.372997616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2884708124 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 17329497 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 01:12:02 AM UTC 24 |
| Finished | Oct 15 01:12:04 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884708124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.2884708124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3574824874 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 36803939358 ps |
| CPU time | 798.47 seconds |
| Started | Oct 15 01:11:59 AM UTC 24 |
| Finished | Oct 15 01:25:26 AM UTC 24 |
| Peak memory | 369608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574824874 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.3574824874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.3774315972 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7060744880 ps |
| CPU time | 33.3 seconds |
| Started | Oct 15 01:11:56 AM UTC 24 |
| Finished | Oct 15 01:12:31 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774315972 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.3774315972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1192304403 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 5155883530 ps |
| CPU time | 83.18 seconds |
| Started | Oct 15 01:11:56 AM UTC 24 |
| Finished | Oct 15 01:13:21 AM UTC 24 |
| Peak memory | 379764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1192304403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_m ax_throughput.1192304403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1560719779 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 21000848897 ps |
| CPU time | 337.1 seconds |
| Started | Oct 15 01:12:00 AM UTC 24 |
| Finished | Oct 15 01:17:42 AM UTC 24 |
| Peak memory | 221548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560719779 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.1560719779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2562094558 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4441554278 ps |
| CPU time | 332.64 seconds |
| Started | Oct 15 01:11:54 AM UTC 24 |
| Finished | Oct 15 01:17:31 AM UTC 24 |
| Peak memory | 373900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562094558 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.2562094558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1116118061 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1559724604 ps |
| CPU time | 12.99 seconds |
| Started | Oct 15 01:11:55 AM UTC 24 |
| Finished | Oct 15 01:12:09 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116118061 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.1116118061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2905883254 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 5918441080 ps |
| CPU time | 318.93 seconds |
| Started | Oct 15 01:11:56 AM UTC 24 |
| Finished | Oct 15 01:17:19 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905883254 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_ac cess_b2b.2905883254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.981834855 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 675646238 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 01:12:00 AM UTC 24 |
| Finished | Oct 15 01:12:06 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981834855 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.981834855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_readback_err.590551811 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 686237033 ps |
| CPU time | 7.8 seconds |
| Started | Oct 15 01:12:01 AM UTC 24 |
| Finished | Oct 15 01:12:10 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590551811 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_readback_err.590551811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1122843324 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2572174573 ps |
| CPU time | 670.03 seconds |
| Started | Oct 15 01:12:00 AM UTC 24 |
| Finished | Oct 15 01:23:18 AM UTC 24 |
| Peak memory | 388028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122843324 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1122843324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.3784604325 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3946442793 ps |
| CPU time | 24.19 seconds |
| Started | Oct 15 01:11:54 AM UTC 24 |
| Finished | Oct 15 01:12:19 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784604325 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3784604325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.644650846 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 55437638495 ps |
| CPU time | 3826.64 seconds |
| Started | Oct 15 01:12:01 AM UTC 24 |
| Finished | Oct 15 02:16:26 AM UTC 24 |
| Peak memory | 390148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64465084 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.644650846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1571923101 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5572971962 ps |
| CPU time | 43.83 seconds |
| Started | Oct 15 01:12:01 AM UTC 24 |
| Finished | Oct 15 01:12:46 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571923101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1571923101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.3633966142 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4675461630 ps |
| CPU time | 362.3 seconds |
| Started | Oct 15 01:11:55 AM UTC 24 |
| Finished | Oct 15 01:18:02 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633966142 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.3633966142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4101660540 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2512228006 ps |
| CPU time | 23.78 seconds |
| Started | Oct 15 01:11:56 AM UTC 24 |
| Finished | Oct 15 01:12:21 AM UTC 24 |
| Peak memory | 300160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4101660540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ throughput_w_partial_write.4101660540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3958473940 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 129540523725 ps |
| CPU time | 884.77 seconds |
| Started | Oct 15 01:44:15 AM UTC 24 |
| Finished | Oct 15 01:59:10 AM UTC 24 |
| Peak memory | 383872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958473940 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_duri ng_key_req.3958473940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.286683501 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 25025923 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 01:45:18 AM UTC 24 |
| Finished | Oct 15 01:45:20 AM UTC 24 |
| Peak memory | 210880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286683501 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.286683501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.918280839 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 276394105478 ps |
| CPU time | 1909.19 seconds |
| Started | Oct 15 01:43:36 AM UTC 24 |
| Finished | Oct 15 02:15:47 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918280839 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.918280839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.3090197815 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3895854278 ps |
| CPU time | 170.69 seconds |
| Started | Oct 15 01:44:32 AM UTC 24 |
| Finished | Oct 15 01:47:26 AM UTC 24 |
| Peak memory | 330700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090197815 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.3090197815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.1739017351 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 14471049576 ps |
| CPU time | 45.66 seconds |
| Started | Oct 15 01:44:04 AM UTC 24 |
| Finished | Oct 15 01:44:51 AM UTC 24 |
| Peak memory | 221328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739017351 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.1739017351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1223752443 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3123912583 ps |
| CPU time | 62.07 seconds |
| Started | Oct 15 01:43:46 AM UTC 24 |
| Finished | Oct 15 01:44:49 AM UTC 24 |
| Peak memory | 355188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1223752443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ max_throughput.1223752443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3948546817 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 6848277126 ps |
| CPU time | 86.57 seconds |
| Started | Oct 15 01:44:58 AM UTC 24 |
| Finished | Oct 15 01:46:27 AM UTC 24 |
| Peak memory | 221452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948546817 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.3948546817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.147571591 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 5368757403 ps |
| CPU time | 139.08 seconds |
| Started | Oct 15 01:44:52 AM UTC 24 |
| Finished | Oct 15 01:47:14 AM UTC 24 |
| Peak memory | 221492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147571591 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.147571591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.644415630 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2977641748 ps |
| CPU time | 268.26 seconds |
| Started | Oct 15 01:43:27 AM UTC 24 |
| Finished | Oct 15 01:47:59 AM UTC 24 |
| Peak memory | 386116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644415630 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.644415630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3020229054 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2832351528 ps |
| CPU time | 29.7 seconds |
| Started | Oct 15 01:43:43 AM UTC 24 |
| Finished | Oct 15 01:44:14 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020229054 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.3020229054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1412897591 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 19795754019 ps |
| CPU time | 423.59 seconds |
| Started | Oct 15 01:43:46 AM UTC 24 |
| Finished | Oct 15 01:50:54 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412897591 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_a ccess_b2b.1412897591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.823277802 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 346340476 ps |
| CPU time | 4.47 seconds |
| Started | Oct 15 01:44:52 AM UTC 24 |
| Finished | Oct 15 01:44:58 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823277802 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.823277802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_readback_err.1865412529 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2773160081 ps |
| CPU time | 12.89 seconds |
| Started | Oct 15 01:45:00 AM UTC 24 |
| Finished | Oct 15 01:45:14 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865412529 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_readback_err.1865412529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2661560104 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 13391790289 ps |
| CPU time | 927.26 seconds |
| Started | Oct 15 01:44:50 AM UTC 24 |
| Finished | Oct 15 02:00:27 AM UTC 24 |
| Peak memory | 385984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661560104 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2661560104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.1883884108 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 690779456 ps |
| CPU time | 17.17 seconds |
| Started | Oct 15 01:43:26 AM UTC 24 |
| Finished | Oct 15 01:43:44 AM UTC 24 |
| Peak memory | 238388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883884108 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1883884108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.2001442384 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 19655765654 ps |
| CPU time | 2525.94 seconds |
| Started | Oct 15 01:45:15 AM UTC 24 |
| Finished | Oct 15 02:27:48 AM UTC 24 |
| Peak memory | 390012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20014423 84 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_a ll.2001442384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1971564255 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 370454568 ps |
| CPU time | 14 seconds |
| Started | Oct 15 01:45:02 AM UTC 24 |
| Finished | Oct 15 01:45:17 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971564255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1971564255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3708592999 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 10023313008 ps |
| CPU time | 379.5 seconds |
| Started | Oct 15 01:43:42 AM UTC 24 |
| Finished | Oct 15 01:50:07 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708592999 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.3708592999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2274904313 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 769150681 ps |
| CPU time | 27.53 seconds |
| Started | Oct 15 01:44:02 AM UTC 24 |
| Finished | Oct 15 01:44:31 AM UTC 24 |
| Peak memory | 310076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2274904313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl _throughput_w_partial_write.2274904313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2665418999 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 16277913174 ps |
| CPU time | 365.6 seconds |
| Started | Oct 15 01:45:57 AM UTC 24 |
| Finished | Oct 15 01:52:08 AM UTC 24 |
| Peak memory | 379780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665418999 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_duri ng_key_req.2665418999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.609704032 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 61595845 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 01:47:27 AM UTC 24 |
| Finished | Oct 15 01:47:29 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609704032 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.609704032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.1644047142 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 843771666202 ps |
| CPU time | 2267.45 seconds |
| Started | Oct 15 01:45:21 AM UTC 24 |
| Finished | Oct 15 02:23:33 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644047142 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.1644047142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.823637345 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 5033367694 ps |
| CPU time | 189.04 seconds |
| Started | Oct 15 01:46:00 AM UTC 24 |
| Finished | Oct 15 01:49:12 AM UTC 24 |
| Peak memory | 353344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823637345 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.823637345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1346614371 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 69654848184 ps |
| CPU time | 99 seconds |
| Started | Oct 15 01:45:48 AM UTC 24 |
| Finished | Oct 15 01:47:29 AM UTC 24 |
| Peak memory | 221424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346614371 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.1346614371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3371412885 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 696380396 ps |
| CPU time | 16.54 seconds |
| Started | Oct 15 01:45:42 AM UTC 24 |
| Finished | Oct 15 01:45:59 AM UTC 24 |
| Peak memory | 250748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3371412885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ max_throughput.3371412885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1089243077 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 6566178365 ps |
| CPU time | 175.41 seconds |
| Started | Oct 15 01:46:36 AM UTC 24 |
| Finished | Oct 15 01:49:35 AM UTC 24 |
| Peak memory | 221548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089243077 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.1089243077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.3933454055 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 7222675514 ps |
| CPU time | 237.74 seconds |
| Started | Oct 15 01:46:31 AM UTC 24 |
| Finished | Oct 15 01:50:33 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933454055 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.3933454055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.4206296315 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 73072433964 ps |
| CPU time | 912.89 seconds |
| Started | Oct 15 01:45:21 AM UTC 24 |
| Finished | Oct 15 02:00:44 AM UTC 24 |
| Peak memory | 388032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206296315 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.4206296315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1464551280 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 496342017 ps |
| CPU time | 9.23 seconds |
| Started | Oct 15 01:45:35 AM UTC 24 |
| Finished | Oct 15 01:45:46 AM UTC 24 |
| Peak memory | 236604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464551280 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.1464551280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3793901933 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 89048221032 ps |
| CPU time | 376.3 seconds |
| Started | Oct 15 01:45:39 AM UTC 24 |
| Finished | Oct 15 01:52:01 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793901933 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_a ccess_b2b.3793901933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.381753457 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1471222170 ps |
| CPU time | 6.61 seconds |
| Started | Oct 15 01:46:28 AM UTC 24 |
| Finished | Oct 15 01:46:36 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381753457 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.381753457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_readback_err.2428686219 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 674859818 ps |
| CPU time | 10.53 seconds |
| Started | Oct 15 01:47:04 AM UTC 24 |
| Finished | Oct 15 01:47:15 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428686219 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_readback_err.2428686219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.4102342152 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 10142883275 ps |
| CPU time | 855.39 seconds |
| Started | Oct 15 01:46:09 AM UTC 24 |
| Finished | Oct 15 02:00:35 AM UTC 24 |
| Peak memory | 373620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102342152 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.4102342152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.3320181725 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1091565504 ps |
| CPU time | 19.65 seconds |
| Started | Oct 15 01:45:18 AM UTC 24 |
| Finished | Oct 15 01:45:39 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320181725 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3320181725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1909021740 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 233457936111 ps |
| CPU time | 2640.44 seconds |
| Started | Oct 15 01:47:16 AM UTC 24 |
| Finished | Oct 15 02:31:45 AM UTC 24 |
| Peak memory | 387964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19090217 40 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_a ll.1909021740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.748051633 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3718538134 ps |
| CPU time | 305.01 seconds |
| Started | Oct 15 01:45:31 AM UTC 24 |
| Finished | Oct 15 01:50:41 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748051633 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.748051633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1315046188 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1614067478 ps |
| CPU time | 100.84 seconds |
| Started | Oct 15 01:45:47 AM UTC 24 |
| Finished | Oct 15 01:47:30 AM UTC 24 |
| Peak memory | 381892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1315046188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _throughput_w_partial_write.1315046188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3884996504 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 14099665431 ps |
| CPU time | 36.98 seconds |
| Started | Oct 15 01:49:17 AM UTC 24 |
| Finished | Oct 15 01:49:56 AM UTC 24 |
| Peak memory | 248908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884996504 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_duri ng_key_req.3884996504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1113258321 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 21876240 ps |
| CPU time | 1 seconds |
| Started | Oct 15 01:50:04 AM UTC 24 |
| Finished | Oct 15 01:50:06 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113258321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1113258321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.781387229 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 248504810207 ps |
| CPU time | 2316.11 seconds |
| Started | Oct 15 01:47:31 AM UTC 24 |
| Finished | Oct 15 02:26:33 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781387229 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.781387229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.4067410315 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 5201869017 ps |
| CPU time | 88.53 seconds |
| Started | Oct 15 01:49:26 AM UTC 24 |
| Finished | Oct 15 01:50:57 AM UTC 24 |
| Peak memory | 281544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067410315 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.4067410315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.342522676 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 151797535482 ps |
| CPU time | 113.81 seconds |
| Started | Oct 15 01:49:13 AM UTC 24 |
| Finished | Oct 15 01:51:09 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342522676 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.342522676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1194638140 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 806939397 ps |
| CPU time | 70.28 seconds |
| Started | Oct 15 01:48:38 AM UTC 24 |
| Finished | Oct 15 01:49:50 AM UTC 24 |
| Peak memory | 342924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1194638140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ max_throughput.1194638140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.2560898786 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 9389652934 ps |
| CPU time | 97.34 seconds |
| Started | Oct 15 01:49:42 AM UTC 24 |
| Finished | Oct 15 01:51:21 AM UTC 24 |
| Peak memory | 221524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560898786 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.2560898786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2181756785 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 5255995737 ps |
| CPU time | 345.29 seconds |
| Started | Oct 15 01:49:36 AM UTC 24 |
| Finished | Oct 15 01:55:25 AM UTC 24 |
| Peak memory | 221356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181756785 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.2181756785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3191627211 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 4178367109 ps |
| CPU time | 530.21 seconds |
| Started | Oct 15 01:47:30 AM UTC 24 |
| Finished | Oct 15 01:56:27 AM UTC 24 |
| Peak memory | 388032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191627211 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.3191627211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1886591369 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1387653232 ps |
| CPU time | 35.25 seconds |
| Started | Oct 15 01:48:00 AM UTC 24 |
| Finished | Oct 15 01:48:37 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886591369 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.1886591369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.3299992641 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 58042546052 ps |
| CPU time | 326.79 seconds |
| Started | Oct 15 01:48:21 AM UTC 24 |
| Finished | Oct 15 01:53:52 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299992641 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_a ccess_b2b.3299992641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1573228281 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 691756616 ps |
| CPU time | 4.54 seconds |
| Started | Oct 15 01:49:35 AM UTC 24 |
| Finished | Oct 15 01:49:41 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573228281 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1573228281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_readback_err.1348860425 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3038334403 ps |
| CPU time | 11.54 seconds |
| Started | Oct 15 01:49:51 AM UTC 24 |
| Finished | Oct 15 01:50:03 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348860425 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_readback_err.1348860425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.482118970 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 5037451037 ps |
| CPU time | 286.54 seconds |
| Started | Oct 15 01:49:29 AM UTC 24 |
| Finished | Oct 15 01:54:20 AM UTC 24 |
| Peak memory | 379772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482118970 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.482118970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.1432968810 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 6702884694 ps |
| CPU time | 13.37 seconds |
| Started | Oct 15 01:47:30 AM UTC 24 |
| Finished | Oct 15 01:47:45 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432968810 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1432968810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.3098862785 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 70426880949 ps |
| CPU time | 2669.48 seconds |
| Started | Oct 15 01:50:01 AM UTC 24 |
| Finished | Oct 15 02:34:59 AM UTC 24 |
| Peak memory | 385992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30988627 85 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_a ll.3098862785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.4013028144 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 12011300094 ps |
| CPU time | 267.89 seconds |
| Started | Oct 15 01:47:45 AM UTC 24 |
| Finished | Oct 15 01:52:17 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013028144 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.4013028144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2784834225 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2996445763 ps |
| CPU time | 33.12 seconds |
| Started | Oct 15 01:48:42 AM UTC 24 |
| Finished | Oct 15 01:49:16 AM UTC 24 |
| Peak memory | 287684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2784834225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl _throughput_w_partial_write.2784834225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2898322291 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 86658551590 ps |
| CPU time | 1391.32 seconds |
| Started | Oct 15 01:50:57 AM UTC 24 |
| Finished | Oct 15 02:14:24 AM UTC 24 |
| Peak memory | 383876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898322291 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_duri ng_key_req.2898322291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.558340144 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 14245364 ps |
| CPU time | 0.87 seconds |
| Started | Oct 15 01:52:01 AM UTC 24 |
| Finished | Oct 15 01:52:03 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558340144 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.558340144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.2991485427 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 243470338213 ps |
| CPU time | 3156.86 seconds |
| Started | Oct 15 01:50:28 AM UTC 24 |
| Finished | Oct 15 02:43:41 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991485427 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.2991485427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.2770889226 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 8700359918 ps |
| CPU time | 305.8 seconds |
| Started | Oct 15 01:51:09 AM UTC 24 |
| Finished | Oct 15 01:56:19 AM UTC 24 |
| Peak memory | 379848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770889226 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.2770889226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1593196574 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 10611501513 ps |
| CPU time | 108.26 seconds |
| Started | Oct 15 01:50:57 AM UTC 24 |
| Finished | Oct 15 01:52:48 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593196574 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.1593196574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1044467758 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 4604647368 ps |
| CPU time | 20.97 seconds |
| Started | Oct 15 01:50:53 AM UTC 24 |
| Finished | Oct 15 01:51:15 AM UTC 24 |
| Peak memory | 248960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1044467758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ max_throughput.1044467758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.680698490 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 5251305956 ps |
| CPU time | 206.86 seconds |
| Started | Oct 15 01:51:28 AM UTC 24 |
| Finished | Oct 15 01:54:58 AM UTC 24 |
| Peak memory | 221584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680698490 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.680698490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2235914918 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 28861544656 ps |
| CPU time | 159.32 seconds |
| Started | Oct 15 01:51:27 AM UTC 24 |
| Finished | Oct 15 01:54:09 AM UTC 24 |
| Peak memory | 221436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235914918 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2235914918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2271735219 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 42572427338 ps |
| CPU time | 1054.28 seconds |
| Started | Oct 15 01:50:08 AM UTC 24 |
| Finished | Oct 15 02:07:54 AM UTC 24 |
| Peak memory | 387956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271735219 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.2271735219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2012112070 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 823384539 ps |
| CPU time | 13.44 seconds |
| Started | Oct 15 01:50:42 AM UTC 24 |
| Finished | Oct 15 01:50:57 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012112070 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.2012112070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.1702939807 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 5766659794 ps |
| CPU time | 306.39 seconds |
| Started | Oct 15 01:50:44 AM UTC 24 |
| Finished | Oct 15 01:55:54 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702939807 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_a ccess_b2b.1702939807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2911415821 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 374823894 ps |
| CPU time | 4.79 seconds |
| Started | Oct 15 01:51:22 AM UTC 24 |
| Finished | Oct 15 01:51:27 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911415821 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2911415821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_readback_err.2798579884 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2636693084 ps |
| CPU time | 9.21 seconds |
| Started | Oct 15 01:51:37 AM UTC 24 |
| Finished | Oct 15 01:51:47 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798579884 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_readback_err.2798579884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.293572399 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 9582619620 ps |
| CPU time | 884.98 seconds |
| Started | Oct 15 01:51:17 AM UTC 24 |
| Finished | Oct 15 02:06:11 AM UTC 24 |
| Peak memory | 388028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293572399 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.293572399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1757916143 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1183642281 ps |
| CPU time | 18.75 seconds |
| Started | Oct 15 01:50:07 AM UTC 24 |
| Finished | Oct 15 01:50:27 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757916143 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1757916143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.61118679 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 420520832767 ps |
| CPU time | 3974.55 seconds |
| Started | Oct 15 01:51:52 AM UTC 24 |
| Finished | Oct 15 02:58:50 AM UTC 24 |
| Peak memory | 388100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61118679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.61118679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1737548086 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 315409566 ps |
| CPU time | 11.33 seconds |
| Started | Oct 15 01:51:48 AM UTC 24 |
| Finished | Oct 15 01:52:01 AM UTC 24 |
| Peak memory | 221684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737548086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1737548086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.526572660 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2460636557 ps |
| CPU time | 178.6 seconds |
| Started | Oct 15 01:50:34 AM UTC 24 |
| Finished | Oct 15 01:53:35 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526572660 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.526572660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.954830048 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 723577290 ps |
| CPU time | 29.37 seconds |
| Started | Oct 15 01:50:55 AM UTC 24 |
| Finished | Oct 15 01:51:26 AM UTC 24 |
| Peak memory | 287552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =954830048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ throughput_w_partial_write.954830048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.646955917 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 10218514905 ps |
| CPU time | 636.7 seconds |
| Started | Oct 15 01:52:55 AM UTC 24 |
| Finished | Oct 15 02:03:39 AM UTC 24 |
| Peak memory | 386116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646955917 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_durin g_key_req.646955917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2064191777 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 38009344 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 01:54:23 AM UTC 24 |
| Finished | Oct 15 01:54:25 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064191777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2064191777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.1429014075 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 23637538360 ps |
| CPU time | 1847.7 seconds |
| Started | Oct 15 01:52:09 AM UTC 24 |
| Finished | Oct 15 02:23:18 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429014075 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.1429014075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.428203420 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 6352495893 ps |
| CPU time | 785.01 seconds |
| Started | Oct 15 01:53:16 AM UTC 24 |
| Finished | Oct 15 02:06:30 AM UTC 24 |
| Peak memory | 385988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428203420 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.428203420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.276117306 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 14523379330 ps |
| CPU time | 134.11 seconds |
| Started | Oct 15 01:52:48 AM UTC 24 |
| Finished | Oct 15 01:55:05 AM UTC 24 |
| Peak memory | 221416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276117306 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.276117306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.1765911216 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 797985755 ps |
| CPU time | 106.97 seconds |
| Started | Oct 15 01:52:36 AM UTC 24 |
| Finished | Oct 15 01:54:25 AM UTC 24 |
| Peak memory | 379904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1765911216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ max_throughput.1765911216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1112796113 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 19619184719 ps |
| CPU time | 175.55 seconds |
| Started | Oct 15 01:54:09 AM UTC 24 |
| Finished | Oct 15 01:57:08 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112796113 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.1112796113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.3145739531 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 7360504312 ps |
| CPU time | 156.51 seconds |
| Started | Oct 15 01:54:00 AM UTC 24 |
| Finished | Oct 15 01:56:39 AM UTC 24 |
| Peak memory | 221464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145739531 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.3145739531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.811673861 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 40360188080 ps |
| CPU time | 949.08 seconds |
| Started | Oct 15 01:52:05 AM UTC 24 |
| Finished | Oct 15 02:08:03 AM UTC 24 |
| Peak memory | 388032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811673861 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.811673861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1404211299 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 7264399589 ps |
| CPU time | 35.6 seconds |
| Started | Oct 15 01:52:18 AM UTC 24 |
| Finished | Oct 15 01:52:55 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404211299 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.1404211299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1506117977 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 76702130669 ps |
| CPU time | 346.72 seconds |
| Started | Oct 15 01:52:33 AM UTC 24 |
| Finished | Oct 15 01:58:25 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506117977 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_a ccess_b2b.1506117977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2948136304 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1702934234 ps |
| CPU time | 4.88 seconds |
| Started | Oct 15 01:53:53 AM UTC 24 |
| Finished | Oct 15 01:53:59 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948136304 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2948136304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_readback_err.1482712112 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 692024296 ps |
| CPU time | 10.75 seconds |
| Started | Oct 15 01:54:10 AM UTC 24 |
| Finished | Oct 15 01:54:22 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482712112 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_readback_err.1482712112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.2115950834 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 16871964194 ps |
| CPU time | 524.64 seconds |
| Started | Oct 15 01:53:36 AM UTC 24 |
| Finished | Oct 15 02:02:27 AM UTC 24 |
| Peak memory | 379768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115950834 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2115950834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.897428481 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 842849274 ps |
| CPU time | 11.82 seconds |
| Started | Oct 15 01:52:02 AM UTC 24 |
| Finished | Oct 15 01:52:15 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897428481 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.897428481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2090956056 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 282798430537 ps |
| CPU time | 1385.27 seconds |
| Started | Oct 15 01:54:20 AM UTC 24 |
| Finished | Oct 15 02:17:41 AM UTC 24 |
| Peak memory | 388140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20909560 56 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_a ll.2090956056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2765172114 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1992257041 ps |
| CPU time | 20.59 seconds |
| Started | Oct 15 01:54:15 AM UTC 24 |
| Finished | Oct 15 01:54:37 AM UTC 24 |
| Peak memory | 221480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765172114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2765172114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1655835958 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 12087561246 ps |
| CPU time | 143.75 seconds |
| Started | Oct 15 01:52:17 AM UTC 24 |
| Finished | Oct 15 01:54:43 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655835958 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.1655835958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3972362575 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 735819067 ps |
| CPU time | 34.39 seconds |
| Started | Oct 15 01:52:39 AM UTC 24 |
| Finished | Oct 15 01:53:15 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3972362575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl _throughput_w_partial_write.3972362575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1911308199 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 34826364832 ps |
| CPU time | 749.03 seconds |
| Started | Oct 15 01:55:07 AM UTC 24 |
| Finished | Oct 15 02:07:45 AM UTC 24 |
| Peak memory | 377928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911308199 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_duri ng_key_req.1911308199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1184899943 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 16726828 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 01:56:11 AM UTC 24 |
| Finished | Oct 15 01:56:13 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184899943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1184899943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.3588925276 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 383308290794 ps |
| CPU time | 1962.12 seconds |
| Started | Oct 15 01:54:38 AM UTC 24 |
| Finished | Oct 15 02:27:42 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588925276 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.3588925276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.94893876 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 15387834235 ps |
| CPU time | 940.26 seconds |
| Started | Oct 15 01:55:10 AM UTC 24 |
| Finished | Oct 15 02:11:01 AM UTC 24 |
| Peak memory | 385980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94893876 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.94893876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3705141586 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 11208391201 ps |
| CPU time | 104.91 seconds |
| Started | Oct 15 01:55:06 AM UTC 24 |
| Finished | Oct 15 01:56:54 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705141586 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.3705141586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.166042026 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 962240552 ps |
| CPU time | 25.51 seconds |
| Started | Oct 15 01:54:58 AM UTC 24 |
| Finished | Oct 15 01:55:25 AM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 166042026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_m ax_throughput.166042026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3500940769 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 5787986062 ps |
| CPU time | 75.91 seconds |
| Started | Oct 15 01:55:37 AM UTC 24 |
| Finished | Oct 15 01:56:55 AM UTC 24 |
| Peak memory | 221396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500940769 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.3500940769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.199130457 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 13138662356 ps |
| CPU time | 280.09 seconds |
| Started | Oct 15 01:55:33 AM UTC 24 |
| Finished | Oct 15 02:00:17 AM UTC 24 |
| Peak memory | 221484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199130457 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.199130457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3518349952 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 23484983804 ps |
| CPU time | 797.14 seconds |
| Started | Oct 15 01:54:26 AM UTC 24 |
| Finished | Oct 15 02:07:52 AM UTC 24 |
| Peak memory | 388036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518349952 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.3518349952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.709620628 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1086725254 ps |
| CPU time | 20.75 seconds |
| Started | Oct 15 01:54:44 AM UTC 24 |
| Finished | Oct 15 01:55:06 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709620628 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.709620628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1618317289 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 13905482921 ps |
| CPU time | 459.31 seconds |
| Started | Oct 15 01:54:53 AM UTC 24 |
| Finished | Oct 15 02:02:38 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618317289 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_a ccess_b2b.1618317289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2209462854 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1294595881 ps |
| CPU time | 4.86 seconds |
| Started | Oct 15 01:55:26 AM UTC 24 |
| Finished | Oct 15 01:55:32 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209462854 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2209462854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_readback_err.2644916057 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2749873432 ps |
| CPU time | 12.29 seconds |
| Started | Oct 15 01:55:55 AM UTC 24 |
| Finished | Oct 15 01:56:09 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644916057 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_readback_err.2644916057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2713737544 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2969177208 ps |
| CPU time | 43.84 seconds |
| Started | Oct 15 01:55:26 AM UTC 24 |
| Finished | Oct 15 01:56:12 AM UTC 24 |
| Peak memory | 265280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713737544 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2713737544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.548320572 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4640859856 ps |
| CPU time | 14.99 seconds |
| Started | Oct 15 01:54:26 AM UTC 24 |
| Finished | Oct 15 01:54:42 AM UTC 24 |
| Peak memory | 220028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548320572 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.548320572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.2823582049 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 107234174608 ps |
| CPU time | 3052.09 seconds |
| Started | Oct 15 01:56:10 AM UTC 24 |
| Finished | Oct 15 02:47:34 AM UTC 24 |
| Peak memory | 385924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28235820 49 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_a ll.2823582049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3238025929 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3058410564 ps |
| CPU time | 33.36 seconds |
| Started | Oct 15 01:56:00 AM UTC 24 |
| Finished | Oct 15 01:56:34 AM UTC 24 |
| Peak memory | 221620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238025929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3238025929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.3328391725 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 44758697242 ps |
| CPU time | 305.16 seconds |
| Started | Oct 15 01:54:43 AM UTC 24 |
| Finished | Oct 15 01:59:53 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328391725 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.3328391725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.4035026753 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 964773589 ps |
| CPU time | 54.63 seconds |
| Started | Oct 15 01:55:03 AM UTC 24 |
| Finished | Oct 15 01:55:59 AM UTC 24 |
| Peak memory | 361348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4035026753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl _throughput_w_partial_write.4035026753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3855477632 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4680450868 ps |
| CPU time | 68.02 seconds |
| Started | Oct 15 01:56:55 AM UTC 24 |
| Finished | Oct 15 01:58:05 AM UTC 24 |
| Peak memory | 314316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855477632 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_duri ng_key_req.3855477632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2364636966 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 40946265 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 01:58:04 AM UTC 24 |
| Finished | Oct 15 01:58:06 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364636966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2364636966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.1635136725 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 29190168246 ps |
| CPU time | 2117.79 seconds |
| Started | Oct 15 01:56:17 AM UTC 24 |
| Finished | Oct 15 02:31:59 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635136725 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.1635136725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.1450228606 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 7110503078 ps |
| CPU time | 223.61 seconds |
| Started | Oct 15 01:56:56 AM UTC 24 |
| Finished | Oct 15 02:00:43 AM UTC 24 |
| Peak memory | 347016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450228606 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.1450228606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3788509489 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 16737138347 ps |
| CPU time | 71.85 seconds |
| Started | Oct 15 01:56:50 AM UTC 24 |
| Finished | Oct 15 01:58:03 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788509489 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.3788509489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.990925799 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1936984091 ps |
| CPU time | 82.11 seconds |
| Started | Oct 15 01:56:40 AM UTC 24 |
| Finished | Oct 15 01:58:04 AM UTC 24 |
| Peak memory | 361348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 990925799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_m ax_throughput.990925799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2653646085 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 27892362981 ps |
| CPU time | 221.08 seconds |
| Started | Oct 15 01:57:25 AM UTC 24 |
| Finished | Oct 15 02:01:10 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653646085 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.2653646085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3624518328 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 27646603454 ps |
| CPU time | 346.04 seconds |
| Started | Oct 15 01:57:15 AM UTC 24 |
| Finished | Oct 15 02:03:06 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624518328 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.3624518328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.763074887 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 104296850441 ps |
| CPU time | 1804.94 seconds |
| Started | Oct 15 01:56:14 AM UTC 24 |
| Finished | Oct 15 02:26:37 AM UTC 24 |
| Peak memory | 390148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763074887 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.763074887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3417683206 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1723694775 ps |
| CPU time | 71.88 seconds |
| Started | Oct 15 01:56:27 AM UTC 24 |
| Finished | Oct 15 01:57:41 AM UTC 24 |
| Peak memory | 369468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417683206 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.3417683206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.841995018 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 46940671166 ps |
| CPU time | 313.69 seconds |
| Started | Oct 15 01:56:35 AM UTC 24 |
| Finished | Oct 15 02:01:54 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841995018 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_ac cess_b2b.841995018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.932319393 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1402224863 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 01:57:08 AM UTC 24 |
| Finished | Oct 15 01:57:14 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932319393 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.932319393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_readback_err.654582752 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 678588697 ps |
| CPU time | 6.07 seconds |
| Started | Oct 15 01:57:42 AM UTC 24 |
| Finished | Oct 15 01:57:49 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654582752 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_readback_err.654582752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.316085192 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 9184719773 ps |
| CPU time | 466.88 seconds |
| Started | Oct 15 01:57:01 AM UTC 24 |
| Finished | Oct 15 02:04:53 AM UTC 24 |
| Peak memory | 386108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316085192 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.316085192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.1897367409 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 426054475 ps |
| CPU time | 35.48 seconds |
| Started | Oct 15 01:56:12 AM UTC 24 |
| Finished | Oct 15 01:56:49 AM UTC 24 |
| Peak memory | 308024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897367409 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1897367409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2627075301 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 151551627285 ps |
| CPU time | 4180.49 seconds |
| Started | Oct 15 01:57:53 AM UTC 24 |
| Finished | Oct 15 03:08:14 AM UTC 24 |
| Peak memory | 402504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26270753 01 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_a ll.2627075301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1359216767 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1056851662 ps |
| CPU time | 24.99 seconds |
| Started | Oct 15 01:57:50 AM UTC 24 |
| Finished | Oct 15 01:58:16 AM UTC 24 |
| Peak memory | 221624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359216767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1359216767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.779850752 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 6205471362 ps |
| CPU time | 367.53 seconds |
| Started | Oct 15 01:56:20 AM UTC 24 |
| Finished | Oct 15 02:02:33 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779850752 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.779850752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3679787106 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1465667630 ps |
| CPU time | 17.68 seconds |
| Started | Oct 15 01:56:41 AM UTC 24 |
| Finished | Oct 15 01:57:00 AM UTC 24 |
| Peak memory | 261000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3679787106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl _throughput_w_partial_write.3679787106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3930100419 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2554035101 ps |
| CPU time | 111.2 seconds |
| Started | Oct 15 01:59:53 AM UTC 24 |
| Finished | Oct 15 02:01:47 AM UTC 24 |
| Peak memory | 340936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930100419 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_duri ng_key_req.3930100419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3345867043 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 35381724 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 02:00:42 AM UTC 24 |
| Finished | Oct 15 02:00:44 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345867043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3345867043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.1076792771 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 95786594916 ps |
| CPU time | 1707.64 seconds |
| Started | Oct 15 01:58:07 AM UTC 24 |
| Finished | Oct 15 02:26:53 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076792771 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.1076792771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.3971209703 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 21939865732 ps |
| CPU time | 523.84 seconds |
| Started | Oct 15 01:59:53 AM UTC 24 |
| Finished | Oct 15 02:08:43 AM UTC 24 |
| Peak memory | 385996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971209703 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.3971209703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2423296879 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 7016265613 ps |
| CPU time | 49.57 seconds |
| Started | Oct 15 01:59:36 AM UTC 24 |
| Finished | Oct 15 02:00:28 AM UTC 24 |
| Peak memory | 221404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423296879 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.2423296879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1691611883 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1483633629 ps |
| CPU time | 51.09 seconds |
| Started | Oct 15 01:59:00 AM UTC 24 |
| Finished | Oct 15 01:59:52 AM UTC 24 |
| Peak memory | 312204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1691611883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ max_throughput.1691611883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3506819361 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 5823805645 ps |
| CPU time | 70.83 seconds |
| Started | Oct 15 02:00:28 AM UTC 24 |
| Finished | Oct 15 02:01:40 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506819361 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.3506819361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1741992081 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 57684337632 ps |
| CPU time | 203.77 seconds |
| Started | Oct 15 02:00:27 AM UTC 24 |
| Finished | Oct 15 02:03:54 AM UTC 24 |
| Peak memory | 221592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741992081 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.1741992081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1904060180 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 41886995128 ps |
| CPU time | 1249.68 seconds |
| Started | Oct 15 01:58:06 AM UTC 24 |
| Finished | Oct 15 02:19:09 AM UTC 24 |
| Peak memory | 387964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904060180 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.1904060180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2288905539 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1728806013 ps |
| CPU time | 36.39 seconds |
| Started | Oct 15 01:58:21 AM UTC 24 |
| Finished | Oct 15 01:58:59 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288905539 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.2288905539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.150854762 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 15630447400 ps |
| CPU time | 454.24 seconds |
| Started | Oct 15 01:58:26 AM UTC 24 |
| Finished | Oct 15 02:06:06 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150854762 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_ac cess_b2b.150854762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2395552581 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 706704523 ps |
| CPU time | 6.17 seconds |
| Started | Oct 15 02:00:19 AM UTC 24 |
| Finished | Oct 15 02:00:26 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395552581 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2395552581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_readback_err.21677233 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2632010924 ps |
| CPU time | 11.16 seconds |
| Started | Oct 15 02:00:29 AM UTC 24 |
| Finished | Oct 15 02:00:41 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21677233 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_readback_err.21677233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.2568030325 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 17801956254 ps |
| CPU time | 406.45 seconds |
| Started | Oct 15 02:00:12 AM UTC 24 |
| Finished | Oct 15 02:07:03 AM UTC 24 |
| Peak memory | 363584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568030325 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2568030325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2347106750 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2945424304 ps |
| CPU time | 12.82 seconds |
| Started | Oct 15 01:58:05 AM UTC 24 |
| Finished | Oct 15 01:58:19 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347106750 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2347106750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.529731155 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 893683847306 ps |
| CPU time | 4488.1 seconds |
| Started | Oct 15 02:00:35 AM UTC 24 |
| Finished | Oct 15 03:16:12 AM UTC 24 |
| Peak memory | 389436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52973115 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.529731155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1985634157 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 5270416014 ps |
| CPU time | 67.26 seconds |
| Started | Oct 15 02:00:31 AM UTC 24 |
| Finished | Oct 15 02:01:40 AM UTC 24 |
| Peak memory | 287740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985634157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.1985634157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2378309577 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 15526206472 ps |
| CPU time | 306.54 seconds |
| Started | Oct 15 01:58:16 AM UTC 24 |
| Finished | Oct 15 02:03:27 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378309577 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2378309577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3820542190 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 6939400346 ps |
| CPU time | 77.29 seconds |
| Started | Oct 15 01:59:11 AM UTC 24 |
| Finished | Oct 15 02:00:30 AM UTC 24 |
| Peak memory | 351172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3820542190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl _throughput_w_partial_write.3820542190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.813767574 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 75868839279 ps |
| CPU time | 853.21 seconds |
| Started | Oct 15 02:01:48 AM UTC 24 |
| Finished | Oct 15 02:16:11 AM UTC 24 |
| Peak memory | 379964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813767574 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_durin g_key_req.813767574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1746606553 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 12908405 ps |
| CPU time | 0.93 seconds |
| Started | Oct 15 02:02:42 AM UTC 24 |
| Finished | Oct 15 02:02:44 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746606553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1746606553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.1262989627 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 116140811140 ps |
| CPU time | 1983.37 seconds |
| Started | Oct 15 02:00:46 AM UTC 24 |
| Finished | Oct 15 02:34:11 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262989627 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.1262989627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.883543271 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 11044308319 ps |
| CPU time | 226.89 seconds |
| Started | Oct 15 02:01:54 AM UTC 24 |
| Finished | Oct 15 02:05:43 AM UTC 24 |
| Peak memory | 381892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883543271 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.883543271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3763083029 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 14990874979 ps |
| CPU time | 112.42 seconds |
| Started | Oct 15 02:01:47 AM UTC 24 |
| Finished | Oct 15 02:03:42 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763083029 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.3763083029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3864135162 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1310536044 ps |
| CPU time | 11.99 seconds |
| Started | Oct 15 02:01:41 AM UTC 24 |
| Finished | Oct 15 02:01:54 AM UTC 24 |
| Peak memory | 221516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3864135162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ max_throughput.3864135162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3831436294 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3982236228 ps |
| CPU time | 80.41 seconds |
| Started | Oct 15 02:02:28 AM UTC 24 |
| Finished | Oct 15 02:03:50 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831436294 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.3831436294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.401768264 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 16420091005 ps |
| CPU time | 286.46 seconds |
| Started | Oct 15 02:02:03 AM UTC 24 |
| Finished | Oct 15 02:06:53 AM UTC 24 |
| Peak memory | 221432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401768264 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.401768264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2088252457 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 54711125033 ps |
| CPU time | 363.85 seconds |
| Started | Oct 15 02:00:45 AM UTC 24 |
| Finished | Oct 15 02:06:54 AM UTC 24 |
| Peak memory | 381892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088252457 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.2088252457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.4048074227 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2784291115 ps |
| CPU time | 10.04 seconds |
| Started | Oct 15 02:01:11 AM UTC 24 |
| Finished | Oct 15 02:01:22 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048074227 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.4048074227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1188476549 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 9072328261 ps |
| CPU time | 289.61 seconds |
| Started | Oct 15 02:01:23 AM UTC 24 |
| Finished | Oct 15 02:06:17 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188476549 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_a ccess_b2b.1188476549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2339093033 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1407522642 ps |
| CPU time | 5.94 seconds |
| Started | Oct 15 02:01:55 AM UTC 24 |
| Finished | Oct 15 02:02:02 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339093033 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2339093033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_readback_err.180389995 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 698742275 ps |
| CPU time | 8.29 seconds |
| Started | Oct 15 02:02:32 AM UTC 24 |
| Finished | Oct 15 02:02:41 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180389995 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_readback_err.180389995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.1537928566 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 20894601939 ps |
| CPU time | 679.56 seconds |
| Started | Oct 15 02:01:55 AM UTC 24 |
| Finished | Oct 15 02:13:22 AM UTC 24 |
| Peak memory | 369604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537928566 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1537928566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.165911914 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 3815362038 ps |
| CPU time | 61.5 seconds |
| Started | Oct 15 02:00:44 AM UTC 24 |
| Finished | Oct 15 02:01:47 AM UTC 24 |
| Peak memory | 359364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165911914 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.165911914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3211649381 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 1298369512320 ps |
| CPU time | 6826.37 seconds |
| Started | Oct 15 02:02:39 AM UTC 24 |
| Finished | Oct 15 03:57:32 AM UTC 24 |
| Peak memory | 399672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32116493 81 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_a ll.3211649381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2151725778 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3370215135 ps |
| CPU time | 114.88 seconds |
| Started | Oct 15 02:02:33 AM UTC 24 |
| Finished | Oct 15 02:04:30 AM UTC 24 |
| Peak memory | 365564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151725778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2151725778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.35439987 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3618346115 ps |
| CPU time | 272.18 seconds |
| Started | Oct 15 02:00:47 AM UTC 24 |
| Finished | Oct 15 02:05:23 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35439987 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.35439987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1809497445 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 679827152 ps |
| CPU time | 10.32 seconds |
| Started | Oct 15 02:01:41 AM UTC 24 |
| Finished | Oct 15 02:01:53 AM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1809497445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl _throughput_w_partial_write.1809497445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.4212241903 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3320892054 ps |
| CPU time | 171.28 seconds |
| Started | Oct 15 02:04:00 AM UTC 24 |
| Finished | Oct 15 02:06:54 AM UTC 24 |
| Peak memory | 367692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212241903 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_duri ng_key_req.4212241903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.3154675833 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 45465436 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 02:05:45 AM UTC 24 |
| Finished | Oct 15 02:05:47 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154675833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.3154675833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.499487642 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 17470633720 ps |
| CPU time | 1196.99 seconds |
| Started | Oct 15 02:03:14 AM UTC 24 |
| Finished | Oct 15 02:23:25 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499487642 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.499487642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.2779927330 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 16433488786 ps |
| CPU time | 1187.23 seconds |
| Started | Oct 15 02:04:14 AM UTC 24 |
| Finished | Oct 15 02:24:14 AM UTC 24 |
| Peak memory | 388040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779927330 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.2779927330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.771415841 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 19529350362 ps |
| CPU time | 107.44 seconds |
| Started | Oct 15 02:03:54 AM UTC 24 |
| Finished | Oct 15 02:05:44 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771415841 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.771415841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.550296756 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 3252038764 ps |
| CPU time | 74.34 seconds |
| Started | Oct 15 02:03:51 AM UTC 24 |
| Finished | Oct 15 02:05:07 AM UTC 24 |
| Peak memory | 357320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 550296756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_m ax_throughput.550296756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.3947184298 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 6383180145 ps |
| CPU time | 105.01 seconds |
| Started | Oct 15 02:05:08 AM UTC 24 |
| Finished | Oct 15 02:06:55 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947184298 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.3947184298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2272644442 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 3950149679 ps |
| CPU time | 253.68 seconds |
| Started | Oct 15 02:05:00 AM UTC 24 |
| Finished | Oct 15 02:09:17 AM UTC 24 |
| Peak memory | 221392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272644442 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.2272644442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.129941801 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1080432896 ps |
| CPU time | 50.57 seconds |
| Started | Oct 15 02:03:07 AM UTC 24 |
| Finished | Oct 15 02:03:59 AM UTC 24 |
| Peak memory | 300016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129941801 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.129941801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.4222594971 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 692852373 ps |
| CPU time | 9.75 seconds |
| Started | Oct 15 02:03:40 AM UTC 24 |
| Finished | Oct 15 02:03:51 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222594971 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.4222594971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1886501491 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 11071626470 ps |
| CPU time | 423.61 seconds |
| Started | Oct 15 02:03:42 AM UTC 24 |
| Finished | Oct 15 02:10:51 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886501491 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_a ccess_b2b.1886501491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1104191130 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 425982897 ps |
| CPU time | 4.47 seconds |
| Started | Oct 15 02:04:54 AM UTC 24 |
| Finished | Oct 15 02:05:00 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104191130 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1104191130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_readback_err.685025824 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1507681972 ps |
| CPU time | 8.33 seconds |
| Started | Oct 15 02:05:23 AM UTC 24 |
| Finished | Oct 15 02:05:33 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685025824 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_readback_err.685025824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1571166252 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 11167280338 ps |
| CPU time | 331.24 seconds |
| Started | Oct 15 02:04:31 AM UTC 24 |
| Finished | Oct 15 02:10:07 AM UTC 24 |
| Peak memory | 373704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571166252 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1571166252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.3517593788 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 756442433 ps |
| CPU time | 26 seconds |
| Started | Oct 15 02:02:46 AM UTC 24 |
| Finished | Oct 15 02:03:13 AM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517593788 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3517593788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1538109294 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 75045490530 ps |
| CPU time | 2726.02 seconds |
| Started | Oct 15 02:05:45 AM UTC 24 |
| Finished | Oct 15 02:51:39 AM UTC 24 |
| Peak memory | 388164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15381092 94 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_a ll.1538109294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.718066614 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 48558481248 ps |
| CPU time | 145.07 seconds |
| Started | Oct 15 02:05:34 AM UTC 24 |
| Finished | Oct 15 02:08:01 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718066614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.718066614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2644114117 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 28006236583 ps |
| CPU time | 248.24 seconds |
| Started | Oct 15 02:03:28 AM UTC 24 |
| Finished | Oct 15 02:07:40 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644114117 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.2644114117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.323997664 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 711092847 ps |
| CPU time | 19.95 seconds |
| Started | Oct 15 02:03:51 AM UTC 24 |
| Finished | Oct 15 02:04:12 AM UTC 24 |
| Peak memory | 260932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =323997664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ throughput_w_partial_write.323997664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2349532231 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 33094401108 ps |
| CPU time | 691.42 seconds |
| Started | Oct 15 01:12:10 AM UTC 24 |
| Finished | Oct 15 01:24:07 AM UTC 24 |
| Peak memory | 386112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349532231 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_durin g_key_req.2349532231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.4095404976 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 13692091 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 01:12:23 AM UTC 24 |
| Finished | Oct 15 01:12:28 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095404976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.4095404976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.3032335977 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 37797762615 ps |
| CPU time | 955.8 seconds |
| Started | Oct 15 01:12:06 AM UTC 24 |
| Finished | Oct 15 01:28:32 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032335977 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.3032335977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1107090965 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 10955440759 ps |
| CPU time | 565.55 seconds |
| Started | Oct 15 01:12:10 AM UTC 24 |
| Finished | Oct 15 01:21:59 AM UTC 24 |
| Peak memory | 386112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107090965 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.1107090965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2591995014 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 28842329854 ps |
| CPU time | 77.8 seconds |
| Started | Oct 15 01:12:09 AM UTC 24 |
| Finished | Oct 15 01:13:47 AM UTC 24 |
| Peak memory | 221432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591995014 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.2591995014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3461706076 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 5771055866 ps |
| CPU time | 15.58 seconds |
| Started | Oct 15 01:12:09 AM UTC 24 |
| Finished | Oct 15 01:12:44 AM UTC 24 |
| Peak memory | 260980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3461706076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m ax_throughput.3461706076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3890087305 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 19964413070 ps |
| CPU time | 175.69 seconds |
| Started | Oct 15 01:12:15 AM UTC 24 |
| Finished | Oct 15 01:15:23 AM UTC 24 |
| Peak memory | 221460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890087305 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.3890087305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.4204396208 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 23888827193 ps |
| CPU time | 209.19 seconds |
| Started | Oct 15 01:12:14 AM UTC 24 |
| Finished | Oct 15 01:15:57 AM UTC 24 |
| Peak memory | 221492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204396208 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.4204396208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2379963486 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 110217423413 ps |
| CPU time | 1363.07 seconds |
| Started | Oct 15 01:12:05 AM UTC 24 |
| Finished | Oct 15 01:35:23 AM UTC 24 |
| Peak memory | 377856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379963486 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.2379963486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1580932766 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1367397902 ps |
| CPU time | 68.22 seconds |
| Started | Oct 15 01:12:08 AM UTC 24 |
| Finished | Oct 15 01:13:35 AM UTC 24 |
| Peak memory | 367464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580932766 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.1580932766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.740010748 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 11566528737 ps |
| CPU time | 288.04 seconds |
| Started | Oct 15 01:12:09 AM UTC 24 |
| Finished | Oct 15 01:17:19 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740010748 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acc ess_b2b.740010748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2994045029 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 361873049 ps |
| CPU time | 3.55 seconds |
| Started | Oct 15 01:12:12 AM UTC 24 |
| Finished | Oct 15 01:12:24 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994045029 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2994045029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_readback_err.937273316 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3471018999 ps |
| CPU time | 7.33 seconds |
| Started | Oct 15 01:12:16 AM UTC 24 |
| Finished | Oct 15 01:12:34 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937273316 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_readback_err.937273316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.4069153104 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 54250913742 ps |
| CPU time | 374.12 seconds |
| Started | Oct 15 01:12:10 AM UTC 24 |
| Finished | Oct 15 01:18:46 AM UTC 24 |
| Peak memory | 361408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069153104 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.4069153104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2312658289 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 262428893 ps |
| CPU time | 2.01 seconds |
| Started | Oct 15 01:12:22 AM UTC 24 |
| Finished | Oct 15 01:12:28 AM UTC 24 |
| Peak memory | 246572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312658289 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.2312658289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2186526464 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 703296039 ps |
| CPU time | 33.78 seconds |
| Started | Oct 15 01:12:04 AM UTC 24 |
| Finished | Oct 15 01:13:01 AM UTC 24 |
| Peak memory | 300032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186526464 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2186526464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.428502400 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 496418021 ps |
| CPU time | 23.78 seconds |
| Started | Oct 15 01:12:20 AM UTC 24 |
| Finished | Oct 15 01:12:52 AM UTC 24 |
| Peak memory | 221548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428502400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.428502400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.4256490220 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 10549810719 ps |
| CPU time | 425.89 seconds |
| Started | Oct 15 01:12:07 AM UTC 24 |
| Finished | Oct 15 01:19:38 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256490220 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.4256490220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.32239713 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4596569155 ps |
| CPU time | 83.81 seconds |
| Started | Oct 15 01:12:09 AM UTC 24 |
| Finished | Oct 15 01:13:53 AM UTC 24 |
| Peak memory | 381888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =32239713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_th roughput_w_partial_write.32239713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2245717596 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 40507745727 ps |
| CPU time | 723.68 seconds |
| Started | Oct 15 02:06:55 AM UTC 24 |
| Finished | Oct 15 02:19:07 AM UTC 24 |
| Peak memory | 385924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245717596 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_duri ng_key_req.2245717596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.626234626 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 100877323 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 02:07:46 AM UTC 24 |
| Finished | Oct 15 02:07:48 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626234626 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.626234626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.2941925546 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 112682608712 ps |
| CPU time | 2015.73 seconds |
| Started | Oct 15 02:06:12 AM UTC 24 |
| Finished | Oct 15 02:40:10 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941925546 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.2941925546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.904478893 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 106624153334 ps |
| CPU time | 561.25 seconds |
| Started | Oct 15 02:06:55 AM UTC 24 |
| Finished | Oct 15 02:16:23 AM UTC 24 |
| Peak memory | 357320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904478893 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.904478893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2726113248 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 28392524588 ps |
| CPU time | 83.38 seconds |
| Started | Oct 15 02:06:54 AM UTC 24 |
| Finished | Oct 15 02:08:19 AM UTC 24 |
| Peak memory | 221392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726113248 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.2726113248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2823520548 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 736820640 ps |
| CPU time | 25.77 seconds |
| Started | Oct 15 02:06:32 AM UTC 24 |
| Finished | Oct 15 02:06:59 AM UTC 24 |
| Peak memory | 283660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2823520548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ max_throughput.2823520548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.789498249 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 21856729793 ps |
| CPU time | 208 seconds |
| Started | Oct 15 02:07:04 AM UTC 24 |
| Finished | Oct 15 02:10:36 AM UTC 24 |
| Peak memory | 221388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789498249 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.789498249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3270654416 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 3947436420 ps |
| CPU time | 314 seconds |
| Started | Oct 15 02:07:01 AM UTC 24 |
| Finished | Oct 15 02:12:20 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270654416 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.3270654416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2939748398 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 24478048716 ps |
| CPU time | 1157.64 seconds |
| Started | Oct 15 02:06:07 AM UTC 24 |
| Finished | Oct 15 02:25:37 AM UTC 24 |
| Peak memory | 388036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939748398 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.2939748398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.197010183 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 3609296588 ps |
| CPU time | 21.88 seconds |
| Started | Oct 15 02:06:20 AM UTC 24 |
| Finished | Oct 15 02:06:44 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197010183 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.197010183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.3468221217 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 17153198235 ps |
| CPU time | 248.48 seconds |
| Started | Oct 15 02:06:30 AM UTC 24 |
| Finished | Oct 15 02:10:43 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468221217 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_a ccess_b2b.3468221217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2326670659 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 351950123 ps |
| CPU time | 4.6 seconds |
| Started | Oct 15 02:06:59 AM UTC 24 |
| Finished | Oct 15 02:07:05 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326670659 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2326670659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_readback_err.2454313382 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 4120351117 ps |
| CPU time | 10.29 seconds |
| Started | Oct 15 02:07:06 AM UTC 24 |
| Finished | Oct 15 02:07:17 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454313382 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_readback_err.2454313382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.738653054 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 160969587171 ps |
| CPU time | 944.04 seconds |
| Started | Oct 15 02:06:56 AM UTC 24 |
| Finished | Oct 15 02:22:50 AM UTC 24 |
| Peak memory | 386172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738653054 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.738653054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.1033745393 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 827556505 ps |
| CPU time | 30.01 seconds |
| Started | Oct 15 02:05:48 AM UTC 24 |
| Finished | Oct 15 02:06:19 AM UTC 24 |
| Peak memory | 295816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033745393 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1033745393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.2150267789 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 207084242979 ps |
| CPU time | 1604.61 seconds |
| Started | Oct 15 02:07:41 AM UTC 24 |
| Finished | Oct 15 02:34:43 AM UTC 24 |
| Peak memory | 402380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21502677 89 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_a ll.2150267789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4027206346 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 4360529481 ps |
| CPU time | 79.45 seconds |
| Started | Oct 15 02:07:18 AM UTC 24 |
| Finished | Oct 15 02:08:39 AM UTC 24 |
| Peak memory | 339144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027206346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.4027206346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1205229852 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 11287103282 ps |
| CPU time | 262.72 seconds |
| Started | Oct 15 02:06:17 AM UTC 24 |
| Finished | Oct 15 02:10:44 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205229852 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.1205229852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3509339089 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3095793378 ps |
| CPU time | 88.68 seconds |
| Started | Oct 15 02:06:45 AM UTC 24 |
| Finished | Oct 15 02:08:15 AM UTC 24 |
| Peak memory | 371592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3509339089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl _throughput_w_partial_write.3509339089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.2583112210 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 4336898617 ps |
| CPU time | 234.31 seconds |
| Started | Oct 15 02:08:36 AM UTC 24 |
| Finished | Oct 15 02:12:34 AM UTC 24 |
| Peak memory | 363392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583112210 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_duri ng_key_req.2583112210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.777717023 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 147697193 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 02:09:39 AM UTC 24 |
| Finished | Oct 15 02:09:41 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777717023 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.777717023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.2712835059 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 32208348557 ps |
| CPU time | 1142.95 seconds |
| Started | Oct 15 02:07:53 AM UTC 24 |
| Finished | Oct 15 02:27:09 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712835059 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.2712835059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.4108755244 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 5712319136 ps |
| CPU time | 212.35 seconds |
| Started | Oct 15 02:08:40 AM UTC 24 |
| Finished | Oct 15 02:12:16 AM UTC 24 |
| Peak memory | 383948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108755244 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.4108755244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3778737140 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 6954970137 ps |
| CPU time | 47.65 seconds |
| Started | Oct 15 02:08:34 AM UTC 24 |
| Finished | Oct 15 02:09:23 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778737140 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.3778737140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2486317549 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 696677394 ps |
| CPU time | 18.59 seconds |
| Started | Oct 15 02:08:16 AM UTC 24 |
| Finished | Oct 15 02:08:36 AM UTC 24 |
| Peak memory | 250892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2486317549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ max_throughput.2486317549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.4001028342 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2749697276 ps |
| CPU time | 106.98 seconds |
| Started | Oct 15 02:09:19 AM UTC 24 |
| Finished | Oct 15 02:11:08 AM UTC 24 |
| Peak memory | 221524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001028342 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.4001028342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.4283802297 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 41435723625 ps |
| CPU time | 218.83 seconds |
| Started | Oct 15 02:09:19 AM UTC 24 |
| Finished | Oct 15 02:13:01 AM UTC 24 |
| Peak memory | 221360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283802297 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.4283802297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1308806923 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2883738139 ps |
| CPU time | 29.11 seconds |
| Started | Oct 15 02:08:03 AM UTC 24 |
| Finished | Oct 15 02:08:33 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308806923 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.1308806923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1280064521 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 16105715127 ps |
| CPU time | 453.37 seconds |
| Started | Oct 15 02:08:04 AM UTC 24 |
| Finished | Oct 15 02:15:43 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280064521 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_a ccess_b2b.1280064521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.341047339 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1361501673 ps |
| CPU time | 4.96 seconds |
| Started | Oct 15 02:09:12 AM UTC 24 |
| Finished | Oct 15 02:09:18 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341047339 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.341047339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_readback_err.3561799239 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 699016780 ps |
| CPU time | 10.96 seconds |
| Started | Oct 15 02:09:24 AM UTC 24 |
| Finished | Oct 15 02:09:36 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561799239 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_readback_err.3561799239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.2718665803 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 52071804644 ps |
| CPU time | 843 seconds |
| Started | Oct 15 02:08:43 AM UTC 24 |
| Finished | Oct 15 02:22:56 AM UTC 24 |
| Peak memory | 387964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718665803 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2718665803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.199379369 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 5728099947 ps |
| CPU time | 93.28 seconds |
| Started | Oct 15 02:07:48 AM UTC 24 |
| Finished | Oct 15 02:09:23 AM UTC 24 |
| Peak memory | 375748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199379369 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.199379369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.90752208 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 46300923629 ps |
| CPU time | 4573.57 seconds |
| Started | Oct 15 02:09:37 AM UTC 24 |
| Finished | Oct 15 03:26:41 AM UTC 24 |
| Peak memory | 391492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90752208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.90752208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.652304495 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 141615394 ps |
| CPU time | 12.61 seconds |
| Started | Oct 15 02:09:24 AM UTC 24 |
| Finished | Oct 15 02:09:38 AM UTC 24 |
| Peak memory | 221476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652304495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.652304495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.2947047656 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 21008742097 ps |
| CPU time | 426.96 seconds |
| Started | Oct 15 02:07:55 AM UTC 24 |
| Finished | Oct 15 02:15:08 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947047656 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.2947047656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1011660548 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2755663717 ps |
| CPU time | 48.98 seconds |
| Started | Oct 15 02:08:20 AM UTC 24 |
| Finished | Oct 15 02:09:10 AM UTC 24 |
| Peak memory | 314308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1011660548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl _throughput_w_partial_write.1011660548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3849898336 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 66526503996 ps |
| CPU time | 761.36 seconds |
| Started | Oct 15 02:11:12 AM UTC 24 |
| Finished | Oct 15 02:24:01 AM UTC 24 |
| Peak memory | 388048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849898336 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_duri ng_key_req.3849898336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.4273889385 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 20680729 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 02:12:35 AM UTC 24 |
| Finished | Oct 15 02:12:37 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273889385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.4273889385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.1140561790 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 8207680982 ps |
| CPU time | 576.31 seconds |
| Started | Oct 15 02:10:37 AM UTC 24 |
| Finished | Oct 15 02:20:20 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140561790 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.1140561790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2752867377 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 30534595083 ps |
| CPU time | 260.57 seconds |
| Started | Oct 15 02:11:13 AM UTC 24 |
| Finished | Oct 15 02:15:37 AM UTC 24 |
| Peak memory | 357324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752867377 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.2752867377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1430431133 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 8939128035 ps |
| CPU time | 79.55 seconds |
| Started | Oct 15 02:11:08 AM UTC 24 |
| Finished | Oct 15 02:12:30 AM UTC 24 |
| Peak memory | 225648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430431133 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.1430431133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.1535214302 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 733292638 ps |
| CPU time | 19.62 seconds |
| Started | Oct 15 02:10:52 AM UTC 24 |
| Finished | Oct 15 02:11:13 AM UTC 24 |
| Peak memory | 260988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1535214302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ max_throughput.1535214302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3458590509 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1453214826 ps |
| CPU time | 85.32 seconds |
| Started | Oct 15 02:12:16 AM UTC 24 |
| Finished | Oct 15 02:13:43 AM UTC 24 |
| Peak memory | 221468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458590509 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.3458590509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1239837907 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 8981081373 ps |
| CPU time | 175.69 seconds |
| Started | Oct 15 02:11:59 AM UTC 24 |
| Finished | Oct 15 02:14:58 AM UTC 24 |
| Peak memory | 221388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239837907 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.1239837907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3800808986 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 14058612203 ps |
| CPU time | 488.24 seconds |
| Started | Oct 15 02:10:07 AM UTC 24 |
| Finished | Oct 15 02:18:21 AM UTC 24 |
| Peak memory | 385916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800808986 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.3800808986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2765818315 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 3098319861 ps |
| CPU time | 23.52 seconds |
| Started | Oct 15 02:10:45 AM UTC 24 |
| Finished | Oct 15 02:11:10 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765818315 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.2765818315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.426900746 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 7799032237 ps |
| CPU time | 234.74 seconds |
| Started | Oct 15 02:10:47 AM UTC 24 |
| Finished | Oct 15 02:14:46 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426900746 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_ac cess_b2b.426900746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.499090577 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 356874433 ps |
| CPU time | 5.92 seconds |
| Started | Oct 15 02:11:51 AM UTC 24 |
| Finished | Oct 15 02:11:58 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499090577 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.499090577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_readback_err.3503740860 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 697089109 ps |
| CPU time | 9.47 seconds |
| Started | Oct 15 02:12:20 AM UTC 24 |
| Finished | Oct 15 02:12:31 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503740860 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_readback_err.3503740860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.2734915306 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 5102064037 ps |
| CPU time | 1007.87 seconds |
| Started | Oct 15 02:11:14 AM UTC 24 |
| Finished | Oct 15 02:28:12 AM UTC 24 |
| Peak memory | 383940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734915306 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2734915306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.1189682174 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 9179411877 ps |
| CPU time | 62.21 seconds |
| Started | Oct 15 02:09:42 AM UTC 24 |
| Finished | Oct 15 02:10:46 AM UTC 24 |
| Peak memory | 330692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189682174 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1189682174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1311960150 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 64687617873 ps |
| CPU time | 5911.54 seconds |
| Started | Oct 15 02:12:33 AM UTC 24 |
| Finished | Oct 15 03:52:07 AM UTC 24 |
| Peak memory | 397712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13119601 50 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_a ll.1311960150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.501487297 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 4697279582 ps |
| CPU time | 89.35 seconds |
| Started | Oct 15 02:12:31 AM UTC 24 |
| Finished | Oct 15 02:14:03 AM UTC 24 |
| Peak memory | 330748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501487297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.501487297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.614035906 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 12907058696 ps |
| CPU time | 338.29 seconds |
| Started | Oct 15 02:10:44 AM UTC 24 |
| Finished | Oct 15 02:16:27 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614035906 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.614035906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3487224508 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2828073840 ps |
| CPU time | 9.48 seconds |
| Started | Oct 15 02:11:01 AM UTC 24 |
| Finished | Oct 15 02:11:12 AM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3487224508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl _throughput_w_partial_write.3487224508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.4225123595 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 160851396209 ps |
| CPU time | 989.71 seconds |
| Started | Oct 15 02:14:57 AM UTC 24 |
| Finished | Oct 15 02:31:38 AM UTC 24 |
| Peak memory | 388172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225123595 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_duri ng_key_req.4225123595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.610824026 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 48296141 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 02:15:44 AM UTC 24 |
| Finished | Oct 15 02:15:46 AM UTC 24 |
| Peak memory | 210884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610824026 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.610824026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.939059304 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 113021970484 ps |
| CPU time | 1160.74 seconds |
| Started | Oct 15 02:13:23 AM UTC 24 |
| Finished | Oct 15 02:32:58 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939059304 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.939059304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.3211288865 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 21137517795 ps |
| CPU time | 1018.28 seconds |
| Started | Oct 15 02:14:58 AM UTC 24 |
| Finished | Oct 15 02:32:09 AM UTC 24 |
| Peak memory | 383872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211288865 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.3211288865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.140609387 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 6776846862 ps |
| CPU time | 57 seconds |
| Started | Oct 15 02:14:53 AM UTC 24 |
| Finished | Oct 15 02:15:52 AM UTC 24 |
| Peak memory | 225512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140609387 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.140609387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3005711230 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 3015481584 ps |
| CPU time | 50.14 seconds |
| Started | Oct 15 02:14:25 AM UTC 24 |
| Finished | Oct 15 02:15:17 AM UTC 24 |
| Peak memory | 310220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3005711230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ max_throughput.3005711230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.4043106161 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2751022842 ps |
| CPU time | 101.31 seconds |
| Started | Oct 15 02:15:17 AM UTC 24 |
| Finished | Oct 15 02:17:01 AM UTC 24 |
| Peak memory | 221384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043106161 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.4043106161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.4270309569 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 30880069246 ps |
| CPU time | 381.27 seconds |
| Started | Oct 15 02:15:16 AM UTC 24 |
| Finished | Oct 15 02:21:42 AM UTC 24 |
| Peak memory | 221616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270309569 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.4270309569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1170782 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 37913951758 ps |
| CPU time | 272.19 seconds |
| Started | Oct 15 02:13:02 AM UTC 24 |
| Finished | Oct 15 02:17:38 AM UTC 24 |
| Peak memory | 373624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170782 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.1170782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3490159551 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 3383199872 ps |
| CPU time | 76.28 seconds |
| Started | Oct 15 02:13:57 AM UTC 24 |
| Finished | Oct 15 02:15:15 AM UTC 24 |
| Peak memory | 373828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490159551 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.3490159551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.626755494 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 5821034713 ps |
| CPU time | 415.1 seconds |
| Started | Oct 15 02:14:05 AM UTC 24 |
| Finished | Oct 15 02:21:06 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626755494 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_ac cess_b2b.626755494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2681133797 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 346694871 ps |
| CPU time | 5.78 seconds |
| Started | Oct 15 02:15:10 AM UTC 24 |
| Finished | Oct 15 02:15:16 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681133797 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2681133797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_readback_err.1066486928 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1388975576 ps |
| CPU time | 11.87 seconds |
| Started | Oct 15 02:15:18 AM UTC 24 |
| Finished | Oct 15 02:15:31 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066486928 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_readback_err.1066486928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.2848590545 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 2771797363 ps |
| CPU time | 1028.44 seconds |
| Started | Oct 15 02:15:07 AM UTC 24 |
| Finished | Oct 15 02:32:26 AM UTC 24 |
| Peak memory | 388156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848590545 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2848590545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.451131529 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 4702291307 ps |
| CPU time | 75.63 seconds |
| Started | Oct 15 02:12:38 AM UTC 24 |
| Finished | Oct 15 02:13:56 AM UTC 24 |
| Peak memory | 347072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451131529 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.451131529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2563326820 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 52673921255 ps |
| CPU time | 2509.65 seconds |
| Started | Oct 15 02:15:38 AM UTC 24 |
| Finished | Oct 15 02:57:54 AM UTC 24 |
| Peak memory | 390208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25633268 20 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_a ll.2563326820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.69121083 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 773639072 ps |
| CPU time | 15.45 seconds |
| Started | Oct 15 02:15:32 AM UTC 24 |
| Finished | Oct 15 02:15:49 AM UTC 24 |
| Peak memory | 221548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69121083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.69121083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.663022786 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 10473241866 ps |
| CPU time | 394.17 seconds |
| Started | Oct 15 02:13:44 AM UTC 24 |
| Finished | Oct 15 02:20:24 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663022786 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.663022786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.521909296 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 699712944 ps |
| CPU time | 9.75 seconds |
| Started | Oct 15 02:14:46 AM UTC 24 |
| Finished | Oct 15 02:14:57 AM UTC 24 |
| Peak memory | 228284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =521909296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ throughput_w_partial_write.521909296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2363663653 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 10209945863 ps |
| CPU time | 396.8 seconds |
| Started | Oct 15 02:16:27 AM UTC 24 |
| Finished | Oct 15 02:23:10 AM UTC 24 |
| Peak memory | 386060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363663653 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_duri ng_key_req.2363663653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3339031988 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 47235894 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 02:17:43 AM UTC 24 |
| Finished | Oct 15 02:17:45 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339031988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3339031988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.4127892641 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 96794571383 ps |
| CPU time | 1560.41 seconds |
| Started | Oct 15 02:15:50 AM UTC 24 |
| Finished | Oct 15 02:42:07 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127892641 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.4127892641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.4168914957 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 102721602913 ps |
| CPU time | 681.4 seconds |
| Started | Oct 15 02:16:32 AM UTC 24 |
| Finished | Oct 15 02:28:02 AM UTC 24 |
| Peak memory | 373628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168914957 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.4168914957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1186279683 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 8565774514 ps |
| CPU time | 76.8 seconds |
| Started | Oct 15 02:16:27 AM UTC 24 |
| Finished | Oct 15 02:17:46 AM UTC 24 |
| Peak memory | 221424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186279683 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.1186279683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2787336748 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1428078706 ps |
| CPU time | 12.06 seconds |
| Started | Oct 15 02:16:17 AM UTC 24 |
| Finished | Oct 15 02:16:30 AM UTC 24 |
| Peak memory | 221516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2787336748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ max_throughput.2787336748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.4112052195 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 16862826010 ps |
| CPU time | 109.98 seconds |
| Started | Oct 15 02:17:06 AM UTC 24 |
| Finished | Oct 15 02:18:58 AM UTC 24 |
| Peak memory | 223572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112052195 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.4112052195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3456733501 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 30302021826 ps |
| CPU time | 254.58 seconds |
| Started | Oct 15 02:17:02 AM UTC 24 |
| Finished | Oct 15 02:21:20 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456733501 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.3456733501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2629975817 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 13226110161 ps |
| CPU time | 93.54 seconds |
| Started | Oct 15 02:15:48 AM UTC 24 |
| Finished | Oct 15 02:17:23 AM UTC 24 |
| Peak memory | 332932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629975817 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.2629975817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3866597426 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 12635391354 ps |
| CPU time | 43.69 seconds |
| Started | Oct 15 02:16:12 AM UTC 24 |
| Finished | Oct 15 02:16:57 AM UTC 24 |
| Peak memory | 293800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866597426 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.3866597426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3000639757 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 15824151356 ps |
| CPU time | 411.39 seconds |
| Started | Oct 15 02:16:12 AM UTC 24 |
| Finished | Oct 15 02:23:09 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000639757 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_a ccess_b2b.3000639757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1657841117 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1695926360 ps |
| CPU time | 6.14 seconds |
| Started | Oct 15 02:16:58 AM UTC 24 |
| Finished | Oct 15 02:17:06 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657841117 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1657841117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_readback_err.2079695954 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1452608132 ps |
| CPU time | 6.58 seconds |
| Started | Oct 15 02:17:24 AM UTC 24 |
| Finished | Oct 15 02:17:32 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079695954 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_readback_err.2079695954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.2272652728 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 204383144102 ps |
| CPU time | 963.44 seconds |
| Started | Oct 15 02:16:40 AM UTC 24 |
| Finished | Oct 15 02:32:53 AM UTC 24 |
| Peak memory | 379908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272652728 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2272652728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.514303906 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 14222767086 ps |
| CPU time | 22.33 seconds |
| Started | Oct 15 02:15:47 AM UTC 24 |
| Finished | Oct 15 02:16:11 AM UTC 24 |
| Peak memory | 279480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514303906 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.514303906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.744600646 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 1289014504488 ps |
| CPU time | 4761.33 seconds |
| Started | Oct 15 02:17:39 AM UTC 24 |
| Finished | Oct 15 03:37:49 AM UTC 24 |
| Peak memory | 393608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74460064 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.744600646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2313147898 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1569778812 ps |
| CPU time | 72.92 seconds |
| Started | Oct 15 02:17:32 AM UTC 24 |
| Finished | Oct 15 02:18:47 AM UTC 24 |
| Peak memory | 326588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313147898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2313147898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.878686029 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 8126011799 ps |
| CPU time | 161.46 seconds |
| Started | Oct 15 02:15:53 AM UTC 24 |
| Finished | Oct 15 02:18:37 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878686029 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.878686029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2234760492 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 3670039354 ps |
| CPU time | 14.64 seconds |
| Started | Oct 15 02:16:23 AM UTC 24 |
| Finished | Oct 15 02:16:39 AM UTC 24 |
| Peak memory | 261188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2234760492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl _throughput_w_partial_write.2234760492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3110694125 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 8507210523 ps |
| CPU time | 250.97 seconds |
| Started | Oct 15 02:19:10 AM UTC 24 |
| Finished | Oct 15 02:23:25 AM UTC 24 |
| Peak memory | 383868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110694125 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_duri ng_key_req.3110694125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.4003379150 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 203111306 ps |
| CPU time | 1.03 seconds |
| Started | Oct 15 02:20:35 AM UTC 24 |
| Finished | Oct 15 02:20:37 AM UTC 24 |
| Peak memory | 210520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003379150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.4003379150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.617825645 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 368152302277 ps |
| CPU time | 2345.98 seconds |
| Started | Oct 15 02:18:05 AM UTC 24 |
| Finished | Oct 15 02:57:37 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617825645 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.617825645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.2611760455 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 40689515826 ps |
| CPU time | 1060.53 seconds |
| Started | Oct 15 02:19:20 AM UTC 24 |
| Finished | Oct 15 02:37:13 AM UTC 24 |
| Peak memory | 377800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611760455 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.2611760455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3628118161 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 80434226324 ps |
| CPU time | 79.58 seconds |
| Started | Oct 15 02:19:08 AM UTC 24 |
| Finished | Oct 15 02:20:29 AM UTC 24 |
| Peak memory | 221416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628118161 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.3628118161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3234752162 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 742541150 ps |
| CPU time | 21.14 seconds |
| Started | Oct 15 02:18:57 AM UTC 24 |
| Finished | Oct 15 02:19:19 AM UTC 24 |
| Peak memory | 277376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3234752162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ max_throughput.3234752162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3730283401 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 4605891260 ps |
| CPU time | 171.17 seconds |
| Started | Oct 15 02:20:21 AM UTC 24 |
| Finished | Oct 15 02:23:15 AM UTC 24 |
| Peak memory | 228196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730283401 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.3730283401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.1137876989 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 4026672470 ps |
| CPU time | 299.84 seconds |
| Started | Oct 15 02:20:18 AM UTC 24 |
| Finished | Oct 15 02:25:23 AM UTC 24 |
| Peak memory | 221392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137876989 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.1137876989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1210004105 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 14786741587 ps |
| CPU time | 139.71 seconds |
| Started | Oct 15 02:17:47 AM UTC 24 |
| Finished | Oct 15 02:20:09 AM UTC 24 |
| Peak memory | 357292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210004105 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.1210004105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.353552640 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 463477380 ps |
| CPU time | 16.34 seconds |
| Started | Oct 15 02:18:38 AM UTC 24 |
| Finished | Oct 15 02:18:56 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353552640 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.353552640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.2754665929 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 46790018883 ps |
| CPU time | 227.66 seconds |
| Started | Oct 15 02:18:48 AM UTC 24 |
| Finished | Oct 15 02:22:39 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754665929 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_a ccess_b2b.2754665929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2717842010 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1354002464 ps |
| CPU time | 6.32 seconds |
| Started | Oct 15 02:20:10 AM UTC 24 |
| Finished | Oct 15 02:20:18 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717842010 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2717842010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_readback_err.1861385447 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2743611478 ps |
| CPU time | 7.05 seconds |
| Started | Oct 15 02:20:25 AM UTC 24 |
| Finished | Oct 15 02:20:33 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861385447 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_readback_err.1861385447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.2866018012 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 7121864060 ps |
| CPU time | 638.84 seconds |
| Started | Oct 15 02:19:22 AM UTC 24 |
| Finished | Oct 15 02:30:09 AM UTC 24 |
| Peak memory | 381816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866018012 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2866018012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.2906659755 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 5464245038 ps |
| CPU time | 17.61 seconds |
| Started | Oct 15 02:17:46 AM UTC 24 |
| Finished | Oct 15 02:18:04 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906659755 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2906659755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3347687818 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 372484870351 ps |
| CPU time | 3699.3 seconds |
| Started | Oct 15 02:20:34 AM UTC 24 |
| Finished | Oct 15 03:22:53 AM UTC 24 |
| Peak memory | 396352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33476878 18 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_a ll.3347687818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3296126876 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 8916014332 ps |
| CPU time | 103.7 seconds |
| Started | Oct 15 02:20:30 AM UTC 24 |
| Finished | Oct 15 02:22:16 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296126876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3296126876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3136036680 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2933977046 ps |
| CPU time | 200.29 seconds |
| Started | Oct 15 02:18:22 AM UTC 24 |
| Finished | Oct 15 02:21:46 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136036680 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.3136036680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1616058577 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1638980584 ps |
| CPU time | 92 seconds |
| Started | Oct 15 02:19:00 AM UTC 24 |
| Finished | Oct 15 02:20:34 AM UTC 24 |
| Peak memory | 381752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1616058577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _throughput_w_partial_write.1616058577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3276549756 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 114299828224 ps |
| CPU time | 1039.04 seconds |
| Started | Oct 15 02:22:51 AM UTC 24 |
| Finished | Oct 15 02:40:21 AM UTC 24 |
| Peak memory | 379852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276549756 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_duri ng_key_req.3276549756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1711315232 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 12234098 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 02:23:24 AM UTC 24 |
| Finished | Oct 15 02:23:26 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711315232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1711315232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.1631980223 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 133748392056 ps |
| CPU time | 3099.6 seconds |
| Started | Oct 15 02:21:07 AM UTC 24 |
| Finished | Oct 15 03:13:21 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631980223 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.1631980223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.2900712210 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 17095746475 ps |
| CPU time | 683.43 seconds |
| Started | Oct 15 02:22:57 AM UTC 24 |
| Finished | Oct 15 02:34:28 AM UTC 24 |
| Peak memory | 375884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900712210 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.2900712210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.499518576 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5872682592 ps |
| CPU time | 38.94 seconds |
| Started | Oct 15 02:22:42 AM UTC 24 |
| Finished | Oct 15 02:23:22 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499518576 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.499518576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.2458821971 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3641975468 ps |
| CPU time | 22.73 seconds |
| Started | Oct 15 02:22:16 AM UTC 24 |
| Finished | Oct 15 02:22:40 AM UTC 24 |
| Peak memory | 261052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2458821971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ max_throughput.2458821971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.997769053 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2507946714 ps |
| CPU time | 141.43 seconds |
| Started | Oct 15 02:23:10 AM UTC 24 |
| Finished | Oct 15 02:25:34 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997769053 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.997769053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3558082432 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 3952222667 ps |
| CPU time | 122.41 seconds |
| Started | Oct 15 02:23:09 AM UTC 24 |
| Finished | Oct 15 02:25:14 AM UTC 24 |
| Peak memory | 221620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558082432 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.3558082432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3153207937 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1512663736 ps |
| CPU time | 124.72 seconds |
| Started | Oct 15 02:20:50 AM UTC 24 |
| Finished | Oct 15 02:22:58 AM UTC 24 |
| Peak memory | 344960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153207937 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.3153207937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1762734156 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2606329207 ps |
| CPU time | 97.32 seconds |
| Started | Oct 15 02:21:43 AM UTC 24 |
| Finished | Oct 15 02:23:22 AM UTC 24 |
| Peak memory | 375944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762734156 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.1762734156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2200740991 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 80777907305 ps |
| CPU time | 688.59 seconds |
| Started | Oct 15 02:21:47 AM UTC 24 |
| Finished | Oct 15 02:33:24 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200740991 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_a ccess_b2b.2200740991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3267377806 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 368289700 ps |
| CPU time | 4.54 seconds |
| Started | Oct 15 02:23:02 AM UTC 24 |
| Finished | Oct 15 02:23:08 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267377806 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3267377806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_readback_err.2627946113 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2749900740 ps |
| CPU time | 11.14 seconds |
| Started | Oct 15 02:23:10 AM UTC 24 |
| Finished | Oct 15 02:23:22 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627946113 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_readback_err.2627946113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.2452687584 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 16798818515 ps |
| CPU time | 1136.89 seconds |
| Started | Oct 15 02:22:59 AM UTC 24 |
| Finished | Oct 15 02:42:09 AM UTC 24 |
| Peak memory | 390004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452687584 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2452687584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.1089465169 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 705908464 ps |
| CPU time | 9.93 seconds |
| Started | Oct 15 02:20:38 AM UTC 24 |
| Finished | Oct 15 02:20:49 AM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089465169 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1089465169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.744009685 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 191026585799 ps |
| CPU time | 3307.02 seconds |
| Started | Oct 15 02:23:18 AM UTC 24 |
| Finished | Oct 15 03:19:02 AM UTC 24 |
| Peak memory | 273276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74400968 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.744009685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1965589276 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2221465414 ps |
| CPU time | 25.07 seconds |
| Started | Oct 15 02:23:15 AM UTC 24 |
| Finished | Oct 15 02:23:42 AM UTC 24 |
| Peak memory | 221544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965589276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1965589276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.675689325 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 19307650362 ps |
| CPU time | 306.3 seconds |
| Started | Oct 15 02:21:21 AM UTC 24 |
| Finished | Oct 15 02:26:32 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675689325 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.675689325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.2201311127 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2832130320 ps |
| CPU time | 19.54 seconds |
| Started | Oct 15 02:22:40 AM UTC 24 |
| Finished | Oct 15 02:23:01 AM UTC 24 |
| Peak memory | 269380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2201311127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl _throughput_w_partial_write.2201311127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2738203859 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 25738018038 ps |
| CPU time | 1115.91 seconds |
| Started | Oct 15 02:24:02 AM UTC 24 |
| Finished | Oct 15 02:42:50 AM UTC 24 |
| Peak memory | 385988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738203859 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_duri ng_key_req.2738203859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1773793593 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 27670137 ps |
| CPU time | 0.88 seconds |
| Started | Oct 15 02:25:35 AM UTC 24 |
| Finished | Oct 15 02:25:37 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773793593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1773793593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.228738149 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 61561360497 ps |
| CPU time | 960.45 seconds |
| Started | Oct 15 02:23:26 AM UTC 24 |
| Finished | Oct 15 02:39:37 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228738149 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.228738149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.567780580 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 22509125661 ps |
| CPU time | 1318.82 seconds |
| Started | Oct 15 02:24:08 AM UTC 24 |
| Finished | Oct 15 02:46:21 AM UTC 24 |
| Peak memory | 388028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567780580 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.567780580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.93942428 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1125316156 ps |
| CPU time | 10.64 seconds |
| Started | Oct 15 02:23:57 AM UTC 24 |
| Finished | Oct 15 02:24:09 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93942428 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.93942428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1793900056 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 2771041501 ps |
| CPU time | 13.06 seconds |
| Started | Oct 15 02:23:42 AM UTC 24 |
| Finished | Oct 15 02:23:56 AM UTC 24 |
| Peak memory | 221232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1793900056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ max_throughput.1793900056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.7554305 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3812422046 ps |
| CPU time | 74.27 seconds |
| Started | Oct 15 02:24:23 AM UTC 24 |
| Finished | Oct 15 02:25:39 AM UTC 24 |
| Peak memory | 221664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7554305 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.7554305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.223029886 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 147670278968 ps |
| CPU time | 171.18 seconds |
| Started | Oct 15 02:24:15 AM UTC 24 |
| Finished | Oct 15 02:27:09 AM UTC 24 |
| Peak memory | 221416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223029886 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.223029886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.717162677 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 23641796396 ps |
| CPU time | 1218.79 seconds |
| Started | Oct 15 02:23:24 AM UTC 24 |
| Finished | Oct 15 02:43:56 AM UTC 24 |
| Peak memory | 387960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717162677 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.717162677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.2364807834 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1810419284 ps |
| CPU time | 12.82 seconds |
| Started | Oct 15 02:23:27 AM UTC 24 |
| Finished | Oct 15 02:23:41 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364807834 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.2364807834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.405166930 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 6568201016 ps |
| CPU time | 420.28 seconds |
| Started | Oct 15 02:23:34 AM UTC 24 |
| Finished | Oct 15 02:30:40 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405166930 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_ac cess_b2b.405166930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.912123175 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1355891898 ps |
| CPU time | 6.87 seconds |
| Started | Oct 15 02:24:14 AM UTC 24 |
| Finished | Oct 15 02:24:22 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912123175 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.912123175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_readback_err.3372950324 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 665568388 ps |
| CPU time | 7.54 seconds |
| Started | Oct 15 02:25:15 AM UTC 24 |
| Finished | Oct 15 02:25:23 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372950324 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_readback_err.3372950324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.495163018 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 20906535410 ps |
| CPU time | 805.56 seconds |
| Started | Oct 15 02:24:11 AM UTC 24 |
| Finished | Oct 15 02:37:46 AM UTC 24 |
| Peak memory | 385924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495163018 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.495163018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.2624490513 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2776542778 ps |
| CPU time | 42 seconds |
| Started | Oct 15 02:23:24 AM UTC 24 |
| Finished | Oct 15 02:24:07 AM UTC 24 |
| Peak memory | 295936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624490513 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2624490513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3999608775 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 58166711940 ps |
| CPU time | 2062.35 seconds |
| Started | Oct 15 02:25:24 AM UTC 24 |
| Finished | Oct 15 03:00:07 AM UTC 24 |
| Peak memory | 385996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39996087 75 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_a ll.3999608775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3255078401 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 7896679249 ps |
| CPU time | 56.69 seconds |
| Started | Oct 15 02:25:24 AM UTC 24 |
| Finished | Oct 15 02:26:22 AM UTC 24 |
| Peak memory | 225716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255078401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3255078401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1093475966 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4842671146 ps |
| CPU time | 348.65 seconds |
| Started | Oct 15 02:23:26 AM UTC 24 |
| Finished | Oct 15 02:29:19 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093475966 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.1093475966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1316113926 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 769183970 ps |
| CPU time | 29.44 seconds |
| Started | Oct 15 02:23:42 AM UTC 24 |
| Finished | Oct 15 02:24:13 AM UTC 24 |
| Peak memory | 314100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1316113926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _throughput_w_partial_write.1316113926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.656061829 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 12353042894 ps |
| CPU time | 783.93 seconds |
| Started | Oct 15 02:26:54 AM UTC 24 |
| Finished | Oct 15 02:40:06 AM UTC 24 |
| Peak memory | 388028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656061829 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_durin g_key_req.656061829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3920677809 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 49714707 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 02:27:48 AM UTC 24 |
| Finished | Oct 15 02:27:50 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920677809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3920677809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.4156081414 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 267787604521 ps |
| CPU time | 1323.11 seconds |
| Started | Oct 15 02:25:40 AM UTC 24 |
| Finished | Oct 15 02:47:59 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156081414 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.4156081414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.1501604705 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 23487693951 ps |
| CPU time | 557.72 seconds |
| Started | Oct 15 02:27:07 AM UTC 24 |
| Finished | Oct 15 02:36:32 AM UTC 24 |
| Peak memory | 385992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501604705 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.1501604705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2536761724 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 14826980296 ps |
| CPU time | 29.34 seconds |
| Started | Oct 15 02:26:51 AM UTC 24 |
| Finished | Oct 15 02:27:22 AM UTC 24 |
| Peak memory | 221352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536761724 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.2536761724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1632623278 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3062452166 ps |
| CPU time | 31.39 seconds |
| Started | Oct 15 02:26:34 AM UTC 24 |
| Finished | Oct 15 02:27:07 AM UTC 24 |
| Peak memory | 277380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1632623278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ max_throughput.1632623278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.687562989 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 10052370499 ps |
| CPU time | 168.23 seconds |
| Started | Oct 15 02:27:18 AM UTC 24 |
| Finished | Oct 15 02:30:09 AM UTC 24 |
| Peak memory | 221384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687562989 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.687562989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.527935359 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 14419041947 ps |
| CPU time | 358.85 seconds |
| Started | Oct 15 02:27:18 AM UTC 24 |
| Finished | Oct 15 02:33:22 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527935359 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.527935359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.120374287 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 42149030586 ps |
| CPU time | 614.72 seconds |
| Started | Oct 15 02:25:38 AM UTC 24 |
| Finished | Oct 15 02:35:59 AM UTC 24 |
| Peak memory | 387964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120374287 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.120374287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.407779069 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1036509768 ps |
| CPU time | 25.9 seconds |
| Started | Oct 15 02:26:23 AM UTC 24 |
| Finished | Oct 15 02:26:50 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407779069 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.407779069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3859933 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 16022864894 ps |
| CPU time | 435.14 seconds |
| Started | Oct 15 02:26:33 AM UTC 24 |
| Finished | Oct 15 02:33:54 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859933 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acce ss_b2b.3859933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.3725106785 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 360117228 ps |
| CPU time | 5 seconds |
| Started | Oct 15 02:27:11 AM UTC 24 |
| Finished | Oct 15 02:27:17 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725106785 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3725106785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_readback_err.1818400533 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 666503877 ps |
| CPU time | 10.65 seconds |
| Started | Oct 15 02:27:23 AM UTC 24 |
| Finished | Oct 15 02:27:35 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818400533 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_readback_err.1818400533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.274011353 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 9868677635 ps |
| CPU time | 657.03 seconds |
| Started | Oct 15 02:27:09 AM UTC 24 |
| Finished | Oct 15 02:38:14 AM UTC 24 |
| Peak memory | 383928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274011353 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.274011353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.981621585 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 557059329 ps |
| CPU time | 16.36 seconds |
| Started | Oct 15 02:25:38 AM UTC 24 |
| Finished | Oct 15 02:25:56 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981621585 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.981621585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2646138377 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 93098818807 ps |
| CPU time | 2822.06 seconds |
| Started | Oct 15 02:27:43 AM UTC 24 |
| Finished | Oct 15 03:15:13 AM UTC 24 |
| Peak memory | 390220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26461383 77 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_a ll.2646138377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.641866592 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 5538053646 ps |
| CPU time | 78.42 seconds |
| Started | Oct 15 02:27:36 AM UTC 24 |
| Finished | Oct 15 02:28:56 AM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641866592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.641866592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.11497077 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 25626869869 ps |
| CPU time | 296.84 seconds |
| Started | Oct 15 02:25:56 AM UTC 24 |
| Finished | Oct 15 02:30:57 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11497077 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.11497077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2485664627 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3134858728 ps |
| CPU time | 104.64 seconds |
| Started | Oct 15 02:26:38 AM UTC 24 |
| Finished | Oct 15 02:28:25 AM UTC 24 |
| Peak memory | 381896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2485664627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _throughput_w_partial_write.2485664627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.4088265767 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 12329237455 ps |
| CPU time | 589.22 seconds |
| Started | Oct 15 02:29:25 AM UTC 24 |
| Finished | Oct 15 02:39:21 AM UTC 24 |
| Peak memory | 381904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088265767 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_duri ng_key_req.4088265767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.919473584 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 13172186 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 02:31:03 AM UTC 24 |
| Finished | Oct 15 02:31:05 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919473584 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.919473584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.658633806 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 21751120968 ps |
| CPU time | 1561.07 seconds |
| Started | Oct 15 02:28:03 AM UTC 24 |
| Finished | Oct 15 02:54:22 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658633806 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.658633806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.1281925997 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3799717437 ps |
| CPU time | 228.68 seconds |
| Started | Oct 15 02:29:49 AM UTC 24 |
| Finished | Oct 15 02:33:41 AM UTC 24 |
| Peak memory | 359344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281925997 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.1281925997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2741380061 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 20885191865 ps |
| CPU time | 53.97 seconds |
| Started | Oct 15 02:29:20 AM UTC 24 |
| Finished | Oct 15 02:30:15 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741380061 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2741380061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3854330856 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5982938707 ps |
| CPU time | 24.83 seconds |
| Started | Oct 15 02:28:57 AM UTC 24 |
| Finished | Oct 15 02:29:23 AM UTC 24 |
| Peak memory | 299896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3854330856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ max_throughput.3854330856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.1244887194 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 10110496934 ps |
| CPU time | 93.04 seconds |
| Started | Oct 15 02:30:17 AM UTC 24 |
| Finished | Oct 15 02:31:52 AM UTC 24 |
| Peak memory | 221540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244887194 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.1244887194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.566767923 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 14104003811 ps |
| CPU time | 170.95 seconds |
| Started | Oct 15 02:30:16 AM UTC 24 |
| Finished | Oct 15 02:33:10 AM UTC 24 |
| Peak memory | 221356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566767923 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.566767923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.723413470 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1801787604 ps |
| CPU time | 58.81 seconds |
| Started | Oct 15 02:28:02 AM UTC 24 |
| Finished | Oct 15 02:29:02 AM UTC 24 |
| Peak memory | 312320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723413470 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.723413470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2434250661 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2956712851 ps |
| CPU time | 22.67 seconds |
| Started | Oct 15 02:28:26 AM UTC 24 |
| Finished | Oct 15 02:28:50 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434250661 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.2434250661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1835164157 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 33786700700 ps |
| CPU time | 247.05 seconds |
| Started | Oct 15 02:28:51 AM UTC 24 |
| Finished | Oct 15 02:33:02 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835164157 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_a ccess_b2b.1835164157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1661197046 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 360351886 ps |
| CPU time | 5.47 seconds |
| Started | Oct 15 02:30:10 AM UTC 24 |
| Finished | Oct 15 02:30:17 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661197046 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1661197046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3087798568 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2647572876 ps |
| CPU time | 8.43 seconds |
| Started | Oct 15 02:30:40 AM UTC 24 |
| Finished | Oct 15 02:30:50 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087798568 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_readback_err.3087798568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.3751748059 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 47165987978 ps |
| CPU time | 547.78 seconds |
| Started | Oct 15 02:30:10 AM UTC 24 |
| Finished | Oct 15 02:39:24 AM UTC 24 |
| Peak memory | 380040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751748059 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3751748059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.4070878201 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 484858085 ps |
| CPU time | 7.8 seconds |
| Started | Oct 15 02:27:51 AM UTC 24 |
| Finished | Oct 15 02:28:00 AM UTC 24 |
| Peak memory | 238464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070878201 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.4070878201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1015388922 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 3599568342599 ps |
| CPU time | 8526.83 seconds |
| Started | Oct 15 02:30:58 AM UTC 24 |
| Finished | Oct 15 04:54:36 AM UTC 24 |
| Peak memory | 385420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10153889 22 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_a ll.1015388922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.519025781 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1030475824 ps |
| CPU time | 10.49 seconds |
| Started | Oct 15 02:30:51 AM UTC 24 |
| Finished | Oct 15 02:31:02 AM UTC 24 |
| Peak memory | 221548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519025781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.519025781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3791137611 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 23115830791 ps |
| CPU time | 466.26 seconds |
| Started | Oct 15 02:28:13 AM UTC 24 |
| Finished | Oct 15 02:36:05 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791137611 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.3791137611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.2312488674 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2984858206 ps |
| CPU time | 43.43 seconds |
| Started | Oct 15 02:29:03 AM UTC 24 |
| Finished | Oct 15 02:29:48 AM UTC 24 |
| Peak memory | 322432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2312488674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _throughput_w_partial_write.2312488674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2810576236 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 66584924680 ps |
| CPU time | 1161.32 seconds |
| Started | Oct 15 01:12:37 AM UTC 24 |
| Finished | Oct 15 01:32:10 AM UTC 24 |
| Peak memory | 384064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810576236 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_durin g_key_req.2810576236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2466087966 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 38160826 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 01:13:07 AM UTC 24 |
| Finished | Oct 15 01:13:09 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466087966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2466087966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.4282568080 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 53698501551 ps |
| CPU time | 1794.21 seconds |
| Started | Oct 15 01:12:25 AM UTC 24 |
| Finished | Oct 15 01:42:39 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282568080 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.4282568080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.654167685 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 14588297642 ps |
| CPU time | 728.58 seconds |
| Started | Oct 15 01:12:45 AM UTC 24 |
| Finished | Oct 15 01:25:03 AM UTC 24 |
| Peak memory | 385736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654167685 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.654167685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2460662628 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 51010654733 ps |
| CPU time | 155.78 seconds |
| Started | Oct 15 01:12:35 AM UTC 24 |
| Finished | Oct 15 01:15:13 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460662628 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.2460662628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3923695966 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 766098560 ps |
| CPU time | 59.22 seconds |
| Started | Oct 15 01:12:30 AM UTC 24 |
| Finished | Oct 15 01:13:31 AM UTC 24 |
| Peak memory | 349060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3923695966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_m ax_throughput.3923695966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2725600642 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 10122541599 ps |
| CPU time | 171.16 seconds |
| Started | Oct 15 01:12:53 AM UTC 24 |
| Finished | Oct 15 01:15:47 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725600642 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.2725600642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.1940922577 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 57622184488 ps |
| CPU time | 352.52 seconds |
| Started | Oct 15 01:12:49 AM UTC 24 |
| Finished | Oct 15 01:18:47 AM UTC 24 |
| Peak memory | 221560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940922577 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.1940922577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.1391668651 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 167899500280 ps |
| CPU time | 881.7 seconds |
| Started | Oct 15 01:12:25 AM UTC 24 |
| Finished | Oct 15 01:27:17 AM UTC 24 |
| Peak memory | 385568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391668651 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.1391668651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1401848026 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2126366966 ps |
| CPU time | 18.16 seconds |
| Started | Oct 15 01:12:29 AM UTC 24 |
| Finished | Oct 15 01:12:48 AM UTC 24 |
| Peak memory | 254848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401848026 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.1401848026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1829652014 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1782103082 ps |
| CPU time | 5.55 seconds |
| Started | Oct 15 01:12:47 AM UTC 24 |
| Finished | Oct 15 01:12:54 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829652014 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1829652014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_readback_err.2690819631 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6577464179 ps |
| CPU time | 11.07 seconds |
| Started | Oct 15 01:12:54 AM UTC 24 |
| Finished | Oct 15 01:13:06 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690819631 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_readback_err.2690819631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.306220672 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 418382655 ps |
| CPU time | 5.9 seconds |
| Started | Oct 15 01:13:07 AM UTC 24 |
| Finished | Oct 15 01:13:14 AM UTC 24 |
| Peak memory | 247632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306220672 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.306220672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.2827552402 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1185656107 ps |
| CPU time | 46.14 seconds |
| Started | Oct 15 01:12:24 AM UTC 24 |
| Finished | Oct 15 01:13:13 AM UTC 24 |
| Peak memory | 332596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827552402 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2827552402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3968433238 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 40289667347 ps |
| CPU time | 3252.28 seconds |
| Started | Oct 15 01:13:02 AM UTC 24 |
| Finished | Oct 15 02:07:47 AM UTC 24 |
| Peak memory | 396156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39684332 38 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.3968433238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2154343796 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 216594634 ps |
| CPU time | 10.38 seconds |
| Started | Oct 15 01:12:55 AM UTC 24 |
| Finished | Oct 15 01:13:06 AM UTC 24 |
| Peak memory | 221672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154343796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2154343796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.3749163996 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 20512857888 ps |
| CPU time | 436.35 seconds |
| Started | Oct 15 01:12:28 AM UTC 24 |
| Finished | Oct 15 01:19:50 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749163996 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.3749163996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.2680943504 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 6602219343 ps |
| CPU time | 42.32 seconds |
| Started | Oct 15 01:12:32 AM UTC 24 |
| Finished | Oct 15 01:13:16 AM UTC 24 |
| Peak memory | 297796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2680943504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ throughput_w_partial_write.2680943504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.612938378 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 41787991451 ps |
| CPU time | 327.6 seconds |
| Started | Oct 15 02:32:53 AM UTC 24 |
| Finished | Oct 15 02:38:25 AM UTC 24 |
| Peak memory | 385980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612938378 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_durin g_key_req.612938378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3074910398 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 21812334 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 02:33:35 AM UTC 24 |
| Finished | Oct 15 02:33:38 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074910398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.3074910398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.515545555 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 62519547964 ps |
| CPU time | 1743.19 seconds |
| Started | Oct 15 02:31:39 AM UTC 24 |
| Finished | Oct 15 03:01:03 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515545555 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.515545555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1478556014 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 19526382217 ps |
| CPU time | 1177.13 seconds |
| Started | Oct 15 02:32:58 AM UTC 24 |
| Finished | Oct 15 02:52:49 AM UTC 24 |
| Peak memory | 388040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478556014 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.1478556014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2268751505 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 40619119404 ps |
| CPU time | 97.46 seconds |
| Started | Oct 15 02:32:32 AM UTC 24 |
| Finished | Oct 15 02:34:12 AM UTC 24 |
| Peak memory | 221404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268751505 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.2268751505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2509569357 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 6361057597 ps |
| CPU time | 108.92 seconds |
| Started | Oct 15 02:32:10 AM UTC 24 |
| Finished | Oct 15 02:34:01 AM UTC 24 |
| Peak memory | 381816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2509569357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ max_throughput.2509569357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2189675585 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 10951706063 ps |
| CPU time | 117.15 seconds |
| Started | Oct 15 02:33:23 AM UTC 24 |
| Finished | Oct 15 02:35:22 AM UTC 24 |
| Peak memory | 228252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189675585 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.2189675585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2599459866 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 103516714430 ps |
| CPU time | 229.52 seconds |
| Started | Oct 15 02:33:19 AM UTC 24 |
| Finished | Oct 15 02:37:12 AM UTC 24 |
| Peak memory | 221616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599459866 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.2599459866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2876473810 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 13402556452 ps |
| CPU time | 1512.94 seconds |
| Started | Oct 15 02:31:18 AM UTC 24 |
| Finished | Oct 15 02:56:48 AM UTC 24 |
| Peak memory | 387948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876473810 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.2876473810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1206420196 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3334215183 ps |
| CPU time | 36.68 seconds |
| Started | Oct 15 02:31:54 AM UTC 24 |
| Finished | Oct 15 02:32:32 AM UTC 24 |
| Peak memory | 291908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206420196 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.1206420196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3184656313 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 16312831433 ps |
| CPU time | 209.54 seconds |
| Started | Oct 15 02:32:00 AM UTC 24 |
| Finished | Oct 15 02:35:32 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184656313 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_a ccess_b2b.3184656313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2447108010 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 1416492877 ps |
| CPU time | 5.86 seconds |
| Started | Oct 15 02:33:11 AM UTC 24 |
| Finished | Oct 15 02:33:18 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447108010 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2447108010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_readback_err.3474312641 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 7349756234 ps |
| CPU time | 8.38 seconds |
| Started | Oct 15 02:33:25 AM UTC 24 |
| Finished | Oct 15 02:33:34 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474312641 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_readback_err.3474312641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.152184903 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1914959362 ps |
| CPU time | 27.22 seconds |
| Started | Oct 15 02:33:02 AM UTC 24 |
| Finished | Oct 15 02:33:31 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152184903 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.152184903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.116370319 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1468637629 ps |
| CPU time | 10.1 seconds |
| Started | Oct 15 02:31:06 AM UTC 24 |
| Finished | Oct 15 02:31:17 AM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116370319 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.116370319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.736631700 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 167939694616 ps |
| CPU time | 2413.62 seconds |
| Started | Oct 15 02:33:32 AM UTC 24 |
| Finished | Oct 15 03:14:10 AM UTC 24 |
| Peak memory | 390008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73663170 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.736631700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3799373395 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5040995167 ps |
| CPU time | 15.42 seconds |
| Started | Oct 15 02:33:25 AM UTC 24 |
| Finished | Oct 15 02:33:42 AM UTC 24 |
| Peak memory | 221624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799373395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.3799373395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.778143093 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 17777359655 ps |
| CPU time | 434.68 seconds |
| Started | Oct 15 02:31:45 AM UTC 24 |
| Finished | Oct 15 02:39:06 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778143093 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.778143093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.776525046 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2979374769 ps |
| CPU time | 55.89 seconds |
| Started | Oct 15 02:32:27 AM UTC 24 |
| Finished | Oct 15 02:33:24 AM UTC 24 |
| Peak memory | 320380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =776525046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ throughput_w_partial_write.776525046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.474695104 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 19428931138 ps |
| CPU time | 1062.96 seconds |
| Started | Oct 15 02:34:26 AM UTC 24 |
| Finished | Oct 15 02:52:21 AM UTC 24 |
| Peak memory | 388160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474695104 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_durin g_key_req.474695104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.1044419350 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 35439396 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 02:35:23 AM UTC 24 |
| Finished | Oct 15 02:35:25 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044419350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.1044419350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.195269584 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 749916510249 ps |
| CPU time | 1469.73 seconds |
| Started | Oct 15 02:33:43 AM UTC 24 |
| Finished | Oct 15 02:58:29 AM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195269584 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.195269584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.593330372 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 206739968465 ps |
| CPU time | 1440.22 seconds |
| Started | Oct 15 02:34:29 AM UTC 24 |
| Finished | Oct 15 02:58:47 AM UTC 24 |
| Peak memory | 385992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593330372 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.593330372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.130565851 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 14187389262 ps |
| CPU time | 46.46 seconds |
| Started | Oct 15 02:34:13 AM UTC 24 |
| Finished | Oct 15 02:35:01 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130565851 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.130565851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.4256586047 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 2845683523 ps |
| CPU time | 15.44 seconds |
| Started | Oct 15 02:34:12 AM UTC 24 |
| Finished | Oct 15 02:34:29 AM UTC 24 |
| Peak memory | 238540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4256586047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ max_throughput.4256586047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.852658812 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 5860676029 ps |
| CPU time | 120.97 seconds |
| Started | Oct 15 02:34:44 AM UTC 24 |
| Finished | Oct 15 02:36:47 AM UTC 24 |
| Peak memory | 221588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852658812 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.852658812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.351903195 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 6920637960 ps |
| CPU time | 191.42 seconds |
| Started | Oct 15 02:34:41 AM UTC 24 |
| Finished | Oct 15 02:37:55 AM UTC 24 |
| Peak memory | 221428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351903195 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.351903195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.3725026817 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 1822268633 ps |
| CPU time | 41.52 seconds |
| Started | Oct 15 02:33:42 AM UTC 24 |
| Finished | Oct 15 02:34:25 AM UTC 24 |
| Peak memory | 257024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725026817 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.3725026817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3465648406 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1573271311 ps |
| CPU time | 15.74 seconds |
| Started | Oct 15 02:33:55 AM UTC 24 |
| Finished | Oct 15 02:34:12 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465648406 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.3465648406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3068484448 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 12221395422 ps |
| CPU time | 319.12 seconds |
| Started | Oct 15 02:34:02 AM UTC 24 |
| Finished | Oct 15 02:39:25 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068484448 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_a ccess_b2b.3068484448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2952268489 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 363377407 ps |
| CPU time | 5.27 seconds |
| Started | Oct 15 02:34:34 AM UTC 24 |
| Finished | Oct 15 02:34:40 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952268489 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2952268489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_readback_err.4245671623 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 668728453 ps |
| CPU time | 10.35 seconds |
| Started | Oct 15 02:35:00 AM UTC 24 |
| Finished | Oct 15 02:35:12 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245671623 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_readback_err.4245671623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.2041820276 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 12185364538 ps |
| CPU time | 779.87 seconds |
| Started | Oct 15 02:34:29 AM UTC 24 |
| Finished | Oct 15 02:47:38 AM UTC 24 |
| Peak memory | 386112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041820276 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2041820276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.2625440920 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 679152539 ps |
| CPU time | 10.36 seconds |
| Started | Oct 15 02:33:38 AM UTC 24 |
| Finished | Oct 15 02:33:50 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625440920 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2625440920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1198515101 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 2901900982 ps |
| CPU time | 73.19 seconds |
| Started | Oct 15 02:35:02 AM UTC 24 |
| Finished | Oct 15 02:36:17 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198515101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1198515101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2873714547 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 5230001088 ps |
| CPU time | 306.45 seconds |
| Started | Oct 15 02:33:51 AM UTC 24 |
| Finished | Oct 15 02:39:01 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873714547 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.2873714547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.70951039 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 737222777 ps |
| CPU time | 19.74 seconds |
| Started | Oct 15 02:34:12 AM UTC 24 |
| Finished | Oct 15 02:34:33 AM UTC 24 |
| Peak memory | 250748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =70951039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t hroughput_w_partial_write.70951039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3069241192 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 20655275742 ps |
| CPU time | 1092.03 seconds |
| Started | Oct 15 02:36:58 AM UTC 24 |
| Finished | Oct 15 02:55:22 AM UTC 24 |
| Peak memory | 388040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069241192 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_duri ng_key_req.3069241192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.2815825223 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 18225742 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 02:38:26 AM UTC 24 |
| Finished | Oct 15 02:38:28 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815825223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2815825223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.2890554712 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 31555436472 ps |
| CPU time | 557.2 seconds |
| Started | Oct 15 02:36:01 AM UTC 24 |
| Finished | Oct 15 02:45:25 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890554712 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.2890554712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.1057877948 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 13871955514 ps |
| CPU time | 234.96 seconds |
| Started | Oct 15 02:37:13 AM UTC 24 |
| Finished | Oct 15 02:41:11 AM UTC 24 |
| Peak memory | 375884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057877948 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.1057877948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2521570289 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 12832146133 ps |
| CPU time | 130.49 seconds |
| Started | Oct 15 02:36:48 AM UTC 24 |
| Finished | Oct 15 02:39:01 AM UTC 24 |
| Peak memory | 221424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521570289 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.2521570289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.4237542962 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3001526368 ps |
| CPU time | 102.31 seconds |
| Started | Oct 15 02:36:24 AM UTC 24 |
| Finished | Oct 15 02:38:09 AM UTC 24 |
| Peak memory | 379780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4237542962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ max_throughput.4237542962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.4004424583 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2390634157 ps |
| CPU time | 87.28 seconds |
| Started | Oct 15 02:37:56 AM UTC 24 |
| Finished | Oct 15 02:39:25 AM UTC 24 |
| Peak memory | 228292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004424583 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.4004424583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.3240328624 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 2060194720 ps |
| CPU time | 159.03 seconds |
| Started | Oct 15 02:37:54 AM UTC 24 |
| Finished | Oct 15 02:40:36 AM UTC 24 |
| Peak memory | 221328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240328624 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.3240328624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1407945807 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 53069877195 ps |
| CPU time | 693.56 seconds |
| Started | Oct 15 02:35:34 AM UTC 24 |
| Finished | Oct 15 02:47:15 AM UTC 24 |
| Peak memory | 388032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407945807 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.1407945807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1451140199 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 870105949 ps |
| CPU time | 15.8 seconds |
| Started | Oct 15 02:36:06 AM UTC 24 |
| Finished | Oct 15 02:36:23 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451140199 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.1451140199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2484378583 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 52611730932 ps |
| CPU time | 324.38 seconds |
| Started | Oct 15 02:36:18 AM UTC 24 |
| Finished | Oct 15 02:41:47 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484378583 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_a ccess_b2b.2484378583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.276970828 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 3044544620 ps |
| CPU time | 5.79 seconds |
| Started | Oct 15 02:37:46 AM UTC 24 |
| Finished | Oct 15 02:37:53 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276970828 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.276970828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_readback_err.2873056098 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2173069106 ps |
| CPU time | 9.14 seconds |
| Started | Oct 15 02:38:09 AM UTC 24 |
| Finished | Oct 15 02:38:20 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873056098 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_readback_err.2873056098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.45869298 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 36328416321 ps |
| CPU time | 743.18 seconds |
| Started | Oct 15 02:37:14 AM UTC 24 |
| Finished | Oct 15 02:49:46 AM UTC 24 |
| Peak memory | 388164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45869298 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.45869298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.3297160408 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 789812723 ps |
| CPU time | 32.91 seconds |
| Started | Oct 15 02:35:26 AM UTC 24 |
| Finished | Oct 15 02:36:01 AM UTC 24 |
| Peak memory | 314160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297160408 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3297160408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1120440196 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 86435190739 ps |
| CPU time | 2390.51 seconds |
| Started | Oct 15 02:38:21 AM UTC 24 |
| Finished | Oct 15 03:18:36 AM UTC 24 |
| Peak memory | 388040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11204401 96 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_a ll.1120440196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2723402859 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7871090020 ps |
| CPU time | 47.01 seconds |
| Started | Oct 15 02:38:16 AM UTC 24 |
| Finished | Oct 15 02:39:04 AM UTC 24 |
| Peak memory | 221616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723402859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2723402859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1363304999 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 17762575350 ps |
| CPU time | 351.99 seconds |
| Started | Oct 15 02:36:02 AM UTC 24 |
| Finished | Oct 15 02:41:59 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363304999 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.1363304999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1062947451 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2930404749 ps |
| CPU time | 21.72 seconds |
| Started | Oct 15 02:36:33 AM UTC 24 |
| Finished | Oct 15 02:36:56 AM UTC 24 |
| Peak memory | 265096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1062947451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl _throughput_w_partial_write.1062947451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3586746961 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 12672570679 ps |
| CPU time | 624.87 seconds |
| Started | Oct 15 02:39:26 AM UTC 24 |
| Finished | Oct 15 02:49:59 AM UTC 24 |
| Peak memory | 383876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586746961 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_duri ng_key_req.3586746961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1179493683 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 31056231 ps |
| CPU time | 1.03 seconds |
| Started | Oct 15 02:40:22 AM UTC 24 |
| Finished | Oct 15 02:40:24 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179493683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1179493683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.3170091765 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 152468318409 ps |
| CPU time | 2627.66 seconds |
| Started | Oct 15 02:39:02 AM UTC 24 |
| Finished | Oct 15 03:23:19 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170091765 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.3170091765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1880769755 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 6668219698 ps |
| CPU time | 438.14 seconds |
| Started | Oct 15 02:39:35 AM UTC 24 |
| Finished | Oct 15 02:46:59 AM UTC 24 |
| Peak memory | 385992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880769755 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.1880769755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.36438335 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 16993494744 ps |
| CPU time | 44.82 seconds |
| Started | Oct 15 02:39:26 AM UTC 24 |
| Finished | Oct 15 02:40:12 AM UTC 24 |
| Peak memory | 221416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36438335 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.36438335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.699064794 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 1635249914 ps |
| CPU time | 25.53 seconds |
| Started | Oct 15 02:39:22 AM UTC 24 |
| Finished | Oct 15 02:39:48 AM UTC 24 |
| Peak memory | 299912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 699064794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_m ax_throughput.699064794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3174597054 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 9111622590 ps |
| CPU time | 146.77 seconds |
| Started | Oct 15 02:40:07 AM UTC 24 |
| Finished | Oct 15 02:42:36 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174597054 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.3174597054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3769878538 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 21086364012 ps |
| CPU time | 405.81 seconds |
| Started | Oct 15 02:39:57 AM UTC 24 |
| Finished | Oct 15 02:46:49 AM UTC 24 |
| Peak memory | 221484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769878538 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.3769878538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2491719500 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 43508795753 ps |
| CPU time | 367.35 seconds |
| Started | Oct 15 02:39:02 AM UTC 24 |
| Finished | Oct 15 02:45:14 AM UTC 24 |
| Peak memory | 361416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491719500 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.2491719500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1465444892 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 850039477 ps |
| CPU time | 7.96 seconds |
| Started | Oct 15 02:39:06 AM UTC 24 |
| Finished | Oct 15 02:39:15 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465444892 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.1465444892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1769622165 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 177321786778 ps |
| CPU time | 691.48 seconds |
| Started | Oct 15 02:39:17 AM UTC 24 |
| Finished | Oct 15 02:50:56 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769622165 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_a ccess_b2b.1769622165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3692221638 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1019359136 ps |
| CPU time | 5.6 seconds |
| Started | Oct 15 02:39:49 AM UTC 24 |
| Finished | Oct 15 02:39:56 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692221638 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3692221638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_readback_err.613471737 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3166071467 ps |
| CPU time | 10.36 seconds |
| Started | Oct 15 02:40:11 AM UTC 24 |
| Finished | Oct 15 02:40:22 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613471737 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_readback_err.613471737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.3258924214 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 21286678651 ps |
| CPU time | 968.42 seconds |
| Started | Oct 15 02:39:37 AM UTC 24 |
| Finished | Oct 15 02:55:56 AM UTC 24 |
| Peak memory | 385984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258924214 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3258924214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1298680140 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 490101743 ps |
| CPU time | 63.33 seconds |
| Started | Oct 15 02:38:29 AM UTC 24 |
| Finished | Oct 15 02:39:34 AM UTC 24 |
| Peak memory | 357312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298680140 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1298680140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3516122899 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 34518486977 ps |
| CPU time | 1211.41 seconds |
| Started | Oct 15 02:40:18 AM UTC 24 |
| Finished | Oct 15 03:00:44 AM UTC 24 |
| Peak memory | 383876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35161228 99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_a ll.3516122899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.203747733 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 5787052004 ps |
| CPU time | 41 seconds |
| Started | Oct 15 02:40:13 AM UTC 24 |
| Finished | Oct 15 02:40:55 AM UTC 24 |
| Peak memory | 221540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203747733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.203747733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3261711055 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 9037369875 ps |
| CPU time | 361.26 seconds |
| Started | Oct 15 02:39:05 AM UTC 24 |
| Finished | Oct 15 02:45:11 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261711055 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.3261711055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3088476181 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1225458650 ps |
| CPU time | 50.44 seconds |
| Started | Oct 15 02:39:25 AM UTC 24 |
| Finished | Oct 15 02:40:17 AM UTC 24 |
| Peak memory | 340872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3088476181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _throughput_w_partial_write.3088476181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.882051941 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2100094736 ps |
| CPU time | 37.28 seconds |
| Started | Oct 15 02:42:01 AM UTC 24 |
| Finished | Oct 15 02:42:40 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882051941 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_durin g_key_req.882051941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.4143310119 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 14333291 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 02:42:54 AM UTC 24 |
| Finished | Oct 15 02:42:56 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143310119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.4143310119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.3088201694 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 311462011544 ps |
| CPU time | 1531.51 seconds |
| Started | Oct 15 02:40:37 AM UTC 24 |
| Finished | Oct 15 03:06:26 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088201694 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.3088201694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.2921734827 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 93402925539 ps |
| CPU time | 633.65 seconds |
| Started | Oct 15 02:42:08 AM UTC 24 |
| Finished | Oct 15 02:52:49 AM UTC 24 |
| Peak memory | 369608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921734827 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.2921734827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.4166725472 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 29198584817 ps |
| CPU time | 52.81 seconds |
| Started | Oct 15 02:41:59 AM UTC 24 |
| Finished | Oct 15 02:42:54 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166725472 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.4166725472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3195415715 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2486348264 ps |
| CPU time | 25.13 seconds |
| Started | Oct 15 02:41:34 AM UTC 24 |
| Finished | Oct 15 02:42:01 AM UTC 24 |
| Peak memory | 260984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3195415715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ max_throughput.3195415715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1210875578 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 4713549970 ps |
| CPU time | 106.94 seconds |
| Started | Oct 15 02:42:37 AM UTC 24 |
| Finished | Oct 15 02:44:27 AM UTC 24 |
| Peak memory | 221452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210875578 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.1210875578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1738491977 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 13845485453 ps |
| CPU time | 161.66 seconds |
| Started | Oct 15 02:42:35 AM UTC 24 |
| Finished | Oct 15 02:45:19 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738491977 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.1738491977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2928168197 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 12740668607 ps |
| CPU time | 547.54 seconds |
| Started | Oct 15 02:40:25 AM UTC 24 |
| Finished | Oct 15 02:49:40 AM UTC 24 |
| Peak memory | 381828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928168197 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.2928168197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1232424079 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 5505101833 ps |
| CPU time | 20.22 seconds |
| Started | Oct 15 02:41:12 AM UTC 24 |
| Finished | Oct 15 02:41:33 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232424079 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.1232424079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.583024053 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 18415769774 ps |
| CPU time | 508.97 seconds |
| Started | Oct 15 02:41:27 AM UTC 24 |
| Finished | Oct 15 02:50:03 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583024053 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_ac cess_b2b.583024053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3423870148 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 1460262055 ps |
| CPU time | 6.18 seconds |
| Started | Oct 15 02:42:27 AM UTC 24 |
| Finished | Oct 15 02:42:34 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423870148 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3423870148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_readback_err.1727923215 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2747854933 ps |
| CPU time | 10.7 seconds |
| Started | Oct 15 02:42:41 AM UTC 24 |
| Finished | Oct 15 02:42:53 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727923215 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_readback_err.1727923215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.589898242 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 11458922541 ps |
| CPU time | 875.75 seconds |
| Started | Oct 15 02:42:10 AM UTC 24 |
| Finished | Oct 15 02:56:55 AM UTC 24 |
| Peak memory | 379836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589898242 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.589898242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.1488323638 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3097492693 ps |
| CPU time | 60.82 seconds |
| Started | Oct 15 02:40:23 AM UTC 24 |
| Finished | Oct 15 02:41:26 AM UTC 24 |
| Peak memory | 334792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488323638 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1488323638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1829275159 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 1432231295661 ps |
| CPU time | 6444.97 seconds |
| Started | Oct 15 02:42:53 AM UTC 24 |
| Finished | Oct 15 04:31:28 AM UTC 24 |
| Peak memory | 385424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18292751 59 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_a ll.1829275159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2979654032 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2125664004 ps |
| CPU time | 110.14 seconds |
| Started | Oct 15 02:42:50 AM UTC 24 |
| Finished | Oct 15 02:44:43 AM UTC 24 |
| Peak memory | 223604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979654032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2979654032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2929608109 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 5283042125 ps |
| CPU time | 342.39 seconds |
| Started | Oct 15 02:40:57 AM UTC 24 |
| Finished | Oct 15 02:46:44 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929608109 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.2929608109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3167967009 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 3067681266 ps |
| CPU time | 35.86 seconds |
| Started | Oct 15 02:41:48 AM UTC 24 |
| Finished | Oct 15 02:42:25 AM UTC 24 |
| Peak memory | 310216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3167967009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl _throughput_w_partial_write.3167967009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1906088815 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 22408623404 ps |
| CPU time | 885.61 seconds |
| Started | Oct 15 02:45:20 AM UTC 24 |
| Finished | Oct 15 03:00:17 AM UTC 24 |
| Peak memory | 382004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906088815 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_duri ng_key_req.1906088815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3997550173 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 16762115 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 02:47:00 AM UTC 24 |
| Finished | Oct 15 02:47:02 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997550173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.3997550173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1593120108 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 383721212560 ps |
| CPU time | 2418.48 seconds |
| Started | Oct 15 02:43:56 AM UTC 24 |
| Finished | Oct 15 03:24:41 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593120108 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.1593120108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.2400752670 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 13041579335 ps |
| CPU time | 547.13 seconds |
| Started | Oct 15 02:45:26 AM UTC 24 |
| Finished | Oct 15 02:54:39 AM UTC 24 |
| Peak memory | 379984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400752670 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.2400752670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.708229663 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 11933769936 ps |
| CPU time | 114.52 seconds |
| Started | Oct 15 02:45:15 AM UTC 24 |
| Finished | Oct 15 02:47:11 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708229663 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.708229663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.4238992601 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 1562253377 ps |
| CPU time | 93.69 seconds |
| Started | Oct 15 02:44:56 AM UTC 24 |
| Finished | Oct 15 02:46:32 AM UTC 24 |
| Peak memory | 377868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4238992601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ max_throughput.4238992601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3702589724 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 10283137932 ps |
| CPU time | 72.03 seconds |
| Started | Oct 15 02:46:41 AM UTC 24 |
| Finished | Oct 15 02:47:55 AM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702589724 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.3702589724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2922244289 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2039532691 ps |
| CPU time | 163.85 seconds |
| Started | Oct 15 02:46:39 AM UTC 24 |
| Finished | Oct 15 02:49:26 AM UTC 24 |
| Peak memory | 221556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922244289 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.2922244289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.226672980 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 214118397209 ps |
| CPU time | 1004.08 seconds |
| Started | Oct 15 02:43:42 AM UTC 24 |
| Finished | Oct 15 03:00:37 AM UTC 24 |
| Peak memory | 383936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226672980 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.226672980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1706368182 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 906825464 ps |
| CPU time | 26.95 seconds |
| Started | Oct 15 02:44:27 AM UTC 24 |
| Finished | Oct 15 02:44:55 AM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706368182 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.1706368182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.3037014714 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 9375987564 ps |
| CPU time | 283.84 seconds |
| Started | Oct 15 02:44:43 AM UTC 24 |
| Finished | Oct 15 02:49:32 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037014714 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_a ccess_b2b.3037014714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1070785415 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 4801412987 ps |
| CPU time | 5.94 seconds |
| Started | Oct 15 02:46:33 AM UTC 24 |
| Finished | Oct 15 02:46:40 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070785415 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1070785415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_readback_err.4181399356 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1359304365 ps |
| CPU time | 10.47 seconds |
| Started | Oct 15 02:46:44 AM UTC 24 |
| Finished | Oct 15 02:46:56 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181399356 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_readback_err.4181399356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.2743729668 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 71506835074 ps |
| CPU time | 735.91 seconds |
| Started | Oct 15 02:46:22 AM UTC 24 |
| Finished | Oct 15 02:58:46 AM UTC 24 |
| Peak memory | 388096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743729668 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2743729668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.1796654335 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 1651205254 ps |
| CPU time | 55.4 seconds |
| Started | Oct 15 02:42:57 AM UTC 24 |
| Finished | Oct 15 02:43:55 AM UTC 24 |
| Peak memory | 324480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796654335 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1796654335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1853469322 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 306345718919 ps |
| CPU time | 4194.94 seconds |
| Started | Oct 15 02:46:57 AM UTC 24 |
| Finished | Oct 15 03:57:37 AM UTC 24 |
| Peak memory | 389380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18534693 22 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_a ll.1853469322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3143600079 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 4381363303 ps |
| CPU time | 34.76 seconds |
| Started | Oct 15 02:46:50 AM UTC 24 |
| Finished | Oct 15 02:47:26 AM UTC 24 |
| Peak memory | 221616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143600079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3143600079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.4112150020 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 23007544707 ps |
| CPU time | 290.26 seconds |
| Started | Oct 15 02:43:57 AM UTC 24 |
| Finished | Oct 15 02:48:51 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112150020 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.4112150020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.1292785613 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1602199081 ps |
| CPU time | 84.4 seconds |
| Started | Oct 15 02:45:13 AM UTC 24 |
| Finished | Oct 15 02:46:39 AM UTC 24 |
| Peak memory | 357176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1292785613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _throughput_w_partial_write.1292785613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.203805027 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 72297570865 ps |
| CPU time | 495.51 seconds |
| Started | Oct 15 02:48:09 AM UTC 24 |
| Finished | Oct 15 02:56:31 AM UTC 24 |
| Peak memory | 383932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203805027 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_durin g_key_req.203805027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.3786721270 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 43514348 ps |
| CPU time | 1 seconds |
| Started | Oct 15 02:49:32 AM UTC 24 |
| Finished | Oct 15 02:49:34 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786721270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.3786721270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.1968843018 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 276847694661 ps |
| CPU time | 1329.21 seconds |
| Started | Oct 15 02:47:16 AM UTC 24 |
| Finished | Oct 15 03:09:41 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968843018 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.1968843018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.3650362409 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 21078157990 ps |
| CPU time | 665.67 seconds |
| Started | Oct 15 02:48:13 AM UTC 24 |
| Finished | Oct 15 02:59:27 AM UTC 24 |
| Peak memory | 385924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650362409 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.3650362409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.689120453 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 12143724701 ps |
| CPU time | 42.57 seconds |
| Started | Oct 15 02:48:00 AM UTC 24 |
| Finished | Oct 15 02:48:44 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689120453 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.689120453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.922883135 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1500077705 ps |
| CPU time | 19.93 seconds |
| Started | Oct 15 02:47:51 AM UTC 24 |
| Finished | Oct 15 02:48:12 AM UTC 24 |
| Peak memory | 273352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 922883135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_m ax_throughput.922883135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.264459404 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 11001246226 ps |
| CPU time | 108.19 seconds |
| Started | Oct 15 02:48:52 AM UTC 24 |
| Finished | Oct 15 02:50:42 AM UTC 24 |
| Peak memory | 221536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264459404 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.264459404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.4012071535 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 7295915470 ps |
| CPU time | 175 seconds |
| Started | Oct 15 02:48:45 AM UTC 24 |
| Finished | Oct 15 02:51:43 AM UTC 24 |
| Peak memory | 221556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012071535 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.4012071535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.1140700227 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 1719559827 ps |
| CPU time | 89.36 seconds |
| Started | Oct 15 02:47:12 AM UTC 24 |
| Finished | Oct 15 02:48:43 AM UTC 24 |
| Peak memory | 345088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140700227 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.1140700227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3475341798 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 1469875862 ps |
| CPU time | 12.27 seconds |
| Started | Oct 15 02:47:36 AM UTC 24 |
| Finished | Oct 15 02:47:50 AM UTC 24 |
| Peak memory | 217452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475341798 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.3475341798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1872723587 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 34337727984 ps |
| CPU time | 480.69 seconds |
| Started | Oct 15 02:47:39 AM UTC 24 |
| Finished | Oct 15 02:55:46 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872723587 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_a ccess_b2b.1872723587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.1702117709 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 350475237 ps |
| CPU time | 5.38 seconds |
| Started | Oct 15 02:48:44 AM UTC 24 |
| Finished | Oct 15 02:48:51 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702117709 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1702117709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_readback_err.1735182225 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 690339586 ps |
| CPU time | 10.78 seconds |
| Started | Oct 15 02:48:52 AM UTC 24 |
| Finished | Oct 15 02:49:04 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735182225 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_readback_err.1735182225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3108443023 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 12700446689 ps |
| CPU time | 820.24 seconds |
| Started | Oct 15 02:48:33 AM UTC 24 |
| Finished | Oct 15 03:02:23 AM UTC 24 |
| Peak memory | 384072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108443023 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3108443023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.432452251 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4980287127 ps |
| CPU time | 87.91 seconds |
| Started | Oct 15 02:47:03 AM UTC 24 |
| Finished | Oct 15 02:48:33 AM UTC 24 |
| Peak memory | 371780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432452251 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.432452251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.2981676180 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 509760917497 ps |
| CPU time | 4397.31 seconds |
| Started | Oct 15 02:49:27 AM UTC 24 |
| Finished | Oct 15 04:03:32 AM UTC 24 |
| Peak memory | 391620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29816761 80 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_a ll.2981676180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2412043922 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2464150080 ps |
| CPU time | 120.77 seconds |
| Started | Oct 15 02:49:05 AM UTC 24 |
| Finished | Oct 15 02:51:08 AM UTC 24 |
| Peak memory | 341064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412043922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2412043922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.555315375 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 37381700283 ps |
| CPU time | 365.12 seconds |
| Started | Oct 15 02:47:26 AM UTC 24 |
| Finished | Oct 15 02:53:37 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555315375 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.555315375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3476728771 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1234725680 ps |
| CPU time | 10.66 seconds |
| Started | Oct 15 02:47:56 AM UTC 24 |
| Finished | Oct 15 02:48:08 AM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3476728771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _throughput_w_partial_write.3476728771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.490710793 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 13821529086 ps |
| CPU time | 736.68 seconds |
| Started | Oct 15 02:51:02 AM UTC 24 |
| Finished | Oct 15 03:03:27 AM UTC 24 |
| Peak memory | 381884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490710793 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_durin g_key_req.490710793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1004352348 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 15106014 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 02:52:50 AM UTC 24 |
| Finished | Oct 15 02:52:52 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004352348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1004352348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.1043224180 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 148265870467 ps |
| CPU time | 819.15 seconds |
| Started | Oct 15 02:49:47 AM UTC 24 |
| Finished | Oct 15 03:03:36 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043224180 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.1043224180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.2044290989 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 48193783011 ps |
| CPU time | 641.9 seconds |
| Started | Oct 15 02:51:09 AM UTC 24 |
| Finished | Oct 15 03:01:58 AM UTC 24 |
| Peak memory | 383872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044290989 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.2044290989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.4007108317 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 22767116966 ps |
| CPU time | 131.54 seconds |
| Started | Oct 15 02:50:57 AM UTC 24 |
| Finished | Oct 15 02:53:11 AM UTC 24 |
| Peak memory | 221424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007108317 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.4007108317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.3147708597 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2874373910 ps |
| CPU time | 17.22 seconds |
| Started | Oct 15 02:50:43 AM UTC 24 |
| Finished | Oct 15 02:51:01 AM UTC 24 |
| Peak memory | 248768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3147708597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ max_throughput.3147708597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3597246107 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 1417995097 ps |
| CPU time | 100.52 seconds |
| Started | Oct 15 02:51:47 AM UTC 24 |
| Finished | Oct 15 02:53:29 AM UTC 24 |
| Peak memory | 221448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597246107 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.3597246107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.586078035 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 10792510772 ps |
| CPU time | 208.09 seconds |
| Started | Oct 15 02:51:45 AM UTC 24 |
| Finished | Oct 15 02:55:16 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586078035 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.586078035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.560329888 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 52779802551 ps |
| CPU time | 1597.09 seconds |
| Started | Oct 15 02:49:40 AM UTC 24 |
| Finished | Oct 15 03:16:35 AM UTC 24 |
| Peak memory | 388164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560329888 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.560329888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2608797381 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 808098841 ps |
| CPU time | 43.76 seconds |
| Started | Oct 15 02:50:04 AM UTC 24 |
| Finished | Oct 15 02:50:49 AM UTC 24 |
| Peak memory | 295940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608797381 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.2608797381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3106320944 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 20316786043 ps |
| CPU time | 479.97 seconds |
| Started | Oct 15 02:50:19 AM UTC 24 |
| Finished | Oct 15 02:58:25 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106320944 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_a ccess_b2b.3106320944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.4030119208 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 5589775373 ps |
| CPU time | 5.57 seconds |
| Started | Oct 15 02:51:39 AM UTC 24 |
| Finished | Oct 15 02:51:46 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030119208 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.4030119208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_readback_err.2529873172 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 667475383 ps |
| CPU time | 8.21 seconds |
| Started | Oct 15 02:52:22 AM UTC 24 |
| Finished | Oct 15 02:52:31 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529873172 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_readback_err.2529873172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.2202441235 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 18136361747 ps |
| CPU time | 1688.14 seconds |
| Started | Oct 15 02:51:29 AM UTC 24 |
| Finished | Oct 15 03:19:55 AM UTC 24 |
| Peak memory | 390212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202441235 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2202441235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.776733816 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2888709150 ps |
| CPU time | 40.95 seconds |
| Started | Oct 15 02:49:35 AM UTC 24 |
| Finished | Oct 15 02:50:18 AM UTC 24 |
| Peak memory | 293816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776733816 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.776733816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1915791062 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 223035425184 ps |
| CPU time | 5911.18 seconds |
| Started | Oct 15 02:52:50 AM UTC 24 |
| Finished | Oct 15 04:32:26 AM UTC 24 |
| Peak memory | 391628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19157910 62 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_a ll.1915791062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1345983635 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 2714103810 ps |
| CPU time | 58.3 seconds |
| Started | Oct 15 02:52:32 AM UTC 24 |
| Finished | Oct 15 02:53:32 AM UTC 24 |
| Peak memory | 221620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345983635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1345983635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3255373985 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 12629689698 ps |
| CPU time | 296.55 seconds |
| Started | Oct 15 02:49:59 AM UTC 24 |
| Finished | Oct 15 02:55:00 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255373985 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.3255373985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.387218212 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 741864038 ps |
| CPU time | 37.46 seconds |
| Started | Oct 15 02:50:50 AM UTC 24 |
| Finished | Oct 15 02:51:29 AM UTC 24 |
| Peak memory | 299916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =387218212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ throughput_w_partial_write.387218212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.261981392 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 29390213450 ps |
| CPU time | 682.18 seconds |
| Started | Oct 15 02:54:49 AM UTC 24 |
| Finished | Oct 15 03:06:19 AM UTC 24 |
| Peak memory | 385980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261981392 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_durin g_key_req.261981392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3116711120 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 17801605 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 02:56:17 AM UTC 24 |
| Finished | Oct 15 02:56:19 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116711120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3116711120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.2953952022 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 374257332206 ps |
| CPU time | 1720.81 seconds |
| Started | Oct 15 02:53:31 AM UTC 24 |
| Finished | Oct 15 03:22:32 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953952022 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.2953952022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.3220290434 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 107351939745 ps |
| CPU time | 1172.44 seconds |
| Started | Oct 15 02:55:01 AM UTC 24 |
| Finished | Oct 15 03:14:46 AM UTC 24 |
| Peak memory | 388032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220290434 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.3220290434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2224906121 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 34987249467 ps |
| CPU time | 93.05 seconds |
| Started | Oct 15 02:54:40 AM UTC 24 |
| Finished | Oct 15 02:56:16 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224906121 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.2224906121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.283135934 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 1005294203 ps |
| CPU time | 94.07 seconds |
| Started | Oct 15 02:54:17 AM UTC 24 |
| Finished | Oct 15 02:55:53 AM UTC 24 |
| Peak memory | 365452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 283135934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_m ax_throughput.283135934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2373932066 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2897482739 ps |
| CPU time | 91.54 seconds |
| Started | Oct 15 02:55:47 AM UTC 24 |
| Finished | Oct 15 02:57:21 AM UTC 24 |
| Peak memory | 221648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373932066 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.2373932066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3088743870 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 15180452202 ps |
| CPU time | 171.15 seconds |
| Started | Oct 15 02:55:32 AM UTC 24 |
| Finished | Oct 15 02:58:26 AM UTC 24 |
| Peak memory | 221416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088743870 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.3088743870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3369684058 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 31402236085 ps |
| CPU time | 716.57 seconds |
| Started | Oct 15 02:53:11 AM UTC 24 |
| Finished | Oct 15 03:05:16 AM UTC 24 |
| Peak memory | 383864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369684058 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.3369684058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.3619645224 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 2725577377 ps |
| CPU time | 31.09 seconds |
| Started | Oct 15 02:53:38 AM UTC 24 |
| Finished | Oct 15 02:54:10 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619645224 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.3619645224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1208519115 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 8940590001 ps |
| CPU time | 254.03 seconds |
| Started | Oct 15 02:54:11 AM UTC 24 |
| Finished | Oct 15 02:58:29 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208519115 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_a ccess_b2b.1208519115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.3156530520 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 1403490158 ps |
| CPU time | 6.71 seconds |
| Started | Oct 15 02:55:23 AM UTC 24 |
| Finished | Oct 15 02:55:31 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156530520 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3156530520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_readback_err.4196503417 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 1901349347 ps |
| CPU time | 10.69 seconds |
| Started | Oct 15 02:55:54 AM UTC 24 |
| Finished | Oct 15 02:56:07 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196503417 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_readback_err.4196503417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.2198680511 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 8869137300 ps |
| CPU time | 368.48 seconds |
| Started | Oct 15 02:55:17 AM UTC 24 |
| Finished | Oct 15 03:01:30 AM UTC 24 |
| Peak memory | 377720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198680511 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2198680511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.773114803 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 441893091 ps |
| CPU time | 80.92 seconds |
| Started | Oct 15 02:52:53 AM UTC 24 |
| Finished | Oct 15 02:54:16 AM UTC 24 |
| Peak memory | 363396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773114803 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.773114803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3536070228 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 283601168775 ps |
| CPU time | 5899.6 seconds |
| Started | Oct 15 02:56:08 AM UTC 24 |
| Finished | Oct 15 04:35:30 AM UTC 24 |
| Peak memory | 389516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35360702 28 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_a ll.3536070228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1942202168 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 3229577308 ps |
| CPU time | 19.76 seconds |
| Started | Oct 15 02:55:57 AM UTC 24 |
| Finished | Oct 15 02:56:19 AM UTC 24 |
| Peak memory | 221524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942202168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1942202168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.698652946 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 3488957719 ps |
| CPU time | 175.81 seconds |
| Started | Oct 15 02:53:33 AM UTC 24 |
| Finished | Oct 15 02:56:32 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698652946 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.698652946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.70208536 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1322486867 ps |
| CPU time | 22.99 seconds |
| Started | Oct 15 02:54:23 AM UTC 24 |
| Finished | Oct 15 02:54:48 AM UTC 24 |
| Peak memory | 267056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =70208536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_t hroughput_w_partial_write.70208536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3170201171 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 61822596199 ps |
| CPU time | 796.71 seconds |
| Started | Oct 15 02:57:38 AM UTC 24 |
| Finished | Oct 15 03:11:04 AM UTC 24 |
| Peak memory | 388176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170201171 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_duri ng_key_req.3170201171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2076086863 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 21665163 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 02:58:37 AM UTC 24 |
| Finished | Oct 15 02:58:39 AM UTC 24 |
| Peak memory | 209932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076086863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2076086863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.726197348 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 498420513854 ps |
| CPU time | 2588.95 seconds |
| Started | Oct 15 02:56:32 AM UTC 24 |
| Finished | Oct 15 03:40:11 AM UTC 24 |
| Peak memory | 212596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726197348 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.726197348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1557153121 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 125438717960 ps |
| CPU time | 1376.29 seconds |
| Started | Oct 15 02:57:40 AM UTC 24 |
| Finished | Oct 15 03:20:52 AM UTC 24 |
| Peak memory | 388044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557153121 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.1557153121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.439930222 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 8123735288 ps |
| CPU time | 60.56 seconds |
| Started | Oct 15 02:57:34 AM UTC 24 |
| Finished | Oct 15 02:58:36 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439930222 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.439930222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3166821577 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 780999077 ps |
| CPU time | 64.9 seconds |
| Started | Oct 15 02:56:56 AM UTC 24 |
| Finished | Oct 15 02:58:03 AM UTC 24 |
| Peak memory | 334844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3166821577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ max_throughput.3166821577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1846829043 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 9830330884 ps |
| CPU time | 86.5 seconds |
| Started | Oct 15 02:58:25 AM UTC 24 |
| Finished | Oct 15 02:59:54 AM UTC 24 |
| Peak memory | 228296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846829043 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.1846829043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1123816872 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 6925096209 ps |
| CPU time | 170.49 seconds |
| Started | Oct 15 02:58:12 AM UTC 24 |
| Finished | Oct 15 03:01:05 AM UTC 24 |
| Peak memory | 221392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123816872 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.1123816872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.204809735 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 25773013785 ps |
| CPU time | 1181.1 seconds |
| Started | Oct 15 02:56:20 AM UTC 24 |
| Finished | Oct 15 03:16:13 AM UTC 24 |
| Peak memory | 382024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204809735 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.204809735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3923583044 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 3423354940 ps |
| CPU time | 54.87 seconds |
| Started | Oct 15 02:56:42 AM UTC 24 |
| Finished | Oct 15 02:57:39 AM UTC 24 |
| Peak memory | 320584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923583044 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.3923583044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3870384291 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 26026369895 ps |
| CPU time | 657.39 seconds |
| Started | Oct 15 02:56:49 AM UTC 24 |
| Finished | Oct 15 03:07:55 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870384291 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_a ccess_b2b.3870384291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.268693530 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 3049973477 ps |
| CPU time | 6.5 seconds |
| Started | Oct 15 02:58:04 AM UTC 24 |
| Finished | Oct 15 02:58:12 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268693530 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.268693530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_readback_err.685004793 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2824792072 ps |
| CPU time | 7.83 seconds |
| Started | Oct 15 02:58:27 AM UTC 24 |
| Finished | Oct 15 02:58:37 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685004793 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_readback_err.685004793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.539123066 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 17089091487 ps |
| CPU time | 776.64 seconds |
| Started | Oct 15 02:57:55 AM UTC 24 |
| Finished | Oct 15 03:11:00 AM UTC 24 |
| Peak memory | 383932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539123066 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.539123066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.3632125699 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 1059991806 ps |
| CPU time | 71.02 seconds |
| Started | Oct 15 02:56:20 AM UTC 24 |
| Finished | Oct 15 02:57:32 AM UTC 24 |
| Peak memory | 373444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632125699 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3632125699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3004995150 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 8704339084 ps |
| CPU time | 974.04 seconds |
| Started | Oct 15 02:58:31 AM UTC 24 |
| Finished | Oct 15 03:14:56 AM UTC 24 |
| Peak memory | 383940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30049951 50 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_a ll.3004995150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3372911484 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 5417253228 ps |
| CPU time | 152.22 seconds |
| Started | Oct 15 02:58:30 AM UTC 24 |
| Finished | Oct 15 03:01:06 AM UTC 24 |
| Peak memory | 228376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372911484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3372911484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.1509681017 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 8718493404 ps |
| CPU time | 216.31 seconds |
| Started | Oct 15 02:56:32 AM UTC 24 |
| Finished | Oct 15 03:00:12 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509681017 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.1509681017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.2271186641 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 3240214120 ps |
| CPU time | 86.47 seconds |
| Started | Oct 15 02:57:21 AM UTC 24 |
| Finished | Oct 15 02:58:50 AM UTC 24 |
| Peak memory | 373828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2271186641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl _throughput_w_partial_write.2271186641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.4070536253 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8511314212 ps |
| CPU time | 493.03 seconds |
| Started | Oct 15 01:13:32 AM UTC 24 |
| Finished | Oct 15 01:21:50 AM UTC 24 |
| Peak memory | 387968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070536253 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_durin g_key_req.4070536253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3732207641 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 35836754 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 01:14:31 AM UTC 24 |
| Finished | Oct 15 01:14:33 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732207641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3732207641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.1882931405 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 43331621499 ps |
| CPU time | 1286.62 seconds |
| Started | Oct 15 01:13:15 AM UTC 24 |
| Finished | Oct 15 01:34:58 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882931405 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.1882931405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3914198858 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 6338206562 ps |
| CPU time | 586.44 seconds |
| Started | Oct 15 01:13:35 AM UTC 24 |
| Finished | Oct 15 01:23:28 AM UTC 24 |
| Peak memory | 379916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914198858 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.3914198858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1151009207 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1613617794 ps |
| CPU time | 26.36 seconds |
| Started | Oct 15 01:13:22 AM UTC 24 |
| Finished | Oct 15 01:13:49 AM UTC 24 |
| Peak memory | 279356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1151009207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_m ax_throughput.1151009207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.4042844307 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3990365723 ps |
| CPU time | 92.15 seconds |
| Started | Oct 15 01:13:54 AM UTC 24 |
| Finished | Oct 15 01:15:29 AM UTC 24 |
| Peak memory | 221584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042844307 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.4042844307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1336331881 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 27740420669 ps |
| CPU time | 190.91 seconds |
| Started | Oct 15 01:13:53 AM UTC 24 |
| Finished | Oct 15 01:17:07 AM UTC 24 |
| Peak memory | 221560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336331881 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.1336331881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.329442044 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 254907506709 ps |
| CPU time | 1564.27 seconds |
| Started | Oct 15 01:13:14 AM UTC 24 |
| Finished | Oct 15 01:39:34 AM UTC 24 |
| Peak memory | 388160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329442044 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.329442044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.4257416566 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2248939751 ps |
| CPU time | 6 seconds |
| Started | Oct 15 01:13:16 AM UTC 24 |
| Finished | Oct 15 01:13:24 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257416566 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.4257416566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2427804298 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 22009506037 ps |
| CPU time | 404.71 seconds |
| Started | Oct 15 01:13:16 AM UTC 24 |
| Finished | Oct 15 01:20:07 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427804298 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_ac cess_b2b.2427804298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1217542011 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 694519428 ps |
| CPU time | 4.68 seconds |
| Started | Oct 15 01:13:50 AM UTC 24 |
| Finished | Oct 15 01:13:56 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217542011 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1217542011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3399294981 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 13565138440 ps |
| CPU time | 878.35 seconds |
| Started | Oct 15 01:13:48 AM UTC 24 |
| Finished | Oct 15 01:28:36 AM UTC 24 |
| Peak memory | 388156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399294981 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3399294981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.1351766200 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1366731083 ps |
| CPU time | 78.46 seconds |
| Started | Oct 15 01:13:10 AM UTC 24 |
| Finished | Oct 15 01:14:30 AM UTC 24 |
| Peak memory | 375684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351766200 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1351766200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.461189124 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 514002597573 ps |
| CPU time | 3109.14 seconds |
| Started | Oct 15 01:14:07 AM UTC 24 |
| Finished | Oct 15 02:06:31 AM UTC 24 |
| Peak memory | 223532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46118912 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.461189124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2854665830 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4708935375 ps |
| CPU time | 69.29 seconds |
| Started | Oct 15 01:13:57 AM UTC 24 |
| Finished | Oct 15 01:15:08 AM UTC 24 |
| Peak memory | 223596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854665830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2854665830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.662130537 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 7701305032 ps |
| CPU time | 283.03 seconds |
| Started | Oct 15 01:13:15 AM UTC 24 |
| Finished | Oct 15 01:18:02 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662130537 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.662130537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.315505229 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2419494642 ps |
| CPU time | 27.36 seconds |
| Started | Oct 15 01:13:25 AM UTC 24 |
| Finished | Oct 15 01:13:54 AM UTC 24 |
| Peak memory | 295880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =315505229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_t hroughput_w_partial_write.315505229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3782059949 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 6574117994 ps |
| CPU time | 491.87 seconds |
| Started | Oct 15 01:15:47 AM UTC 24 |
| Finished | Oct 15 01:24:05 AM UTC 24 |
| Peak memory | 381884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782059949 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_durin g_key_req.3782059949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.221631048 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 18136954 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 01:16:37 AM UTC 24 |
| Finished | Oct 15 01:16:39 AM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221631048 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.221631048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.3553753167 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 62222380194 ps |
| CPU time | 2401.26 seconds |
| Started | Oct 15 01:15:08 AM UTC 24 |
| Finished | Oct 15 01:55:36 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553753167 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.3553753167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.1263036858 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 8762372316 ps |
| CPU time | 471.46 seconds |
| Started | Oct 15 01:15:58 AM UTC 24 |
| Finished | Oct 15 01:23:56 AM UTC 24 |
| Peak memory | 382016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263036858 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.1263036858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3969598227 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 61926644599 ps |
| CPU time | 95.41 seconds |
| Started | Oct 15 01:15:30 AM UTC 24 |
| Finished | Oct 15 01:17:08 AM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969598227 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.3969598227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3339334179 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 4464589219 ps |
| CPU time | 82.11 seconds |
| Started | Oct 15 01:15:22 AM UTC 24 |
| Finished | Oct 15 01:16:46 AM UTC 24 |
| Peak memory | 373892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3339334179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_m ax_throughput.3339334179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1109562880 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 6365163413 ps |
| CPU time | 146.39 seconds |
| Started | Oct 15 01:16:07 AM UTC 24 |
| Finished | Oct 15 01:18:37 AM UTC 24 |
| Peak memory | 221420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109562880 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.1109562880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.395283502 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 94573582450 ps |
| CPU time | 373.55 seconds |
| Started | Oct 15 01:16:03 AM UTC 24 |
| Finished | Oct 15 01:22:22 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395283502 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.395283502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.1081857295 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 9935913402 ps |
| CPU time | 91.95 seconds |
| Started | Oct 15 01:14:47 AM UTC 24 |
| Finished | Oct 15 01:16:21 AM UTC 24 |
| Peak memory | 347124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081857295 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.1081857295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.739566871 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 343133986 ps |
| CPU time | 5.36 seconds |
| Started | Oct 15 01:15:15 AM UTC 24 |
| Finished | Oct 15 01:15:21 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739566871 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.739566871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1229512196 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 15892452737 ps |
| CPU time | 443.14 seconds |
| Started | Oct 15 01:15:21 AM UTC 24 |
| Finished | Oct 15 01:22:50 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229512196 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_ac cess_b2b.1229512196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.3757397710 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 364938858 ps |
| CPU time | 4.53 seconds |
| Started | Oct 15 01:16:01 AM UTC 24 |
| Finished | Oct 15 01:16:07 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757397710 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3757397710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_readback_err.1588548272 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 669012926 ps |
| CPU time | 9.52 seconds |
| Started | Oct 15 01:16:22 AM UTC 24 |
| Finished | Oct 15 01:16:32 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588548272 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_readback_err.1588548272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1978321539 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 235455460709 ps |
| CPU time | 1454.51 seconds |
| Started | Oct 15 01:15:58 AM UTC 24 |
| Finished | Oct 15 01:40:28 AM UTC 24 |
| Peak memory | 387960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978321539 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1978321539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.2004715628 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1803790885 ps |
| CPU time | 80.36 seconds |
| Started | Oct 15 01:14:35 AM UTC 24 |
| Finished | Oct 15 01:15:58 AM UTC 24 |
| Peak memory | 355128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004715628 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.2004715628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3886072136 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 200010296623 ps |
| CPU time | 7357.65 seconds |
| Started | Oct 15 01:16:33 AM UTC 24 |
| Finished | Oct 15 03:20:30 AM UTC 24 |
| Peak memory | 393536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38860721 36 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.3886072136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3981826040 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10876049478 ps |
| CPU time | 160.59 seconds |
| Started | Oct 15 01:16:23 AM UTC 24 |
| Finished | Oct 15 01:19:06 AM UTC 24 |
| Peak memory | 338944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981826040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3981826040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1628069853 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2921559076 ps |
| CPU time | 167.83 seconds |
| Started | Oct 15 01:15:13 AM UTC 24 |
| Finished | Oct 15 01:18:03 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628069853 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.1628069853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1523426633 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 757730158 ps |
| CPU time | 70.76 seconds |
| Started | Oct 15 01:15:24 AM UTC 24 |
| Finished | Oct 15 01:16:36 AM UTC 24 |
| Peak memory | 336784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1523426633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ throughput_w_partial_write.1523426633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3322964890 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 25619869893 ps |
| CPU time | 489.55 seconds |
| Started | Oct 15 01:17:32 AM UTC 24 |
| Finished | Oct 15 01:25:48 AM UTC 24 |
| Peak memory | 383944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322964890 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_durin g_key_req.3322964890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3240730802 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 17766322 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 01:18:15 AM UTC 24 |
| Finished | Oct 15 01:18:17 AM UTC 24 |
| Peak memory | 210524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240730802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3240730802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1518034915 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 64891005004 ps |
| CPU time | 1225.02 seconds |
| Started | Oct 15 01:17:00 AM UTC 24 |
| Finished | Oct 15 01:37:39 AM UTC 24 |
| Peak memory | 211248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518034915 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.1518034915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.888314175 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 19068928445 ps |
| CPU time | 1250.18 seconds |
| Started | Oct 15 01:17:39 AM UTC 24 |
| Finished | Oct 15 01:38:42 AM UTC 24 |
| Peak memory | 387940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888314175 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.888314175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.433761599 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3610886616 ps |
| CPU time | 37.43 seconds |
| Started | Oct 15 01:17:31 AM UTC 24 |
| Finished | Oct 15 01:18:10 AM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433761599 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.433761599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1068938446 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4806769441 ps |
| CPU time | 9.09 seconds |
| Started | Oct 15 01:17:19 AM UTC 24 |
| Finished | Oct 15 01:17:30 AM UTC 24 |
| Peak memory | 227992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1068938446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_m ax_throughput.1068938446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.497585575 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 10033825019 ps |
| CPU time | 184.55 seconds |
| Started | Oct 15 01:18:02 AM UTC 24 |
| Finished | Oct 15 01:21:10 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497585575 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.497585575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1872216082 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 21565325566 ps |
| CPU time | 411.42 seconds |
| Started | Oct 15 01:17:56 AM UTC 24 |
| Finished | Oct 15 01:24:53 AM UTC 24 |
| Peak memory | 221432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872216082 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.1872216082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3449474505 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 6208629920 ps |
| CPU time | 587.47 seconds |
| Started | Oct 15 01:16:46 AM UTC 24 |
| Finished | Oct 15 01:26:40 AM UTC 24 |
| Peak memory | 388032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449474505 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.3449474505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1523619089 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3853754225 ps |
| CPU time | 28.77 seconds |
| Started | Oct 15 01:17:08 AM UTC 24 |
| Finished | Oct 15 01:17:38 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523619089 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.1523619089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.4226087402 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 15550135132 ps |
| CPU time | 548.51 seconds |
| Started | Oct 15 01:17:08 AM UTC 24 |
| Finished | Oct 15 01:26:23 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226087402 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_ac cess_b2b.4226087402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1123999563 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 367379477 ps |
| CPU time | 5.97 seconds |
| Started | Oct 15 01:17:48 AM UTC 24 |
| Finished | Oct 15 01:17:55 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123999563 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1123999563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_readback_err.3952714254 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 707838327 ps |
| CPU time | 9.43 seconds |
| Started | Oct 15 01:18:03 AM UTC 24 |
| Finished | Oct 15 01:18:14 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952714254 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_readback_err.3952714254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3342060340 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 3178488526 ps |
| CPU time | 541.02 seconds |
| Started | Oct 15 01:17:42 AM UTC 24 |
| Finished | Oct 15 01:26:50 AM UTC 24 |
| Peak memory | 383996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342060340 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3342060340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.3796269534 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 872122815 ps |
| CPU time | 22.14 seconds |
| Started | Oct 15 01:16:40 AM UTC 24 |
| Finished | Oct 15 01:17:03 AM UTC 24 |
| Peak memory | 250748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796269534 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3796269534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3598501241 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 436414337155 ps |
| CPU time | 7685.07 seconds |
| Started | Oct 15 01:18:11 AM UTC 24 |
| Finished | Oct 15 03:27:37 AM UTC 24 |
| Peak memory | 397712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35985012 41 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.3598501241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2243253479 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1593461969 ps |
| CPU time | 25.73 seconds |
| Started | Oct 15 01:18:04 AM UTC 24 |
| Finished | Oct 15 01:18:32 AM UTC 24 |
| Peak memory | 221468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243253479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2243253479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2589030801 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3144873196 ps |
| CPU time | 232.84 seconds |
| Started | Oct 15 01:17:04 AM UTC 24 |
| Finished | Oct 15 01:21:01 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589030801 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.2589030801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1933067900 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3061893306 ps |
| CPU time | 25.76 seconds |
| Started | Oct 15 01:17:21 AM UTC 24 |
| Finished | Oct 15 01:17:48 AM UTC 24 |
| Peak memory | 295876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1933067900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ throughput_w_partial_write.1933067900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2451831930 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 33817799390 ps |
| CPU time | 760.76 seconds |
| Started | Oct 15 01:19:05 AM UTC 24 |
| Finished | Oct 15 01:31:55 AM UTC 24 |
| Peak memory | 383860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451831930 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_durin g_key_req.2451831930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.742291111 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 14979958 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 01:19:57 AM UTC 24 |
| Finished | Oct 15 01:19:59 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742291111 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.742291111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3996619548 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 234643357022 ps |
| CPU time | 2171.88 seconds |
| Started | Oct 15 01:18:33 AM UTC 24 |
| Finished | Oct 15 01:55:09 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996619548 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.3996619548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3002905092 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 31836700481 ps |
| CPU time | 431.5 seconds |
| Started | Oct 15 01:19:07 AM UTC 24 |
| Finished | Oct 15 01:26:24 AM UTC 24 |
| Peak memory | 381892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002905092 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.3002905092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.460266086 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 9641601040 ps |
| CPU time | 64.49 seconds |
| Started | Oct 15 01:18:53 AM UTC 24 |
| Finished | Oct 15 01:19:59 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460266086 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.460266086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3499876361 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1493785722 ps |
| CPU time | 51.55 seconds |
| Started | Oct 15 01:18:53 AM UTC 24 |
| Finished | Oct 15 01:19:46 AM UTC 24 |
| Peak memory | 316284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3499876361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_m ax_throughput.3499876361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1155613192 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 4540283936 ps |
| CPU time | 179.8 seconds |
| Started | Oct 15 01:19:47 AM UTC 24 |
| Finished | Oct 15 01:22:50 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155613192 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.1155613192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2838867405 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 6987924912 ps |
| CPU time | 182.95 seconds |
| Started | Oct 15 01:19:43 AM UTC 24 |
| Finished | Oct 15 01:22:49 AM UTC 24 |
| Peak memory | 221532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838867405 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.2838867405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3779020535 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 7386652300 ps |
| CPU time | 445.93 seconds |
| Started | Oct 15 01:18:27 AM UTC 24 |
| Finished | Oct 15 01:25:58 AM UTC 24 |
| Peak memory | 383872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779020535 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.3779020535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3814942135 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1211025084 ps |
| CPU time | 76.63 seconds |
| Started | Oct 15 01:18:38 AM UTC 24 |
| Finished | Oct 15 01:19:56 AM UTC 24 |
| Peak memory | 355200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814942135 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.3814942135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4009397532 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 129400478691 ps |
| CPU time | 435.01 seconds |
| Started | Oct 15 01:18:53 AM UTC 24 |
| Finished | Oct 15 01:26:13 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009397532 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_ac cess_b2b.4009397532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1869763058 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 683672748 ps |
| CPU time | 4.84 seconds |
| Started | Oct 15 01:19:39 AM UTC 24 |
| Finished | Oct 15 01:19:45 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869763058 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1869763058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_readback_err.3269983028 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1377478191 ps |
| CPU time | 8.2 seconds |
| Started | Oct 15 01:19:47 AM UTC 24 |
| Finished | Oct 15 01:19:56 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269983028 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_readback_err.3269983028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.111316130 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1289121777 ps |
| CPU time | 228.26 seconds |
| Started | Oct 15 01:19:30 AM UTC 24 |
| Finished | Oct 15 01:23:22 AM UTC 24 |
| Peak memory | 383796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111316130 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.111316130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.3884132415 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1402947003 ps |
| CPU time | 22.73 seconds |
| Started | Oct 15 01:18:18 AM UTC 24 |
| Finished | Oct 15 01:18:42 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884132415 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3884132415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2325389095 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 59897803047 ps |
| CPU time | 3258.5 seconds |
| Started | Oct 15 01:19:57 AM UTC 24 |
| Finished | Oct 15 02:14:52 AM UTC 24 |
| Peak memory | 367552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23253890 95 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.2325389095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2111610891 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3569040259 ps |
| CPU time | 252.65 seconds |
| Started | Oct 15 01:18:37 AM UTC 24 |
| Finished | Oct 15 01:22:53 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111610891 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.2111610891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3656557909 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2971370473 ps |
| CPU time | 35.16 seconds |
| Started | Oct 15 01:18:53 AM UTC 24 |
| Finished | Oct 15 01:19:29 AM UTC 24 |
| Peak memory | 314308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3656557909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ throughput_w_partial_write.3656557909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2711164891 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 6243714701 ps |
| CPU time | 200.16 seconds |
| Started | Oct 15 01:21:11 AM UTC 24 |
| Finished | Oct 15 01:24:35 AM UTC 24 |
| Peak memory | 375680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711164891 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_durin g_key_req.2711164891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1153651719 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 25162548 ps |
| CPU time | 1.03 seconds |
| Started | Oct 15 01:22:27 AM UTC 24 |
| Finished | Oct 15 01:22:29 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153651719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1153651719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2349973286 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 116700622875 ps |
| CPU time | 2377.28 seconds |
| Started | Oct 15 01:20:07 AM UTC 24 |
| Finished | Oct 15 02:00:11 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349973286 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.2349973286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1042015136 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 15725301887 ps |
| CPU time | 883.52 seconds |
| Started | Oct 15 01:21:18 AM UTC 24 |
| Finished | Oct 15 01:36:11 AM UTC 24 |
| Peak memory | 385992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042015136 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.1042015136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.580973144 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 13705521048 ps |
| CPU time | 101.02 seconds |
| Started | Oct 15 01:21:02 AM UTC 24 |
| Finished | Oct 15 01:22:45 AM UTC 24 |
| Peak memory | 221348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580973144 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.580973144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3551548553 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2977001230 ps |
| CPU time | 36.03 seconds |
| Started | Oct 15 01:20:40 AM UTC 24 |
| Finished | Oct 15 01:21:17 AM UTC 24 |
| Peak memory | 293756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3551548553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_m ax_throughput.3551548553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3033730189 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 91070420941 ps |
| CPU time | 199.52 seconds |
| Started | Oct 15 01:22:00 AM UTC 24 |
| Finished | Oct 15 01:25:22 AM UTC 24 |
| Peak memory | 221468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033730189 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.3033730189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3455021078 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 5722485978 ps |
| CPU time | 173.51 seconds |
| Started | Oct 15 01:21:58 AM UTC 24 |
| Finished | Oct 15 01:24:54 AM UTC 24 |
| Peak memory | 221432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455021078 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.3455021078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.271899818 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 14662497093 ps |
| CPU time | 721.51 seconds |
| Started | Oct 15 01:20:00 AM UTC 24 |
| Finished | Oct 15 01:32:10 AM UTC 24 |
| Peak memory | 383944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271899818 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.271899818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.2588899386 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 374016381 ps |
| CPU time | 4.86 seconds |
| Started | Oct 15 01:20:27 AM UTC 24 |
| Finished | Oct 15 01:20:33 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588899386 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.2588899386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3584778359 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 153021289089 ps |
| CPU time | 374.16 seconds |
| Started | Oct 15 01:20:35 AM UTC 24 |
| Finished | Oct 15 01:26:54 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584778359 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_ac cess_b2b.3584778359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3483270629 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 352846308 ps |
| CPU time | 3.87 seconds |
| Started | Oct 15 01:21:51 AM UTC 24 |
| Finished | Oct 15 01:21:56 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483270629 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3483270629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_readback_err.642234483 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 697770866 ps |
| CPU time | 7.27 seconds |
| Started | Oct 15 01:22:18 AM UTC 24 |
| Finished | Oct 15 01:22:26 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642234483 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_readback_err.642234483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_readback_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2108911100 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8732607863 ps |
| CPU time | 255.55 seconds |
| Started | Oct 15 01:21:46 AM UTC 24 |
| Finished | Oct 15 01:26:05 AM UTC 24 |
| Peak memory | 385912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108911100 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2108911100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.111150562 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 14976092174 ps |
| CPU time | 54.42 seconds |
| Started | Oct 15 01:20:00 AM UTC 24 |
| Finished | Oct 15 01:20:56 AM UTC 24 |
| Peak memory | 326508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111150562 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.111150562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1730025908 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 32771682716 ps |
| CPU time | 1793.35 seconds |
| Started | Oct 15 01:22:23 AM UTC 24 |
| Finished | Oct 15 01:52:36 AM UTC 24 |
| Peak memory | 388012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17300259 08 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.1730025908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.586364839 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 1268765319 ps |
| CPU time | 112.79 seconds |
| Started | Oct 15 01:22:20 AM UTC 24 |
| Finished | Oct 15 01:24:15 AM UTC 24 |
| Peak memory | 377856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586364839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.586364839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3101598765 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3212668526 ps |
| CPU time | 208.92 seconds |
| Started | Oct 15 01:20:08 AM UTC 24 |
| Finished | Oct 15 01:23:40 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101598765 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.3101598765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1487156754 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 787999030 ps |
| CPU time | 47.43 seconds |
| Started | Oct 15 01:20:57 AM UTC 24 |
| Finished | Oct 15 01:21:46 AM UTC 24 |
| Peak memory | 330640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1487156754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ throughput_w_partial_write.1487156754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
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