| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.323997664 |
|
|
Oct 15 02:03:51 AM UTC 24 |
Oct 15 02:04:12 AM UTC 24 |
711092847 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2151725778 |
|
|
Oct 15 02:02:33 AM UTC 24 |
Oct 15 02:04:30 AM UTC 24 |
3370215135 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.316085192 |
|
|
Oct 15 01:57:01 AM UTC 24 |
Oct 15 02:04:53 AM UTC 24 |
9184719773 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1104191130 |
|
|
Oct 15 02:04:54 AM UTC 24 |
Oct 15 02:05:00 AM UTC 24 |
425982897 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.550296756 |
|
|
Oct 15 02:03:51 AM UTC 24 |
Oct 15 02:05:07 AM UTC 24 |
3252038764 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.35439987 |
|
|
Oct 15 02:00:47 AM UTC 24 |
Oct 15 02:05:23 AM UTC 24 |
3618346115 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_readback_err.685025824 |
|
|
Oct 15 02:05:23 AM UTC 24 |
Oct 15 02:05:33 AM UTC 24 |
1507681972 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.883543271 |
|
|
Oct 15 02:01:54 AM UTC 24 |
Oct 15 02:05:43 AM UTC 24 |
11044308319 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.771415841 |
|
|
Oct 15 02:03:54 AM UTC 24 |
Oct 15 02:05:44 AM UTC 24 |
19529350362 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.3154675833 |
|
|
Oct 15 02:05:45 AM UTC 24 |
Oct 15 02:05:47 AM UTC 24 |
45465436 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.150854762 |
|
|
Oct 15 01:58:26 AM UTC 24 |
Oct 15 02:06:06 AM UTC 24 |
15630447400 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.293572399 |
|
|
Oct 15 01:51:17 AM UTC 24 |
Oct 15 02:06:11 AM UTC 24 |
9582619620 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.1188476549 |
|
|
Oct 15 02:01:23 AM UTC 24 |
Oct 15 02:06:17 AM UTC 24 |
9072328261 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.1033745393 |
|
|
Oct 15 02:05:48 AM UTC 24 |
Oct 15 02:06:19 AM UTC 24 |
827556505 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.428203420 |
|
|
Oct 15 01:53:16 AM UTC 24 |
Oct 15 02:06:30 AM UTC 24 |
6352495893 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.461189124 |
|
|
Oct 15 01:14:07 AM UTC 24 |
Oct 15 02:06:31 AM UTC 24 |
514002597573 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.197010183 |
|
|
Oct 15 02:06:20 AM UTC 24 |
Oct 15 02:06:44 AM UTC 24 |
3609296588 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.401768264 |
|
|
Oct 15 02:02:03 AM UTC 24 |
Oct 15 02:06:53 AM UTC 24 |
16420091005 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.4212241903 |
|
|
Oct 15 02:04:00 AM UTC 24 |
Oct 15 02:06:54 AM UTC 24 |
3320892054 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2088252457 |
|
|
Oct 15 02:00:45 AM UTC 24 |
Oct 15 02:06:54 AM UTC 24 |
54711125033 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.3947184298 |
|
|
Oct 15 02:05:08 AM UTC 24 |
Oct 15 02:06:55 AM UTC 24 |
6383180145 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2823520548 |
|
|
Oct 15 02:06:32 AM UTC 24 |
Oct 15 02:06:59 AM UTC 24 |
736820640 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.2065434432 |
|
|
Oct 15 01:39:26 AM UTC 24 |
Oct 15 02:07:01 AM UTC 24 |
179433320046 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.2568030325 |
|
|
Oct 15 02:00:12 AM UTC 24 |
Oct 15 02:07:03 AM UTC 24 |
17801956254 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2326670659 |
|
|
Oct 15 02:06:59 AM UTC 24 |
Oct 15 02:07:05 AM UTC 24 |
351950123 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_readback_err.2454313382 |
|
|
Oct 15 02:07:06 AM UTC 24 |
Oct 15 02:07:17 AM UTC 24 |
4120351117 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2644114117 |
|
|
Oct 15 02:03:28 AM UTC 24 |
Oct 15 02:07:40 AM UTC 24 |
28006236583 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1911308199 |
|
|
Oct 15 01:55:07 AM UTC 24 |
Oct 15 02:07:45 AM UTC 24 |
34826364832 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3968433238 |
|
|
Oct 15 01:13:02 AM UTC 24 |
Oct 15 02:07:47 AM UTC 24 |
40289667347 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.626234626 |
|
|
Oct 15 02:07:46 AM UTC 24 |
Oct 15 02:07:48 AM UTC 24 |
100877323 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3518349952 |
|
|
Oct 15 01:54:26 AM UTC 24 |
Oct 15 02:07:52 AM UTC 24 |
23484983804 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2271735219 |
|
|
Oct 15 01:50:08 AM UTC 24 |
Oct 15 02:07:54 AM UTC 24 |
42572427338 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.718066614 |
|
|
Oct 15 02:05:34 AM UTC 24 |
Oct 15 02:08:01 AM UTC 24 |
48558481248 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.811673861 |
|
|
Oct 15 01:52:05 AM UTC 24 |
Oct 15 02:08:03 AM UTC 24 |
40360188080 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3509339089 |
|
|
Oct 15 02:06:45 AM UTC 24 |
Oct 15 02:08:15 AM UTC 24 |
3095793378 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2726113248 |
|
|
Oct 15 02:06:54 AM UTC 24 |
Oct 15 02:08:19 AM UTC 24 |
28392524588 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1308806923 |
|
|
Oct 15 02:08:03 AM UTC 24 |
Oct 15 02:08:33 AM UTC 24 |
2883738139 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2486317549 |
|
|
Oct 15 02:08:16 AM UTC 24 |
Oct 15 02:08:36 AM UTC 24 |
696677394 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4027206346 |
|
|
Oct 15 02:07:18 AM UTC 24 |
Oct 15 02:08:39 AM UTC 24 |
4360529481 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.3971209703 |
|
|
Oct 15 01:59:53 AM UTC 24 |
Oct 15 02:08:43 AM UTC 24 |
21939865732 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.1011660548 |
|
|
Oct 15 02:08:20 AM UTC 24 |
Oct 15 02:09:10 AM UTC 24 |
2755663717 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2272644442 |
|
|
Oct 15 02:05:00 AM UTC 24 |
Oct 15 02:09:17 AM UTC 24 |
3950149679 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.341047339 |
|
|
Oct 15 02:09:12 AM UTC 24 |
Oct 15 02:09:18 AM UTC 24 |
1361501673 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3778737140 |
|
|
Oct 15 02:08:34 AM UTC 24 |
Oct 15 02:09:23 AM UTC 24 |
6954970137 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.199379369 |
|
|
Oct 15 02:07:48 AM UTC 24 |
Oct 15 02:09:23 AM UTC 24 |
5728099947 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_readback_err.3561799239 |
|
|
Oct 15 02:09:24 AM UTC 24 |
Oct 15 02:09:36 AM UTC 24 |
699016780 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.652304495 |
|
|
Oct 15 02:09:24 AM UTC 24 |
Oct 15 02:09:38 AM UTC 24 |
141615394 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.777717023 |
|
|
Oct 15 02:09:39 AM UTC 24 |
Oct 15 02:09:41 AM UTC 24 |
147697193 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1571166252 |
|
|
Oct 15 02:04:31 AM UTC 24 |
Oct 15 02:10:07 AM UTC 24 |
11167280338 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.789498249 |
|
|
Oct 15 02:07:04 AM UTC 24 |
Oct 15 02:10:36 AM UTC 24 |
21856729793 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.3468221217 |
|
|
Oct 15 02:06:30 AM UTC 24 |
Oct 15 02:10:43 AM UTC 24 |
17153198235 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1205229852 |
|
|
Oct 15 02:06:17 AM UTC 24 |
Oct 15 02:10:44 AM UTC 24 |
11287103282 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.1189682174 |
|
|
Oct 15 02:09:42 AM UTC 24 |
Oct 15 02:10:46 AM UTC 24 |
9179411877 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1886501491 |
|
|
Oct 15 02:03:42 AM UTC 24 |
Oct 15 02:10:51 AM UTC 24 |
11071626470 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.94893876 |
|
|
Oct 15 01:55:10 AM UTC 24 |
Oct 15 02:11:01 AM UTC 24 |
15387834235 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.4001028342 |
|
|
Oct 15 02:09:19 AM UTC 24 |
Oct 15 02:11:08 AM UTC 24 |
2749697276 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2765818315 |
|
|
Oct 15 02:10:45 AM UTC 24 |
Oct 15 02:11:10 AM UTC 24 |
3098319861 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3487224508 |
|
|
Oct 15 02:11:01 AM UTC 24 |
Oct 15 02:11:12 AM UTC 24 |
2828073840 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.1535214302 |
|
|
Oct 15 02:10:52 AM UTC 24 |
Oct 15 02:11:13 AM UTC 24 |
733292638 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.1358101080 |
|
|
Oct 15 01:26:55 AM UTC 24 |
Oct 15 02:11:50 AM UTC 24 |
423721223337 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.499090577 |
|
|
Oct 15 02:11:51 AM UTC 24 |
Oct 15 02:11:58 AM UTC 24 |
356874433 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.4108755244 |
|
|
Oct 15 02:08:40 AM UTC 24 |
Oct 15 02:12:16 AM UTC 24 |
5712319136 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3270654416 |
|
|
Oct 15 02:07:01 AM UTC 24 |
Oct 15 02:12:20 AM UTC 24 |
3947436420 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1430431133 |
|
|
Oct 15 02:11:08 AM UTC 24 |
Oct 15 02:12:30 AM UTC 24 |
8939128035 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_readback_err.3503740860 |
|
|
Oct 15 02:12:20 AM UTC 24 |
Oct 15 02:12:31 AM UTC 24 |
697089109 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.2583112210 |
|
|
Oct 15 02:08:36 AM UTC 24 |
Oct 15 02:12:34 AM UTC 24 |
4336898617 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.4273889385 |
|
|
Oct 15 02:12:35 AM UTC 24 |
Oct 15 02:12:37 AM UTC 24 |
20680729 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.4283802297 |
|
|
Oct 15 02:09:19 AM UTC 24 |
Oct 15 02:13:01 AM UTC 24 |
41435723625 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.1537928566 |
|
|
Oct 15 02:01:55 AM UTC 24 |
Oct 15 02:13:22 AM UTC 24 |
20894601939 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3458590509 |
|
|
Oct 15 02:12:16 AM UTC 24 |
Oct 15 02:13:43 AM UTC 24 |
1453214826 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.451131529 |
|
|
Oct 15 02:12:38 AM UTC 24 |
Oct 15 02:13:56 AM UTC 24 |
4702291307 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.501487297 |
|
|
Oct 15 02:12:31 AM UTC 24 |
Oct 15 02:14:03 AM UTC 24 |
4697279582 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2898322291 |
|
|
Oct 15 01:50:57 AM UTC 24 |
Oct 15 02:14:24 AM UTC 24 |
86658551590 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.426900746 |
|
|
Oct 15 02:10:47 AM UTC 24 |
Oct 15 02:14:46 AM UTC 24 |
7799032237 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2325389095 |
|
|
Oct 15 01:19:57 AM UTC 24 |
Oct 15 02:14:52 AM UTC 24 |
59897803047 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.521909296 |
|
|
Oct 15 02:14:46 AM UTC 24 |
Oct 15 02:14:57 AM UTC 24 |
699712944 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1239837907 |
|
|
Oct 15 02:11:59 AM UTC 24 |
Oct 15 02:14:58 AM UTC 24 |
8981081373 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.2432260228 |
|
|
Oct 15 01:41:13 AM UTC 24 |
Oct 15 02:15:05 AM UTC 24 |
122225863542 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.2947047656 |
|
|
Oct 15 02:07:55 AM UTC 24 |
Oct 15 02:15:08 AM UTC 24 |
21008742097 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3490159551 |
|
|
Oct 15 02:13:57 AM UTC 24 |
Oct 15 02:15:15 AM UTC 24 |
3383199872 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2681133797 |
|
|
Oct 15 02:15:10 AM UTC 24 |
Oct 15 02:15:16 AM UTC 24 |
346694871 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3005711230 |
|
|
Oct 15 02:14:25 AM UTC 24 |
Oct 15 02:15:17 AM UTC 24 |
3015481584 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_readback_err.1066486928 |
|
|
Oct 15 02:15:18 AM UTC 24 |
Oct 15 02:15:31 AM UTC 24 |
1388975576 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2752867377 |
|
|
Oct 15 02:11:13 AM UTC 24 |
Oct 15 02:15:37 AM UTC 24 |
30534595083 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1280064521 |
|
|
Oct 15 02:08:04 AM UTC 24 |
Oct 15 02:15:43 AM UTC 24 |
16105715127 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.610824026 |
|
|
Oct 15 02:15:44 AM UTC 24 |
Oct 15 02:15:46 AM UTC 24 |
48296141 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.918280839 |
|
|
Oct 15 01:43:36 AM UTC 24 |
Oct 15 02:15:47 AM UTC 24 |
276394105478 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.69121083 |
|
|
Oct 15 02:15:32 AM UTC 24 |
Oct 15 02:15:49 AM UTC 24 |
773639072 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.140609387 |
|
|
Oct 15 02:14:53 AM UTC 24 |
Oct 15 02:15:52 AM UTC 24 |
6776846862 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.514303906 |
|
|
Oct 15 02:15:47 AM UTC 24 |
Oct 15 02:16:11 AM UTC 24 |
14222767086 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.813767574 |
|
|
Oct 15 02:01:48 AM UTC 24 |
Oct 15 02:16:11 AM UTC 24 |
75868839279 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.904478893 |
|
|
Oct 15 02:06:55 AM UTC 24 |
Oct 15 02:16:23 AM UTC 24 |
106624153334 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.644650846 |
|
|
Oct 15 01:12:01 AM UTC 24 |
Oct 15 02:16:26 AM UTC 24 |
55437638495 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.614035906 |
|
|
Oct 15 02:10:44 AM UTC 24 |
Oct 15 02:16:27 AM UTC 24 |
12907058696 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2787336748 |
|
|
Oct 15 02:16:17 AM UTC 24 |
Oct 15 02:16:30 AM UTC 24 |
1428078706 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2234760492 |
|
|
Oct 15 02:16:23 AM UTC 24 |
Oct 15 02:16:39 AM UTC 24 |
3670039354 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3866597426 |
|
|
Oct 15 02:16:12 AM UTC 24 |
Oct 15 02:16:57 AM UTC 24 |
12635391354 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.4043106161 |
|
|
Oct 15 02:15:17 AM UTC 24 |
Oct 15 02:17:01 AM UTC 24 |
2751022842 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.1657841117 |
|
|
Oct 15 02:16:58 AM UTC 24 |
Oct 15 02:17:06 AM UTC 24 |
1695926360 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2629975817 |
|
|
Oct 15 02:15:48 AM UTC 24 |
Oct 15 02:17:23 AM UTC 24 |
13226110161 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_readback_err.2079695954 |
|
|
Oct 15 02:17:24 AM UTC 24 |
Oct 15 02:17:32 AM UTC 24 |
1452608132 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1170782 |
|
|
Oct 15 02:13:02 AM UTC 24 |
Oct 15 02:17:38 AM UTC 24 |
37913951758 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2090956056 |
|
|
Oct 15 01:54:20 AM UTC 24 |
Oct 15 02:17:41 AM UTC 24 |
282798430537 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3339031988 |
|
|
Oct 15 02:17:43 AM UTC 24 |
Oct 15 02:17:45 AM UTC 24 |
47235894 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1186279683 |
|
|
Oct 15 02:16:27 AM UTC 24 |
Oct 15 02:17:46 AM UTC 24 |
8565774514 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.2906659755 |
|
|
Oct 15 02:17:46 AM UTC 24 |
Oct 15 02:18:04 AM UTC 24 |
5464245038 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3800808986 |
|
|
Oct 15 02:10:07 AM UTC 24 |
Oct 15 02:18:21 AM UTC 24 |
14058612203 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.878686029 |
|
|
Oct 15 02:15:53 AM UTC 24 |
Oct 15 02:18:37 AM UTC 24 |
8126011799 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2313147898 |
|
|
Oct 15 02:17:32 AM UTC 24 |
Oct 15 02:18:47 AM UTC 24 |
1569778812 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.353552640 |
|
|
Oct 15 02:18:38 AM UTC 24 |
Oct 15 02:18:56 AM UTC 24 |
463477380 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.4112052195 |
|
|
Oct 15 02:17:06 AM UTC 24 |
Oct 15 02:18:58 AM UTC 24 |
16862826010 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2245717596 |
|
|
Oct 15 02:06:55 AM UTC 24 |
Oct 15 02:19:07 AM UTC 24 |
40507745727 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1904060180 |
|
|
Oct 15 01:58:06 AM UTC 24 |
Oct 15 02:19:09 AM UTC 24 |
41886995128 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3234752162 |
|
|
Oct 15 02:18:57 AM UTC 24 |
Oct 15 02:19:19 AM UTC 24 |
742541150 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3150956767 |
|
|
Oct 15 01:39:02 AM UTC 24 |
Oct 15 02:19:21 AM UTC 24 |
573637511011 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1210004105 |
|
|
Oct 15 02:17:47 AM UTC 24 |
Oct 15 02:20:09 AM UTC 24 |
14786741587 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2717842010 |
|
|
Oct 15 02:20:10 AM UTC 24 |
Oct 15 02:20:18 AM UTC 24 |
1354002464 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.1140561790 |
|
|
Oct 15 02:10:37 AM UTC 24 |
Oct 15 02:20:20 AM UTC 24 |
8207680982 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.663022786 |
|
|
Oct 15 02:13:44 AM UTC 24 |
Oct 15 02:20:24 AM UTC 24 |
10473241866 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3628118161 |
|
|
Oct 15 02:19:08 AM UTC 24 |
Oct 15 02:20:29 AM UTC 24 |
80434226324 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_readback_err.1861385447 |
|
|
Oct 15 02:20:25 AM UTC 24 |
Oct 15 02:20:33 AM UTC 24 |
2743611478 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1616058577 |
|
|
Oct 15 02:19:00 AM UTC 24 |
Oct 15 02:20:34 AM UTC 24 |
1638980584 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.4003379150 |
|
|
Oct 15 02:20:35 AM UTC 24 |
Oct 15 02:20:37 AM UTC 24 |
203111306 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.1089465169 |
|
|
Oct 15 02:20:38 AM UTC 24 |
Oct 15 02:20:49 AM UTC 24 |
705908464 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.626755494 |
|
|
Oct 15 02:14:05 AM UTC 24 |
Oct 15 02:21:06 AM UTC 24 |
5821034713 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3456733501 |
|
|
Oct 15 02:17:02 AM UTC 24 |
Oct 15 02:21:20 AM UTC 24 |
30302021826 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.4270309569 |
|
|
Oct 15 02:15:16 AM UTC 24 |
Oct 15 02:21:42 AM UTC 24 |
30880069246 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3136036680 |
|
|
Oct 15 02:18:22 AM UTC 24 |
Oct 15 02:21:46 AM UTC 24 |
2933977046 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3296126876 |
|
|
Oct 15 02:20:30 AM UTC 24 |
Oct 15 02:22:16 AM UTC 24 |
8916014332 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.2754665929 |
|
|
Oct 15 02:18:48 AM UTC 24 |
Oct 15 02:22:39 AM UTC 24 |
46790018883 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.2458821971 |
|
|
Oct 15 02:22:16 AM UTC 24 |
Oct 15 02:22:40 AM UTC 24 |
3641975468 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.738653054 |
|
|
Oct 15 02:06:56 AM UTC 24 |
Oct 15 02:22:50 AM UTC 24 |
160969587171 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.2718665803 |
|
|
Oct 15 02:08:43 AM UTC 24 |
Oct 15 02:22:56 AM UTC 24 |
52071804644 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3153207937 |
|
|
Oct 15 02:20:50 AM UTC 24 |
Oct 15 02:22:58 AM UTC 24 |
1512663736 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.2201311127 |
|
|
Oct 15 02:22:40 AM UTC 24 |
Oct 15 02:23:01 AM UTC 24 |
2832130320 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3267377806 |
|
|
Oct 15 02:23:02 AM UTC 24 |
Oct 15 02:23:08 AM UTC 24 |
368289700 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3000639757 |
|
|
Oct 15 02:16:12 AM UTC 24 |
Oct 15 02:23:09 AM UTC 24 |
15824151356 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2363663653 |
|
|
Oct 15 02:16:27 AM UTC 24 |
Oct 15 02:23:10 AM UTC 24 |
10209945863 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3730283401 |
|
|
Oct 15 02:20:21 AM UTC 24 |
Oct 15 02:23:15 AM UTC 24 |
4605891260 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.1429014075 |
|
|
Oct 15 01:52:09 AM UTC 24 |
Oct 15 02:23:18 AM UTC 24 |
23637538360 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.499518576 |
|
|
Oct 15 02:22:42 AM UTC 24 |
Oct 15 02:23:22 AM UTC 24 |
5872682592 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1762734156 |
|
|
Oct 15 02:21:43 AM UTC 24 |
Oct 15 02:23:22 AM UTC 24 |
2606329207 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_readback_err.2627946113 |
|
|
Oct 15 02:23:10 AM UTC 24 |
Oct 15 02:23:22 AM UTC 24 |
2749900740 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3110694125 |
|
|
Oct 15 02:19:10 AM UTC 24 |
Oct 15 02:23:25 AM UTC 24 |
8507210523 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.499487642 |
|
|
Oct 15 02:03:14 AM UTC 24 |
Oct 15 02:23:25 AM UTC 24 |
17470633720 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1711315232 |
|
|
Oct 15 02:23:24 AM UTC 24 |
Oct 15 02:23:26 AM UTC 24 |
12234098 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.1644047142 |
|
|
Oct 15 01:45:21 AM UTC 24 |
Oct 15 02:23:33 AM UTC 24 |
843771666202 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.2364807834 |
|
|
Oct 15 02:23:27 AM UTC 24 |
Oct 15 02:23:41 AM UTC 24 |
1810419284 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1965589276 |
|
|
Oct 15 02:23:15 AM UTC 24 |
Oct 15 02:23:42 AM UTC 24 |
2221465414 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1793900056 |
|
|
Oct 15 02:23:42 AM UTC 24 |
Oct 15 02:23:56 AM UTC 24 |
2771041501 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3849898336 |
|
|
Oct 15 02:11:12 AM UTC 24 |
Oct 15 02:24:01 AM UTC 24 |
66526503996 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.2624490513 |
|
|
Oct 15 02:23:24 AM UTC 24 |
Oct 15 02:24:07 AM UTC 24 |
2776542778 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.93942428 |
|
|
Oct 15 02:23:57 AM UTC 24 |
Oct 15 02:24:09 AM UTC 24 |
1125316156 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1316113926 |
|
|
Oct 15 02:23:42 AM UTC 24 |
Oct 15 02:24:13 AM UTC 24 |
769183970 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.2779927330 |
|
|
Oct 15 02:04:14 AM UTC 24 |
Oct 15 02:24:14 AM UTC 24 |
16433488786 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.912123175 |
|
|
Oct 15 02:24:14 AM UTC 24 |
Oct 15 02:24:22 AM UTC 24 |
1355891898 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3558082432 |
|
|
Oct 15 02:23:09 AM UTC 24 |
Oct 15 02:25:14 AM UTC 24 |
3952222667 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.1137876989 |
|
|
Oct 15 02:20:18 AM UTC 24 |
Oct 15 02:25:23 AM UTC 24 |
4026672470 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_readback_err.3372950324 |
|
|
Oct 15 02:25:15 AM UTC 24 |
Oct 15 02:25:23 AM UTC 24 |
665568388 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.997769053 |
|
|
Oct 15 02:23:10 AM UTC 24 |
Oct 15 02:25:34 AM UTC 24 |
2507946714 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1773793593 |
|
|
Oct 15 02:25:35 AM UTC 24 |
Oct 15 02:25:37 AM UTC 24 |
27670137 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2939748398 |
|
|
Oct 15 02:06:07 AM UTC 24 |
Oct 15 02:25:37 AM UTC 24 |
24478048716 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.7554305 |
|
|
Oct 15 02:24:23 AM UTC 24 |
Oct 15 02:25:39 AM UTC 24 |
3812422046 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.981621585 |
|
|
Oct 15 02:25:38 AM UTC 24 |
Oct 15 02:25:56 AM UTC 24 |
557059329 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3255078401 |
|
|
Oct 15 02:25:24 AM UTC 24 |
Oct 15 02:26:22 AM UTC 24 |
7896679249 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.675689325 |
|
|
Oct 15 02:21:21 AM UTC 24 |
Oct 15 02:26:32 AM UTC 24 |
19307650362 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.781387229 |
|
|
Oct 15 01:47:31 AM UTC 24 |
Oct 15 02:26:33 AM UTC 24 |
248504810207 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.763074887 |
|
|
Oct 15 01:56:14 AM UTC 24 |
Oct 15 02:26:37 AM UTC 24 |
104296850441 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.407779069 |
|
|
Oct 15 02:26:23 AM UTC 24 |
Oct 15 02:26:50 AM UTC 24 |
1036509768 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.1076792771 |
|
|
Oct 15 01:58:07 AM UTC 24 |
Oct 15 02:26:53 AM UTC 24 |
95786594916 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1632623278 |
|
|
Oct 15 02:26:34 AM UTC 24 |
Oct 15 02:27:07 AM UTC 24 |
3062452166 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.223029886 |
|
|
Oct 15 02:24:15 AM UTC 24 |
Oct 15 02:27:09 AM UTC 24 |
147670278968 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.2712835059 |
|
|
Oct 15 02:07:53 AM UTC 24 |
Oct 15 02:27:09 AM UTC 24 |
32208348557 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1663035286 |
|
|
Oct 15 01:34:26 AM UTC 24 |
Oct 15 02:27:16 AM UTC 24 |
123894594642 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.3725106785 |
|
|
Oct 15 02:27:11 AM UTC 24 |
Oct 15 02:27:17 AM UTC 24 |
360117228 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2536761724 |
|
|
Oct 15 02:26:51 AM UTC 24 |
Oct 15 02:27:22 AM UTC 24 |
14826980296 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_readback_err.1818400533 |
|
|
Oct 15 02:27:23 AM UTC 24 |
Oct 15 02:27:35 AM UTC 24 |
666503877 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.3588925276 |
|
|
Oct 15 01:54:38 AM UTC 24 |
Oct 15 02:27:42 AM UTC 24 |
383308290794 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.2001442384 |
|
|
Oct 15 01:45:15 AM UTC 24 |
Oct 15 02:27:48 AM UTC 24 |
19655765654 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3920677809 |
|
|
Oct 15 02:27:48 AM UTC 24 |
Oct 15 02:27:50 AM UTC 24 |
49714707 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.4070878201 |
|
|
Oct 15 02:27:51 AM UTC 24 |
Oct 15 02:28:00 AM UTC 24 |
484858085 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.4168914957 |
|
|
Oct 15 02:16:32 AM UTC 24 |
Oct 15 02:28:02 AM UTC 24 |
102721602913 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.2734915306 |
|
|
Oct 15 02:11:14 AM UTC 24 |
Oct 15 02:28:12 AM UTC 24 |
5102064037 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2485664627 |
|
|
Oct 15 02:26:38 AM UTC 24 |
Oct 15 02:28:25 AM UTC 24 |
3134858728 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2434250661 |
|
|
Oct 15 02:28:26 AM UTC 24 |
Oct 15 02:28:50 AM UTC 24 |
2956712851 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.641866592 |
|
|
Oct 15 02:27:36 AM UTC 24 |
Oct 15 02:28:56 AM UTC 24 |
5538053646 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.723413470 |
|
|
Oct 15 02:28:02 AM UTC 24 |
Oct 15 02:29:02 AM UTC 24 |
1801787604 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1093475966 |
|
|
Oct 15 02:23:26 AM UTC 24 |
Oct 15 02:29:19 AM UTC 24 |
4842671146 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3854330856 |
|
|
Oct 15 02:28:57 AM UTC 24 |
Oct 15 02:29:23 AM UTC 24 |
5982938707 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.2312488674 |
|
|
Oct 15 02:29:03 AM UTC 24 |
Oct 15 02:29:48 AM UTC 24 |
2984858206 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.687562989 |
|
|
Oct 15 02:27:18 AM UTC 24 |
Oct 15 02:30:09 AM UTC 24 |
10052370499 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.2866018012 |
|
|
Oct 15 02:19:22 AM UTC 24 |
Oct 15 02:30:09 AM UTC 24 |
7121864060 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2741380061 |
|
|
Oct 15 02:29:20 AM UTC 24 |
Oct 15 02:30:15 AM UTC 24 |
20885191865 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1661197046 |
|
|
Oct 15 02:30:10 AM UTC 24 |
Oct 15 02:30:17 AM UTC 24 |
360351886 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.405166930 |
|
|
Oct 15 02:23:34 AM UTC 24 |
Oct 15 02:30:40 AM UTC 24 |
6568201016 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3087798568 |
|
|
Oct 15 02:30:40 AM UTC 24 |
Oct 15 02:30:50 AM UTC 24 |
2647572876 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.11497077 |
|
|
Oct 15 02:25:56 AM UTC 24 |
Oct 15 02:30:57 AM UTC 24 |
25626869869 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.519025781 |
|
|
Oct 15 02:30:51 AM UTC 24 |
Oct 15 02:31:02 AM UTC 24 |
1030475824 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.919473584 |
|
|
Oct 15 02:31:03 AM UTC 24 |
Oct 15 02:31:05 AM UTC 24 |
13172186 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.116370319 |
|
|
Oct 15 02:31:06 AM UTC 24 |
Oct 15 02:31:17 AM UTC 24 |
1468637629 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.4225123595 |
|
|
Oct 15 02:14:57 AM UTC 24 |
Oct 15 02:31:38 AM UTC 24 |
160851396209 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1909021740 |
|
|
Oct 15 01:47:16 AM UTC 24 |
Oct 15 02:31:45 AM UTC 24 |
233457936111 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.1244887194 |
|
|
Oct 15 02:30:17 AM UTC 24 |
Oct 15 02:31:52 AM UTC 24 |
10110496934 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.1635136725 |
|
|
Oct 15 01:56:17 AM UTC 24 |
Oct 15 02:31:59 AM UTC 24 |
29190168246 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.3211288865 |
|
|
Oct 15 02:14:58 AM UTC 24 |
Oct 15 02:32:09 AM UTC 24 |
21137517795 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.2848590545 |
|
|
Oct 15 02:15:07 AM UTC 24 |
Oct 15 02:32:26 AM UTC 24 |
2771797363 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1206420196 |
|
|
Oct 15 02:31:54 AM UTC 24 |
Oct 15 02:32:32 AM UTC 24 |
3334215183 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.2272652728 |
|
|
Oct 15 02:16:40 AM UTC 24 |
Oct 15 02:32:53 AM UTC 24 |
204383144102 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.939059304 |
|
|
Oct 15 02:13:23 AM UTC 24 |
Oct 15 02:32:58 AM UTC 24 |
113021970484 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1835164157 |
|
|
Oct 15 02:28:51 AM UTC 24 |
Oct 15 02:33:02 AM UTC 24 |
33786700700 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.566767923 |
|
|
Oct 15 02:30:16 AM UTC 24 |
Oct 15 02:33:10 AM UTC 24 |
14104003811 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2447108010 |
|
|
Oct 15 02:33:11 AM UTC 24 |
Oct 15 02:33:18 AM UTC 24 |
1416492877 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.527935359 |
|
|
Oct 15 02:27:18 AM UTC 24 |
Oct 15 02:33:22 AM UTC 24 |
14419041947 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2200740991 |
|
|
Oct 15 02:21:47 AM UTC 24 |
Oct 15 02:33:24 AM UTC 24 |
80777907305 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.776525046 |
|
|
Oct 15 02:32:27 AM UTC 24 |
Oct 15 02:33:24 AM UTC 24 |
2979374769 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.152184903 |
|
|
Oct 15 02:33:02 AM UTC 24 |
Oct 15 02:33:31 AM UTC 24 |
1914959362 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_readback_err.3474312641 |
|
|
Oct 15 02:33:25 AM UTC 24 |
Oct 15 02:33:34 AM UTC 24 |
7349756234 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3074910398 |
|
|
Oct 15 02:33:35 AM UTC 24 |
Oct 15 02:33:38 AM UTC 24 |
21812334 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.1281925997 |
|
|
Oct 15 02:29:49 AM UTC 24 |
Oct 15 02:33:41 AM UTC 24 |
3799717437 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3799373395 |
|
|
Oct 15 02:33:25 AM UTC 24 |
Oct 15 02:33:42 AM UTC 24 |
5040995167 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.2625440920 |
|
|
Oct 15 02:33:38 AM UTC 24 |
Oct 15 02:33:50 AM UTC 24 |
679152539 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3859933 |
|
|
Oct 15 02:26:33 AM UTC 24 |
Oct 15 02:33:54 AM UTC 24 |
16022864894 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2509569357 |
|
|
Oct 15 02:32:10 AM UTC 24 |
Oct 15 02:34:01 AM UTC 24 |
6361057597 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.1262989627 |
|
|
Oct 15 02:00:46 AM UTC 24 |
Oct 15 02:34:11 AM UTC 24 |
116140811140 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2268751505 |
|
|
Oct 15 02:32:32 AM UTC 24 |
Oct 15 02:34:12 AM UTC 24 |
40619119404 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3465648406 |
|
|
Oct 15 02:33:55 AM UTC 24 |
Oct 15 02:34:12 AM UTC 24 |
1573271311 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.3725026817 |
|
|
Oct 15 02:33:42 AM UTC 24 |
Oct 15 02:34:25 AM UTC 24 |
1822268633 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.2900712210 |
|
|
Oct 15 02:22:57 AM UTC 24 |
Oct 15 02:34:28 AM UTC 24 |
17095746475 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.4256586047 |
|
|
Oct 15 02:34:12 AM UTC 24 |
Oct 15 02:34:29 AM UTC 24 |
2845683523 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.70951039 |
|
|
Oct 15 02:34:12 AM UTC 24 |
Oct 15 02:34:33 AM UTC 24 |
737222777 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2952268489 |
|
|
Oct 15 02:34:34 AM UTC 24 |
Oct 15 02:34:40 AM UTC 24 |
363377407 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.2150267789 |
|
|
Oct 15 02:07:41 AM UTC 24 |
Oct 15 02:34:43 AM UTC 24 |
207084242979 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.3098862785 |
|
|
Oct 15 01:50:01 AM UTC 24 |
Oct 15 02:34:59 AM UTC 24 |
70426880949 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.130565851 |
|
|
Oct 15 02:34:13 AM UTC 24 |
Oct 15 02:35:01 AM UTC 24 |
14187389262 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_readback_err.4245671623 |
|
|
Oct 15 02:35:00 AM UTC 24 |
Oct 15 02:35:12 AM UTC 24 |
668728453 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2189675585 |
|
|
Oct 15 02:33:23 AM UTC 24 |
Oct 15 02:35:22 AM UTC 24 |
10951706063 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.1044419350 |
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Oct 15 02:35:23 AM UTC 24 |
Oct 15 02:35:25 AM UTC 24 |
35439396 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3184656313 |
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Oct 15 02:32:00 AM UTC 24 |
Oct 15 02:35:32 AM UTC 24 |
16312831433 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.120374287 |
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Oct 15 02:25:38 AM UTC 24 |
Oct 15 02:35:59 AM UTC 24 |
42149030586 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.3297160408 |
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Oct 15 02:35:26 AM UTC 24 |
Oct 15 02:36:01 AM UTC 24 |
789812723 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3791137611 |
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Oct 15 02:28:13 AM UTC 24 |
Oct 15 02:36:05 AM UTC 24 |
23115830791 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1198515101 |
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Oct 15 02:35:02 AM UTC 24 |
Oct 15 02:36:17 AM UTC 24 |
2901900982 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1451140199 |
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Oct 15 02:36:06 AM UTC 24 |
Oct 15 02:36:23 AM UTC 24 |
870105949 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.1501604705 |
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Oct 15 02:27:07 AM UTC 24 |
Oct 15 02:36:32 AM UTC 24 |
23487693951 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.852658812 |
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Oct 15 02:34:44 AM UTC 24 |
Oct 15 02:36:47 AM UTC 24 |
5860676029 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1062947451 |
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Oct 15 02:36:33 AM UTC 24 |
Oct 15 02:36:56 AM UTC 24 |
2930404749 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2599459866 |
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Oct 15 02:33:19 AM UTC 24 |
Oct 15 02:37:12 AM UTC 24 |
103516714430 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.2611760455 |
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Oct 15 02:19:20 AM UTC 24 |
Oct 15 02:37:13 AM UTC 24 |
40689515826 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.495163018 |
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Oct 15 02:24:11 AM UTC 24 |
Oct 15 02:37:46 AM UTC 24 |
20906535410 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.276970828 |
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Oct 15 02:37:46 AM UTC 24 |
Oct 15 02:37:53 AM UTC 24 |
3044544620 ps |