| T555 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.452450685 |
|
|
Feb 08 04:41:15 PM UTC 25 |
Feb 08 05:01:33 PM UTC 25 |
32703100927 ps |
| T556 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3815627097 |
|
|
Feb 08 05:01:10 PM UTC 25 |
Feb 08 05:01:35 PM UTC 25 |
1892155634 ps |
| T557 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.367305916 |
|
|
Feb 08 02:49:55 PM UTC 25 |
Feb 08 05:01:42 PM UTC 25 |
298897572008 ps |
| T113 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2725514250 |
|
|
Feb 08 04:59:57 PM UTC 25 |
Feb 08 05:02:12 PM UTC 25 |
8618310231 ps |
| T558 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1945014237 |
|
|
Feb 08 05:01:36 PM UTC 25 |
Feb 08 05:02:15 PM UTC 25 |
742201239 ps |
| T559 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.3188748754 |
|
|
Feb 08 04:48:23 PM UTC 25 |
Feb 08 05:02:18 PM UTC 25 |
12090552703 ps |
| T560 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.3451171966 |
|
|
Feb 08 04:47:03 PM UTC 25 |
Feb 08 05:02:24 PM UTC 25 |
6471449364 ps |
| T561 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2398336533 |
|
|
Feb 08 05:02:25 PM UTC 25 |
Feb 08 05:02:31 PM UTC 25 |
721214143 ps |
| T562 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2281068556 |
|
|
Feb 08 04:52:35 PM UTC 25 |
Feb 08 05:02:32 PM UTC 25 |
43995949463 ps |
| T563 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.847050172 |
|
|
Feb 08 05:01:34 PM UTC 25 |
Feb 08 05:02:56 PM UTC 25 |
3154090438 ps |
| T564 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.994195098 |
|
|
Feb 08 04:55:51 PM UTC 25 |
Feb 08 05:02:57 PM UTC 25 |
5408553586 ps |
| T565 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1272160605 |
|
|
Feb 08 04:59:56 PM UTC 25 |
Feb 08 05:02:57 PM UTC 25 |
19080635068 ps |
| T566 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.1241831900 |
|
|
Feb 08 05:02:58 PM UTC 25 |
Feb 08 05:03:01 PM UTC 25 |
30337925 ps |
| T567 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.3244123162 |
|
|
Feb 08 05:03:01 PM UTC 25 |
Feb 08 05:03:16 PM UTC 25 |
10007786228 ps |
| T568 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3152667040 |
|
|
Feb 08 05:01:44 PM UTC 25 |
Feb 08 05:03:50 PM UTC 25 |
23039246748 ps |
| T569 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.3565636728 |
|
|
Feb 08 05:02:16 PM UTC 25 |
Feb 08 05:04:28 PM UTC 25 |
2477779480 ps |
| T570 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.458377452 |
|
|
Feb 08 05:04:39 PM UTC 25 |
Feb 08 05:04:55 PM UTC 25 |
458083187 ps |
| T571 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1758272123 |
|
|
Feb 08 05:02:57 PM UTC 25 |
Feb 08 05:04:55 PM UTC 25 |
2770169404 ps |
| T572 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.266071518 |
|
|
Feb 08 04:57:57 PM UTC 25 |
Feb 08 05:04:59 PM UTC 25 |
10938985045 ps |
| T573 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3813979114 |
|
|
Feb 08 04:59:50 PM UTC 25 |
Feb 08 05:05:06 PM UTC 25 |
5253796951 ps |
| T574 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2605016530 |
|
|
Feb 08 05:04:56 PM UTC 25 |
Feb 08 05:05:14 PM UTC 25 |
3107903354 ps |
| T575 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3418907417 |
|
|
Feb 08 05:04:59 PM UTC 25 |
Feb 08 05:05:26 PM UTC 25 |
1496408125 ps |
| T576 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2065303988 |
|
|
Feb 08 04:14:35 PM UTC 25 |
Feb 08 05:05:32 PM UTC 25 |
72310575954 ps |
| T577 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.2646031634 |
|
|
Feb 08 05:05:33 PM UTC 25 |
Feb 08 05:05:40 PM UTC 25 |
1246971557 ps |
| T89 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.525931218 |
|
|
Feb 08 05:02:33 PM UTC 25 |
Feb 08 05:05:52 PM UTC 25 |
5522028044 ps |
| T578 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.385824297 |
|
|
Feb 08 05:05:04 PM UTC 25 |
Feb 08 05:05:52 PM UTC 25 |
4577732776 ps |
| T579 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.533557792 |
|
|
Feb 08 04:47:22 PM UTC 25 |
Feb 08 05:06:05 PM UTC 25 |
173297740084 ps |
| T580 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.3487596975 |
|
|
Feb 08 04:58:15 PM UTC 25 |
Feb 08 05:06:07 PM UTC 25 |
68461787738 ps |
| T581 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3888098813 |
|
|
Feb 08 05:06:08 PM UTC 25 |
Feb 08 05:06:10 PM UTC 25 |
38925051 ps |
| T582 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.302070295 |
|
|
Feb 08 05:02:32 PM UTC 25 |
Feb 08 05:06:15 PM UTC 25 |
15731126752 ps |
| T583 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.1365711411 |
|
|
Feb 08 05:06:11 PM UTC 25 |
Feb 08 05:06:24 PM UTC 25 |
1688396715 ps |
| T584 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3545655813 |
|
|
Feb 08 05:05:53 PM UTC 25 |
Feb 08 05:06:37 PM UTC 25 |
2759961832 ps |
| T585 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.3117405472 |
|
|
Feb 08 05:06:51 PM UTC 25 |
Feb 08 05:07:10 PM UTC 25 |
11111481866 ps |
| T586 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.2326335271 |
|
|
Feb 08 04:53:25 PM UTC 25 |
Feb 08 05:07:29 PM UTC 25 |
16331884246 ps |
| T587 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1759527720 |
|
|
Feb 08 04:10:50 PM UTC 25 |
Feb 08 05:07:30 PM UTC 25 |
718169159406 ps |
| T588 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.1459198173 |
|
|
Feb 08 04:56:52 PM UTC 25 |
Feb 08 05:07:31 PM UTC 25 |
69555707917 ps |
| T589 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.292433439 |
|
|
Feb 08 05:07:32 PM UTC 25 |
Feb 08 05:07:38 PM UTC 25 |
1463227052 ps |
| T590 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.70745834 |
|
|
Feb 08 05:07:10 PM UTC 25 |
Feb 08 05:07:44 PM UTC 25 |
1485366018 ps |
| T591 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.4161796252 |
|
|
Feb 08 04:50:29 PM UTC 25 |
Feb 08 05:07:48 PM UTC 25 |
85843734887 ps |
| T592 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1741613127 |
|
|
Feb 08 05:00:36 PM UTC 25 |
Feb 08 05:07:49 PM UTC 25 |
19201618068 ps |
| T593 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.596123315 |
|
|
Feb 08 05:06:31 PM UTC 25 |
Feb 08 05:07:50 PM UTC 25 |
504101125 ps |
| T594 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.3132299644 |
|
|
Feb 08 05:07:52 PM UTC 25 |
Feb 08 05:07:54 PM UTC 25 |
12608912 ps |
| T595 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1142706362 |
|
|
Feb 08 05:07:48 PM UTC 25 |
Feb 08 05:08:03 PM UTC 25 |
1217368767 ps |
| T596 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.3661923815 |
|
|
Feb 08 04:56:41 PM UTC 25 |
Feb 08 05:08:06 PM UTC 25 |
28727961001 ps |
| T597 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.590626209 |
|
|
Feb 08 05:07:55 PM UTC 25 |
Feb 08 05:08:15 PM UTC 25 |
2048748003 ps |
| T598 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2178885780 |
|
|
Feb 08 05:05:40 PM UTC 25 |
Feb 08 05:08:16 PM UTC 25 |
28755142168 ps |
| T599 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.1988067183 |
|
|
Feb 08 05:07:31 PM UTC 25 |
Feb 08 05:08:18 PM UTC 25 |
4310912822 ps |
| T600 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1602124322 |
|
|
Feb 08 05:08:15 PM UTC 25 |
Feb 08 05:08:39 PM UTC 25 |
963240534 ps |
| T601 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.2772546291 |
|
|
Feb 08 05:04:29 PM UTC 25 |
Feb 08 05:08:45 PM UTC 25 |
3119268384 ps |
| T602 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1827266472 |
|
|
Feb 08 04:59:31 PM UTC 25 |
Feb 08 05:08:47 PM UTC 25 |
9749597202 ps |
| T603 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.592190465 |
|
|
Feb 08 05:05:53 PM UTC 25 |
Feb 08 05:08:50 PM UTC 25 |
3155004887 ps |
| T604 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2152398267 |
|
|
Feb 08 05:08:18 PM UTC 25 |
Feb 08 05:08:51 PM UTC 25 |
2974442043 ps |
| T605 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.3450107102 |
|
|
Feb 08 04:57:28 PM UTC 25 |
Feb 08 05:08:57 PM UTC 25 |
63330448555 ps |
| T606 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.4241188779 |
|
|
Feb 08 05:08:52 PM UTC 25 |
Feb 08 05:08:58 PM UTC 25 |
1399607495 ps |
| T607 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2168497300 |
|
|
Feb 08 05:07:44 PM UTC 25 |
Feb 08 05:09:04 PM UTC 25 |
962322568 ps |
| T608 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3510299043 |
|
|
Feb 08 05:07:15 PM UTC 25 |
Feb 08 05:09:08 PM UTC 25 |
24767254557 ps |
| T609 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2273928048 |
|
|
Feb 08 05:09:09 PM UTC 25 |
Feb 08 05:09:11 PM UTC 25 |
44263788 ps |
| T610 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3484313562 |
|
|
Feb 08 05:08:45 PM UTC 25 |
Feb 08 05:09:17 PM UTC 25 |
15025664386 ps |
| T611 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.1896658241 |
|
|
Feb 08 04:50:46 PM UTC 25 |
Feb 08 05:09:19 PM UTC 25 |
124740157813 ps |
| T612 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.3769369953 |
|
|
Feb 08 05:09:12 PM UTC 25 |
Feb 08 05:09:30 PM UTC 25 |
2860580881 ps |
| T613 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2090758480 |
|
|
Feb 08 05:05:15 PM UTC 25 |
Feb 08 05:09:32 PM UTC 25 |
5285773409 ps |
| T614 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.4087148816 |
|
|
Feb 08 05:09:33 PM UTC 25 |
Feb 08 05:09:55 PM UTC 25 |
809041312 ps |
| T615 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.620903150 |
|
|
Feb 08 05:08:39 PM UTC 25 |
Feb 08 05:09:57 PM UTC 25 |
765970294 ps |
| T616 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2526242542 |
|
|
Feb 08 05:09:04 PM UTC 25 |
Feb 08 05:09:57 PM UTC 25 |
4653015234 ps |
| T617 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.61523668 |
|
|
Feb 08 05:09:57 PM UTC 25 |
Feb 08 05:10:17 PM UTC 25 |
1622839728 ps |
| T618 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.569516554 |
|
|
Feb 08 05:01:18 PM UTC 25 |
Feb 08 05:10:28 PM UTC 25 |
66339386295 ps |
| T619 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.3159700147 |
|
|
Feb 08 05:03:18 PM UTC 25 |
Feb 08 05:10:45 PM UTC 25 |
23436430908 ps |
| T620 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.1990582048 |
|
|
Feb 08 05:09:57 PM UTC 25 |
Feb 08 05:10:45 PM UTC 25 |
1508377915 ps |
| T621 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1037691012 |
|
|
Feb 08 04:48:09 PM UTC 25 |
Feb 08 05:11:12 PM UTC 25 |
113636896969 ps |
| T622 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.2209640090 |
|
|
Feb 08 05:04:55 PM UTC 25 |
Feb 08 05:11:16 PM UTC 25 |
19620386964 ps |
| T623 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.109154071 |
|
|
Feb 08 05:11:13 PM UTC 25 |
Feb 08 05:11:19 PM UTC 25 |
378468221 ps |
| T624 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.794966831 |
|
|
Feb 08 05:05:07 PM UTC 25 |
Feb 08 05:11:32 PM UTC 25 |
29364833713 ps |
| T625 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1779907604 |
|
|
Feb 08 05:08:59 PM UTC 25 |
Feb 08 05:11:33 PM UTC 25 |
7346900917 ps |
| T626 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.2588710866 |
|
|
Feb 08 05:06:17 PM UTC 25 |
Feb 08 05:11:41 PM UTC 25 |
43195113570 ps |
| T627 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.4232158922 |
|
|
Feb 08 05:11:42 PM UTC 25 |
Feb 08 05:11:44 PM UTC 25 |
23029715 ps |
| T628 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2889864545 |
|
|
Feb 08 05:06:25 PM UTC 25 |
Feb 08 05:11:46 PM UTC 25 |
8013569101 ps |
| T629 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.2256000713 |
|
|
Feb 08 05:10:17 PM UTC 25 |
Feb 08 05:11:52 PM UTC 25 |
36584066545 ps |
| T630 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.106490851 |
|
|
Feb 08 05:11:45 PM UTC 25 |
Feb 08 05:12:09 PM UTC 25 |
392510498 ps |
| T114 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3810260473 |
|
|
Feb 08 05:11:32 PM UTC 25 |
Feb 08 05:12:34 PM UTC 25 |
7279487532 ps |
| T631 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.2545229415 |
|
|
Feb 08 05:08:58 PM UTC 25 |
Feb 08 05:12:45 PM UTC 25 |
54440430160 ps |
| T632 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2128771857 |
|
|
Feb 08 05:12:35 PM UTC 25 |
Feb 08 05:12:54 PM UTC 25 |
1813309378 ps |
| T90 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.595286511 |
|
|
Feb 08 05:11:20 PM UTC 25 |
Feb 08 05:12:55 PM UTC 25 |
1401836465 ps |
| T633 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.3510910921 |
|
|
Feb 08 05:08:07 PM UTC 25 |
Feb 08 05:12:59 PM UTC 25 |
4113518154 ps |
| T634 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.1600298483 |
|
|
Feb 08 05:10:47 PM UTC 25 |
Feb 08 05:13:16 PM UTC 25 |
6020038383 ps |
| T635 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1472238107 |
|
|
Feb 08 05:12:55 PM UTC 25 |
Feb 08 05:13:29 PM UTC 25 |
2582774706 ps |
| T636 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1330957635 |
|
|
Feb 08 05:12:48 PM UTC 25 |
Feb 08 05:13:33 PM UTC 25 |
1216994756 ps |
| T637 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1889211611 |
|
|
Feb 08 05:13:34 PM UTC 25 |
Feb 08 05:13:41 PM UTC 25 |
1341009911 ps |
| T638 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2046490097 |
|
|
Feb 08 05:06:38 PM UTC 25 |
Feb 08 05:13:42 PM UTC 25 |
58794305260 ps |
| T639 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.463350512 |
|
|
Feb 08 05:12:56 PM UTC 25 |
Feb 08 05:14:00 PM UTC 25 |
31404449933 ps |
| T640 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.492043251 |
|
|
Feb 08 04:49:39 PM UTC 25 |
Feb 08 05:14:03 PM UTC 25 |
57678144122 ps |
| T641 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1720414598 |
|
|
Feb 08 05:07:39 PM UTC 25 |
Feb 08 05:14:09 PM UTC 25 |
108823622379 ps |
| T642 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.550640186 |
|
|
Feb 08 05:14:10 PM UTC 25 |
Feb 08 05:14:12 PM UTC 25 |
16048415 ps |
| T643 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1320414001 |
|
|
Feb 08 05:14:01 PM UTC 25 |
Feb 08 05:14:17 PM UTC 25 |
446342773 ps |
| T644 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3274190905 |
|
|
Feb 08 05:07:57 PM UTC 25 |
Feb 08 05:14:24 PM UTC 25 |
7011951068 ps |
| T645 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.2845884664 |
|
|
Feb 08 05:14:13 PM UTC 25 |
Feb 08 05:15:29 PM UTC 25 |
4117693578 ps |
| T646 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.491225153 |
|
|
Feb 08 05:13:43 PM UTC 25 |
Feb 08 05:15:33 PM UTC 25 |
4831043938 ps |
| T647 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2518005371 |
|
|
Feb 08 05:07:26 PM UTC 25 |
Feb 08 05:15:35 PM UTC 25 |
18379780512 ps |
| T648 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.3248041659 |
|
|
Feb 08 05:09:31 PM UTC 25 |
Feb 08 05:15:38 PM UTC 25 |
17495104439 ps |
| T649 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.58224222 |
|
|
Feb 08 05:12:59 PM UTC 25 |
Feb 08 05:16:06 PM UTC 25 |
4067661334 ps |
| T650 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.3860704674 |
|
|
Feb 08 05:15:30 PM UTC 25 |
Feb 08 05:16:10 PM UTC 25 |
821209283 ps |
| T651 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3909786472 |
|
|
Feb 08 05:15:36 PM UTC 25 |
Feb 08 05:16:13 PM UTC 25 |
729883384 ps |
| T652 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1970172228 |
|
|
Feb 08 05:02:13 PM UTC 25 |
Feb 08 05:16:21 PM UTC 25 |
25576191953 ps |
| T653 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.4179791571 |
|
|
Feb 08 05:13:43 PM UTC 25 |
Feb 08 05:16:26 PM UTC 25 |
25625430947 ps |
| T654 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1255100844 |
|
|
Feb 08 05:16:27 PM UTC 25 |
Feb 08 05:16:33 PM UTC 25 |
400453901 ps |
| T655 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.861463485 |
|
|
Feb 08 05:25:57 PM UTC 25 |
Feb 08 05:27:11 PM UTC 25 |
11400956871 ps |
| T656 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3973621289 |
|
|
Feb 08 05:15:38 PM UTC 25 |
Feb 08 05:16:37 PM UTC 25 |
8400934921 ps |
| T657 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.486335684 |
|
|
Feb 08 05:05:27 PM UTC 25 |
Feb 08 05:16:40 PM UTC 25 |
43979990149 ps |
| T658 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.3782335976 |
|
|
Feb 08 05:06:22 PM UTC 25 |
Feb 08 05:17:02 PM UTC 25 |
39059409214 ps |
| T659 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.668499924 |
|
|
Feb 08 05:09:18 PM UTC 25 |
Feb 08 05:17:11 PM UTC 25 |
6411915912 ps |
| T660 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.690847996 |
|
|
Feb 08 05:17:11 PM UTC 25 |
Feb 08 05:17:13 PM UTC 25 |
55400030 ps |
| T661 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3954819256 |
|
|
Feb 08 05:16:41 PM UTC 25 |
Feb 08 05:17:19 PM UTC 25 |
750234789 ps |
| T662 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.2585475259 |
|
|
Feb 08 04:59:23 PM UTC 25 |
Feb 08 05:17:27 PM UTC 25 |
22366722153 ps |
| T663 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1907641406 |
|
|
Feb 08 05:11:17 PM UTC 25 |
Feb 08 05:17:35 PM UTC 25 |
53088016508 ps |
| T664 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.501265240 |
|
|
Feb 08 05:12:10 PM UTC 25 |
Feb 08 05:17:53 PM UTC 25 |
18664275900 ps |
| T665 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2615540409 |
|
|
Feb 08 05:16:06 PM UTC 25 |
Feb 08 05:18:09 PM UTC 25 |
57050812218 ps |
| T666 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.1656626369 |
|
|
Feb 08 05:14:18 PM UTC 25 |
Feb 08 05:18:10 PM UTC 25 |
13010525838 ps |
| T667 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1196983926 |
|
|
Feb 08 05:17:54 PM UTC 25 |
Feb 08 05:18:25 PM UTC 25 |
4372636162 ps |
| T668 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.2508229328 |
|
|
Feb 08 05:18:11 PM UTC 25 |
Feb 08 05:18:25 PM UTC 25 |
2734594048 ps |
| T669 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.2662217397 |
|
|
Feb 08 05:09:56 PM UTC 25 |
Feb 08 05:18:27 PM UTC 25 |
18437181603 ps |
| T670 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.3787674678 |
|
|
Feb 08 05:17:14 PM UTC 25 |
Feb 08 05:18:44 PM UTC 25 |
781043359 ps |
| T671 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.4224954770 |
|
|
Feb 08 05:16:10 PM UTC 25 |
Feb 08 05:18:46 PM UTC 25 |
10594240706 ps |
| T672 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3397674910 |
|
|
Feb 08 05:16:34 PM UTC 25 |
Feb 08 05:19:09 PM UTC 25 |
7358579339 ps |
| T673 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.337421497 |
|
|
Feb 08 05:18:26 PM UTC 25 |
Feb 08 05:19:12 PM UTC 25 |
8930988179 ps |
| T674 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3043825410 |
|
|
Feb 08 05:18:26 PM UTC 25 |
Feb 08 05:19:17 PM UTC 25 |
3108075085 ps |
| T675 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.3920174286 |
|
|
Feb 08 05:19:10 PM UTC 25 |
Feb 08 05:19:17 PM UTC 25 |
350066411 ps |
| T676 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2290145228 |
|
|
Feb 08 05:16:38 PM UTC 25 |
Feb 08 05:19:31 PM UTC 25 |
4881755042 ps |
| T677 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.3002502729 |
|
|
Feb 08 05:08:51 PM UTC 25 |
Feb 08 05:19:42 PM UTC 25 |
44069108226 ps |
| T678 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1760572458 |
|
|
Feb 08 05:19:17 PM UTC 25 |
Feb 08 05:19:43 PM UTC 25 |
667604628 ps |
| T679 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1749177529 |
|
|
Feb 08 05:19:43 PM UTC 25 |
Feb 08 05:19:45 PM UTC 25 |
34652539 ps |
| T680 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.43224243 |
|
|
Feb 08 05:16:22 PM UTC 25 |
Feb 08 05:19:51 PM UTC 25 |
5266711172 ps |
| T681 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2873295244 |
|
|
Feb 08 05:19:44 PM UTC 25 |
Feb 08 05:20:00 PM UTC 25 |
1900681417 ps |
| T682 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.9428254 |
|
|
Feb 08 04:57:49 PM UTC 25 |
Feb 08 05:20:01 PM UTC 25 |
131837281097 ps |
| T683 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.3791809796 |
|
|
Feb 08 04:52:03 PM UTC 25 |
Feb 08 05:20:26 PM UTC 25 |
40830637417 ps |
| T684 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3633864464 |
|
|
Feb 08 05:11:47 PM UTC 25 |
Feb 08 05:20:48 PM UTC 25 |
99001419887 ps |
| T685 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1866959479 |
|
|
Feb 08 05:20:02 PM UTC 25 |
Feb 08 05:21:00 PM UTC 25 |
8624529414 ps |
| T686 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.452164484 |
|
|
Feb 08 05:08:48 PM UTC 25 |
Feb 08 05:21:00 PM UTC 25 |
57128127546 ps |
| T687 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2906036675 |
|
|
Feb 08 05:19:17 PM UTC 25 |
Feb 08 05:21:08 PM UTC 25 |
37408900187 ps |
| T688 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2780689820 |
|
|
Feb 08 05:08:17 PM UTC 25 |
Feb 08 05:21:19 PM UTC 25 |
226998881190 ps |
| T689 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.837204287 |
|
|
Feb 08 05:17:37 PM UTC 25 |
Feb 08 05:21:39 PM UTC 25 |
11826680747 ps |
| T690 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4277099106 |
|
|
Feb 08 05:21:40 PM UTC 25 |
Feb 08 05:21:47 PM UTC 25 |
1351791607 ps |
| T691 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2941537022 |
|
|
Feb 08 05:20:01 PM UTC 25 |
Feb 08 05:21:56 PM UTC 25 |
8919918625 ps |
| T692 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.430390327 |
|
|
Feb 08 05:02:19 PM UTC 25 |
Feb 08 05:22:04 PM UTC 25 |
105620927978 ps |
| T693 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.3435540692 |
|
|
Feb 08 05:20:49 PM UTC 25 |
Feb 08 05:22:06 PM UTC 25 |
8375329577 ps |
| T694 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.2968142046 |
|
|
Feb 08 05:20:46 PM UTC 25 |
Feb 08 05:22:06 PM UTC 25 |
3127151264 ps |
| T695 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.1326010555 |
|
|
Feb 08 04:35:57 PM UTC 25 |
Feb 08 05:22:08 PM UTC 25 |
110300064388 ps |
| T696 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3324246471 |
|
|
Feb 08 05:22:07 PM UTC 25 |
Feb 08 05:22:09 PM UTC 25 |
12724705 ps |
| T697 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2248901454 |
|
|
Feb 08 05:21:01 PM UTC 25 |
Feb 08 05:22:19 PM UTC 25 |
35138435423 ps |
| T698 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.2827200562 |
|
|
Feb 08 05:12:46 PM UTC 25 |
Feb 08 05:22:37 PM UTC 25 |
52280223252 ps |
| T115 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2896714024 |
|
|
Feb 08 05:22:04 PM UTC 25 |
Feb 08 05:22:45 PM UTC 25 |
4105081697 ps |
| T699 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.3339384413 |
|
|
Feb 08 05:22:09 PM UTC 25 |
Feb 08 05:22:48 PM UTC 25 |
2011366573 ps |
| T700 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.824799505 |
|
|
Feb 08 05:14:42 PM UTC 25 |
Feb 08 05:22:55 PM UTC 25 |
22874644109 ps |
| T701 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3555722361 |
|
|
Feb 08 05:22:38 PM UTC 25 |
Feb 08 05:22:57 PM UTC 25 |
5804397125 ps |
| T702 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3094485921 |
|
|
Feb 08 05:22:58 PM UTC 25 |
Feb 08 05:23:19 PM UTC 25 |
1724868758 ps |
| T703 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1232858908 |
|
|
Feb 08 05:18:46 PM UTC 25 |
Feb 08 05:23:30 PM UTC 25 |
15717468258 ps |
| T704 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2246930682 |
|
|
Feb 08 05:22:48 PM UTC 25 |
Feb 08 05:23:35 PM UTC 25 |
1508214337 ps |
| T705 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1811167548 |
|
|
Feb 08 05:23:36 PM UTC 25 |
Feb 08 05:23:44 PM UTC 25 |
929353106 ps |
| T706 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.4220086175 |
|
|
Feb 08 05:22:56 PM UTC 25 |
Feb 08 05:24:03 PM UTC 25 |
1580523060 ps |
| T707 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.1636770435 |
|
|
Feb 08 04:55:30 PM UTC 25 |
Feb 08 05:24:39 PM UTC 25 |
23999418812 ps |
| T708 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2187085721 |
|
|
Feb 08 05:21:01 PM UTC 25 |
Feb 08 05:24:45 PM UTC 25 |
19006268273 ps |
| T709 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.324967769 |
|
|
Feb 08 05:24:46 PM UTC 25 |
Feb 08 05:24:48 PM UTC 25 |
30157392 ps |
| T710 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.2398787092 |
|
|
Feb 08 04:44:34 PM UTC 25 |
Feb 08 05:24:49 PM UTC 25 |
132571202755 ps |
| T711 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1569971750 |
|
|
Feb 08 04:40:32 PM UTC 25 |
Feb 08 05:24:51 PM UTC 25 |
194805041844 ps |
| T712 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.3057307379 |
|
|
Feb 08 05:18:45 PM UTC 25 |
Feb 08 05:25:14 PM UTC 25 |
21424736341 ps |
| T713 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.241686907 |
|
|
Feb 08 05:24:49 PM UTC 25 |
Feb 08 05:25:17 PM UTC 25 |
849217929 ps |
| T714 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3779815081 |
|
|
Feb 08 05:21:57 PM UTC 25 |
Feb 08 05:25:22 PM UTC 25 |
21846772694 ps |
| T715 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1114244800 |
|
|
Feb 08 05:25:17 PM UTC 25 |
Feb 08 05:25:42 PM UTC 25 |
933559774 ps |
| T716 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2023978036 |
|
|
Feb 08 05:07:30 PM UTC 25 |
Feb 08 05:25:56 PM UTC 25 |
31634321710 ps |
| T717 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.97596604 |
|
|
Feb 08 05:17:19 PM UTC 25 |
Feb 08 05:26:01 PM UTC 25 |
57090847152 ps |
| T718 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1355735859 |
|
|
Feb 08 05:10:46 PM UTC 25 |
Feb 08 05:26:11 PM UTC 25 |
73362275304 ps |
| T719 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2963691836 |
|
|
Feb 08 05:24:04 PM UTC 25 |
Feb 08 05:26:27 PM UTC 25 |
6371743273 ps |
| T720 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1305577182 |
|
|
Feb 08 05:15:34 PM UTC 25 |
Feb 08 05:26:33 PM UTC 25 |
19692935485 ps |
| T721 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1682512383 |
|
|
Feb 08 05:19:12 PM UTC 25 |
Feb 08 05:26:37 PM UTC 25 |
82828423309 ps |
| T722 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.974636246 |
|
|
Feb 08 05:13:30 PM UTC 25 |
Feb 08 05:26:39 PM UTC 25 |
80154100477 ps |
| T723 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2485242935 |
|
|
Feb 08 05:26:34 PM UTC 25 |
Feb 08 05:26:41 PM UTC 25 |
693740142 ps |
| T724 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1330805200 |
|
|
Feb 08 05:23:44 PM UTC 25 |
Feb 08 05:26:44 PM UTC 25 |
2634286745 ps |
| T725 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.1619502799 |
|
|
Feb 08 05:25:47 PM UTC 25 |
Feb 08 05:26:51 PM UTC 25 |
1602003375 ps |
| T726 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.4263616474 |
|
|
Feb 08 05:26:52 PM UTC 25 |
Feb 08 05:26:54 PM UTC 25 |
12566766 ps |
| T727 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.447194331 |
|
|
Feb 08 05:22:20 PM UTC 25 |
Feb 08 05:27:03 PM UTC 25 |
3793941051 ps |
| T728 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1649281133 |
|
|
Feb 08 05:08:51 PM UTC 25 |
Feb 08 05:27:05 PM UTC 25 |
20813924201 ps |
| T729 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.3874089272 |
|
|
Feb 08 05:26:55 PM UTC 25 |
Feb 08 05:27:09 PM UTC 25 |
2427919908 ps |
| T730 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3811427630 |
|
|
Feb 08 05:00:25 PM UTC 25 |
Feb 08 05:27:10 PM UTC 25 |
102445298735 ps |
| T731 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.2578076309 |
|
|
Feb 08 05:25:44 PM UTC 25 |
Feb 08 05:27:17 PM UTC 25 |
3039447912 ps |
| T732 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.4188767451 |
|
|
Feb 08 05:27:11 PM UTC 25 |
Feb 08 05:27:24 PM UTC 25 |
2730483576 ps |
| T733 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3757356071 |
|
|
Feb 08 05:18:10 PM UTC 25 |
Feb 08 05:27:39 PM UTC 25 |
90403069141 ps |
| T734 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3125980654 |
|
|
Feb 08 05:26:42 PM UTC 25 |
Feb 08 05:27:41 PM UTC 25 |
4541420888 ps |
| T735 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.812271425 |
|
|
Feb 08 05:08:04 PM UTC 25 |
Feb 08 05:27:41 PM UTC 25 |
230767428392 ps |
| T736 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2257381576 |
|
|
Feb 08 05:24:21 PM UTC 25 |
Feb 08 05:27:57 PM UTC 25 |
1728988987 ps |
| T737 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2321003411 |
|
|
Feb 08 05:21:48 PM UTC 25 |
Feb 08 05:27:58 PM UTC 25 |
10718853218 ps |
| T738 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4072734971 |
|
|
Feb 08 05:22:11 PM UTC 25 |
Feb 08 05:27:59 PM UTC 25 |
35480804260 ps |
| T739 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.3298179839 |
|
|
Feb 08 05:11:52 PM UTC 25 |
Feb 08 05:28:03 PM UTC 25 |
14010736255 ps |
| T740 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1849877263 |
|
|
Feb 08 05:27:59 PM UTC 25 |
Feb 08 05:28:05 PM UTC 25 |
2143402457 ps |
| T741 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.4259589548 |
|
|
Feb 08 05:16:15 PM UTC 25 |
Feb 08 05:28:05 PM UTC 25 |
38211288030 ps |
| T742 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.2321283782 |
|
|
Feb 08 05:10:29 PM UTC 25 |
Feb 08 05:28:12 PM UTC 25 |
55373353127 ps |
| T743 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3068627180 |
|
|
Feb 08 05:28:12 PM UTC 25 |
Feb 08 05:28:14 PM UTC 25 |
22964234 ps |
| T744 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.956405529 |
|
|
Feb 08 05:26:40 PM UTC 25 |
Feb 08 05:28:15 PM UTC 25 |
2781644881 ps |
| T116 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1945342413 |
|
|
Feb 08 05:28:06 PM UTC 25 |
Feb 08 05:28:22 PM UTC 25 |
260168337 ps |
| T745 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.2894331568 |
|
|
Feb 08 04:49:22 PM UTC 25 |
Feb 08 05:28:22 PM UTC 25 |
147594423227 ps |
| T746 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2068114591 |
|
|
Feb 08 05:18:28 PM UTC 25 |
Feb 08 05:28:27 PM UTC 25 |
6386702557 ps |
| T747 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.4013700580 |
|
|
Feb 08 05:28:15 PM UTC 25 |
Feb 08 05:28:27 PM UTC 25 |
682729304 ps |
| T748 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2560365652 |
|
|
Feb 08 05:27:24 PM UTC 25 |
Feb 08 05:28:33 PM UTC 25 |
1576926093 ps |
| T749 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.567045045 |
|
|
Feb 08 05:22:46 PM UTC 25 |
Feb 08 05:28:36 PM UTC 25 |
37372478497 ps |
| T750 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.3768634898 |
|
|
Feb 08 05:27:18 PM UTC 25 |
Feb 08 05:28:46 PM UTC 25 |
1178414494 ps |
| T751 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3303780364 |
|
|
Feb 08 05:28:28 PM UTC 25 |
Feb 08 05:28:50 PM UTC 25 |
1029393647 ps |
| T752 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.2771846010 |
|
|
Feb 08 05:28:37 PM UTC 25 |
Feb 08 05:29:07 PM UTC 25 |
1498369001 ps |
| T753 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.758683074 |
|
|
Feb 08 05:23:36 PM UTC 25 |
Feb 08 05:29:26 PM UTC 25 |
31147905171 ps |
| T754 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.174326193 |
|
|
Feb 08 05:28:34 PM UTC 25 |
Feb 08 05:29:50 PM UTC 25 |
753518531 ps |
| T755 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.241396646 |
|
|
Feb 08 05:27:39 PM UTC 25 |
Feb 08 05:29:52 PM UTC 25 |
13566945271 ps |
| T756 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.979764683 |
|
|
Feb 08 05:21:20 PM UTC 25 |
Feb 08 05:29:53 PM UTC 25 |
4221667613 ps |
| T757 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.2641049261 |
|
|
Feb 08 05:29:50 PM UTC 25 |
Feb 08 05:29:56 PM UTC 25 |
364607953 ps |
| T758 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.210758384 |
|
|
Feb 08 05:28:04 PM UTC 25 |
Feb 08 05:30:10 PM UTC 25 |
3203237498 ps |
| T759 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1960204184 |
|
|
Feb 08 04:41:19 PM UTC 25 |
Feb 08 05:30:19 PM UTC 25 |
317246177459 ps |
| T760 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1787515500 |
|
|
Feb 08 05:30:20 PM UTC 25 |
Feb 08 05:30:22 PM UTC 25 |
60974136 ps |
| T761 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3413208623 |
|
|
Feb 08 05:29:57 PM UTC 25 |
Feb 08 05:30:26 PM UTC 25 |
1276663346 ps |
| T762 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.3494371395 |
|
|
Feb 08 05:30:23 PM UTC 25 |
Feb 08 05:30:30 PM UTC 25 |
356358703 ps |
| T763 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2887477482 |
|
|
Feb 08 05:25:14 PM UTC 25 |
Feb 08 05:30:48 PM UTC 25 |
17617444994 ps |
| T764 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.211655286 |
|
|
Feb 08 05:26:37 PM UTC 25 |
Feb 08 05:31:04 PM UTC 25 |
43162234654 ps |
| T765 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3612863547 |
|
|
Feb 08 05:28:47 PM UTC 25 |
Feb 08 05:31:07 PM UTC 25 |
13527064739 ps |
| T766 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.4293614642 |
|
|
Feb 08 05:31:04 PM UTC 25 |
Feb 08 05:31:17 PM UTC 25 |
1496469604 ps |
| T767 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.20700681 |
|
|
Feb 08 05:20:27 PM UTC 25 |
Feb 08 05:31:19 PM UTC 25 |
24389334774 ps |
| T768 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2466210165 |
|
|
Feb 08 05:27:12 PM UTC 25 |
Feb 08 05:31:20 PM UTC 25 |
3193436632 ps |
| T769 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3357863436 |
|
|
Feb 08 05:29:54 PM UTC 25 |
Feb 08 05:31:23 PM UTC 25 |
3424812359 ps |
| T770 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.795340815 |
|
|
Feb 08 05:25:22 PM UTC 25 |
Feb 08 05:31:34 PM UTC 25 |
6630733018 ps |
| T771 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.342279111 |
|
|
Feb 08 05:28:51 PM UTC 25 |
Feb 08 05:31:36 PM UTC 25 |
4351585468 ps |
| T772 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.4213706628 |
|
|
Feb 08 05:26:28 PM UTC 25 |
Feb 08 05:32:07 PM UTC 25 |
7988103339 ps |
| T773 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1313786426 |
|
|
Feb 08 05:32:08 PM UTC 25 |
Feb 08 05:32:14 PM UTC 25 |
674798535 ps |
| T774 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.4199879703 |
|
|
Feb 08 05:27:10 PM UTC 25 |
Feb 08 05:32:19 PM UTC 25 |
3616214089 ps |
| T775 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.1646220061 |
|
|
Feb 08 05:23:32 PM UTC 25 |
Feb 08 05:32:20 PM UTC 25 |
10045838213 ps |
| T776 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1460807263 |
|
|
Feb 08 05:30:27 PM UTC 25 |
Feb 08 05:32:24 PM UTC 25 |
5952674551 ps |
| T777 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.1521494914 |
|
|
Feb 08 05:31:19 PM UTC 25 |
Feb 08 05:32:25 PM UTC 25 |
784887881 ps |
| T778 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2210429646 |
|
|
Feb 08 05:32:25 PM UTC 25 |
Feb 08 05:32:27 PM UTC 25 |
16412892 ps |
| T779 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.472821441 |
|
|
Feb 08 05:31:20 PM UTC 25 |
Feb 08 05:32:38 PM UTC 25 |
31845239836 ps |
| T780 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1108788179 |
|
|
Feb 08 05:31:18 PM UTC 25 |
Feb 08 05:32:40 PM UTC 25 |
1573778810 ps |
| T781 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.505127119 |
|
|
Feb 08 05:29:52 PM UTC 25 |
Feb 08 05:32:50 PM UTC 25 |
34521300326 ps |
| T782 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.718756921 |
|
|
Feb 08 05:32:28 PM UTC 25 |
Feb 08 05:32:58 PM UTC 25 |
3246277161 ps |
| T783 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.3988722797 |
|
|
Feb 08 05:29:27 PM UTC 25 |
Feb 08 05:33:11 PM UTC 25 |
4224325568 ps |
| T784 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1684196047 |
|
|
Feb 08 05:28:00 PM UTC 25 |
Feb 08 05:33:21 PM UTC 25 |
25003503931 ps |
| T785 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.153127884 |
|
|
Feb 08 05:28:23 PM UTC 25 |
Feb 08 05:33:33 PM UTC 25 |
7158994822 ps |
| T786 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.92449221 |
|
|
Feb 08 05:33:22 PM UTC 25 |
Feb 08 05:34:11 PM UTC 25 |
742152722 ps |
| T787 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.355125606 |
|
|
Feb 08 05:33:34 PM UTC 25 |
Feb 08 05:34:12 PM UTC 25 |
724185880 ps |
| T788 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3230837417 |
|
|
Feb 08 05:32:19 PM UTC 25 |
Feb 08 05:34:13 PM UTC 25 |
47147894082 ps |
| T789 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3635212812 |
|
|
Feb 08 05:30:49 PM UTC 25 |
Feb 08 05:34:16 PM UTC 25 |
12812751749 ps |
| T790 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3138798101 |
|
|
Feb 08 05:34:17 PM UTC 25 |
Feb 08 05:34:24 PM UTC 25 |
1403936570 ps |
| T791 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3756826247 |
|
|
Feb 08 05:32:59 PM UTC 25 |
Feb 08 05:34:27 PM UTC 25 |
1025414489 ps |
| T792 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2713510077 |
|
|
Feb 08 05:32:21 PM UTC 25 |
Feb 08 05:34:35 PM UTC 25 |
4286699299 ps |
| T793 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3696348235 |
|
|
Feb 08 05:34:36 PM UTC 25 |
Feb 08 05:35:01 PM UTC 25 |
2562461754 ps |
| T794 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.107753657 |
|
|
Feb 08 05:24:50 PM UTC 25 |
Feb 08 05:35:18 PM UTC 25 |
13797403414 ps |
| T795 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1601070459 |
|
|
Feb 08 05:35:19 PM UTC 25 |
Feb 08 05:35:21 PM UTC 25 |
49254504 ps |
| T796 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.444696707 |
|
|
Feb 08 05:34:03 PM UTC 25 |
Feb 08 05:35:22 PM UTC 25 |
15745010678 ps |
| T797 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.4080701635 |
|
|
Feb 08 05:35:22 PM UTC 25 |
Feb 08 05:35:37 PM UTC 25 |
943047747 ps |
| T798 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1368874189 |
|
|
Feb 08 05:31:08 PM UTC 25 |
Feb 08 05:35:41 PM UTC 25 |
16830294607 ps |