| T799 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.505152126 |
|
|
Feb 08 05:34:13 PM UTC 25 |
Feb 08 05:35:51 PM UTC 25 |
2031884243 ps |
| T800 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2123968825 |
|
|
Feb 08 05:34:28 PM UTC 25 |
Feb 08 05:36:30 PM UTC 25 |
1646475136 ps |
| T801 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3568756099 |
|
|
Feb 08 05:26:02 PM UTC 25 |
Feb 08 05:36:31 PM UTC 25 |
6788110561 ps |
| T802 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1599989705 |
|
|
Feb 08 05:35:52 PM UTC 25 |
Feb 08 05:36:39 PM UTC 25 |
763169018 ps |
| T803 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3609372525 |
|
|
Feb 08 05:34:25 PM UTC 25 |
Feb 08 05:37:15 PM UTC 25 |
11619761436 ps |
| T804 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2575739446 |
|
|
Feb 08 05:36:32 PM UTC 25 |
Feb 08 05:37:16 PM UTC 25 |
3026881336 ps |
| T805 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1781321639 |
|
|
Feb 08 05:28:15 PM UTC 25 |
Feb 08 05:37:28 PM UTC 25 |
56477957692 ps |
| T806 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.2662091638 |
|
|
Feb 08 05:26:11 PM UTC 25 |
Feb 08 05:37:31 PM UTC 25 |
7280863414 ps |
| T807 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.453454359 |
|
|
Feb 08 05:36:39 PM UTC 25 |
Feb 08 05:37:41 PM UTC 25 |
7595268236 ps |
| T808 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3451627254 |
|
|
Feb 08 05:37:43 PM UTC 25 |
Feb 08 05:37:50 PM UTC 25 |
361595061 ps |
| T809 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3705176802 |
|
|
Feb 08 05:32:15 PM UTC 25 |
Feb 08 05:37:58 PM UTC 25 |
42003242833 ps |
| T810 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.3418037582 |
|
|
Feb 08 05:32:51 PM UTC 25 |
Feb 08 05:38:00 PM UTC 25 |
14572469087 ps |
| T811 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1038167007 |
|
|
Feb 08 05:37:58 PM UTC 25 |
Feb 08 05:38:16 PM UTC 25 |
369249528 ps |
| T812 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.264442527 |
|
|
Feb 08 05:29:08 PM UTC 25 |
Feb 08 05:38:19 PM UTC 25 |
13121287185 ps |
| T813 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3151907030 |
|
|
Feb 08 05:38:18 PM UTC 25 |
Feb 08 05:38:20 PM UTC 25 |
16583484 ps |
| T814 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1661930724 |
|
|
Feb 08 05:38:20 PM UTC 25 |
Feb 08 05:38:51 PM UTC 25 |
5558831312 ps |
| T815 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.154333725 |
|
|
Feb 08 05:37:33 PM UTC 25 |
Feb 08 05:39:09 PM UTC 25 |
13957617620 ps |
| T816 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.4032812357 |
|
|
Feb 08 05:21:09 PM UTC 25 |
Feb 08 05:39:55 PM UTC 25 |
31739957956 ps |
| T817 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.4229152239 |
|
|
Feb 08 05:31:36 PM UTC 25 |
Feb 08 05:39:55 PM UTC 25 |
8524672291 ps |
| T818 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2246756217 |
|
|
Feb 08 05:31:24 PM UTC 25 |
Feb 08 05:39:58 PM UTC 25 |
11918935593 ps |
| T819 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.3496722616 |
|
|
Feb 08 05:13:17 PM UTC 25 |
Feb 08 05:40:05 PM UTC 25 |
26393094710 ps |
| T820 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.756096604 |
|
|
Feb 08 05:39:59 PM UTC 25 |
Feb 08 05:40:09 PM UTC 25 |
1361374935 ps |
| T821 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.180815797 |
|
|
Feb 08 05:40:07 PM UTC 25 |
Feb 08 05:40:22 PM UTC 25 |
710076918 ps |
| T822 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3802374007 |
|
|
Feb 08 05:37:15 PM UTC 25 |
Feb 08 05:40:29 PM UTC 25 |
18313671386 ps |
| T823 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.3753667041 |
|
|
Feb 08 05:34:14 PM UTC 25 |
Feb 08 05:40:31 PM UTC 25 |
1784245126 ps |
| T824 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.4035543170 |
|
|
Feb 08 05:19:46 PM UTC 25 |
Feb 08 05:40:36 PM UTC 25 |
50904719225 ps |
| T825 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3782340316 |
|
|
Feb 08 05:40:37 PM UTC 25 |
Feb 08 05:40:44 PM UTC 25 |
354228337 ps |
| T826 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.111659869 |
|
|
Feb 08 05:37:51 PM UTC 25 |
Feb 08 05:41:04 PM UTC 25 |
5263959849 ps |
| T827 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.3596496926 |
|
|
Feb 08 05:03:51 PM UTC 25 |
Feb 08 05:41:05 PM UTC 25 |
90141122848 ps |
| T828 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.302326658 |
|
|
Feb 08 05:39:56 PM UTC 25 |
Feb 08 05:41:15 PM UTC 25 |
4750778578 ps |
| T829 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2300670571 |
|
|
Feb 08 05:23:20 PM UTC 25 |
Feb 08 05:41:18 PM UTC 25 |
65380537507 ps |
| T830 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2363648994 |
|
|
Feb 08 05:41:18 PM UTC 25 |
Feb 08 05:41:20 PM UTC 25 |
60281224 ps |
| T831 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.37475447 |
|
|
Feb 08 05:33:12 PM UTC 25 |
Feb 08 05:41:31 PM UTC 25 |
62751697757 ps |
| T832 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3726490491 |
|
|
Feb 08 05:35:22 PM UTC 25 |
Feb 08 05:41:38 PM UTC 25 |
9111507755 ps |
| T833 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.4218587692 |
|
|
Feb 08 05:27:58 PM UTC 25 |
Feb 08 05:41:40 PM UTC 25 |
3387685449 ps |
| T834 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1383611399 |
|
|
Feb 08 05:36:31 PM UTC 25 |
Feb 08 05:41:54 PM UTC 25 |
11538334433 ps |
| T835 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1211543013 |
|
|
Feb 08 05:40:10 PM UTC 25 |
Feb 08 05:42:02 PM UTC 25 |
38364351939 ps |
| T836 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.3741411413 |
|
|
Feb 08 05:35:42 PM UTC 25 |
Feb 08 05:42:04 PM UTC 25 |
4759105327 ps |
| T837 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.4016982739 |
|
|
Feb 08 05:41:55 PM UTC 25 |
Feb 08 05:42:14 PM UTC 25 |
3184391550 ps |
| T838 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.3597571863 |
|
|
Feb 08 05:42:04 PM UTC 25 |
Feb 08 05:42:16 PM UTC 25 |
842859587 ps |
| T839 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2824372064 |
|
|
Feb 08 05:37:51 PM UTC 25 |
Feb 08 05:42:21 PM UTC 25 |
17134678063 ps |
| T840 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.2252734274 |
|
|
Feb 08 05:27:42 PM UTC 25 |
Feb 08 05:42:33 PM UTC 25 |
82199617560 ps |
| T841 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2696714033 |
|
|
Feb 08 05:28:28 PM UTC 25 |
Feb 08 05:42:38 PM UTC 25 |
81729255041 ps |
| T842 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3192380434 |
|
|
Feb 08 05:42:16 PM UTC 25 |
Feb 08 05:42:41 PM UTC 25 |
9472825924 ps |
| T843 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.441617613 |
|
|
Feb 08 05:42:42 PM UTC 25 |
Feb 08 05:42:49 PM UTC 25 |
1464608683 ps |
| T844 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1331540932 |
|
|
Feb 08 05:41:05 PM UTC 25 |
Feb 08 05:42:51 PM UTC 25 |
2900434404 ps |
| T845 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.3396941818 |
|
|
Feb 08 05:41:22 PM UTC 25 |
Feb 08 05:43:01 PM UTC 25 |
2694637346 ps |
| T846 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.506175738 |
|
|
Feb 08 05:41:05 PM UTC 25 |
Feb 08 05:43:06 PM UTC 25 |
7088549301 ps |
| T847 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.622197649 |
|
|
Feb 08 05:40:45 PM UTC 25 |
Feb 08 05:43:09 PM UTC 25 |
2061803865 ps |
| T848 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.2690589723 |
|
|
Feb 08 05:41:32 PM UTC 25 |
Feb 08 05:43:11 PM UTC 25 |
2204004391 ps |
| T849 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1128775276 |
|
|
Feb 08 05:43:10 PM UTC 25 |
Feb 08 05:43:12 PM UTC 25 |
47025469 ps |
| T850 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1011722155 |
|
|
Feb 08 05:42:14 PM UTC 25 |
Feb 08 05:44:12 PM UTC 25 |
1705285527 ps |
| T851 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2466200707 |
|
|
Feb 08 05:42:52 PM UTC 25 |
Feb 08 05:44:14 PM UTC 25 |
10924788944 ps |
| T117 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.182614542 |
|
|
Feb 08 05:43:02 PM UTC 25 |
Feb 08 05:44:20 PM UTC 25 |
1992898472 ps |
| T852 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.321692260 |
|
|
Feb 08 05:43:12 PM UTC 25 |
Feb 08 05:44:30 PM UTC 25 |
4671294717 ps |
| T853 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.251742338 |
|
|
Feb 08 05:44:21 PM UTC 25 |
Feb 08 05:44:37 PM UTC 25 |
3011313317 ps |
| T854 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.1998707743 |
|
|
Feb 08 05:40:32 PM UTC 25 |
Feb 08 05:44:44 PM UTC 25 |
19039381142 ps |
| T855 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2041793281 |
|
|
Feb 08 05:39:10 PM UTC 25 |
Feb 08 05:44:45 PM UTC 25 |
15554523379 ps |
| T856 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1477786621 |
|
|
Feb 08 05:27:04 PM UTC 25 |
Feb 08 05:44:56 PM UTC 25 |
13203638189 ps |
| T857 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.1851146707 |
|
|
Feb 08 05:42:22 PM UTC 25 |
Feb 08 05:44:57 PM UTC 25 |
3516266242 ps |
| T858 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.740603944 |
|
|
Feb 08 05:44:38 PM UTC 25 |
Feb 08 05:44:58 PM UTC 25 |
1801250925 ps |
| T859 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.2572974964 |
|
|
Feb 08 05:00:26 PM UTC 25 |
Feb 08 05:45:10 PM UTC 25 |
110426871151 ps |
| T860 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3942846843 |
|
|
Feb 08 05:38:21 PM UTC 25 |
Feb 08 05:45:11 PM UTC 25 |
3705074200 ps |
| T861 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.580653163 |
|
|
Feb 08 05:45:11 PM UTC 25 |
Feb 08 05:45:18 PM UTC 25 |
345228724 ps |
| T862 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.4133319610 |
|
|
Feb 08 05:44:46 PM UTC 25 |
Feb 08 05:45:18 PM UTC 25 |
14560069715 ps |
| T863 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2572837678 |
|
|
Feb 08 05:45:19 PM UTC 25 |
Feb 08 05:45:53 PM UTC 25 |
629365082 ps |
| T864 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.3569646352 |
|
|
Feb 08 05:28:22 PM UTC 25 |
Feb 08 05:45:56 PM UTC 25 |
63478233476 ps |
| T865 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3512721272 |
|
|
Feb 08 05:45:57 PM UTC 25 |
Feb 08 05:45:59 PM UTC 25 |
39394107 ps |
| T866 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.3784341514 |
|
|
Feb 08 05:14:25 PM UTC 25 |
Feb 08 05:46:05 PM UTC 25 |
106472323706 ps |
| T867 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3100852421 |
|
|
Feb 08 05:44:45 PM UTC 25 |
Feb 08 05:46:09 PM UTC 25 |
1558618347 ps |
| T868 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.4027164869 |
|
|
Feb 08 05:39:56 PM UTC 25 |
Feb 08 05:46:20 PM UTC 25 |
83369521086 ps |
| T869 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.952994661 |
|
|
Feb 08 05:46:00 PM UTC 25 |
Feb 08 05:46:49 PM UTC 25 |
788218255 ps |
| T870 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.985295288 |
|
|
Feb 08 05:32:42 PM UTC 25 |
Feb 08 05:47:18 PM UTC 25 |
12267285644 ps |
| T871 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.773214511 |
|
|
Feb 08 05:46:50 PM UTC 25 |
Feb 08 05:47:19 PM UTC 25 |
11119081744 ps |
| T872 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3044881590 |
|
|
Feb 08 05:45:11 PM UTC 25 |
Feb 08 05:47:26 PM UTC 25 |
6584791537 ps |
| T873 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.271993900 |
|
|
Feb 08 05:32:38 PM UTC 25 |
Feb 08 05:47:36 PM UTC 25 |
32851169926 ps |
| T874 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.1855412940 |
|
|
Feb 08 04:46:55 PM UTC 25 |
Feb 08 05:47:39 PM UTC 25 |
1005887542450 ps |
| T875 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.697814124 |
|
|
Feb 08 05:09:20 PM UTC 25 |
Feb 08 05:47:47 PM UTC 25 |
103205906437 ps |
| T876 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3793918428 |
|
|
Feb 08 05:37:17 PM UTC 25 |
Feb 08 05:47:52 PM UTC 25 |
15699474932 ps |
| T877 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.208870932 |
|
|
Feb 08 05:41:41 PM UTC 25 |
Feb 08 05:47:58 PM UTC 25 |
4225316682 ps |
| T878 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.829821043 |
|
|
Feb 08 05:47:27 PM UTC 25 |
Feb 08 05:48:02 PM UTC 25 |
5584054932 ps |
| T879 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.4147313010 |
|
|
Feb 08 05:47:59 PM UTC 25 |
Feb 08 05:48:06 PM UTC 25 |
2405006041 ps |
| T880 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1044890828 |
|
|
Feb 08 05:34:12 PM UTC 25 |
Feb 08 05:48:10 PM UTC 25 |
38742390359 ps |
| T881 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.2571620003 |
|
|
Feb 08 05:47:37 PM UTC 25 |
Feb 08 05:48:14 PM UTC 25 |
19667790234 ps |
| T882 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.783278463 |
|
|
Feb 08 05:48:11 PM UTC 25 |
Feb 08 05:48:34 PM UTC 25 |
986329379 ps |
| T883 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3230702244 |
|
|
Feb 08 05:48:35 PM UTC 25 |
Feb 08 05:48:37 PM UTC 25 |
86676284 ps |
| T884 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3061716755 |
|
|
Feb 08 05:47:19 PM UTC 25 |
Feb 08 05:48:50 PM UTC 25 |
791767675 ps |
| T885 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.601128391 |
|
|
Feb 08 05:45:18 PM UTC 25 |
Feb 08 05:48:59 PM UTC 25 |
10213701013 ps |
| T886 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.548795772 |
|
|
Feb 08 05:42:50 PM UTC 25 |
Feb 08 05:49:17 PM UTC 25 |
20665105674 ps |
| T887 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1900664619 |
|
|
Feb 08 05:44:14 PM UTC 25 |
Feb 08 05:49:20 PM UTC 25 |
3886913671 ps |
| T888 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.702828145 |
|
|
Feb 08 05:42:03 PM UTC 25 |
Feb 08 05:49:23 PM UTC 25 |
7134049906 ps |
| T889 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.88374453 |
|
|
Feb 08 05:48:07 PM UTC 25 |
Feb 08 05:49:38 PM UTC 25 |
2750550919 ps |
| T890 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2631251957 |
|
|
Feb 08 05:46:21 PM UTC 25 |
Feb 08 05:49:55 PM UTC 25 |
2831099684 ps |
| T891 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.873544076 |
|
|
Feb 08 05:27:06 PM UTC 25 |
Feb 08 05:49:59 PM UTC 25 |
263646347606 ps |
| T892 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.4074763917 |
|
|
Feb 08 04:27:45 PM UTC 25 |
Feb 08 05:50:03 PM UTC 25 |
1039865886477 ps |
| T893 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2545878829 |
|
|
Feb 08 05:38:01 PM UTC 25 |
Feb 08 05:50:15 PM UTC 25 |
340634335613 ps |
| T894 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1187234790 |
|
|
Feb 08 05:27:42 PM UTC 25 |
Feb 08 05:50:33 PM UTC 25 |
91192371387 ps |
| T895 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2908196476 |
|
|
Feb 08 05:44:31 PM UTC 25 |
Feb 08 05:51:02 PM UTC 25 |
29833001663 ps |
| T896 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.522717493 |
|
|
Feb 08 05:47:18 PM UTC 25 |
Feb 08 05:51:11 PM UTC 25 |
36534612031 ps |
| T897 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.1538363604 |
|
|
Feb 08 05:42:39 PM UTC 25 |
Feb 08 05:51:57 PM UTC 25 |
19089083031 ps |
| T898 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3380341776 |
|
|
Feb 08 03:16:47 PM UTC 25 |
Feb 08 05:52:05 PM UTC 25 |
333839095809 ps |
| T899 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.1771174233 |
|
|
Feb 08 05:44:58 PM UTC 25 |
Feb 08 05:53:59 PM UTC 25 |
17517390374 ps |
| T900 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.482324562 |
|
|
Feb 08 05:48:03 PM UTC 25 |
Feb 08 05:53:59 PM UTC 25 |
39513744842 ps |
| T901 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.1067083476 |
|
|
Feb 08 05:31:37 PM UTC 25 |
Feb 08 05:54:00 PM UTC 25 |
97899376152 ps |
| T902 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.1787306152 |
|
|
Feb 08 05:24:52 PM UTC 25 |
Feb 08 05:54:24 PM UTC 25 |
97543489376 ps |
| T903 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.4293971452 |
|
|
Feb 08 05:37:30 PM UTC 25 |
Feb 08 05:54:55 PM UTC 25 |
27452456799 ps |
| T904 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1840648154 |
|
|
Feb 08 05:02:57 PM UTC 25 |
Feb 08 05:55:26 PM UTC 25 |
21442087742 ps |
| T905 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.8082640 |
|
|
Feb 08 05:24:40 PM UTC 25 |
Feb 08 05:55:32 PM UTC 25 |
86951781926 ps |
| T906 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.30175984 |
|
|
Feb 08 05:38:52 PM UTC 25 |
Feb 08 05:55:42 PM UTC 25 |
240996790591 ps |
| T907 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.1258632785 |
|
|
Feb 08 05:43:13 PM UTC 25 |
Feb 08 05:56:04 PM UTC 25 |
42205675758 ps |
| T908 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.2466554341 |
|
|
Feb 08 05:44:59 PM UTC 25 |
Feb 08 05:56:27 PM UTC 25 |
19361218572 ps |
| T909 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.591623534 |
|
|
Feb 08 05:47:48 PM UTC 25 |
Feb 08 05:56:41 PM UTC 25 |
52628648667 ps |
| T910 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.2475308231 |
|
|
Feb 08 05:22:12 PM UTC 25 |
Feb 08 05:56:42 PM UTC 25 |
59792877958 ps |
| T911 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1404546478 |
|
|
Feb 08 05:40:23 PM UTC 25 |
Feb 08 05:57:41 PM UTC 25 |
129569137130 ps |
| T912 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.2009909976 |
|
|
Feb 08 05:40:30 PM UTC 25 |
Feb 08 05:57:46 PM UTC 25 |
45786855723 ps |
| T913 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.2812785480 |
|
|
Feb 08 05:44:57 PM UTC 25 |
Feb 08 05:58:01 PM UTC 25 |
12678332592 ps |
| T914 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.255540168 |
|
|
Feb 08 05:35:39 PM UTC 25 |
Feb 08 05:58:19 PM UTC 25 |
158483245614 ps |
| T915 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2971790640 |
|
|
Feb 08 04:44:06 PM UTC 25 |
Feb 08 05:58:21 PM UTC 25 |
144276657480 ps |
| T916 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.2152133002 |
|
|
Feb 08 05:44:12 PM UTC 25 |
Feb 08 05:58:26 PM UTC 25 |
11280615176 ps |
| T917 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.2929706391 |
|
|
Feb 08 05:47:40 PM UTC 25 |
Feb 08 05:58:43 PM UTC 25 |
11349675751 ps |
| T918 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.4276122073 |
|
|
Feb 08 05:19:52 PM UTC 25 |
Feb 08 06:00:53 PM UTC 25 |
459786059191 ps |
| T919 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.4206788123 |
|
|
Feb 08 05:42:34 PM UTC 25 |
Feb 08 06:02:04 PM UTC 25 |
95876489432 ps |
| T920 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.719355488 |
|
|
Feb 08 05:46:06 PM UTC 25 |
Feb 08 06:04:13 PM UTC 25 |
48994821714 ps |
| T921 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1146591783 |
|
|
Feb 08 05:19:33 PM UTC 25 |
Feb 08 06:05:21 PM UTC 25 |
24308071384 ps |
| T922 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.2705154660 |
|
|
Feb 08 05:17:28 PM UTC 25 |
Feb 08 06:05:46 PM UTC 25 |
690351734170 ps |
| T923 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2160347672 |
|
|
Feb 08 05:47:53 PM UTC 25 |
Feb 08 06:07:01 PM UTC 25 |
5948992348 ps |
| T924 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.1979042227 |
|
|
Feb 08 05:41:39 PM UTC 25 |
Feb 08 06:09:29 PM UTC 25 |
83876872990 ps |
| T925 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1137945876 |
|
|
Feb 08 05:32:24 PM UTC 25 |
Feb 08 06:09:36 PM UTC 25 |
144467143592 ps |
| T926 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.59386042 |
|
|
Feb 08 05:14:04 PM UTC 25 |
Feb 08 06:10:42 PM UTC 25 |
303620335793 ps |
| T927 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3908498954 |
|
|
Feb 08 05:11:34 PM UTC 25 |
Feb 08 06:10:49 PM UTC 25 |
34854966723 ps |
| T928 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.3209519563 |
|
|
Feb 08 05:30:31 PM UTC 25 |
Feb 08 06:11:35 PM UTC 25 |
33128968319 ps |
| T929 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.3975324910 |
|
|
Feb 08 05:28:06 PM UTC 25 |
Feb 08 06:11:48 PM UTC 25 |
343329584284 ps |
| T930 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3313313972 |
|
|
Feb 08 04:51:28 PM UTC 25 |
Feb 08 06:12:02 PM UTC 25 |
79539010441 ps |
| T931 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1390219209 |
|
|
Feb 08 05:35:02 PM UTC 25 |
Feb 08 06:14:08 PM UTC 25 |
36121090337 ps |
| T932 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.412953305 |
|
|
Feb 08 05:26:45 PM UTC 25 |
Feb 08 06:16:19 PM UTC 25 |
781271861069 ps |
| T933 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.4050398031 |
|
|
Feb 08 05:48:14 PM UTC 25 |
Feb 08 06:17:12 PM UTC 25 |
14261210253 ps |
| T934 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.585558825 |
|
|
Feb 08 04:54:45 PM UTC 25 |
Feb 08 06:18:54 PM UTC 25 |
508873378390 ps |
| T935 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1098870315 |
|
|
Feb 08 05:22:06 PM UTC 25 |
Feb 08 06:19:43 PM UTC 25 |
44652398718 ps |
| T936 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1584412074 |
|
|
Feb 08 05:43:07 PM UTC 25 |
Feb 08 06:23:47 PM UTC 25 |
444905292247 ps |
| T937 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.629759665 |
|
|
Feb 08 05:30:12 PM UTC 25 |
Feb 08 06:27:31 PM UTC 25 |
518691683188 ps |
| T938 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1996484321 |
|
|
Feb 08 05:09:06 PM UTC 25 |
Feb 08 06:30:34 PM UTC 25 |
466944105332 ps |
| T939 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.278465397 |
|
|
Feb 08 05:46:10 PM UTC 25 |
Feb 08 06:31:44 PM UTC 25 |
136345745162 ps |
| T940 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.782383128 |
|
|
Feb 08 04:59:57 PM UTC 25 |
Feb 08 06:37:53 PM UTC 25 |
1022390745251 ps |
| T941 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3317996495 |
|
|
Feb 08 05:41:15 PM UTC 25 |
Feb 08 06:42:12 PM UTC 25 |
194002144965 ps |
| T942 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3764825576 |
|
|
Feb 08 05:07:51 PM UTC 25 |
Feb 08 06:48:43 PM UTC 25 |
70007659108 ps |
| T943 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3422987559 |
|
|
Feb 08 04:57:23 PM UTC 25 |
Feb 08 06:53:56 PM UTC 25 |
273782064889 ps |
| T944 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.939010888 |
|
|
Feb 08 04:34:56 PM UTC 25 |
Feb 08 06:59:05 PM UTC 25 |
459448784558 ps |
| T945 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.687057231 |
|
|
Feb 08 05:17:02 PM UTC 25 |
Feb 08 07:19:37 PM UTC 25 |
3052393918398 ps |
| T946 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2125563302 |
|
|
Feb 08 05:45:54 PM UTC 25 |
Feb 08 07:54:16 PM UTC 25 |
262118639322 ps |
| T947 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1339827093 |
|
|
Feb 08 05:48:50 PM UTC 25 |
Feb 08 05:48:58 PM UTC 25 |
84808796 ps |
| T63 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1396804040 |
|
|
Feb 08 05:49:00 PM UTC 25 |
Feb 08 05:49:02 PM UTC 25 |
24138533 ps |
| T58 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3875943523 |
|
|
Feb 08 05:49:00 PM UTC 25 |
Feb 08 05:49:05 PM UTC 25 |
175240101 ps |
| T64 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2278086019 |
|
|
Feb 08 05:49:03 PM UTC 25 |
Feb 08 05:49:05 PM UTC 25 |
35112154 ps |
| T69 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.511986542 |
|
|
Feb 08 05:49:06 PM UTC 25 |
Feb 08 05:49:08 PM UTC 25 |
38496377 ps |
| T70 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1926564144 |
|
|
Feb 08 05:49:06 PM UTC 25 |
Feb 08 05:49:10 PM UTC 25 |
80111963 ps |
| T98 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.908835872 |
|
|
Feb 08 05:49:09 PM UTC 25 |
Feb 08 05:49:11 PM UTC 25 |
61491068 ps |
| T948 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3803987788 |
|
|
Feb 08 05:49:11 PM UTC 25 |
Feb 08 05:49:20 PM UTC 25 |
456246305 ps |
| T71 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3515718892 |
|
|
Feb 08 05:49:21 PM UTC 25 |
Feb 08 05:49:24 PM UTC 25 |
34012826 ps |
| T59 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3004193061 |
|
|
Feb 08 05:49:20 PM UTC 25 |
Feb 08 05:49:24 PM UTC 25 |
203358629 ps |
| T949 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1181933087 |
|
|
Feb 08 05:49:18 PM UTC 25 |
Feb 08 05:49:24 PM UTC 25 |
273187274 ps |
| T72 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4162278403 |
|
|
Feb 08 05:49:24 PM UTC 25 |
Feb 08 05:49:27 PM UTC 25 |
22670669 ps |
| T73 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2760018587 |
|
|
Feb 08 05:49:25 PM UTC 25 |
Feb 08 05:49:27 PM UTC 25 |
19096644 ps |
| T74 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4249414938 |
|
|
Feb 08 05:49:25 PM UTC 25 |
Feb 08 05:49:27 PM UTC 25 |
26588261 ps |
| T950 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3668971882 |
|
|
Feb 08 05:49:24 PM UTC 25 |
Feb 08 05:49:28 PM UTC 25 |
68361040 ps |
| T75 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2647624883 |
|
|
Feb 08 05:48:38 PM UTC 25 |
Feb 08 05:49:29 PM UTC 25 |
26327612683 ps |
| T76 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1385360010 |
|
|
Feb 08 05:49:30 PM UTC 25 |
Feb 08 05:49:32 PM UTC 25 |
46606171 ps |
| T60 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1481983889 |
|
|
Feb 08 05:49:29 PM UTC 25 |
Feb 08 05:49:33 PM UTC 25 |
1282609761 ps |
| T127 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1333675183 |
|
|
Feb 08 05:49:29 PM UTC 25 |
Feb 08 05:49:34 PM UTC 25 |
511949233 ps |
| T951 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3145584366 |
|
|
Feb 08 05:49:28 PM UTC 25 |
Feb 08 05:49:34 PM UTC 25 |
359796908 ps |
| T952 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1100451006 |
|
|
Feb 08 05:49:33 PM UTC 25 |
Feb 08 05:49:35 PM UTC 25 |
15403727 ps |
| T77 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3070021338 |
|
|
Feb 08 05:49:34 PM UTC 25 |
Feb 08 05:49:37 PM UTC 25 |
110478076 ps |
| T79 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2672275696 |
|
|
Feb 08 05:49:35 PM UTC 25 |
Feb 08 05:49:37 PM UTC 25 |
55919592 ps |
| T99 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4018065477 |
|
|
Feb 08 05:49:35 PM UTC 25 |
Feb 08 05:49:37 PM UTC 25 |
21378389 ps |
| T953 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1674342743 |
|
|
Feb 08 05:49:39 PM UTC 25 |
Feb 08 05:49:41 PM UTC 25 |
13914963 ps |
| T130 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.256940106 |
|
|
Feb 08 05:49:39 PM UTC 25 |
Feb 08 05:49:42 PM UTC 25 |
165847487 ps |
| T954 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4076058444 |
|
|
Feb 08 05:49:36 PM UTC 25 |
Feb 08 05:49:43 PM UTC 25 |
787826176 ps |
| T128 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2312213079 |
|
|
Feb 08 05:49:38 PM UTC 25 |
Feb 08 05:49:43 PM UTC 25 |
272405571 ps |
| T100 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.567981444 |
|
|
Feb 08 05:49:42 PM UTC 25 |
Feb 08 05:49:44 PM UTC 25 |
56815919 ps |
| T101 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4116671992 |
|
|
Feb 08 05:49:44 PM UTC 25 |
Feb 08 05:49:46 PM UTC 25 |
26642066 ps |
| T955 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3585206945 |
|
|
Feb 08 05:49:44 PM UTC 25 |
Feb 08 05:49:46 PM UTC 25 |
43120088 ps |
| T956 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2705779020 |
|
|
Feb 08 05:49:43 PM UTC 25 |
Feb 08 05:49:47 PM UTC 25 |
123092150 ps |
| T957 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2496768197 |
|
|
Feb 08 05:49:45 PM UTC 25 |
Feb 08 05:49:53 PM UTC 25 |
5741566051 ps |
| T131 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3664601474 |
|
|
Feb 08 05:49:48 PM UTC 25 |
Feb 08 05:49:53 PM UTC 25 |
592133636 ps |
| T958 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1418206608 |
|
|
Feb 08 05:49:47 PM UTC 25 |
Feb 08 05:49:54 PM UTC 25 |
330552988 ps |
| T959 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1459336051 |
|
|
Feb 08 05:49:54 PM UTC 25 |
Feb 08 05:49:56 PM UTC 25 |
42432388 ps |
| T960 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4041308992 |
|
|
Feb 08 05:49:55 PM UTC 25 |
Feb 08 05:49:57 PM UTC 25 |
49461185 ps |
| T961 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3732704078 |
|
|
Feb 08 05:49:55 PM UTC 25 |
Feb 08 05:49:58 PM UTC 25 |
33242620 ps |
| T80 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2799504064 |
|
|
Feb 08 05:49:56 PM UTC 25 |
Feb 08 05:49:58 PM UTC 25 |
39951589 ps |
| T102 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.300325681 |
|
|
Feb 08 05:49:57 PM UTC 25 |
Feb 08 05:49:59 PM UTC 25 |
43384501 ps |
| T962 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1774328768 |
|
|
Feb 08 05:50:00 PM UTC 25 |
Feb 08 05:50:02 PM UTC 25 |
67688666 ps |
| T134 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1207702686 |
|
|
Feb 08 05:50:00 PM UTC 25 |
Feb 08 05:50:03 PM UTC 25 |
240404746 ps |
| T963 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1548359975 |
|
|
Feb 08 05:49:58 PM UTC 25 |
Feb 08 05:50:04 PM UTC 25 |
1741046969 ps |
| T103 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1741197795 |
|
|
Feb 08 05:50:03 PM UTC 25 |
Feb 08 05:50:06 PM UTC 25 |
20931649 ps |
| T964 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2372037405 |
|
|
Feb 08 05:49:59 PM UTC 25 |
Feb 08 05:50:08 PM UTC 25 |
530133793 ps |
| T81 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3649140971 |
|
|
Feb 08 05:49:12 PM UTC 25 |
Feb 08 05:50:08 PM UTC 25 |
52770331101 ps |
| T965 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2618699621 |
|
|
Feb 08 05:50:06 PM UTC 25 |
Feb 08 05:50:10 PM UTC 25 |
28904414 ps |
| T966 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.471481008 |
|
|
Feb 08 05:50:03 PM UTC 25 |
Feb 08 05:50:11 PM UTC 25 |
368688113 ps |
| T104 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.475487432 |
|
|
Feb 08 05:50:09 PM UTC 25 |
Feb 08 05:50:11 PM UTC 25 |
15781243 ps |
| T967 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2408795547 |
|
|
Feb 08 05:50:09 PM UTC 25 |
Feb 08 05:50:11 PM UTC 25 |
39135729 ps |
| T132 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1170620373 |
|
|
Feb 08 05:50:07 PM UTC 25 |
Feb 08 05:50:12 PM UTC 25 |
625835436 ps |
| T968 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2244937895 |
|
|
Feb 08 05:50:12 PM UTC 25 |
Feb 08 05:50:15 PM UTC 25 |
32806079 ps |
| T135 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1979370281 |
|
|
Feb 08 05:50:12 PM UTC 25 |
Feb 08 05:50:16 PM UTC 25 |
376151858 ps |
| T969 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1743913569 |
|
|
Feb 08 05:50:10 PM UTC 25 |
Feb 08 05:50:17 PM UTC 25 |
694842843 ps |
| T970 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.40737799 |
|
|
Feb 08 05:50:16 PM UTC 25 |
Feb 08 05:50:18 PM UTC 25 |
27163121 ps |
| T971 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3248828181 |
|
|
Feb 08 05:50:12 PM UTC 25 |
Feb 08 05:50:20 PM UTC 25 |
75674882 ps |
| T972 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1554236520 |
|
|
Feb 08 05:50:18 PM UTC 25 |
Feb 08 05:50:22 PM UTC 25 |
38555325 ps |
| T973 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2732414849 |
|
|
Feb 08 05:50:16 PM UTC 25 |
Feb 08 05:50:22 PM UTC 25 |
1421789159 ps |
| T136 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.732397922 |
|
|
Feb 08 05:50:19 PM UTC 25 |
Feb 08 05:50:23 PM UTC 25 |
330010830 ps |
| T82 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.924985085 |
|
|
Feb 08 05:50:21 PM UTC 25 |
Feb 08 05:50:23 PM UTC 25 |
23538044 ps |
| T83 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3568126881 |
|
|
Feb 08 05:49:28 PM UTC 25 |
Feb 08 05:50:24 PM UTC 25 |
16304314077 ps |
| T974 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3650901397 |
|
|
Feb 08 05:50:22 PM UTC 25 |
Feb 08 05:50:24 PM UTC 25 |
17423765 ps |
| T975 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3067983513 |
|
|
Feb 08 05:50:26 PM UTC 25 |
Feb 08 05:50:28 PM UTC 25 |
16978517 ps |
| T139 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2780599054 |
|
|
Feb 08 05:50:25 PM UTC 25 |
Feb 08 05:50:28 PM UTC 25 |
225225480 ps |
| T976 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3329377787 |
|
|
Feb 08 05:50:25 PM UTC 25 |
Feb 08 05:50:28 PM UTC 25 |
33534697 ps |
| T977 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.459514579 |
|
|
Feb 08 05:50:23 PM UTC 25 |
Feb 08 05:50:30 PM UTC 25 |
389342041 ps |
| T978 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2731424230 |
|
|
Feb 08 05:50:29 PM UTC 25 |
Feb 08 05:50:31 PM UTC 25 |
25007294 ps |
| T979 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4187662777 |
|
|
Feb 08 05:50:33 PM UTC 25 |
Feb 08 05:50:36 PM UTC 25 |
15410905 ps |
| T980 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3040727561 |
|
|
Feb 08 05:50:31 PM UTC 25 |
Feb 08 05:50:36 PM UTC 25 |
77987094 ps |
| T981 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4279034655 |
|
|
Feb 08 05:50:32 PM UTC 25 |
Feb 08 05:50:37 PM UTC 25 |
395491434 ps |
| T982 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.344618374 |
|
|
Feb 08 05:50:36 PM UTC 25 |
Feb 08 05:50:39 PM UTC 25 |
15772868 ps |
| T983 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1205283310 |
|
|
Feb 08 05:50:29 PM UTC 25 |
Feb 08 05:50:39 PM UTC 25 |
377638593 ps |
| T984 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.59764951 |
|
|
Feb 08 05:50:37 PM UTC 25 |
Feb 08 05:50:43 PM UTC 25 |
373349971 ps |
| T140 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1594800708 |
|
|
Feb 08 05:50:40 PM UTC 25 |
Feb 08 05:50:45 PM UTC 25 |
495307688 ps |
| T985 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.223365279 |
|
|
Feb 08 05:50:40 PM UTC 25 |
Feb 08 05:50:46 PM UTC 25 |
92680425 ps |
| T986 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2150396975 |
|
|
Feb 08 05:50:44 PM UTC 25 |
Feb 08 05:50:46 PM UTC 25 |
15357334 ps |
| T987 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3195721300 |
|
|
Feb 08 05:50:46 PM UTC 25 |
Feb 08 05:50:48 PM UTC 25 |
52411353 ps |
| T988 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4142826836 |
|
|
Feb 08 05:50:49 PM UTC 25 |
Feb 08 05:50:54 PM UTC 25 |
59856738 ps |
| T989 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2306101128 |
|
|
Feb 08 05:50:46 PM UTC 25 |
Feb 08 05:50:55 PM UTC 25 |
375194303 ps |
| T990 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.136575115 |
|
|
Feb 08 05:50:56 PM UTC 25 |
Feb 08 05:50:58 PM UTC 25 |
25351840 ps |
| T137 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2708648398 |
|
|
Feb 08 05:50:55 PM UTC 25 |
Feb 08 05:50:59 PM UTC 25 |
325463616 ps |
| T84 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.415262454 |
|
|
Feb 08 05:49:38 PM UTC 25 |
Feb 08 05:51:00 PM UTC 25 |
50316382568 ps |
| T991 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.592531579 |
|
|
Feb 08 05:50:59 PM UTC 25 |
Feb 08 05:51:01 PM UTC 25 |
18012936 ps |
| T91 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1582088223 |
|
|
Feb 08 05:50:11 PM UTC 25 |
Feb 08 05:51:04 PM UTC 25 |
13682353986 ps |
| T992 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.910450779 |
|
|
Feb 08 05:51:00 PM UTC 25 |
Feb 08 05:51:06 PM UTC 25 |
374112320 ps |
| T993 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.112594984 |
|
|
Feb 08 05:51:03 PM UTC 25 |
Feb 08 05:51:06 PM UTC 25 |
542932441 ps |
| T994 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2522114917 |
|
|
Feb 08 05:51:04 PM UTC 25 |
Feb 08 05:51:06 PM UTC 25 |
22287321 ps |
| T92 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3733994549 |
|
|
Feb 08 05:50:17 PM UTC 25 |
Feb 08 05:51:06 PM UTC 25 |
28437683358 ps |
| T995 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3066366662 |
|
|
Feb 08 05:51:02 PM UTC 25 |
Feb 08 05:51:07 PM UTC 25 |
61866903 ps |
| T996 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2721084634 |
|
|
Feb 08 05:51:07 PM UTC 25 |
Feb 08 05:51:09 PM UTC 25 |
19981875 ps |
| T93 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.903142501 |
|
|
Feb 08 05:50:05 PM UTC 25 |
Feb 08 05:51:10 PM UTC 25 |
18093032714 ps |
| T94 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3491456037 |
|
|
Feb 08 05:50:23 PM UTC 25 |
Feb 08 05:51:10 PM UTC 25 |
3894286377 ps |
| T997 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2168218406 |
|
|
Feb 08 05:51:08 PM UTC 25 |
Feb 08 05:51:11 PM UTC 25 |
84863202 ps |
| T998 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1513941916 |
|
|
Feb 08 05:51:09 PM UTC 25 |
Feb 08 05:51:11 PM UTC 25 |
21863024 ps |
| T999 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1408119047 |
|
|
Feb 08 05:51:10 PM UTC 25 |
Feb 08 05:51:13 PM UTC 25 |
83491279 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1640121793 |
|
|
Feb 08 05:51:08 PM UTC 25 |
Feb 08 05:51:14 PM UTC 25 |
31426518 ps |
| T1001 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2598023772 |
|
|
Feb 08 05:51:12 PM UTC 25 |
Feb 08 05:51:16 PM UTC 25 |
370499403 ps |
| T1002 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1771996384 |
|
|
Feb 08 05:51:14 PM UTC 25 |
Feb 08 05:51:16 PM UTC 25 |
13607085 ps |
| T1003 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3059178695 |
|
|
Feb 08 05:51:08 PM UTC 25 |
Feb 08 05:51:16 PM UTC 25 |
2077850896 ps |
| T1004 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.785044860 |
|
|
Feb 08 05:51:12 PM UTC 25 |
Feb 08 05:51:16 PM UTC 25 |
97604262 ps |
| T95 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2021503197 |
|
|
Feb 08 05:49:58 PM UTC 25 |
Feb 08 05:51:17 PM UTC 25 |
7052410887 ps |