| T803 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.351903195 |
|
|
Oct 15 02:34:41 AM UTC 24 |
Oct 15 02:37:55 AM UTC 24 |
6920637960 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.4237542962 |
|
|
Oct 15 02:36:24 AM UTC 24 |
Oct 15 02:38:09 AM UTC 24 |
3001526368 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.274011353 |
|
|
Oct 15 02:27:09 AM UTC 24 |
Oct 15 02:38:14 AM UTC 24 |
9868677635 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_readback_err.2873056098 |
|
|
Oct 15 02:38:09 AM UTC 24 |
Oct 15 02:38:20 AM UTC 24 |
2173069106 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.612938378 |
|
|
Oct 15 02:32:53 AM UTC 24 |
Oct 15 02:38:25 AM UTC 24 |
41787991451 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.2815825223 |
|
|
Oct 15 02:38:26 AM UTC 24 |
Oct 15 02:38:28 AM UTC 24 |
18225742 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2873714547 |
|
|
Oct 15 02:33:51 AM UTC 24 |
Oct 15 02:39:01 AM UTC 24 |
5230001088 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.2521570289 |
|
|
Oct 15 02:36:48 AM UTC 24 |
Oct 15 02:39:01 AM UTC 24 |
12832146133 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2723402859 |
|
|
Oct 15 02:38:16 AM UTC 24 |
Oct 15 02:39:04 AM UTC 24 |
7871090020 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.778143093 |
|
|
Oct 15 02:31:45 AM UTC 24 |
Oct 15 02:39:06 AM UTC 24 |
17777359655 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1465444892 |
|
|
Oct 15 02:39:06 AM UTC 24 |
Oct 15 02:39:15 AM UTC 24 |
850039477 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.4088265767 |
|
|
Oct 15 02:29:25 AM UTC 24 |
Oct 15 02:39:21 AM UTC 24 |
12329237455 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.3751748059 |
|
|
Oct 15 02:30:10 AM UTC 24 |
Oct 15 02:39:24 AM UTC 24 |
47165987978 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3068484448 |
|
|
Oct 15 02:34:02 AM UTC 24 |
Oct 15 02:39:25 AM UTC 24 |
12221395422 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.4004424583 |
|
|
Oct 15 02:37:56 AM UTC 24 |
Oct 15 02:39:25 AM UTC 24 |
2390634157 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1298680140 |
|
|
Oct 15 02:38:29 AM UTC 24 |
Oct 15 02:39:34 AM UTC 24 |
490101743 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.228738149 |
|
|
Oct 15 02:23:26 AM UTC 24 |
Oct 15 02:39:37 AM UTC 24 |
61561360497 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.699064794 |
|
|
Oct 15 02:39:22 AM UTC 24 |
Oct 15 02:39:48 AM UTC 24 |
1635249914 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3692221638 |
|
|
Oct 15 02:39:49 AM UTC 24 |
Oct 15 02:39:56 AM UTC 24 |
1019359136 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.656061829 |
|
|
Oct 15 02:26:54 AM UTC 24 |
Oct 15 02:40:06 AM UTC 24 |
12353042894 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.2941925546 |
|
|
Oct 15 02:06:12 AM UTC 24 |
Oct 15 02:40:10 AM UTC 24 |
112682608712 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.36438335 |
|
|
Oct 15 02:39:26 AM UTC 24 |
Oct 15 02:40:12 AM UTC 24 |
16993494744 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3088476181 |
|
|
Oct 15 02:39:25 AM UTC 24 |
Oct 15 02:40:17 AM UTC 24 |
1225458650 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3276549756 |
|
|
Oct 15 02:22:51 AM UTC 24 |
Oct 15 02:40:21 AM UTC 24 |
114299828224 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_readback_err.613471737 |
|
|
Oct 15 02:40:11 AM UTC 24 |
Oct 15 02:40:22 AM UTC 24 |
3166071467 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.1179493683 |
|
|
Oct 15 02:40:22 AM UTC 24 |
Oct 15 02:40:24 AM UTC 24 |
31056231 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.3240328624 |
|
|
Oct 15 02:37:54 AM UTC 24 |
Oct 15 02:40:36 AM UTC 24 |
2060194720 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.203747733 |
|
|
Oct 15 02:40:13 AM UTC 24 |
Oct 15 02:40:55 AM UTC 24 |
5787052004 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.1057877948 |
|
|
Oct 15 02:37:13 AM UTC 24 |
Oct 15 02:41:11 AM UTC 24 |
13871955514 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.1488323638 |
|
|
Oct 15 02:40:23 AM UTC 24 |
Oct 15 02:41:26 AM UTC 24 |
3097492693 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1232424079 |
|
|
Oct 15 02:41:12 AM UTC 24 |
Oct 15 02:41:33 AM UTC 24 |
5505101833 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2484378583 |
|
|
Oct 15 02:36:18 AM UTC 24 |
Oct 15 02:41:47 AM UTC 24 |
52611730932 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1363304999 |
|
|
Oct 15 02:36:02 AM UTC 24 |
Oct 15 02:41:59 AM UTC 24 |
17762575350 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3195415715 |
|
|
Oct 15 02:41:34 AM UTC 24 |
Oct 15 02:42:01 AM UTC 24 |
2486348264 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.4127892641 |
|
|
Oct 15 02:15:50 AM UTC 24 |
Oct 15 02:42:07 AM UTC 24 |
96794571383 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.2452687584 |
|
|
Oct 15 02:22:59 AM UTC 24 |
Oct 15 02:42:09 AM UTC 24 |
16798818515 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3167967009 |
|
|
Oct 15 02:41:48 AM UTC 24 |
Oct 15 02:42:25 AM UTC 24 |
3067681266 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3423870148 |
|
|
Oct 15 02:42:27 AM UTC 24 |
Oct 15 02:42:34 AM UTC 24 |
1460262055 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3174597054 |
|
|
Oct 15 02:40:07 AM UTC 24 |
Oct 15 02:42:36 AM UTC 24 |
9111622590 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.882051941 |
|
|
Oct 15 02:42:01 AM UTC 24 |
Oct 15 02:42:40 AM UTC 24 |
2100094736 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2738203859 |
|
|
Oct 15 02:24:02 AM UTC 24 |
Oct 15 02:42:50 AM UTC 24 |
25738018038 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_readback_err.1727923215 |
|
|
Oct 15 02:42:41 AM UTC 24 |
Oct 15 02:42:53 AM UTC 24 |
2747854933 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.4166725472 |
|
|
Oct 15 02:41:59 AM UTC 24 |
Oct 15 02:42:54 AM UTC 24 |
29198584817 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.4143310119 |
|
|
Oct 15 02:42:54 AM UTC 24 |
Oct 15 02:42:56 AM UTC 24 |
14333291 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.2991485427 |
|
|
Oct 15 01:50:28 AM UTC 24 |
Oct 15 02:43:41 AM UTC 24 |
243470338213 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.1796654335 |
|
|
Oct 15 02:42:57 AM UTC 24 |
Oct 15 02:43:55 AM UTC 24 |
1651205254 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.717162677 |
|
|
Oct 15 02:23:24 AM UTC 24 |
Oct 15 02:43:56 AM UTC 24 |
23641796396 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1210875578 |
|
|
Oct 15 02:42:37 AM UTC 24 |
Oct 15 02:44:27 AM UTC 24 |
4713549970 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2979654032 |
|
|
Oct 15 02:42:50 AM UTC 24 |
Oct 15 02:44:43 AM UTC 24 |
2125664004 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1706368182 |
|
|
Oct 15 02:44:27 AM UTC 24 |
Oct 15 02:44:55 AM UTC 24 |
906825464 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3261711055 |
|
|
Oct 15 02:39:05 AM UTC 24 |
Oct 15 02:45:11 AM UTC 24 |
9037369875 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2491719500 |
|
|
Oct 15 02:39:02 AM UTC 24 |
Oct 15 02:45:14 AM UTC 24 |
43508795753 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1738491977 |
|
|
Oct 15 02:42:35 AM UTC 24 |
Oct 15 02:45:19 AM UTC 24 |
13845485453 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.2890554712 |
|
|
Oct 15 02:36:01 AM UTC 24 |
Oct 15 02:45:25 AM UTC 24 |
31555436472 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.567780580 |
|
|
Oct 15 02:24:08 AM UTC 24 |
Oct 15 02:46:21 AM UTC 24 |
22509125661 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.4238992601 |
|
|
Oct 15 02:44:56 AM UTC 24 |
Oct 15 02:46:32 AM UTC 24 |
1562253377 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.1292785613 |
|
|
Oct 15 02:45:13 AM UTC 24 |
Oct 15 02:46:39 AM UTC 24 |
1602199081 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1070785415 |
|
|
Oct 15 02:46:33 AM UTC 24 |
Oct 15 02:46:40 AM UTC 24 |
4801412987 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2929608109 |
|
|
Oct 15 02:40:57 AM UTC 24 |
Oct 15 02:46:44 AM UTC 24 |
5283042125 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3769878538 |
|
|
Oct 15 02:39:57 AM UTC 24 |
Oct 15 02:46:49 AM UTC 24 |
21086364012 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_readback_err.4181399356 |
|
|
Oct 15 02:46:44 AM UTC 24 |
Oct 15 02:46:56 AM UTC 24 |
1359304365 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1880769755 |
|
|
Oct 15 02:39:35 AM UTC 24 |
Oct 15 02:46:59 AM UTC 24 |
6668219698 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3997550173 |
|
|
Oct 15 02:47:00 AM UTC 24 |
Oct 15 02:47:02 AM UTC 24 |
16762115 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.708229663 |
|
|
Oct 15 02:45:15 AM UTC 24 |
Oct 15 02:47:11 AM UTC 24 |
11933769936 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1407945807 |
|
|
Oct 15 02:35:34 AM UTC 24 |
Oct 15 02:47:15 AM UTC 24 |
53069877195 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3143600079 |
|
|
Oct 15 02:46:50 AM UTC 24 |
Oct 15 02:47:26 AM UTC 24 |
4381363303 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.2823582049 |
|
|
Oct 15 01:56:10 AM UTC 24 |
Oct 15 02:47:34 AM UTC 24 |
107234174608 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.2041820276 |
|
|
Oct 15 02:34:29 AM UTC 24 |
Oct 15 02:47:38 AM UTC 24 |
12185364538 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3475341798 |
|
|
Oct 15 02:47:36 AM UTC 24 |
Oct 15 02:47:50 AM UTC 24 |
1469875862 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3702589724 |
|
|
Oct 15 02:46:41 AM UTC 24 |
Oct 15 02:47:55 AM UTC 24 |
10283137932 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.4156081414 |
|
|
Oct 15 02:25:40 AM UTC 24 |
Oct 15 02:47:59 AM UTC 24 |
267787604521 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3476728771 |
|
|
Oct 15 02:47:56 AM UTC 24 |
Oct 15 02:48:08 AM UTC 24 |
1234725680 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.922883135 |
|
|
Oct 15 02:47:51 AM UTC 24 |
Oct 15 02:48:12 AM UTC 24 |
1500077705 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.432452251 |
|
|
Oct 15 02:47:03 AM UTC 24 |
Oct 15 02:48:33 AM UTC 24 |
4980287127 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.1140700227 |
|
|
Oct 15 02:47:12 AM UTC 24 |
Oct 15 02:48:43 AM UTC 24 |
1719559827 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.689120453 |
|
|
Oct 15 02:48:00 AM UTC 24 |
Oct 15 02:48:44 AM UTC 24 |
12143724701 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.1702117709 |
|
|
Oct 15 02:48:44 AM UTC 24 |
Oct 15 02:48:51 AM UTC 24 |
350475237 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.4112150020 |
|
|
Oct 15 02:43:57 AM UTC 24 |
Oct 15 02:48:51 AM UTC 24 |
23007544707 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_readback_err.1735182225 |
|
|
Oct 15 02:48:52 AM UTC 24 |
Oct 15 02:49:04 AM UTC 24 |
690339586 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2922244289 |
|
|
Oct 15 02:46:39 AM UTC 24 |
Oct 15 02:49:26 AM UTC 24 |
2039532691 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.3037014714 |
|
|
Oct 15 02:44:43 AM UTC 24 |
Oct 15 02:49:32 AM UTC 24 |
9375987564 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.3786721270 |
|
|
Oct 15 02:49:32 AM UTC 24 |
Oct 15 02:49:34 AM UTC 24 |
43514348 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2928168197 |
|
|
Oct 15 02:40:25 AM UTC 24 |
Oct 15 02:49:40 AM UTC 24 |
12740668607 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.45869298 |
|
|
Oct 15 02:37:14 AM UTC 24 |
Oct 15 02:49:46 AM UTC 24 |
36328416321 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3586746961 |
|
|
Oct 15 02:39:26 AM UTC 24 |
Oct 15 02:49:59 AM UTC 24 |
12672570679 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.583024053 |
|
|
Oct 15 02:41:27 AM UTC 24 |
Oct 15 02:50:03 AM UTC 24 |
18415769774 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.776733816 |
|
|
Oct 15 02:49:35 AM UTC 24 |
Oct 15 02:50:18 AM UTC 24 |
2888709150 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.264459404 |
|
|
Oct 15 02:48:52 AM UTC 24 |
Oct 15 02:50:42 AM UTC 24 |
11001246226 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2608797381 |
|
|
Oct 15 02:50:04 AM UTC 24 |
Oct 15 02:50:49 AM UTC 24 |
808098841 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1769622165 |
|
|
Oct 15 02:39:17 AM UTC 24 |
Oct 15 02:50:56 AM UTC 24 |
177321786778 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.3147708597 |
|
|
Oct 15 02:50:43 AM UTC 24 |
Oct 15 02:51:01 AM UTC 24 |
2874373910 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2412043922 |
|
|
Oct 15 02:49:05 AM UTC 24 |
Oct 15 02:51:08 AM UTC 24 |
2464150080 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.387218212 |
|
|
Oct 15 02:50:50 AM UTC 24 |
Oct 15 02:51:29 AM UTC 24 |
741864038 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1538109294 |
|
|
Oct 15 02:05:45 AM UTC 24 |
Oct 15 02:51:39 AM UTC 24 |
75045490530 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.4012071535 |
|
|
Oct 15 02:48:45 AM UTC 24 |
Oct 15 02:51:43 AM UTC 24 |
7295915470 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.4030119208 |
|
|
Oct 15 02:51:39 AM UTC 24 |
Oct 15 02:51:46 AM UTC 24 |
5589775373 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.474695104 |
|
|
Oct 15 02:34:26 AM UTC 24 |
Oct 15 02:52:21 AM UTC 24 |
19428931138 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_readback_err.2529873172 |
|
|
Oct 15 02:52:22 AM UTC 24 |
Oct 15 02:52:31 AM UTC 24 |
667475383 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.2921734827 |
|
|
Oct 15 02:42:08 AM UTC 24 |
Oct 15 02:52:49 AM UTC 24 |
93402925539 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1478556014 |
|
|
Oct 15 02:32:58 AM UTC 24 |
Oct 15 02:52:49 AM UTC 24 |
19526382217 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1004352348 |
|
|
Oct 15 02:52:50 AM UTC 24 |
Oct 15 02:52:52 AM UTC 24 |
15106014 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.4007108317 |
|
|
Oct 15 02:50:57 AM UTC 24 |
Oct 15 02:53:11 AM UTC 24 |
22767116966 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3597246107 |
|
|
Oct 15 02:51:47 AM UTC 24 |
Oct 15 02:53:29 AM UTC 24 |
1417995097 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1345983635 |
|
|
Oct 15 02:52:32 AM UTC 24 |
Oct 15 02:53:32 AM UTC 24 |
2714103810 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.555315375 |
|
|
Oct 15 02:47:26 AM UTC 24 |
Oct 15 02:53:37 AM UTC 24 |
37381700283 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.3619645224 |
|
|
Oct 15 02:53:38 AM UTC 24 |
Oct 15 02:54:10 AM UTC 24 |
2725577377 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.773114803 |
|
|
Oct 15 02:52:53 AM UTC 24 |
Oct 15 02:54:16 AM UTC 24 |
441893091 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.658633806 |
|
|
Oct 15 02:28:03 AM UTC 24 |
Oct 15 02:54:22 AM UTC 24 |
21751120968 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.2400752670 |
|
|
Oct 15 02:45:26 AM UTC 24 |
Oct 15 02:54:39 AM UTC 24 |
13041579335 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.70208536 |
|
|
Oct 15 02:54:23 AM UTC 24 |
Oct 15 02:54:48 AM UTC 24 |
1322486867 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3255373985 |
|
|
Oct 15 02:49:59 AM UTC 24 |
Oct 15 02:55:00 AM UTC 24 |
12629689698 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.586078035 |
|
|
Oct 15 02:51:45 AM UTC 24 |
Oct 15 02:55:16 AM UTC 24 |
10792510772 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3069241192 |
|
|
Oct 15 02:36:58 AM UTC 24 |
Oct 15 02:55:22 AM UTC 24 |
20655275742 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.3156530520 |
|
|
Oct 15 02:55:23 AM UTC 24 |
Oct 15 02:55:31 AM UTC 24 |
1403490158 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1872723587 |
|
|
Oct 15 02:47:39 AM UTC 24 |
Oct 15 02:55:46 AM UTC 24 |
34337727984 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.283135934 |
|
|
Oct 15 02:54:17 AM UTC 24 |
Oct 15 02:55:53 AM UTC 24 |
1005294203 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.3258924214 |
|
|
Oct 15 02:39:37 AM UTC 24 |
Oct 15 02:55:56 AM UTC 24 |
21286678651 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_readback_err.4196503417 |
|
|
Oct 15 02:55:54 AM UTC 24 |
Oct 15 02:56:07 AM UTC 24 |
1901349347 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2224906121 |
|
|
Oct 15 02:54:40 AM UTC 24 |
Oct 15 02:56:16 AM UTC 24 |
34987249467 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1942202168 |
|
|
Oct 15 02:55:57 AM UTC 24 |
Oct 15 02:56:19 AM UTC 24 |
3229577308 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3116711120 |
|
|
Oct 15 02:56:17 AM UTC 24 |
Oct 15 02:56:19 AM UTC 24 |
17801605 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.203805027 |
|
|
Oct 15 02:48:09 AM UTC 24 |
Oct 15 02:56:31 AM UTC 24 |
72297570865 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.698652946 |
|
|
Oct 15 02:53:33 AM UTC 24 |
Oct 15 02:56:32 AM UTC 24 |
3488957719 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.4140310889 |
|
|
Oct 15 01:43:22 AM UTC 24 |
Oct 15 02:56:41 AM UTC 24 |
193327502247 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2876473810 |
|
|
Oct 15 02:31:18 AM UTC 24 |
Oct 15 02:56:48 AM UTC 24 |
13402556452 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.589898242 |
|
|
Oct 15 02:42:10 AM UTC 24 |
Oct 15 02:56:55 AM UTC 24 |
11458922541 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2373932066 |
|
|
Oct 15 02:55:47 AM UTC 24 |
Oct 15 02:57:21 AM UTC 24 |
2897482739 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.3632125699 |
|
|
Oct 15 02:56:20 AM UTC 24 |
Oct 15 02:57:32 AM UTC 24 |
1059991806 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.617825645 |
|
|
Oct 15 02:18:05 AM UTC 24 |
Oct 15 02:57:37 AM UTC 24 |
368152302277 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3923583044 |
|
|
Oct 15 02:56:42 AM UTC 24 |
Oct 15 02:57:39 AM UTC 24 |
3423354940 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2563326820 |
|
|
Oct 15 02:15:38 AM UTC 24 |
Oct 15 02:57:54 AM UTC 24 |
52673921255 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3166821577 |
|
|
Oct 15 02:56:56 AM UTC 24 |
Oct 15 02:58:03 AM UTC 24 |
780999077 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.268693530 |
|
|
Oct 15 02:58:04 AM UTC 24 |
Oct 15 02:58:12 AM UTC 24 |
3049973477 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3106320944 |
|
|
Oct 15 02:50:19 AM UTC 24 |
Oct 15 02:58:25 AM UTC 24 |
20316786043 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3088743870 |
|
|
Oct 15 02:55:32 AM UTC 24 |
Oct 15 02:58:26 AM UTC 24 |
15180452202 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1208519115 |
|
|
Oct 15 02:54:11 AM UTC 24 |
Oct 15 02:58:29 AM UTC 24 |
8940590001 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.195269584 |
|
|
Oct 15 02:33:43 AM UTC 24 |
Oct 15 02:58:29 AM UTC 24 |
749916510249 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.439930222 |
|
|
Oct 15 02:57:34 AM UTC 24 |
Oct 15 02:58:36 AM UTC 24 |
8123735288 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_readback_err.685004793 |
|
|
Oct 15 02:58:27 AM UTC 24 |
Oct 15 02:58:37 AM UTC 24 |
2824792072 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2076086863 |
|
|
Oct 15 02:58:37 AM UTC 24 |
Oct 15 02:58:39 AM UTC 24 |
21665163 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.2743729668 |
|
|
Oct 15 02:46:22 AM UTC 24 |
Oct 15 02:58:46 AM UTC 24 |
71506835074 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.593330372 |
|
|
Oct 15 02:34:29 AM UTC 24 |
Oct 15 02:58:47 AM UTC 24 |
206739968465 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.2271186641 |
|
|
Oct 15 02:57:21 AM UTC 24 |
Oct 15 02:58:50 AM UTC 24 |
3240214120 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.61118679 |
|
|
Oct 15 01:51:52 AM UTC 24 |
Oct 15 02:58:50 AM UTC 24 |
420520832767 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.3650362409 |
|
|
Oct 15 02:48:13 AM UTC 24 |
Oct 15 02:59:27 AM UTC 24 |
21078157990 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1846829043 |
|
|
Oct 15 02:58:25 AM UTC 24 |
Oct 15 02:59:54 AM UTC 24 |
9830330884 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3999608775 |
|
|
Oct 15 02:25:24 AM UTC 24 |
Oct 15 03:00:07 AM UTC 24 |
58166711940 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.1509681017 |
|
|
Oct 15 02:56:32 AM UTC 24 |
Oct 15 03:00:12 AM UTC 24 |
8718493404 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1906088815 |
|
|
Oct 15 02:45:20 AM UTC 24 |
Oct 15 03:00:17 AM UTC 24 |
22408623404 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.226672980 |
|
|
Oct 15 02:43:42 AM UTC 24 |
Oct 15 03:00:37 AM UTC 24 |
214118397209 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3516122899 |
|
|
Oct 15 02:40:18 AM UTC 24 |
Oct 15 03:00:44 AM UTC 24 |
34518486977 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.515545555 |
|
|
Oct 15 02:31:39 AM UTC 24 |
Oct 15 03:01:03 AM UTC 24 |
62519547964 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1123816872 |
|
|
Oct 15 02:58:12 AM UTC 24 |
Oct 15 03:01:05 AM UTC 24 |
6925096209 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3372911484 |
|
|
Oct 15 02:58:30 AM UTC 24 |
Oct 15 03:01:06 AM UTC 24 |
5417253228 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.2198680511 |
|
|
Oct 15 02:55:17 AM UTC 24 |
Oct 15 03:01:30 AM UTC 24 |
8869137300 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.2044290989 |
|
|
Oct 15 02:51:09 AM UTC 24 |
Oct 15 03:01:58 AM UTC 24 |
48193783011 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3108443023 |
|
|
Oct 15 02:48:33 AM UTC 24 |
Oct 15 03:02:23 AM UTC 24 |
12700446689 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.490710793 |
|
|
Oct 15 02:51:02 AM UTC 24 |
Oct 15 03:03:27 AM UTC 24 |
13821529086 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.1043224180 |
|
|
Oct 15 02:49:47 AM UTC 24 |
Oct 15 03:03:36 AM UTC 24 |
148265870467 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1383489260 |
|
|
Oct 15 01:36:37 AM UTC 24 |
Oct 15 03:04:01 AM UTC 24 |
171402817255 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3369684058 |
|
|
Oct 15 02:53:11 AM UTC 24 |
Oct 15 03:05:16 AM UTC 24 |
31402236085 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.261981392 |
|
|
Oct 15 02:54:49 AM UTC 24 |
Oct 15 03:06:19 AM UTC 24 |
29390213450 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.3088201694 |
|
|
Oct 15 02:40:37 AM UTC 24 |
Oct 15 03:06:26 AM UTC 24 |
311462011544 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3870384291 |
|
|
Oct 15 02:56:49 AM UTC 24 |
Oct 15 03:07:55 AM UTC 24 |
26026369895 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2627075301 |
|
|
Oct 15 01:57:53 AM UTC 24 |
Oct 15 03:08:14 AM UTC 24 |
151551627285 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.528786775 |
|
|
Oct 15 01:25:36 AM UTC 24 |
Oct 15 03:09:24 AM UTC 24 |
86127244835 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.1968843018 |
|
|
Oct 15 02:47:16 AM UTC 24 |
Oct 15 03:09:41 AM UTC 24 |
276847694661 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.539123066 |
|
|
Oct 15 02:57:55 AM UTC 24 |
Oct 15 03:11:00 AM UTC 24 |
17089091487 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3170201171 |
|
|
Oct 15 02:57:38 AM UTC 24 |
Oct 15 03:11:04 AM UTC 24 |
61822596199 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.1631980223 |
|
|
Oct 15 02:21:07 AM UTC 24 |
Oct 15 03:13:21 AM UTC 24 |
133748392056 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.736631700 |
|
|
Oct 15 02:33:32 AM UTC 24 |
Oct 15 03:14:10 AM UTC 24 |
167939694616 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2471397117 |
|
|
Oct 15 01:11:54 AM UTC 24 |
Oct 15 03:14:44 AM UTC 24 |
863783071784 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.3220290434 |
|
|
Oct 15 02:55:01 AM UTC 24 |
Oct 15 03:14:46 AM UTC 24 |
107351939745 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3004995150 |
|
|
Oct 15 02:58:31 AM UTC 24 |
Oct 15 03:14:56 AM UTC 24 |
8704339084 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2646138377 |
|
|
Oct 15 02:27:43 AM UTC 24 |
Oct 15 03:15:13 AM UTC 24 |
93098818807 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.529731155 |
|
|
Oct 15 02:00:35 AM UTC 24 |
Oct 15 03:16:12 AM UTC 24 |
893683847306 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.204809735 |
|
|
Oct 15 02:56:20 AM UTC 24 |
Oct 15 03:16:13 AM UTC 24 |
25773013785 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.560329888 |
|
|
Oct 15 02:49:40 AM UTC 24 |
Oct 15 03:16:35 AM UTC 24 |
52779802551 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3554535322 |
|
|
Oct 15 01:40:58 AM UTC 24 |
Oct 15 03:18:20 AM UTC 24 |
1527721300776 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1120440196 |
|
|
Oct 15 02:38:21 AM UTC 24 |
Oct 15 03:18:36 AM UTC 24 |
86435190739 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.744009685 |
|
|
Oct 15 02:23:18 AM UTC 24 |
Oct 15 03:19:02 AM UTC 24 |
191026585799 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.2202441235 |
|
|
Oct 15 02:51:29 AM UTC 24 |
Oct 15 03:19:55 AM UTC 24 |
18136361747 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3886072136 |
|
|
Oct 15 01:16:33 AM UTC 24 |
Oct 15 03:20:30 AM UTC 24 |
200010296623 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1557153121 |
|
|
Oct 15 02:57:40 AM UTC 24 |
Oct 15 03:20:52 AM UTC 24 |
125438717960 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.2953952022 |
|
|
Oct 15 02:53:31 AM UTC 24 |
Oct 15 03:22:32 AM UTC 24 |
374257332206 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3347687818 |
|
|
Oct 15 02:20:34 AM UTC 24 |
Oct 15 03:22:53 AM UTC 24 |
372484870351 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3057849020 |
|
|
Oct 15 01:31:46 AM UTC 24 |
Oct 15 03:23:13 AM UTC 24 |
477280886370 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.3170091765 |
|
|
Oct 15 02:39:02 AM UTC 24 |
Oct 15 03:23:19 AM UTC 24 |
152468318409 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1593120108 |
|
|
Oct 15 02:43:56 AM UTC 24 |
Oct 15 03:24:41 AM UTC 24 |
383721212560 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.90752208 |
|
|
Oct 15 02:09:37 AM UTC 24 |
Oct 15 03:26:41 AM UTC 24 |
46300923629 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3598501241 |
|
|
Oct 15 01:18:11 AM UTC 24 |
Oct 15 03:27:37 AM UTC 24 |
436414337155 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.744600646 |
|
|
Oct 15 02:17:39 AM UTC 24 |
Oct 15 03:37:49 AM UTC 24 |
1289014504488 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.726197348 |
|
|
Oct 15 02:56:32 AM UTC 24 |
Oct 15 03:40:11 AM UTC 24 |
498420513854 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1311960150 |
|
|
Oct 15 02:12:33 AM UTC 24 |
Oct 15 03:52:07 AM UTC 24 |
64687617873 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3211649381 |
|
|
Oct 15 02:02:39 AM UTC 24 |
Oct 15 03:57:32 AM UTC 24 |
1298369512320 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1853469322 |
|
|
Oct 15 02:46:57 AM UTC 24 |
Oct 15 03:57:37 AM UTC 24 |
306345718919 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.2981676180 |
|
|
Oct 15 02:49:27 AM UTC 24 |
Oct 15 04:03:32 AM UTC 24 |
509760917497 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1829275159 |
|
|
Oct 15 02:42:53 AM UTC 24 |
Oct 15 04:31:28 AM UTC 24 |
1432231295661 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1915791062 |
|
|
Oct 15 02:52:50 AM UTC 24 |
Oct 15 04:32:26 AM UTC 24 |
223035425184 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3536070228 |
|
|
Oct 15 02:56:08 AM UTC 24 |
Oct 15 04:35:30 AM UTC 24 |
283601168775 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1015388922 |
|
|
Oct 15 02:30:58 AM UTC 24 |
Oct 15 04:54:36 AM UTC 24 |
3599568342599 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1717964335 |
|
|
Oct 15 02:58:40 AM UTC 24 |
Oct 15 02:58:47 AM UTC 24 |
130083141 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.243899518 |
|
|
Oct 15 02:58:48 AM UTC 24 |
Oct 15 02:58:50 AM UTC 24 |
37265045 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2760407636 |
|
|
Oct 15 02:58:48 AM UTC 24 |
Oct 15 02:58:50 AM UTC 24 |
32166938 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2714408037 |
|
|
Oct 15 02:58:47 AM UTC 24 |
Oct 15 02:58:51 AM UTC 24 |
990897347 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1357163134 |
|
|
Oct 15 02:58:51 AM UTC 24 |
Oct 15 02:58:53 AM UTC 24 |
56367026 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3699000948 |
|
|
Oct 15 02:58:51 AM UTC 24 |
Oct 15 02:58:54 AM UTC 24 |
32147359 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1050342668 |
|
|
Oct 15 02:58:51 AM UTC 24 |
Oct 15 02:58:56 AM UTC 24 |
349148874 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1766106610 |
|
|
Oct 15 03:00:36 AM UTC 24 |
Oct 15 03:00:44 AM UTC 24 |
141855339 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1170866586 |
|
|
Oct 15 02:58:55 AM UTC 24 |
Oct 15 02:58:59 AM UTC 24 |
348046874 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2918053945 |
|
|
Oct 15 02:58:57 AM UTC 24 |
Oct 15 02:58:59 AM UTC 24 |
51961971 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4125515659 |
|
|
Oct 15 02:58:54 AM UTC 24 |
Oct 15 02:58:59 AM UTC 24 |
92875954 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1388364218 |
|
|
Oct 15 02:58:51 AM UTC 24 |
Oct 15 02:59:00 AM UTC 24 |
4338754248 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3410882639 |
|
|
Oct 15 02:59:00 AM UTC 24 |
Oct 15 02:59:02 AM UTC 24 |
79338706 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2900033711 |
|
|
Oct 15 02:59:00 AM UTC 24 |
Oct 15 02:59:02 AM UTC 24 |
20522963 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3151927024 |
|
|
Oct 15 02:59:00 AM UTC 24 |
Oct 15 02:59:03 AM UTC 24 |
96504159 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3697974352 |
|
|
Oct 15 02:59:01 AM UTC 24 |
Oct 15 02:59:03 AM UTC 24 |
23398327 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3361252583 |
|
|
Oct 15 02:59:02 AM UTC 24 |
Oct 15 02:59:09 AM UTC 24 |
1328783302 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.81111660 |
|
|
Oct 15 02:59:05 AM UTC 24 |
Oct 15 02:59:10 AM UTC 24 |
1766073732 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.922076775 |
|
|
Oct 15 02:59:03 AM UTC 24 |
Oct 15 02:59:11 AM UTC 24 |
47350545 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1186994339 |
|
|
Oct 15 02:59:10 AM UTC 24 |
Oct 15 02:59:12 AM UTC 24 |
27179356 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1608061353 |
|
|
Oct 15 02:59:11 AM UTC 24 |
Oct 15 02:59:13 AM UTC 24 |
14646387 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3070382139 |
|
|
Oct 15 02:59:13 AM UTC 24 |
Oct 15 02:59:15 AM UTC 24 |
16858605 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3589969846 |
|
|
Oct 15 02:59:12 AM UTC 24 |
Oct 15 02:59:15 AM UTC 24 |
44179435 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1369646382 |
|
|
Oct 15 02:59:14 AM UTC 24 |
Oct 15 02:59:16 AM UTC 24 |
35494204 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.804406947 |
|
|
Oct 15 02:59:17 AM UTC 24 |
Oct 15 02:59:25 AM UTC 24 |
144109550 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.261587619 |
|
|
Oct 15 02:59:16 AM UTC 24 |
Oct 15 02:59:25 AM UTC 24 |
1372991197 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1432752329 |
|
|
Oct 15 02:59:27 AM UTC 24 |
Oct 15 02:59:29 AM UTC 24 |
25206289 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2501112119 |
|
|
Oct 15 02:59:25 AM UTC 24 |
Oct 15 02:59:30 AM UTC 24 |
398634342 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.415145083 |
|
|
Oct 15 02:59:28 AM UTC 24 |
Oct 15 02:59:30 AM UTC 24 |
49479967 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2064867187 |
|
|
Oct 15 02:59:30 AM UTC 24 |
Oct 15 02:59:33 AM UTC 24 |
27006667 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2994785783 |
|
|
Oct 15 02:58:38 AM UTC 24 |
Oct 15 02:59:33 AM UTC 24 |
7148600737 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4105613984 |
|
|
Oct 15 02:59:31 AM UTC 24 |
Oct 15 02:59:33 AM UTC 24 |
34944983 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.130768082 |
|
|
Oct 15 02:59:31 AM UTC 24 |
Oct 15 02:59:33 AM UTC 24 |
24058704 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1746849973 |
|
|
Oct 15 02:59:34 AM UTC 24 |
Oct 15 02:59:38 AM UTC 24 |
425334463 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1244489289 |
|
|
Oct 15 02:59:39 AM UTC 24 |
Oct 15 02:59:42 AM UTC 24 |
38075099 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.647165143 |
|
|
Oct 15 02:59:34 AM UTC 24 |
Oct 15 02:59:42 AM UTC 24 |
352211505 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2404302661 |
|
|
Oct 15 02:59:34 AM UTC 24 |
Oct 15 02:59:42 AM UTC 24 |
235498291 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3850412235 |
|
|
Oct 15 02:59:43 AM UTC 24 |
Oct 15 02:59:45 AM UTC 24 |
40969416 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4146237747 |
|
|
Oct 15 02:59:43 AM UTC 24 |
Oct 15 02:59:45 AM UTC 24 |
26427961 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3896007712 |
|
|
Oct 15 02:59:43 AM UTC 24 |
Oct 15 02:59:45 AM UTC 24 |
70385419 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1343126098 |
|
|
Oct 15 02:59:46 AM UTC 24 |
Oct 15 02:59:48 AM UTC 24 |
61948997 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3996962897 |
|
|
Oct 15 02:59:49 AM UTC 24 |
Oct 15 02:59:54 AM UTC 24 |
62273022 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2374798222 |
|
|
Oct 15 02:59:46 AM UTC 24 |
Oct 15 02:59:55 AM UTC 24 |
1451597518 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1945028346 |
|
|
Oct 15 02:59:56 AM UTC 24 |
Oct 15 02:59:57 AM UTC 24 |
13208583 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.954498542 |
|
|
Oct 15 02:59:56 AM UTC 24 |
Oct 15 02:59:58 AM UTC 24 |
75584110 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.58935617 |
|
|
Oct 15 02:59:55 AM UTC 24 |
Oct 15 02:59:59 AM UTC 24 |
91127020 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1363821113 |
|
|
Oct 15 03:00:00 AM UTC 24 |
Oct 15 03:00:05 AM UTC 24 |
118986680 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1763176591 |
|
|
Oct 15 02:59:59 AM UTC 24 |
Oct 15 03:00:06 AM UTC 24 |
1111559942 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1488284237 |
|
|
Oct 15 03:00:06 AM UTC 24 |
Oct 15 03:00:08 AM UTC 24 |
18393942 ps |