SRAM_CTRL/RET Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.470m	572.127us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	24.071us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	36.625us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.690s	2.052ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	39.253us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.880s	35.755us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	36.625us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	39.253us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.280s	1.101ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.390s	177.869us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	36.173m	22.642ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.133m	22.222ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.279m	28.828ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.125m	16.145ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	20.430s	704.077us	50	50	100.00
V2	executable	sram_ctrl_executable	30.303m	36.009ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.092m	2.506ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.169m	26.087ms	45	50	90.00
V2	max_throughput	sram_ctrl_max_throughput	2.603m	133.100us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.535m	563.353us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.530m	46.509ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.220s	33.186us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.096h	68.369ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.700s	11.656us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.340s	426.738us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.340s	426.738us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	24.071us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	36.625us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	39.253us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.790s	78.312us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	24.071us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	36.625us	20	20	100.00
		sram_ctrl_csr_aliasing	0.710s	39.253us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.790s	78.312us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.630s	403.709us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.440s	543.702us	5	5	100.00
		sram_ctrl_tl_intg_err	2.760s	1.901ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.440s	543.702us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.760s	1.901ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.530m	46.509ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	36.625us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.303m	36.009ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.303m	36.009ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.303m	36.009ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	20.430s	704.077us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.630s	403.709us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.470m	572.127us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.470m	572.127us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.303m	36.009ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.440s	543.702us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	20.430s	704.077us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.440s	543.702us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.440s	543.702us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.470m	572.127us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.440s	543.702us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.607h	20.151ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1033	1040	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.23	99.16	93.54	100.00	70.00	97.41	99.70	99.81

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:

Test sram_ctrl_partial_access_b2b has 5 failures.

0.sram_ctrl_partial_access_b2b.1513653919
Line 251, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.sram_ctrl_partial_access_b2b.2978581670
Line 255, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test sram_ctrl_executable has 1 failures.

30.sram_ctrl_executable.3520855292
Line 321, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 19.sram_ctrl_executable.60826501
    Line 243, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 11751443135 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xd369a3cd
  UVM_INFO @ 11751443135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```