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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.95 100.00 97.69 99.14 100.00 99.71 99.70 96.44


Total test records in report: 1040
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T262 /workspace/coverage/default/4.sram_ctrl_alert_test.103506169666329905681006936857426301638319586283446620125663036866021170900259 Nov 22 01:21:30 PM PST 23 Nov 22 01:21:38 PM PST 23 16600825 ps
T263 /workspace/coverage/default/42.sram_ctrl_lc_escalation.42473105319659600814500625253228943886084659619996042243895492118983643514628 Nov 22 01:23:48 PM PST 23 Nov 22 01:24:03 PM PST 23 985753786 ps
T264 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.69555725039975662635840466722958196886000686610202195687427698735516701693085 Nov 22 01:21:11 PM PST 23 Nov 22 01:38:40 PM PST 23 624328106 ps
T265 /workspace/coverage/default/14.sram_ctrl_smoke.18547058055186603045543758241266779878068056227891896423100372499356997522739 Nov 22 01:21:37 PM PST 23 Nov 22 01:21:58 PM PST 23 427865392 ps
T266 /workspace/coverage/default/3.sram_ctrl_ram_cfg.11828548536874172478924429321075210953542155756738961234939645572722719853916 Nov 22 01:21:06 PM PST 23 Nov 22 01:21:09 PM PST 23 40672061 ps
T267 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.25439057603629563368995847711463854141552890603715509737864022803275118617949 Nov 22 01:22:48 PM PST 23 Nov 22 01:28:51 PM PST 23 6491370455 ps
T268 /workspace/coverage/default/10.sram_ctrl_partial_access.34558858233920666983673089601770351694212793793948905081778983565695106242844 Nov 22 01:21:27 PM PST 23 Nov 22 01:21:58 PM PST 23 445204539 ps
T269 /workspace/coverage/default/0.sram_ctrl_regwen.4475447817154333348361899754315957863567778444503658288829567654041364900639 Nov 22 01:21:26 PM PST 23 Nov 22 01:30:23 PM PST 23 19383553031 ps
T270 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.88658527771449893843546683024107881752597769619790464095624576760554681508715 Nov 22 01:21:47 PM PST 23 Nov 22 01:35:21 PM PST 23 4471404472 ps
T271 /workspace/coverage/default/23.sram_ctrl_lc_escalation.88925613948173227497262257573019998352871080092018888076982599440082962560584 Nov 22 01:22:01 PM PST 23 Nov 22 01:22:15 PM PST 23 985753786 ps
T272 /workspace/coverage/default/3.sram_ctrl_regwen.45482692570671442147622260403438847152842269438387518170428662836435303545552 Nov 22 01:20:54 PM PST 23 Nov 22 01:29:23 PM PST 23 19383553031 ps
T273 /workspace/coverage/default/15.sram_ctrl_mem_walk.568158243830308119997389809715560420835544670179033805352875460077757214606 Nov 22 01:21:45 PM PST 23 Nov 22 01:21:56 PM PST 23 590810517 ps
T274 /workspace/coverage/default/5.sram_ctrl_executable.13810264363176128351496225037164812083284797144440116666430512457090456101661 Nov 22 01:21:17 PM PST 23 Nov 22 01:34:58 PM PST 23 23162112088 ps
T275 /workspace/coverage/default/23.sram_ctrl_smoke.5103503325686767163628782977558769838155806170908870673211049359907110684493 Nov 22 01:22:01 PM PST 23 Nov 22 01:22:18 PM PST 23 427865392 ps
T276 /workspace/coverage/default/21.sram_ctrl_max_throughput.37270497210281529782388457466159263067974379829157676008835264731191184352234 Nov 22 01:21:55 PM PST 23 Nov 22 01:23:51 PM PST 23 209242141 ps
T277 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.4264370688063101832323801437058224293272259376030552242799960127695152220303 Nov 22 01:23:08 PM PST 23 Nov 22 01:35:39 PM PST 23 4471404472 ps
T278 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.70843986896915916673619192395212100323634065015669960483527906280131480247400 Nov 22 01:22:01 PM PST 23 Nov 22 01:22:10 PM PST 23 166171057 ps
T279 /workspace/coverage/default/29.sram_ctrl_smoke.16058947075567396008448477271423625561762336590300926193848442167762604889429 Nov 22 01:22:15 PM PST 23 Nov 22 01:22:30 PM PST 23 427865392 ps
T280 /workspace/coverage/default/6.sram_ctrl_regwen.23287645579490758580577757918325195506611203852988081883468930544590490985021 Nov 22 01:21:20 PM PST 23 Nov 22 01:30:54 PM PST 23 19383553031 ps
T281 /workspace/coverage/default/18.sram_ctrl_mem_walk.59201025641653762648010064969138126861918541232015463078891931931880336085297 Nov 22 01:21:43 PM PST 23 Nov 22 01:21:54 PM PST 23 590810517 ps
T282 /workspace/coverage/default/4.sram_ctrl_regwen.111255825566961958584367828899197895228543405144048628258115805487543421881991 Nov 22 01:21:06 PM PST 23 Nov 22 01:29:28 PM PST 23 19383553031 ps
T283 /workspace/coverage/default/15.sram_ctrl_ram_cfg.104008750587819827030250625083966814781499842016617281340404914405058019658836 Nov 22 01:21:49 PM PST 23 Nov 22 01:21:56 PM PST 23 40672061 ps
T284 /workspace/coverage/default/45.sram_ctrl_partial_access.69282408045891926051312506809352436126524904962193721689384787942986381012106 Nov 22 01:23:03 PM PST 23 Nov 22 01:23:27 PM PST 23 445204539 ps
T285 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.59118502712578046963950480561576072436480744631500755687798935964983170818954 Nov 22 01:23:32 PM PST 23 Nov 22 01:25:28 PM PST 23 237420487 ps
T286 /workspace/coverage/default/27.sram_ctrl_max_throughput.41269102707212847844725691702677557924707461014960007085037009182358628272006 Nov 22 01:22:01 PM PST 23 Nov 22 01:23:48 PM PST 23 209242141 ps
T287 /workspace/coverage/default/27.sram_ctrl_lc_escalation.100422980700716799987006678124412649455312357740389207568512204806464814166617 Nov 22 01:22:58 PM PST 23 Nov 22 01:23:15 PM PST 23 985753786 ps
T288 /workspace/coverage/default/27.sram_ctrl_alert_test.58684858784016101846332309784763920398352762867005487704991780420312821597791 Nov 22 01:22:03 PM PST 23 Nov 22 01:22:09 PM PST 23 16600825 ps
T289 /workspace/coverage/default/7.sram_ctrl_lc_escalation.35690086920799195423411771716028634578389106466563056114557304532504448769532 Nov 22 01:22:18 PM PST 23 Nov 22 01:22:28 PM PST 23 985753786 ps
T290 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.37120096152864001586172436804841763529000248915134770895543683897442750462886 Nov 22 01:22:26 PM PST 23 Nov 22 01:38:14 PM PST 23 624328106 ps
T291 /workspace/coverage/default/32.sram_ctrl_stress_all.106484967865010381324047963866373136384926946229969982434506140354842900306603 Nov 22 01:23:23 PM PST 23 Nov 22 02:13:53 PM PST 23 121463254244 ps
T292 /workspace/coverage/default/26.sram_ctrl_bijection.75906025886555239239706063200995618107270343822511257973061770951902237251716 Nov 22 01:23:32 PM PST 23 Nov 22 01:25:06 PM PST 23 9249473390 ps
T293 /workspace/coverage/default/5.sram_ctrl_max_throughput.60205506806035606508533574875654238849093465702644113068633733083232313699338 Nov 22 01:21:45 PM PST 23 Nov 22 01:23:03 PM PST 23 209242141 ps
T294 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.19815221445423473872768134740267653587783349794897050866611557183449035791432 Nov 22 01:21:59 PM PST 23 Nov 22 01:27:58 PM PST 23 6491370455 ps
T295 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.7758713265249514288741464267634964043345624300066058094673666078214663636011 Nov 22 01:23:06 PM PST 23 Nov 22 01:32:02 PM PST 23 42305619653 ps
T296 /workspace/coverage/default/43.sram_ctrl_partial_access.12404690036990706896933731769188139824336631218348425370843569041049202232871 Nov 22 01:23:02 PM PST 23 Nov 22 01:23:26 PM PST 23 445204539 ps
T297 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1840685081289534506975679063620551289631008694571309617799203808170180902206 Nov 22 01:20:55 PM PST 23 Nov 22 01:22:26 PM PST 23 237420487 ps
T298 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2596501180263477885895381754843758332367859132101905112730354490980657841261 Nov 22 01:21:19 PM PST 23 Nov 22 01:22:45 PM PST 23 237420487 ps
T299 /workspace/coverage/default/1.sram_ctrl_bijection.82044129991705919558432374258767450864615196462794922340729626481493399133175 Nov 22 01:21:57 PM PST 23 Nov 22 01:23:28 PM PST 23 9249473390 ps
T300 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.32545732069695554145920612679857925875279604761319881951500406934579601821327 Nov 22 01:21:40 PM PST 23 Nov 22 01:44:26 PM PST 23 624328106 ps
T301 /workspace/coverage/default/13.sram_ctrl_max_throughput.72074197084346800743591083957041485001534054286597534624869091568326750746708 Nov 22 01:21:56 PM PST 23 Nov 22 01:23:38 PM PST 23 209242141 ps
T302 /workspace/coverage/default/9.sram_ctrl_regwen.18638246328515846987062078399420194193206106253239173243212335044274312699231 Nov 22 01:21:31 PM PST 23 Nov 22 01:30:57 PM PST 23 19383553031 ps
T303 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.79536640142247543520656504135521775239735774699227436349305514962298149389515 Nov 22 01:23:41 PM PST 23 Nov 22 01:32:49 PM PST 23 42305619653 ps
T304 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.75440453273503556979271545620088625204620730628311726191760143248025949370399 Nov 22 01:21:06 PM PST 23 Nov 22 01:41:03 PM PST 23 624328106 ps
T305 /workspace/coverage/default/14.sram_ctrl_ram_cfg.68253042602769110272402572026313878604775189191575732875741155817537179402571 Nov 22 01:21:50 PM PST 23 Nov 22 01:21:56 PM PST 23 40672061 ps
T306 /workspace/coverage/default/24.sram_ctrl_stress_all.53834202077257754467198175043584327529597252178042769185864207582877039318195 Nov 22 01:21:52 PM PST 23 Nov 22 02:19:01 PM PST 23 121463254244 ps
T307 /workspace/coverage/default/29.sram_ctrl_max_throughput.19777354255259153583606094269396743452801890962490918104058262539598578040090 Nov 22 01:22:09 PM PST 23 Nov 22 01:23:48 PM PST 23 209242141 ps
T308 /workspace/coverage/default/35.sram_ctrl_bijection.83500284151962537116580790347970478867522264251580528418159881813882658373496 Nov 22 01:23:20 PM PST 23 Nov 22 01:24:54 PM PST 23 9249473390 ps
T309 /workspace/coverage/default/17.sram_ctrl_ram_cfg.6191388656602179445076446254801906373734248297513072467940461902162091655621 Nov 22 01:22:07 PM PST 23 Nov 22 01:22:12 PM PST 23 40672061 ps
T310 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.38123470379995163990774185323463573599666342431782476451387397376416170858539 Nov 22 01:21:51 PM PST 23 Nov 22 01:44:41 PM PST 23 624328106 ps
T311 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.27686005205632278551576811434002572536631085260232974487142374793883822529983 Nov 22 01:22:31 PM PST 23 Nov 22 01:39:12 PM PST 23 624328106 ps
T312 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.97663489366829331861784367953798855649744643661220400831923281639289676752962 Nov 22 01:21:57 PM PST 23 Nov 22 01:31:14 PM PST 23 42305619653 ps
T313 /workspace/coverage/default/27.sram_ctrl_bijection.17819049025391216405370851944927900538941563851745672714468895831784093053483 Nov 22 01:22:00 PM PST 23 Nov 22 01:23:29 PM PST 23 9249473390 ps
T314 /workspace/coverage/default/13.sram_ctrl_mem_walk.84098982112482972361686355016350585827006029356037586316864626477731430724272 Nov 22 01:21:36 PM PST 23 Nov 22 01:21:50 PM PST 23 590810517 ps
T315 /workspace/coverage/default/32.sram_ctrl_ram_cfg.26448548979429278671909339371304218001755400605874039942941990086730360286881 Nov 22 01:22:45 PM PST 23 Nov 22 01:22:58 PM PST 23 40672061 ps
T316 /workspace/coverage/default/1.sram_ctrl_mem_walk.40786041682036373801791997422915705208095415993338762022056590520513625723125 Nov 22 01:21:02 PM PST 23 Nov 22 01:21:12 PM PST 23 590810517 ps
T317 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3577985479266740933981060288818564848706979753750676925402948328193646718712 Nov 22 01:21:08 PM PST 23 Nov 22 01:34:49 PM PST 23 4471404472 ps
T318 /workspace/coverage/default/18.sram_ctrl_max_throughput.20198148913107495986476585031709840596628897990089825525220545557799700729409 Nov 22 01:21:37 PM PST 23 Nov 22 01:23:36 PM PST 23 209242141 ps
T319 /workspace/coverage/default/32.sram_ctrl_lc_escalation.94552566641777646367871917346045292006632130303539846895427696015603914447212 Nov 22 01:22:50 PM PST 23 Nov 22 01:23:12 PM PST 23 985753786 ps
T320 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.394629778744663590191570621761763002412891541964378858056019700688494043163 Nov 22 01:22:23 PM PST 23 Nov 22 01:22:28 PM PST 23 166171057 ps
T321 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.24267759238678880586699732099875785724484909201745079663340507550222982856576 Nov 22 01:22:26 PM PST 23 Nov 22 01:22:34 PM PST 23 166171057 ps
T322 /workspace/coverage/default/33.sram_ctrl_mem_walk.17030683601486414604686960397915615393439051534478587437214733238287532896370 Nov 22 01:22:44 PM PST 23 Nov 22 01:23:01 PM PST 23 590810517 ps
T323 /workspace/coverage/default/17.sram_ctrl_bijection.50038686750229537124527131593666672173483921414089449194579557413186881091348 Nov 22 01:22:25 PM PST 23 Nov 22 01:23:52 PM PST 23 9249473390 ps
T324 /workspace/coverage/default/11.sram_ctrl_alert_test.74449216470032021222578212542569905091402816575202130583538514343836247377917 Nov 22 01:21:53 PM PST 23 Nov 22 01:22:00 PM PST 23 16600825 ps
T325 /workspace/coverage/default/25.sram_ctrl_alert_test.63708960170196924191829095544440866951600339852832783229657464500852936811882 Nov 22 01:22:00 PM PST 23 Nov 22 01:22:06 PM PST 23 16600825 ps
T326 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.85574228340803148204763610565847036662800462989061798906142812772235749237047 Nov 22 01:22:50 PM PST 23 Nov 22 01:24:51 PM PST 23 237420487 ps
T327 /workspace/coverage/default/7.sram_ctrl_ram_cfg.75055511259939642997360943085943001950782419550115774134083590549868738703030 Nov 22 01:21:10 PM PST 23 Nov 22 01:21:12 PM PST 23 40672061 ps
T328 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.96735809454164945566782552529305135350479828436213741031839035237174766239814 Nov 22 01:21:28 PM PST 23 Nov 22 01:35:24 PM PST 23 4471404472 ps
T329 /workspace/coverage/default/15.sram_ctrl_multiple_keys.28002074782692551462345172597411753839213427632021362935063167968492910522640 Nov 22 01:21:37 PM PST 23 Nov 22 01:36:12 PM PST 23 21947461091 ps
T330 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.55145344601983509227634493189036722531301061264311761270257645246253646451228 Nov 22 01:22:58 PM PST 23 Nov 22 01:40:29 PM PST 23 624328106 ps
T331 /workspace/coverage/default/35.sram_ctrl_regwen.53287544100307439617851248919326153641671578865330595265469153693026137623064 Nov 22 01:22:32 PM PST 23 Nov 22 01:31:28 PM PST 23 19383553031 ps
T332 /workspace/coverage/default/33.sram_ctrl_bijection.110562317324218671820284544799763712243519167401066472877982970635826196051217 Nov 22 01:22:29 PM PST 23 Nov 22 01:23:55 PM PST 23 9249473390 ps
T333 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.67968070440807378102792631631493065477508540186141283538383057659322885900482 Nov 22 01:21:59 PM PST 23 Nov 22 01:33:21 PM PST 23 4471404472 ps
T334 /workspace/coverage/default/11.sram_ctrl_smoke.32292288687668905591476760634030675140952831647386127591408999860428553045575 Nov 22 01:21:57 PM PST 23 Nov 22 01:22:15 PM PST 23 427865392 ps
T335 /workspace/coverage/default/10.sram_ctrl_multiple_keys.24408679609093420411205288711853771916212188820478183905683082634744869127528 Nov 22 01:21:57 PM PST 23 Nov 22 01:35:15 PM PST 23 21947461091 ps
T336 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.81577165017458137188073602057195702624063577599108979451281744076387854733340 Nov 22 01:23:53 PM PST 23 Nov 22 01:30:04 PM PST 23 6491370455 ps
T337 /workspace/coverage/default/43.sram_ctrl_lc_escalation.78800977956106845522945127624197601962503575457997370332046578685263654384083 Nov 22 01:23:05 PM PST 23 Nov 22 01:23:23 PM PST 23 985753786 ps
T338 /workspace/coverage/default/24.sram_ctrl_regwen.5947785946782101797468622900514023409659849297330294596861105838128994275039 Nov 22 01:22:05 PM PST 23 Nov 22 01:31:49 PM PST 23 19383553031 ps
T339 /workspace/coverage/default/34.sram_ctrl_multiple_keys.34815341044358832274682557015148299281969762016986168853571594308001785683659 Nov 22 01:22:47 PM PST 23 Nov 22 01:33:43 PM PST 23 21947461091 ps
T340 /workspace/coverage/default/5.sram_ctrl_stress_all.13131518976802970314965441109467322042337836303702394801336242562027473981924 Nov 22 01:21:07 PM PST 23 Nov 22 02:19:10 PM PST 23 121463254244 ps
T341 /workspace/coverage/default/13.sram_ctrl_ram_cfg.68796066301281891997257129654265011107241846176522279773946279551737691510133 Nov 22 01:21:39 PM PST 23 Nov 22 01:21:47 PM PST 23 40672061 ps
T342 /workspace/coverage/default/37.sram_ctrl_ram_cfg.61649707334390966983082283061629988108319170145506596635331735327199562945110 Nov 22 01:22:36 PM PST 23 Nov 22 01:22:42 PM PST 23 40672061 ps
T343 /workspace/coverage/default/26.sram_ctrl_mem_walk.111740155389369561842965408861079439097528201077264153013644191162971976212459 Nov 22 01:22:11 PM PST 23 Nov 22 01:22:20 PM PST 23 590810517 ps
T344 /workspace/coverage/default/11.sram_ctrl_ram_cfg.105360495796018429541510771609364008999666029221390812149560339191879705024804 Nov 22 01:21:40 PM PST 23 Nov 22 01:21:47 PM PST 23 40672061 ps
T345 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.70958695650704793236443990014780495674490055794610668283547750797719118017062 Nov 22 01:22:24 PM PST 23 Nov 22 01:22:30 PM PST 23 166171057 ps
T346 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.104894917897399804860665354449160359313789471616081514404225247173192849627931 Nov 22 01:21:16 PM PST 23 Nov 22 01:23:01 PM PST 23 237420487 ps
T347 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.39583552860548497613186906400491591281472792811352326209416470918231743270034 Nov 22 01:22:26 PM PST 23 Nov 22 01:38:27 PM PST 23 624328106 ps
T348 /workspace/coverage/default/1.sram_ctrl_stress_all.110204961738435288483722509038603680767240436000489913203029791414017645820081 Nov 22 01:20:59 PM PST 23 Nov 22 02:07:47 PM PST 23 121463254244 ps
T349 /workspace/coverage/default/46.sram_ctrl_ram_cfg.25256576601464386246313482409916112643519937324244966138137831836677341077933 Nov 22 01:23:07 PM PST 23 Nov 22 01:23:18 PM PST 23 40672061 ps
T350 /workspace/coverage/default/1.sram_ctrl_executable.278336284309972885597980142078713666268028551645506373814622718845143085165 Nov 22 01:21:20 PM PST 23 Nov 22 01:32:03 PM PST 23 23162112088 ps
T351 /workspace/coverage/default/34.sram_ctrl_ram_cfg.106243136098803284204000774060179770924046347143393499410558769166267447103131 Nov 22 01:22:34 PM PST 23 Nov 22 01:22:39 PM PST 23 40672061 ps
T352 /workspace/coverage/default/25.sram_ctrl_regwen.80904033700446338511234909506129096514002981350221606336068792006142003859199 Nov 22 01:22:54 PM PST 23 Nov 22 01:32:03 PM PST 23 19383553031 ps
T353 /workspace/coverage/default/30.sram_ctrl_mem_walk.111227614850802910914050852502854554546887390312619558583261237739808123782806 Nov 22 01:22:23 PM PST 23 Nov 22 01:22:32 PM PST 23 590810517 ps
T354 /workspace/coverage/default/14.sram_ctrl_bijection.62469204876627672622945248411276991544278499755381468501405636521931542063129 Nov 22 01:21:37 PM PST 23 Nov 22 01:23:07 PM PST 23 9249473390 ps
T355 /workspace/coverage/default/17.sram_ctrl_multiple_keys.29184151703745639376592776102856749591780519957317193535951014331812116616476 Nov 22 01:21:58 PM PST 23 Nov 22 01:36:04 PM PST 23 21947461091 ps
T25 /workspace/coverage/default/4.sram_ctrl_sec_cm.50263457824618149287827590107672156217770018966127915562644636692475924565979 Nov 22 01:21:18 PM PST 23 Nov 22 01:21:22 PM PST 23 216402798 ps
T38 /workspace/coverage/default/1.sram_ctrl_ram_cfg.32059088676509345032985690368491256035417463996244658535726853839659909817419 Nov 22 01:22:45 PM PST 23 Nov 22 01:22:59 PM PST 23 40672061 ps
T39 /workspace/coverage/default/8.sram_ctrl_regwen.1812325402132794412587679296843408336188820318250485269926193785897172315086 Nov 22 01:21:30 PM PST 23 Nov 22 01:30:35 PM PST 23 19383553031 ps
T40 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.26377771903489215886551583531834456193072900353333222119431512868679713461288 Nov 22 01:22:34 PM PST 23 Nov 22 01:34:54 PM PST 23 4471404472 ps
T41 /workspace/coverage/default/3.sram_ctrl_smoke.47165421386263485042414683117419161830623341712199046905524031919490301911135 Nov 22 01:20:54 PM PST 23 Nov 22 01:21:11 PM PST 23 427865392 ps
T42 /workspace/coverage/default/28.sram_ctrl_bijection.38143317090544258330935272428958268971564820081938305472104857059888107839332 Nov 22 01:22:07 PM PST 23 Nov 22 01:23:36 PM PST 23 9249473390 ps
T43 /workspace/coverage/default/19.sram_ctrl_stress_all.85678672079212412004273863052183140880560789971700401061832014566059755096708 Nov 22 01:22:00 PM PST 23 Nov 22 02:13:24 PM PST 23 121463254244 ps
T44 /workspace/coverage/default/41.sram_ctrl_bijection.76873961743068201316389824288696298768375803638922676871255464073513352338601 Nov 22 01:23:45 PM PST 23 Nov 22 01:25:18 PM PST 23 9249473390 ps
T356 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.73049029695375023563995048556801988987155334009850134113190233849896169245594 Nov 22 01:23:07 PM PST 23 Nov 22 01:32:16 PM PST 23 42305619653 ps
T357 /workspace/coverage/default/29.sram_ctrl_partial_access.40666737399595951957750871431559455632620760509617608057379767797065725198522 Nov 22 01:22:05 PM PST 23 Nov 22 01:22:24 PM PST 23 445204539 ps
T358 /workspace/coverage/default/11.sram_ctrl_bijection.6111591823252585861404162947124404504049212752821998852768013173050579918703 Nov 22 01:22:25 PM PST 23 Nov 22 01:23:52 PM PST 23 9249473390 ps
T359 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.34257683314446790986608652804869788465695533575766518242253984625554228330053 Nov 22 01:21:59 PM PST 23 Nov 22 01:34:39 PM PST 23 4471404472 ps
T360 /workspace/coverage/default/19.sram_ctrl_executable.15419834223867358337495901979218048238569654910169746686718116369555421288059 Nov 22 01:22:46 PM PST 23 Nov 22 01:35:30 PM PST 23 23162112088 ps
T361 /workspace/coverage/default/37.sram_ctrl_max_throughput.107960666667195780244194661704106945016309546131879540656578971721298977705717 Nov 22 01:22:43 PM PST 23 Nov 22 01:24:17 PM PST 23 209242141 ps
T362 /workspace/coverage/default/40.sram_ctrl_smoke.11661018894040380990518287940274669932405144802515316309467307757631794110644 Nov 22 01:22:37 PM PST 23 Nov 22 01:22:55 PM PST 23 427865392 ps
T363 /workspace/coverage/default/44.sram_ctrl_regwen.21670171273209610947008885656889399750127269670272988918747881170292054028167 Nov 22 01:23:03 PM PST 23 Nov 22 01:31:12 PM PST 23 19383553031 ps
T364 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.61984956891140548085685104036553521606657873918289853446968909470106954772250 Nov 22 01:21:10 PM PST 23 Nov 22 01:22:49 PM PST 23 237420487 ps
T365 /workspace/coverage/default/23.sram_ctrl_mem_walk.79501753183397826702350219343154962296337124938820423372450168051116285224221 Nov 22 01:21:54 PM PST 23 Nov 22 01:22:05 PM PST 23 590810517 ps
T366 /workspace/coverage/default/27.sram_ctrl_smoke.54309977251195579813466209492556886571323989250452591849592246919812997104548 Nov 22 01:23:34 PM PST 23 Nov 22 01:23:58 PM PST 23 427865392 ps
T367 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.94147231712384236265359515299575840016581679439922063957464875660514498764290 Nov 22 01:23:15 PM PST 23 Nov 22 01:32:38 PM PST 23 42305619653 ps
T368 /workspace/coverage/default/10.sram_ctrl_stress_all.113736029631638892891855970276168019797279711996006835346231489146480822306603 Nov 22 01:22:23 PM PST 23 Nov 22 02:29:19 PM PST 23 121463254244 ps
T369 /workspace/coverage/default/4.sram_ctrl_multiple_keys.71595647345222049492819171507135257132161090602993901527284152972077074868240 Nov 22 01:21:15 PM PST 23 Nov 22 01:34:19 PM PST 23 21947461091 ps
T370 /workspace/coverage/default/4.sram_ctrl_max_throughput.102101582501262828277633920558294269309759022430303168455971678185549798220763 Nov 22 01:21:53 PM PST 23 Nov 22 01:23:10 PM PST 23 209242141 ps
T371 /workspace/coverage/default/24.sram_ctrl_bijection.10470468831180446620107906630515880551767915117129322381951308154104668518220 Nov 22 01:22:36 PM PST 23 Nov 22 01:24:03 PM PST 23 9249473390 ps
T372 /workspace/coverage/default/6.sram_ctrl_lc_escalation.99180398760928107484623878247262781129210864763208644746407766355614007495421 Nov 22 01:21:16 PM PST 23 Nov 22 01:21:25 PM PST 23 985753786 ps
T373 /workspace/coverage/default/37.sram_ctrl_executable.75282013266767910254394085204124889072769343310894846343725755540580602071130 Nov 22 01:22:36 PM PST 23 Nov 22 01:33:03 PM PST 23 23162112088 ps
T374 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.80959526538269950109321416831678405088832592401596050511323708158539244527382 Nov 22 01:22:19 PM PST 23 Nov 22 01:31:20 PM PST 23 42305619653 ps
T375 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.32080709189762270589071028455430180884781450078491915175300131675449803089275 Nov 22 01:22:09 PM PST 23 Nov 22 01:22:15 PM PST 23 166171057 ps
T376 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.56523156200027603815593174863264181581553642497011912080510432891995352766306 Nov 22 01:22:58 PM PST 23 Nov 22 01:29:08 PM PST 23 6491370455 ps
T377 /workspace/coverage/default/0.sram_ctrl_multiple_keys.56375683127001933306015994105872124222253410930596234098489466744116128531729 Nov 22 01:21:30 PM PST 23 Nov 22 01:35:24 PM PST 23 21947461091 ps
T378 /workspace/coverage/default/40.sram_ctrl_max_throughput.84800644061668950723367430299929023076616218397355735256743682869811600006147 Nov 22 01:22:42 PM PST 23 Nov 22 01:24:23 PM PST 23 209242141 ps
T379 /workspace/coverage/default/43.sram_ctrl_stress_all.36078999479833617686386189607074263805146052684765217503944599387599772770538 Nov 22 01:23:02 PM PST 23 Nov 22 02:24:40 PM PST 23 121463254244 ps
T380 /workspace/coverage/default/4.sram_ctrl_executable.61758427030055035226451599463040541677654459985815314554294717292631117235354 Nov 22 01:20:56 PM PST 23 Nov 22 01:33:25 PM PST 23 23162112088 ps
T381 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.62547208545546264182742007887346715613419373262151750855250337158766044156 Nov 22 01:21:56 PM PST 23 Nov 22 01:22:05 PM PST 23 166171057 ps
T382 /workspace/coverage/default/3.sram_ctrl_multiple_keys.75320626026595857965232643305916155196676761366095854972820599258473304301518 Nov 22 01:23:14 PM PST 23 Nov 22 01:33:06 PM PST 23 21947461091 ps
T383 /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.36701522467938322209622059432783849932119255948552589303040923993579692464400 Nov 22 01:23:53 PM PST 23 Nov 22 01:39:39 PM PST 23 624328106 ps
T384 /workspace/coverage/default/31.sram_ctrl_max_throughput.102276814261736180976045509627409995138463027362705076460034719981756842487071 Nov 22 01:22:28 PM PST 23 Nov 22 01:24:21 PM PST 23 209242141 ps
T385 /workspace/coverage/default/36.sram_ctrl_alert_test.9689147253573581940979691329914600134097622170854621411026051627378834754750 Nov 22 01:22:56 PM PST 23 Nov 22 01:23:08 PM PST 23 16600825 ps
T386 /workspace/coverage/default/19.sram_ctrl_regwen.35928090958571562955030502953902969685359870896075656167110712625282902089325 Nov 22 01:22:30 PM PST 23 Nov 22 01:32:13 PM PST 23 19383553031 ps
T387 /workspace/coverage/default/31.sram_ctrl_alert_test.30601382610315449133389715521942001200164827292855907766943785225867444369586 Nov 22 01:22:41 PM PST 23 Nov 22 01:22:49 PM PST 23 16600825 ps
T388 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.108622941655065597048842417336920967265473567494992297383728041028404716543678 Nov 22 01:21:21 PM PST 23 Nov 22 01:30:53 PM PST 23 42305619653 ps
T389 /workspace/coverage/default/32.sram_ctrl_partial_access.56498444243400963256161289005055183535808963979515645890393715943096095526068 Nov 22 01:22:26 PM PST 23 Nov 22 01:22:42 PM PST 23 445204539 ps
T390 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.78795273899138123052736747058794562608606321379983668244753517580361081362178 Nov 22 01:23:09 PM PST 23 Nov 22 01:29:15 PM PST 23 6491370455 ps
T391 /workspace/coverage/default/12.sram_ctrl_bijection.67760993987709421709762512733753328932304314726197225202146971322160334332212 Nov 22 01:21:53 PM PST 23 Nov 22 01:23:23 PM PST 23 9249473390 ps
T392 /workspace/coverage/default/46.sram_ctrl_partial_access.78753890359400512831375276132111109743273484083882683395561477072460105978185 Nov 22 01:23:08 PM PST 23 Nov 22 01:23:31 PM PST 23 445204539 ps
T393 /workspace/coverage/default/35.sram_ctrl_partial_access.103790349648990122657807741320204510966676822664335966933655555037089693233948 Nov 22 01:22:56 PM PST 23 Nov 22 01:23:21 PM PST 23 445204539 ps
T394 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.105012604164137836276244617207961390474646493715865406221106319307229602060670 Nov 22 01:23:16 PM PST 23 Nov 22 01:23:26 PM PST 23 166171057 ps
T395 /workspace/coverage/default/18.sram_ctrl_smoke.68262733975029780565802827467722933627238992004573215392786554364996392440404 Nov 22 01:21:45 PM PST 23 Nov 22 01:22:01 PM PST 23 427865392 ps
T396 /workspace/coverage/default/14.sram_ctrl_regwen.39155771914233427187057714865587262039689948044588915151081086539682273996869 Nov 22 01:21:56 PM PST 23 Nov 22 01:33:10 PM PST 23 19383553031 ps
T397 /workspace/coverage/default/44.sram_ctrl_max_throughput.52750064333656169894990142264963134730388268422230421461226357207092797887457 Nov 22 01:22:53 PM PST 23 Nov 22 01:25:20 PM PST 23 209242141 ps
T398 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.50711361106685758281483707342847654371507839239646902092676739413931451376614 Nov 22 01:22:45 PM PST 23 Nov 22 01:24:52 PM PST 23 237420487 ps
T399 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.65852670214872912964841966869600402672036317418547815112170336275428632688826 Nov 22 01:23:02 PM PST 23 Nov 22 01:23:16 PM PST 23 166171057 ps
T400 /workspace/coverage/default/15.sram_ctrl_max_throughput.54343624843619572752550349372430973824737636370305380592565507802860398480130 Nov 22 01:21:43 PM PST 23 Nov 22 01:22:53 PM PST 23 209242141 ps
T401 /workspace/coverage/default/2.sram_ctrl_mem_walk.35329958257491795212175862471460019540777118895629742546725769184107733283616 Nov 22 01:21:07 PM PST 23 Nov 22 01:21:14 PM PST 23 590810517 ps
T402 /workspace/coverage/default/30.sram_ctrl_stress_all.107371363673409180732562289059650466338623965486129749047486014317922008374665 Nov 22 01:22:49 PM PST 23 Nov 22 02:19:16 PM PST 23 121463254244 ps
T403 /workspace/coverage/default/27.sram_ctrl_stress_all.8534889157657062857609951604860279623950934353644604729621134073807287586878 Nov 22 01:22:29 PM PST 23 Nov 22 02:17:35 PM PST 23 121463254244 ps
T404 /workspace/coverage/default/11.sram_ctrl_max_throughput.52725015345021298434606412263531151542367032381282272528909670027933414898451 Nov 22 01:21:38 PM PST 23 Nov 22 01:22:56 PM PST 23 209242141 ps
T405 /workspace/coverage/default/28.sram_ctrl_max_throughput.103197265519528553486701415013950878700699555370593931783337723850639789151439 Nov 22 01:24:10 PM PST 23 Nov 22 01:25:49 PM PST 23 209242141 ps
T406 /workspace/coverage/default/32.sram_ctrl_bijection.85418018533006769086944640541789746968001124895756132365728881546875650633666 Nov 22 01:22:40 PM PST 23 Nov 22 01:24:09 PM PST 23 9249473390 ps
T407 /workspace/coverage/default/13.sram_ctrl_bijection.66360636004211471477870297614632580008694153381215844366269387673514796196465 Nov 22 01:21:44 PM PST 23 Nov 22 01:23:13 PM PST 23 9249473390 ps
T408 /workspace/coverage/default/1.sram_ctrl_max_throughput.95779764928548695347269301491459743081850219460620698378895054308151097522924 Nov 22 01:21:06 PM PST 23 Nov 22 01:22:38 PM PST 23 209242141 ps
T409 /workspace/coverage/default/36.sram_ctrl_smoke.72241525389844458856484716088293598989216798860220696731666536593723114032694 Nov 22 01:23:11 PM PST 23 Nov 22 01:23:31 PM PST 23 427865392 ps
T410 /workspace/coverage/default/36.sram_ctrl_bijection.81575895419910078421339880455477999875202491199310353549450700436746995349099 Nov 22 01:22:42 PM PST 23 Nov 22 01:24:07 PM PST 23 9249473390 ps
T411 /workspace/coverage/default/2.sram_ctrl_partial_access.13842986444399713122539428047059097028572823730783521025580623920329520652865 Nov 22 01:21:17 PM PST 23 Nov 22 01:21:30 PM PST 23 445204539 ps
T412 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.81750182083227784240805645644329707157151750767181823661915112625539715229122 Nov 22 01:21:55 PM PST 23 Nov 22 01:39:00 PM PST 23 624328106 ps
T413 /workspace/coverage/default/17.sram_ctrl_stress_all.25864859139772063132160036128970448861492219336427027017892718521186888490647 Nov 22 01:22:02 PM PST 23 Nov 22 02:09:37 PM PST 23 121463254244 ps
T414 /workspace/coverage/default/23.sram_ctrl_partial_access.60698303538172742137549888419376752112666491489156966380283557857686686544029 Nov 22 01:21:58 PM PST 23 Nov 22 01:22:17 PM PST 23 445204539 ps
T415 /workspace/coverage/default/9.sram_ctrl_ram_cfg.29237753485018919991620075799628330353839069736796984320284839201822190954964 Nov 22 01:21:27 PM PST 23 Nov 22 01:21:37 PM PST 23 40672061 ps
T416 /workspace/coverage/default/7.sram_ctrl_partial_access.87615826307238445229021457318246765914632255424903165061602085439263363503946 Nov 22 01:21:16 PM PST 23 Nov 22 01:21:31 PM PST 23 445204539 ps
T417 /workspace/coverage/default/39.sram_ctrl_partial_access.59110091668118188555520199043904042315237283036754185789258453205991569851362 Nov 22 01:23:21 PM PST 23 Nov 22 01:23:43 PM PST 23 445204539 ps
T418 /workspace/coverage/default/30.sram_ctrl_multiple_keys.99844583640225190388798048961368711758540233195375959469498349394162814113943 Nov 22 01:22:18 PM PST 23 Nov 22 01:33:20 PM PST 23 21947461091 ps
T419 /workspace/coverage/default/31.sram_ctrl_lc_escalation.4874724070778952191539540442066464034596680587573624267055479885653078207039 Nov 22 01:22:31 PM PST 23 Nov 22 01:22:43 PM PST 23 985753786 ps
T420 /workspace/coverage/default/10.sram_ctrl_alert_test.58450543397002673872023920012556687025057109939288449978408876851833923719954 Nov 22 01:21:21 PM PST 23 Nov 22 01:21:26 PM PST 23 16600825 ps
T421 /workspace/coverage/default/21.sram_ctrl_partial_access.2104540818804549046350492351188292892522631660329554840298269535324234326114 Nov 22 01:22:02 PM PST 23 Nov 22 01:22:20 PM PST 23 445204539 ps
T422 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.13250886203394627309312519467039001432089834940093435949835378176445070951999 Nov 22 01:22:48 PM PST 23 Nov 22 01:24:29 PM PST 23 237420487 ps
T423 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.92642165513155314230708237373206249162877385935602583488046139231911126449686 Nov 22 01:21:54 PM PST 23 Nov 22 01:44:23 PM PST 23 624328106 ps
T424 /workspace/coverage/default/26.sram_ctrl_alert_test.24987119232295643748463824859125172570751492985295211578652735519426081597163 Nov 22 01:22:13 PM PST 23 Nov 22 01:22:17 PM PST 23 16600825 ps
T425 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.31564923962581501935493118878237777986843202760704094704560995073551744363253 Nov 22 01:24:12 PM PST 23 Nov 22 01:34:26 PM PST 23 4471404472 ps
T426 /workspace/coverage/default/18.sram_ctrl_stress_all.108055151186544684042541479581795616737494031175339431523933930313292878046950 Nov 22 01:22:30 PM PST 23 Nov 22 02:12:55 PM PST 23 121463254244 ps
T427 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2925552119834756505644404915621110316931967523407542756676959058935247997125 Nov 22 01:21:37 PM PST 23 Nov 22 01:23:25 PM PST 23 237420487 ps
T428 /workspace/coverage/default/48.sram_ctrl_smoke.34480593930362863207245593588102634665801145922785369165805341221594403254677 Nov 22 01:23:16 PM PST 23 Nov 22 01:23:35 PM PST 23 427865392 ps
T429 /workspace/coverage/default/13.sram_ctrl_smoke.104399096995988127339294919561358189516809149674567582678354513640940896460600 Nov 22 01:21:33 PM PST 23 Nov 22 01:21:52 PM PST 23 427865392 ps
T430 /workspace/coverage/default/36.sram_ctrl_mem_walk.113257187264067867832995736817464726273393669072602221372717539294943162727943 Nov 22 01:22:37 PM PST 23 Nov 22 01:22:49 PM PST 23 590810517 ps
T431 /workspace/coverage/default/46.sram_ctrl_bijection.1090208392977946909696896308229569128600922510397535934146888034434036767156 Nov 22 01:23:07 PM PST 23 Nov 22 01:24:39 PM PST 23 9249473390 ps
T432 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.28342679084446201512968261716123970431905285300927493476157934709727378690667 Nov 22 01:21:59 PM PST 23 Nov 22 01:28:00 PM PST 23 6491370455 ps
T433 /workspace/coverage/default/42.sram_ctrl_max_throughput.86212585281785893193385345796489193405976647078628730584236094335256671474227 Nov 22 01:22:51 PM PST 23 Nov 22 01:24:31 PM PST 23 209242141 ps
T434 /workspace/coverage/default/28.sram_ctrl_stress_all.72400854488576152824533428044769779805398717950991977974340764539542073926779 Nov 22 01:22:38 PM PST 23 Nov 22 02:24:32 PM PST 23 121463254244 ps
T435 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.74455139782275209988555315316271641587060704829595054234964247875453553263116 Nov 22 01:22:52 PM PST 23 Nov 22 01:31:56 PM PST 23 42305619653 ps
T436 /workspace/coverage/default/16.sram_ctrl_max_throughput.108585879890942967653849109386649387548380623835853722684734460753932613803881 Nov 22 01:21:52 PM PST 23 Nov 22 01:23:44 PM PST 23 209242141 ps
T437 /workspace/coverage/default/23.sram_ctrl_ram_cfg.71430735988235233880238058256180454947882893116992627251014074137158537324419 Nov 22 01:22:08 PM PST 23 Nov 22 01:22:13 PM PST 23 40672061 ps
T438 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.50302660298010243769468544089980249872489754309218574675061781670927473005442 Nov 22 01:22:44 PM PST 23 Nov 22 01:24:38 PM PST 23 237420487 ps
T439 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.16776838060477523121894537745347088066982635387990412622831157766561225621437 Nov 22 01:22:22 PM PST 23 Nov 22 01:44:31 PM PST 23 624328106 ps
T440 /workspace/coverage/default/45.sram_ctrl_ram_cfg.913086285923634960151101481117415916892291691642064295715320372530225746290 Nov 22 01:22:52 PM PST 23 Nov 22 01:23:07 PM PST 23 40672061 ps
T441 /workspace/coverage/default/10.sram_ctrl_lc_escalation.90872380840858391219159665013181286968861086935184236665862193144457048404973 Nov 22 01:21:14 PM PST 23 Nov 22 01:21:22 PM PST 23 985753786 ps
T442 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.394108886655264563839910541711247020109034715106605004660392877300166304482 Nov 22 01:21:57 PM PST 23 Nov 22 01:40:44 PM PST 23 624328106 ps
T443 /workspace/coverage/default/10.sram_ctrl_executable.43981064454737590352666334944910001086258496992053971820155644136165661450197 Nov 22 01:22:25 PM PST 23 Nov 22 01:34:50 PM PST 23 23162112088 ps
T444 /workspace/coverage/default/27.sram_ctrl_regwen.39844845131640816048226203779187022299694747594340744551674539286471651363712 Nov 22 01:23:01 PM PST 23 Nov 22 01:30:56 PM PST 23 19383553031 ps
T445 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.60532744262632131955456028347931623453296497322954179499971869502501373599321 Nov 22 01:22:31 PM PST 23 Nov 22 01:23:58 PM PST 23 237420487 ps
T446 /workspace/coverage/default/46.sram_ctrl_alert_test.23938052518927580169512173708219581107005061284742570606278691172629005306608 Nov 22 01:23:25 PM PST 23 Nov 22 01:23:40 PM PST 23 16600825 ps
T447 /workspace/coverage/default/47.sram_ctrl_ram_cfg.30586037327003083421169203127303714462087808201587482696809118899238940759632 Nov 22 01:23:13 PM PST 23 Nov 22 01:23:22 PM PST 23 40672061 ps
T448 /workspace/coverage/default/0.sram_ctrl_smoke.16566756496039585742432328253740532533122801855974305908554147087810027484430 Nov 22 01:21:25 PM PST 23 Nov 22 01:21:46 PM PST 23 427865392 ps
T449 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.31871177499736058379082866657305805841102306376816282711362344667802905502638 Nov 22 01:21:29 PM PST 23 Nov 22 01:27:15 PM PST 23 6491370455 ps
T450 /workspace/coverage/default/8.sram_ctrl_multiple_keys.59324070730549328470587203995667987605031876589872948090160619857091363116144 Nov 22 01:21:31 PM PST 23 Nov 22 01:33:14 PM PST 23 21947461091 ps
T451 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.13903408617780760771046638753693444723458046349074207262676404061605770791083 Nov 22 01:22:13 PM PST 23 Nov 22 01:31:12 PM PST 23 42305619653 ps
T452 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.34416117097049423429081878222168926318002376749334695313517359229418744790470 Nov 22 01:23:22 PM PST 23 Nov 22 01:36:37 PM PST 23 4471404472 ps
T453 /workspace/coverage/default/43.sram_ctrl_regwen.33883016682683902559812497807717087207816021779290180610186513511621772622630 Nov 22 01:22:43 PM PST 23 Nov 22 01:32:17 PM PST 23 19383553031 ps
T454 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.88409666489794234881643821925602129744833700314039488219926898318824804900660 Nov 22 01:23:19 PM PST 23 Nov 22 01:29:09 PM PST 23 6491370455 ps
T455 /workspace/coverage/default/21.sram_ctrl_mem_walk.48780612681691963611874762578071176141171056464908781300244715508990686378399 Nov 22 01:21:53 PM PST 23 Nov 22 01:22:05 PM PST 23 590810517 ps
T456 /workspace/coverage/default/9.sram_ctrl_smoke.52405322244210542872684244780245642756506570679308041845496560130761966386328 Nov 22 01:21:22 PM PST 23 Nov 22 01:21:42 PM PST 23 427865392 ps
T457 /workspace/coverage/default/10.sram_ctrl_bijection.115411313124365479517346108826013996866640495613298900445950805610760908543624 Nov 22 01:21:21 PM PST 23 Nov 22 01:22:52 PM PST 23 9249473390 ps
T458 /workspace/coverage/default/22.sram_ctrl_lc_escalation.54080479405124034563655053727741292576535566043793349751170584090229963129277 Nov 22 01:21:59 PM PST 23 Nov 22 01:22:12 PM PST 23 985753786 ps
T459 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.35044528018834678205149351381305418368950485118888792083548601488788182677430 Nov 22 01:22:34 PM PST 23 Nov 22 01:34:59 PM PST 23 4471404472 ps
T460 /workspace/coverage/default/42.sram_ctrl_mem_walk.20448492074437971816018312519813297485942306557920626853295868560017650063307 Nov 22 01:23:07 PM PST 23 Nov 22 01:23:23 PM PST 23 590810517 ps
T461 /workspace/coverage/default/41.sram_ctrl_alert_test.59120846017129955808395679441941611242045413325234970168285682230983509152776 Nov 22 01:24:04 PM PST 23 Nov 22 01:24:13 PM PST 23 16600825 ps
T462 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.77716753504190530251955522459643201463957837120179292982024503284859226136048 Nov 22 01:23:31 PM PST 23 Nov 22 01:35:49 PM PST 23 4471404472 ps
T463 /workspace/coverage/default/23.sram_ctrl_regwen.59579589077780271655019092999962827779753502371707735311141182808373580079766 Nov 22 01:22:00 PM PST 23 Nov 22 01:29:41 PM PST 23 19383553031 ps
T464 /workspace/coverage/default/48.sram_ctrl_multiple_keys.54052587566274673149689905166056697990192628763678706047295110940316686494825 Nov 22 01:23:09 PM PST 23 Nov 22 01:40:05 PM PST 23 21947461091 ps
T465 /workspace/coverage/default/29.sram_ctrl_ram_cfg.31015990354002846304485019737698002850185134050043163071654231187896977474701 Nov 22 01:22:07 PM PST 23 Nov 22 01:22:12 PM PST 23 40672061 ps
T466 /workspace/coverage/default/26.sram_ctrl_ram_cfg.2489872445264126813967033031374526279483698132321110652280418157175587996998 Nov 22 01:22:08 PM PST 23 Nov 22 01:22:12 PM PST 23 40672061 ps
T467 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.29602726678192382767746124875642795097217082769247553132954910302336101728519 Nov 22 01:21:49 PM PST 23 Nov 22 01:35:26 PM PST 23 4471404472 ps
T468 /workspace/coverage/default/44.sram_ctrl_partial_access.46368212064825787790361824114697899037577857494037569201948508496977174383315 Nov 22 01:22:52 PM PST 23 Nov 22 01:23:18 PM PST 23 445204539 ps
T469 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.9187533895604004838098505881131094625513989162640490661888475263113836849677 Nov 22 01:21:56 PM PST 23 Nov 22 01:31:00 PM PST 23 42305619653 ps
T470 /workspace/coverage/default/30.sram_ctrl_lc_escalation.100608547352060358925212440525064701983471475693909643577729233219688161577659 Nov 22 01:22:30 PM PST 23 Nov 22 01:22:42 PM PST 23 985753786 ps
T471 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.84352338884672114961306165606696335247673590330400477491337908204805247852587 Nov 22 01:21:45 PM PST 23 Nov 22 01:34:47 PM PST 23 4471404472 ps
T472 /workspace/coverage/default/39.sram_ctrl_max_throughput.102961116934249270165048711712805341800017528271010998962912653368205729971858 Nov 22 01:22:58 PM PST 23 Nov 22 01:24:37 PM PST 23 209242141 ps
T473 /workspace/coverage/default/49.sram_ctrl_executable.1087166034442462440366884095814138148271088447918626609406917800846491407259 Nov 22 01:25:00 PM PST 23 Nov 22 01:37:54 PM PST 23 23162112088 ps
T474 /workspace/coverage/default/47.sram_ctrl_regwen.18193712575832323426956200144465581294571174614611342797703030918370653996204 Nov 22 01:23:12 PM PST 23 Nov 22 01:31:51 PM PST 23 19383553031 ps
T475 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.25488888257095237512278335044303526564856350236626303081084972114388428794148 Nov 22 01:22:57 PM PST 23 Nov 22 01:46:46 PM PST 23 624328106 ps
T476 /workspace/coverage/default/35.sram_ctrl_ram_cfg.64297680378420833827503765600204153944295092673261478027823744724011384496383 Nov 22 01:22:43 PM PST 23 Nov 22 01:22:50 PM PST 23 40672061 ps
T477 /workspace/coverage/default/42.sram_ctrl_regwen.77226825393390122072862267926176659362712049084486891977484653230943413981604 Nov 22 01:22:45 PM PST 23 Nov 22 01:31:00 PM PST 23 19383553031 ps
T478 /workspace/coverage/default/4.sram_ctrl_ram_cfg.47890552067783369109805107752724097416438771819371307801209140276211436800450 Nov 22 01:22:27 PM PST 23 Nov 22 01:22:33 PM PST 23 40672061 ps
T479 /workspace/coverage/default/28.sram_ctrl_executable.42375984090776429069506654485708972917730023123997919561511986223463535698503 Nov 22 01:22:04 PM PST 23 Nov 22 01:33:48 PM PST 23 23162112088 ps
T480 /workspace/coverage/default/48.sram_ctrl_stress_all.41996390314102246718287842624170028316489785098543021381249895710978836055540 Nov 22 01:24:13 PM PST 23 Nov 22 02:13:31 PM PST 23 121463254244 ps
T481 /workspace/coverage/default/35.sram_ctrl_alert_test.55105659205311265277289162767016342878791143991530192131908483291057430744527 Nov 22 01:22:26 PM PST 23 Nov 22 01:22:31 PM PST 23 16600825 ps
T482 /workspace/coverage/default/48.sram_ctrl_executable.111334045010501767719041130869676021105475903635299206760690450077978492888496 Nov 22 01:23:26 PM PST 23 Nov 22 01:34:02 PM PST 23 23162112088 ps
T483 /workspace/coverage/default/6.sram_ctrl_partial_access.14344941421282415197790422528215028224121193866675870664768453848515694362217 Nov 22 01:22:06 PM PST 23 Nov 22 01:22:23 PM PST 23 445204539 ps
T484 /workspace/coverage/default/33.sram_ctrl_regwen.115363977783405376774400749958068672413345126611447505898583379149611502434843 Nov 22 01:23:25 PM PST 23 Nov 22 01:32:37 PM PST 23 19383553031 ps
T485 /workspace/coverage/default/23.sram_ctrl_multiple_keys.86824711280584181114870777528222599844432013641000964516905181317253589225468 Nov 22 01:21:46 PM PST 23 Nov 22 01:35:23 PM PST 23 21947461091 ps
T486 /workspace/coverage/default/24.sram_ctrl_executable.19013534387680855534547191089397367527864497645710905983060881419247465859468 Nov 22 01:21:49 PM PST 23 Nov 22 01:34:48 PM PST 23 23162112088 ps
T487 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.86137224317685889341543759281640945851930666147399327462884092107108096705522 Nov 22 01:24:17 PM PST 23 Nov 22 01:24:25 PM PST 23 166171057 ps
T488 /workspace/coverage/default/4.sram_ctrl_partial_access.4940226391140546894112416985046233697431337210926695151215166443504139616827 Nov 22 01:20:55 PM PST 23 Nov 22 01:21:14 PM PST 23 445204539 ps
T489 /workspace/coverage/default/32.sram_ctrl_executable.9740382114373206947392754368835889072663368179262818855709027234917308199746 Nov 22 01:22:58 PM PST 23 Nov 22 01:36:18 PM PST 23 23162112088 ps
T490 /workspace/coverage/default/16.sram_ctrl_executable.1265166489056857458447762318616672440674267016167454286793016338233567345644 Nov 22 01:21:44 PM PST 23 Nov 22 01:33:24 PM PST 23 23162112088 ps
T491 /workspace/coverage/default/35.sram_ctrl_smoke.79383791886118158408079122696954859043738329820834469964886031397122092653333 Nov 22 01:22:32 PM PST 23 Nov 22 01:22:51 PM PST 23 427865392 ps
T492 /workspace/coverage/default/45.sram_ctrl_mem_walk.3006672260875410308113425830547210403519944616268564670185122976566384354711 Nov 22 01:22:58 PM PST 23 Nov 22 01:23:13 PM PST 23 590810517 ps
T493 /workspace/coverage/default/4.sram_ctrl_mem_walk.114237115983677022646018535912072560449808644796688586618989058644678564066439 Nov 22 01:21:08 PM PST 23 Nov 22 01:21:15 PM PST 23 590810517 ps
T494 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.91676495776561747044140572093061711019480363830324939684922621707784460602020 Nov 22 01:22:25 PM PST 23 Nov 22 01:28:31 PM PST 23 6491370455 ps
T495 /workspace/coverage/default/27.sram_ctrl_executable.80846146577615822881418928147045792156230186067850062840403302067304612805862 Nov 22 01:22:04 PM PST 23 Nov 22 01:33:50 PM PST 23 23162112088 ps
T496 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.56278749709228532248327132687351197262289842169004446641856246862663355101268 Nov 22 01:21:49 PM PST 23 Nov 22 01:21:57 PM PST 23 166171057 ps
T497 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.15571965833865165232415295309417857238301350416218078308993670274030180286197 Nov 22 01:22:52 PM PST 23 Nov 22 01:23:10 PM PST 23 166171057 ps
T498 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.89295612533940830866940960316650210888898258651576111245482824728733273376759 Nov 22 01:21:48 PM PST 23 Nov 22 01:30:59 PM PST 23 42305619653 ps
T499 /workspace/coverage/default/6.sram_ctrl_alert_test.16331368040532629229140035269798102078836892359583651510777027652395832003187 Nov 22 01:21:36 PM PST 23 Nov 22 01:21:45 PM PST 23 16600825 ps
T500 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.74961015367579663032371719452050356279523567233570566776407612386285501567382 Nov 22 01:22:13 PM PST 23 Nov 22 01:23:52 PM PST 23 237420487 ps
T501 /workspace/coverage/default/30.sram_ctrl_executable.81370272792579631566324389520701432651883299742492073476851101002518394578588 Nov 22 01:22:28 PM PST 23 Nov 22 01:36:06 PM PST 23 23162112088 ps
T502 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.51931712574251695239354443975205412772506780642130248261983516765130357251462 Nov 22 01:22:51 PM PST 23 Nov 22 01:24:27 PM PST 23 237420487 ps
T503 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.100665002534881425114899479582572198107136907760628814611512338803230615107857 Nov 22 01:22:30 PM PST 23 Nov 22 01:28:46 PM PST 23 6491370455 ps
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