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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.95 100.00 97.69 99.14 100.00 99.71 99.70 96.44


Total test records in report: 1040
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T36 /workspace/coverage/default/2.sram_ctrl_sec_cm.78234893032765485781182879195705033659514577066937459000542609645314798573624 Nov 22 01:20:49 PM PST 23 Nov 22 01:20:54 PM PST 23 216402798 ps
T1002 /workspace/coverage/default/9.sram_ctrl_partial_access.66259496480549433744624919127382445027657773122920471507374287844260032628095 Nov 22 01:21:30 PM PST 23 Nov 22 01:21:52 PM PST 23 445204539 ps
T1003 /workspace/coverage/default/35.sram_ctrl_lc_escalation.3348131799982806050124791055071728071212107280019231492148172698151609558623 Nov 22 01:22:34 PM PST 23 Nov 22 01:22:46 PM PST 23 985753786 ps
T1004 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.84561377665473038285458825499755269632339656604554810582752011106176887211373 Nov 22 01:21:12 PM PST 23 Nov 22 01:30:15 PM PST 23 42305619653 ps
T1005 /workspace/coverage/default/22.sram_ctrl_smoke.6063536473414437932862596536473886806400844333505554729515063842050471746681 Nov 22 01:22:25 PM PST 23 Nov 22 01:22:40 PM PST 23 427865392 ps
T1006 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.63278542981218018898464963124534747204230488440479700846790714098843120549110 Nov 22 01:21:58 PM PST 23 Nov 22 01:27:52 PM PST 23 6491370455 ps
T1007 /workspace/coverage/default/16.sram_ctrl_regwen.72994366006509465993318891549357510486188456932232867133699311172959014876683 Nov 22 01:21:47 PM PST 23 Nov 22 01:31:06 PM PST 23 19383553031 ps
T1008 /workspace/coverage/default/21.sram_ctrl_bijection.55985661758311689086775878590755089395193157028963567776948493798304325203003 Nov 22 01:23:22 PM PST 23 Nov 22 01:24:55 PM PST 23 9249473390 ps
T1009 /workspace/coverage/default/0.sram_ctrl_alert_test.24075098194029623788211001002485949201512845765496266033602947147462055852768 Nov 22 01:21:29 PM PST 23 Nov 22 01:21:37 PM PST 23 16600825 ps
T1010 /workspace/coverage/default/49.sram_ctrl_bijection.2369716376398768214210684996491888436423404626704583315000367965051552164072 Nov 22 01:23:38 PM PST 23 Nov 22 01:25:13 PM PST 23 9249473390 ps
T1011 /workspace/coverage/default/45.sram_ctrl_lc_escalation.4142548324665885882697066011298168233135514340577872670008386375490744858099 Nov 22 01:22:55 PM PST 23 Nov 22 01:23:14 PM PST 23 985753786 ps
T1012 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.100714385279725271632459920497588600050225885989672851693442229107417554753768 Nov 22 01:23:05 PM PST 23 Nov 22 01:29:07 PM PST 23 6491370455 ps
T1013 /workspace/coverage/default/12.sram_ctrl_ram_cfg.107444977533972123586056613076129867218931447910442443332358121074047948091265 Nov 22 01:21:12 PM PST 23 Nov 22 01:21:14 PM PST 23 40672061 ps
T1014 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.108501634093600549896264117295391849352094156490731532437216202419874938412268 Nov 22 01:22:22 PM PST 23 Nov 22 01:31:20 PM PST 23 42305619653 ps
T1015 /workspace/coverage/default/34.sram_ctrl_lc_escalation.67688649650792343254566134228176713078101181672836226540055281658710153999071 Nov 22 01:22:44 PM PST 23 Nov 22 01:23:03 PM PST 23 985753786 ps
T1016 /workspace/coverage/default/5.sram_ctrl_ram_cfg.104982298674061409626793245010376817831671550755350645209443772788291484626062 Nov 22 01:21:33 PM PST 23 Nov 22 01:21:40 PM PST 23 40672061 ps
T1017 /workspace/coverage/default/37.sram_ctrl_partial_access.78468294694908108750260921206023010864639547306847363809963535417648515392197 Nov 22 01:22:25 PM PST 23 Nov 22 01:22:42 PM PST 23 445204539 ps
T1018 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.78106253706552084859486058649466330033060836354345865707738547989927601820716 Nov 22 01:21:27 PM PST 23 Nov 22 01:21:40 PM PST 23 166171057 ps
T1019 /workspace/coverage/default/26.sram_ctrl_max_throughput.3927906530146779319837771979229813388839929404120532785928597892519568622824 Nov 22 01:22:36 PM PST 23 Nov 22 01:24:03 PM PST 23 209242141 ps
T1020 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.95084595706055705461805702240933894320440164539509660218682480951768243703896 Nov 22 01:21:15 PM PST 23 Nov 22 01:27:20 PM PST 23 6491370455 ps
T1021 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.84261187450861594786276704158230136763570879875193095331611899586517206074832 Nov 22 01:22:10 PM PST 23 Nov 22 01:22:17 PM PST 23 166171057 ps
T1022 /workspace/coverage/default/41.sram_ctrl_ram_cfg.64761054167280598574921805514805880248511894769196140996821045404820582868766 Nov 22 01:25:26 PM PST 23 Nov 22 01:25:36 PM PST 23 40672061 ps
T1023 /workspace/coverage/default/21.sram_ctrl_alert_test.94724930932818024819440465083767853005591893726351285608058791069990574877267 Nov 22 01:21:50 PM PST 23 Nov 22 01:21:56 PM PST 23 16600825 ps
T1024 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4790500735461986216542401349145942817350452403592362659996598568229379723425 Nov 22 01:23:20 PM PST 23 Nov 22 01:32:42 PM PST 23 42305619653 ps
T1025 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.96762256270381210423387389987967582881329460046326292336488352425331113439312 Nov 22 01:24:14 PM PST 23 Nov 22 01:25:50 PM PST 23 237420487 ps
T1026 /workspace/coverage/default/16.sram_ctrl_mem_walk.92057940945574498015172537531544081655176744745358545207246189222079919368893 Nov 22 01:22:49 PM PST 23 Nov 22 01:23:08 PM PST 23 590810517 ps
T1027 /workspace/coverage/default/41.sram_ctrl_stress_all.99461594207613885670288294153584717626319501448597985015385359762627974913547 Nov 22 01:23:05 PM PST 23 Nov 22 02:14:55 PM PST 23 121463254244 ps
T1028 /workspace/coverage/default/36.sram_ctrl_regwen.45336721132849854836127742703550917519271297838038247898020491288712671725425 Nov 22 01:22:57 PM PST 23 Nov 22 01:32:07 PM PST 23 19383553031 ps
T1029 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.33778926271562918523284838347564528490678464293331796185108228485265616920329 Nov 22 01:22:24 PM PST 23 Nov 22 01:36:56 PM PST 23 4471404472 ps
T1030 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.10315948033648406850401567193449642887607965920260139580420637224740254005507 Nov 22 01:21:56 PM PST 23 Nov 22 01:34:39 PM PST 23 4471404472 ps
T1031 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.12516807500782608066810349517197481431180909905567788143891292095053056013180 Nov 22 01:24:38 PM PST 23 Nov 22 01:26:10 PM PST 23 237420487 ps
T1032 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3420903167008046249130934732423653252658937877092644614278626837936135512139 Nov 22 01:22:15 PM PST 23 Nov 22 01:31:30 PM PST 23 42305619653 ps
T1033 /workspace/coverage/default/11.sram_ctrl_lc_escalation.44742003966853512871562851048817234616186258361182237635647878697146689424467 Nov 22 01:21:39 PM PST 23 Nov 22 01:21:54 PM PST 23 985753786 ps
T1034 /workspace/coverage/default/19.sram_ctrl_max_throughput.102676048895807797360642450420715112242212212011129938853182037233537985400418 Nov 22 01:22:08 PM PST 23 Nov 22 01:23:54 PM PST 23 209242141 ps
T1035 /workspace/coverage/default/19.sram_ctrl_lc_escalation.52474413591430268079992298837689666487812619830607654715809131452477542321112 Nov 22 01:22:25 PM PST 23 Nov 22 01:22:36 PM PST 23 985753786 ps
T1036 /workspace/coverage/default/20.sram_ctrl_regwen.24419242215727041997140615097843236593222569478661520169593515042449475062827 Nov 22 01:22:23 PM PST 23 Nov 22 01:30:11 PM PST 23 19383553031 ps
T1037 /workspace/coverage/default/45.sram_ctrl_max_throughput.50454740754571347439615712435448981284353617917595676401180731100501637162240 Nov 22 01:22:56 PM PST 23 Nov 22 01:24:55 PM PST 23 209242141 ps
T1038 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.55535587830135771762195911574442532352008834932809203937225104449225979757655 Nov 22 01:22:01 PM PST 23 Nov 22 01:22:10 PM PST 23 166171057 ps
T1039 /workspace/coverage/default/25.sram_ctrl_lc_escalation.47040977288825319334560947122291793954184902997786475893715067910772454543081 Nov 22 01:22:00 PM PST 23 Nov 22 01:22:13 PM PST 23 985753786 ps
T1040 /workspace/coverage/default/13.sram_ctrl_alert_test.59391692174432697692130610185256394209430956999849849711262438229466940172622 Nov 22 01:21:39 PM PST 23 Nov 22 01:21:46 PM PST 23 16600825 ps

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.58041269111263173602035132205774936985529583341179463634931855796375552631540
Short name T9
Test name
Test status
Simulation time 624328106 ps
CPU time 1178.83 seconds
Started Nov 22 01:21:51 PM PST 23
Finished Nov 22 01:41:35 PM PST 23
Peak memory 401808 kb
Host smart-a859c87e-8dde-4e7b-9da5-8b5c2c73ab72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=58041269111263173602035132205774936985529583341179463634931855796375552631540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sr
am_ctrl_stress_all_with_rand_reset.58041269111263173602035132205774936985529583341179463634931855796375552631540
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.60045879587160768985927629605426237556494197672234785830979156816792445551220
Short name T6
Test name
Test status
Simulation time 985753786 ps
CPU time 7.13 seconds
Started Nov 22 01:21:10 PM PST 23
Finished Nov 22 01:21:19 PM PST 23
Peak memory 213096 kb
Host smart-520cc926-cbed-4f91-b3b8-18710224cc58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60045879587160768985927629605426237556494197672234785830979156816792445551220 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.60045879587160768985927629605426237556494197672234785830979156816792445551220
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.76726527580172217618791812908426891607929464264584408294629745670964042896504
Short name T29
Test name
Test status
Simulation time 121463254244 ps
CPU time 2937.5 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 02:11:37 PM PST 23
Peak memory 375472 kb
Host smart-82f0db81-cf14-4f15-b982-66c954cedef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767265275801722176187918129084268916079294642645844082946297456
70964042896504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.76726527580172217618791812908426891607929464264
584408294629745670964042896504
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.105861264971836690020339957343268083172882015463530050502744729721408938984988
Short name T46
Test name
Test status
Simulation time 163313937 ps
CPU time 1.38 seconds
Started Nov 22 01:19:35 PM PST 23
Finished Nov 22 01:19:42 PM PST 23
Peak memory 202124 kb
Host smart-5bb8bd5a-665c-4129-a40b-f4e7150a7438
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10586126497183669002033995734326808317288201546353005050274
4729721408938984988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_intg_err.105861264971836690020339957343268083172
882015463530050502744729721408938984988
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.55983411729176806502455630785210082049545572347247520691748698980290293625625
Short name T24
Test name
Test status
Simulation time 216402798 ps
CPU time 1.93 seconds
Started Nov 22 01:20:51 PM PST 23
Finished Nov 22 01:20:58 PM PST 23
Peak memory 220880 kb
Host smart-e1b2e644-c576-44fe-b083-e47e6aedee26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5598341172917680650245563078521008204954557234724752069174869898029
0293625625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.559834117291768065024556307852100820495455723472475206917486
98980290293625625
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.92230461474630756704872839486050080274745421273963753806409216693576713039293
Short name T70
Test name
Test status
Simulation time 42305619653 ps
CPU time 537.01 seconds
Started Nov 22 01:22:07 PM PST 23
Finished Nov 22 01:31:08 PM PST 23
Peak memory 202692 kb
Host smart-324871c8-89b2-4ead-be32-1075f19b9dc3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922304614746307567048728394860500802747454212739637538064092166935767
13039293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access_b2b.9223046147463075670487283948605008027474
5421273963753806409216693576713039293
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.68167615268811460100428819532594057331999668096690227688706183187060065636988
Short name T27
Test name
Test status
Simulation time 362187346 ps
CPU time 2.86 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:51 PM PST 23
Peak memory 202468 kb
Host smart-8713b649-66e3-422a-a4e6-88128e25e54f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68167615268811460100428819532594057331999668096690227688
706183187060065636988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.6816761526881146010042881
9532594057331999668096690227688706183187060065636988
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.111752112965823221019648180746892051141437160238632699910621944190893099832236
Short name T78
Test name
Test status
Simulation time 4471404472 ps
CPU time 802.44 seconds
Started Nov 22 01:22:32 PM PST 23
Finished Nov 22 01:36:00 PM PST 23
Peak memory 375448 kb
Host smart-1eff40c7-82dd-475c-8c24-333facef593d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11175211296582322101964818074689205114143716023863269991062194419089309983223
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during_key_req.11175211296582322101964818074689205114
1437160238632699910621944190893099832236
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.78486342165084766254364803923343521716211054588174865349805454906242608783702
Short name T100
Test name
Test status
Simulation time 19383553031 ps
CPU time 522.99 seconds
Started Nov 22 01:21:07 PM PST 23
Finished Nov 22 01:29:51 PM PST 23
Peak memory 371752 kb
Host smart-880c81ba-660f-4b91-8be5-f280e1ce02c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78486342165084766254364803923343521716211054588174865349805454906242608783702 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.78486342165084766254364803923343521716211054588174865349805454906242608783702
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.68253042602769110272402572026313878604775189191575732875741155817537179402571
Short name T305
Test name
Test status
Simulation time 40672061 ps
CPU time 0.83 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 202636 kb
Host smart-b1635b9d-3e1a-4056-810b-6d63a4620b09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68253042602769110272402572026313878604775189191575732875741155817537179402571 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.68253042602769110272402572026313878604775189191575732875741155817537179402571
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.2694422976414111949966599320350913487708001951176535173087310513701881384822
Short name T105
Test name
Test status
Simulation time 23162112088 ps
CPU time 678.46 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:33:48 PM PST 23
Peak memory 364500 kb
Host smart-24e72986-8c22-4aeb-8800-73013f33727b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694422976414111949966599320350913487708001951176535173087310513701881384822 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.2694422976414111949966599320350913487708001951176535173087310513701881384822
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.32631246427085174073686477193781337387315092135184159500933604996787251059138
Short name T15
Test name
Test status
Simulation time 6491370455 ps
CPU time 371.47 seconds
Started Nov 22 01:21:44 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 202680 kb
Host smart-40dfb315-a3af-466f-813b-f88e38172399
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32631246427085174073686477193781337387315092135184159500933604996787251059138
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.326312464270851740736864771937813373873150921351841
59500933604996787251059138
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.92536050078508482800888807922858104493572145598988197092959547932662646363543
Short name T141
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 202184 kb
Host smart-13c9b512-bc68-4a12-b857-3b92afc72dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925360500785084828008888079228581044935721455989881970929595479326
62646363543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.9253605007850848280088880792285810449357214559898819709
2959547932662646363543
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.35344207087126131876085535942104836476676219653903720130087161502267037731861
Short name T182
Test name
Test status
Simulation time 22582920 ps
CPU time 0.67 seconds
Started Nov 22 01:19:38 PM PST 23
Finished Nov 22 01:19:45 PM PST 23
Peak memory 202056 kb
Host smart-db76a9fe-387e-4915-9146-5d41c3dbea97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35344207087126131876085535942104836476676219653903720130087161
502267037731861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_aliasing.3534420708712613187608553594210483647667621
9653903720130087161502267037731861
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.58858551621889702820276308727602337265130006528830258127011400908844321094123
Short name T195
Test name
Test status
Simulation time 122117838 ps
CPU time 1.32 seconds
Started Nov 22 01:19:53 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 202352 kb
Host smart-6607e48c-804f-4b59-951c-6e0c58b60055
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58858551621889702820276308727602337265130006528830258127011400
908844321094123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.5885855162188970282027630872760233726513000
6528830258127011400908844321094123
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.85477587543772301161717503353775504570907188800391731153769022184699505533068
Short name T62
Test name
Test status
Simulation time 23779339 ps
CPU time 0.65 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 201936 kb
Host smart-cda59aaf-8609-45e1-a174-c3c90ad61937
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85477587543772301161717503353775504570907188800391731153769022
184699505533068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_reset.8547758754377230116171750335377550457090718
8800391731153769022184699505533068
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.91479072273175075306070035600393194863106187162924901989995271800029054899610
Short name T192
Test name
Test status
Simulation time 42439904 ps
CPU time 0.86 seconds
Started Nov 22 01:19:38 PM PST 23
Finished Nov 22 01:19:46 PM PST 23
Peak memory 202176 kb
Host smart-4865ca4f-6d42-4759-b23d-918fc6db1579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914790722731750
75306070035600393194863106187162924901989995271800029054899610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_r
w_with_rand_reset.91479072273175075306070035600393194863106187162924901989995271800029054899610
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.68004552515598517176285873730012749612904937691785856865985375250281683891349
Short name T202
Test name
Test status
Simulation time 19547230 ps
CPU time 0.66 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 201856 kb
Host smart-8acb5fca-534b-4322-9b26-d6e3d8de4c43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68004552515598517176285873730012749612904937691785856865985375250281
683891349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.6800455251559851717628587373001274961290493769178585686
5985375250281683891349
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.32922490899492211048740377386708372575801231695150379238736533621097615099682
Short name T247
Test name
Test status
Simulation time 362187346 ps
CPU time 2.81 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:51 PM PST 23
Peak memory 202208 kb
Host smart-ac1c3aa0-a0b8-43bb-a622-7e17a6e225d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32922490899492211048740377386708372575801231695150379238
736533621097615099682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3292249089949221104874037
7386708372575801231695150379238736533621097615099682
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.70972529052789942649857724977370985461302969962050019404832726849628068485887
Short name T211
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:19:40 PM PST 23
Finished Nov 22 01:19:46 PM PST 23
Peak memory 201968 kb
Host smart-e0bedbae-7954-4d2d-9535-c80f8f6ce2b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70972529052789942649857724977370985461302969962050
019404832726849628068485887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.70972529052789942649857
724977370985461302969962050019404832726849628068485887
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.17217097611709392722999442758759508812545957286593685436003930116258728363293
Short name T54
Test name
Test status
Simulation time 117100021 ps
CPU time 2.49 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:56 PM PST 23
Peak memory 202288 kb
Host smart-75c00b4c-4a75-41af-8bfc-6d60ccee8a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17217097611709392722999442758759508812545957286593685436003930116258728
363293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.1721709761170939272299944275875950881254595728659368543
6003930116258728363293
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.7699367062620728182965349957926331386081848309592874590431787377959916141965
Short name T194
Test name
Test status
Simulation time 163313937 ps
CPU time 1.45 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:07 PM PST 23
Peak memory 202316 kb
Host smart-67d6baed-78e7-4f9c-832a-dfa52b149e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76993670626207281829653499579263313860818483095928745904317
87377959916141965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_intg_err.769936706262072818296534995792633138608184
8309592874590431787377959916141965
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.76683178373923319445858241035133579666736679970919315042574679802308715297451
Short name T240
Test name
Test status
Simulation time 22582920 ps
CPU time 0.66 seconds
Started Nov 22 01:19:34 PM PST 23
Finished Nov 22 01:19:38 PM PST 23
Peak memory 201992 kb
Host smart-f07f75f4-c521-4de8-aca1-a0ea94639948
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76683178373923319445858241035133579666736679970919315042574679
802308715297451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_aliasing.7668317837392331944585824103513357966673667
9970919315042574679802308715297451
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.64276510853941309502290112967221466991394370226288981512403686340810363262725
Short name T155
Test name
Test status
Simulation time 122117838 ps
CPU time 1.28 seconds
Started Nov 22 01:19:55 PM PST 23
Finished Nov 22 01:20:01 PM PST 23
Peak memory 202324 kb
Host smart-422228f5-3988-4696-9f52-efc797ddaae2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64276510853941309502290112967221466991394370226288981512403686
340810363262725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.6427651085394130950229011296722146699139437
0226288981512403686340810363262725
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.22937024108480776375185664722497461971361756697455679831022104077183056920281
Short name T226
Test name
Test status
Simulation time 23779339 ps
CPU time 0.66 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 202068 kb
Host smart-9316fa66-a961-46bd-af74-b48b4d56bfa8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22937024108480776375185664722497461971361756697455679831022104
077183056920281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_reset.2293702410848077637518566472249746197136175
6697455679831022104077183056920281
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.17881321297257179224929275493829327007584490127851041689026352800527392999061
Short name T74
Test name
Test status
Simulation time 42439904 ps
CPU time 0.89 seconds
Started Nov 22 01:19:35 PM PST 23
Finished Nov 22 01:19:42 PM PST 23
Peak memory 201552 kb
Host smart-dfa8e657-23ce-44c1-a7cd-801ff8066d0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178813212972571
79224929275493829327007584490127851041689026352800527392999061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_r
w_with_rand_reset.17881321297257179224929275493829327007584490127851041689026352800527392999061
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.20540568762557712705316764335195439831686808225924121824110457876173771387866
Short name T229
Test name
Test status
Simulation time 19547230 ps
CPU time 0.62 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 201992 kb
Host smart-cd35945b-2e8a-4b71-94d4-6f31c720396d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20540568762557712705316764335195439831686808225924121824110457876173
771387866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.2054056876255771270531676433519543983168680822592412182
4110457876173771387866
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.63837900275081450224939668424984364748994281518907393524339178267918912259895
Short name T191
Test name
Test status
Simulation time 23886481 ps
CPU time 0.67 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:49 PM PST 23
Peak memory 201940 kb
Host smart-7b3045a5-4868-46a9-afb4-fd5b377ba177
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63837900275081450224939668424984364748994281518907
393524339178267918912259895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.63837900275081450224939
668424984364748994281518907393524339178267918912259895
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.55301225597065462426600121385056071557568874628244658385475871926404741238731
Short name T189
Test name
Test status
Simulation time 117100021 ps
CPU time 2.39 seconds
Started Nov 22 01:19:51 PM PST 23
Finished Nov 22 01:19:58 PM PST 23
Peak memory 202288 kb
Host smart-f2048f71-bcc5-42da-b614-6bb58e3f64e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55301225597065462426600121385056071557568874628244658385475871926404741
238731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.5530122559706546242660012138505607155756887462824465838
5475871926404741238731
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.51082621758534191823475596832053963699546187025240358594442787446239885574697
Short name T221
Test name
Test status
Simulation time 163313937 ps
CPU time 1.46 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:20:01 PM PST 23
Peak memory 202260 kb
Host smart-03fe0e4f-23b9-4676-ae21-f617f3e95d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51082621758534191823475596832053963699546187025240358594442
787446239885574697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_intg_err.51082621758534191823475596832053963699546
187025240358594442787446239885574697
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.24230074366302847188641141870498691440673437315977087525645900578284387501750
Short name T213
Test name
Test status
Simulation time 42439904 ps
CPU time 0.87 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:49 PM PST 23
Peak memory 202168 kb
Host smart-a03ce74d-b3ff-4164-8d99-b019d6cd2711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242300743663028
47188641141870498691440673437315977087525645900578284387501750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_
rw_with_rand_reset.24230074366302847188641141870498691440673437315977087525645900578284387501750
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.7736057543356939407288076230138740212595468726907831534398721850139410061204
Short name T199
Test name
Test status
Simulation time 19547230 ps
CPU time 0.68 seconds
Started Nov 22 01:19:35 PM PST 23
Finished Nov 22 01:19:42 PM PST 23
Peak memory 201568 kb
Host smart-eee856da-2fd1-4ae2-bfc8-1ec0e9445f16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77360575433569394072880762301387402125954687269078315343987218501394
10061204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.7736057543356939407288076230138740212595468726907831534
398721850139410061204
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.70021960431785744599137763208341306972155498301520972683279592361618758649519
Short name T239
Test name
Test status
Simulation time 362187346 ps
CPU time 2.85 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:51 PM PST 23
Peak memory 202468 kb
Host smart-339bdc4e-728a-452f-ad11-5729c76f3996
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70021960431785744599137763208341306972155498301520972683
279592361618758649519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.700219604317857445991377
63208341306972155498301520972683279592361618758649519
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.38076547875381042446787350901237567823022004888219054591361580233736925058491
Short name T244
Test name
Test status
Simulation time 23886481 ps
CPU time 0.65 seconds
Started Nov 22 01:19:33 PM PST 23
Finished Nov 22 01:19:37 PM PST 23
Peak memory 202024 kb
Host smart-fb168ccf-3eed-4164-9823-ccae61359b8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38076547875381042446787350901237567823022004888219
054591361580233736925058491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3807654787538104244678
7350901237567823022004888219054591361580233736925058491
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.51100835925318828865839338740187743816129544300044659281198761964949354357472
Short name T157
Test name
Test status
Simulation time 117100021 ps
CPU time 2.41 seconds
Started Nov 22 01:19:34 PM PST 23
Finished Nov 22 01:19:41 PM PST 23
Peak memory 202372 kb
Host smart-f98b6ee8-3348-4284-af95-1ec7f5c293d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51100835925318828865839338740187743816129544300044659281198761964949354
357472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.511008359253188288658393387401877438161295443000446592
81198761964949354357472
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.25535170266456198463081862051437548389045825267908035961894498427131300371571
Short name T58
Test name
Test status
Simulation time 42439904 ps
CPU time 0.87 seconds
Started Nov 22 01:19:46 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 202136 kb
Host smart-c0851b8d-c569-4be3-8dcd-9ebdc3504151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255351702664561
98463081862051437548389045825267908035961894498427131300371571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_
rw_with_rand_reset.25535170266456198463081862051437548389045825267908035961894498427131300371571
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.113032343931052855546912603758491979437863147778081512265700264847191668053654
Short name T248
Test name
Test status
Simulation time 19547230 ps
CPU time 0.63 seconds
Started Nov 22 01:19:41 PM PST 23
Finished Nov 22 01:19:49 PM PST 23
Peak memory 201812 kb
Host smart-547f4b34-a124-4575-a39e-3f3846d6df3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11303234393105285554691260375849197943786314777808151226570026484719
1668053654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.11303234393105285554691260375849197943786314777808151
2265700264847191668053654
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.21836586940944478023012462791064583478390939789173665536173513262272315807434
Short name T232
Test name
Test status
Simulation time 362187346 ps
CPU time 2.89 seconds
Started Nov 22 01:19:39 PM PST 23
Finished Nov 22 01:19:48 PM PST 23
Peak memory 202484 kb
Host smart-b089b5c8-381e-4af6-88ef-1f07ed0f5788
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21836586940944478023012462791064583478390939789173665536
173513262272315807434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.218365869409444780230124
62791064583478390939789173665536173513262272315807434
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.99480986044773749480455138613678834948631220260155604595434185307691748402875
Short name T162
Test name
Test status
Simulation time 23886481 ps
CPU time 0.65 seconds
Started Nov 22 01:19:40 PM PST 23
Finished Nov 22 01:19:46 PM PST 23
Peak memory 201968 kb
Host smart-cbf24de4-f287-47a0-a70b-85213923d7ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99480986044773749480455138613678834948631220260155
604595434185307691748402875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.9948098604477374948045
5138613678834948631220260155604595434185307691748402875
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.103612007506538836847025077029823550436906469921374645314266683869062844606745
Short name T246
Test name
Test status
Simulation time 117100021 ps
CPU time 2.4 seconds
Started Nov 22 01:19:37 PM PST 23
Finished Nov 22 01:19:45 PM PST 23
Peak memory 202372 kb
Host smart-cf514dcd-d57e-4a63-a1b7-58775231d5dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10361200750653883684702507702982355043690646992137464531426668386906284
4606745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.10361200750653883684702507702982355043690646992137464
5314266683869062844606745
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4387352708546492315516285356288403907189969804313283653429668542695991288623
Short name T215
Test name
Test status
Simulation time 163313937 ps
CPU time 1.48 seconds
Started Nov 22 01:19:46 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 202268 kb
Host smart-4977d280-3157-4b29-be8b-fa491e1c153b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43873527085464923155162853562884039071899698043132836534296
68542695991288623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_intg_err.43873527085464923155162853562884039071899
69804313283653429668542695991288623
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.101630742544515552691595586033555755317039311660940184469289387613661462905793
Short name T188
Test name
Test status
Simulation time 42439904 ps
CPU time 0.86 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:57 PM PST 23
Peak memory 202208 kb
Host smart-0f4b8544-21d6-4d26-b448-534de4e6f98c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101630742544515
552691595586033555755317039311660940184469289387613661462905793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem
_rw_with_rand_reset.101630742544515552691595586033555755317039311660940184469289387613661462905793
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.49897033721943595653417566815730997249103618714608509491791052743466660781250
Short name T179
Test name
Test status
Simulation time 19547230 ps
CPU time 0.63 seconds
Started Nov 22 01:19:55 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 202076 kb
Host smart-cc881736-f9fa-49c6-b2dd-d9cfe8e6d65a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49897033721943595653417566815730997249103618714608509491791052743466
660781250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.498970337219435956534175668157309972491036187146085094
91791052743466660781250
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.93551197388887001014519168506317190179767117151237086738996316909420767866342
Short name T64
Test name
Test status
Simulation time 362187346 ps
CPU time 2.94 seconds
Started Nov 22 01:19:34 PM PST 23
Finished Nov 22 01:19:42 PM PST 23
Peak memory 202484 kb
Host smart-d49e91fe-ffba-4a5b-90b4-d5dd0725630f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93551197388887001014519168506317190179767117151237086738
996316909420767866342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.935511973888870010145191
68506317190179767117151237086738996316909420767866342
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.73695448191253724263137503358731545994436351972151025923872527451036011324383
Short name T216
Test name
Test status
Simulation time 23886481 ps
CPU time 0.64 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 202028 kb
Host smart-dbb23e77-c240-4b39-9e8f-f733c30fdfbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73695448191253724263137503358731545994436351972151
025923872527451036011324383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.7369544819125372426313
7503358731545994436351972151025923872527451036011324383
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.18825599753572018064268589239735936383743529846490739158296365265137461760596
Short name T223
Test name
Test status
Simulation time 117100021 ps
CPU time 2.38 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 202156 kb
Host smart-e688ee20-e519-4d1e-a4ac-191554379b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18825599753572018064268589239735936383743529846490739158296365265137461
760596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.188255997535720180642685892397359363837435298464907391
58296365265137461760596
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.13045751856660649503020527848423223453025413990491822605324368746543727589952
Short name T184
Test name
Test status
Simulation time 163313937 ps
CPU time 1.57 seconds
Started Nov 22 01:19:46 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 202268 kb
Host smart-453c0d26-8511-4a2c-b16d-696683c1b66a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13045751856660649503020527848423223453025413990491822605324
368746543727589952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_intg_err.1304575185666064950302052784842322345302
5413990491822605324368746543727589952
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.90059446336839697186273114110426183886829809807442143705357707661965927585351
Short name T63
Test name
Test status
Simulation time 42439904 ps
CPU time 0.83 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 202084 kb
Host smart-2aeb0228-83f2-479a-8035-a9991c94814b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900594463368396
97186273114110426183886829809807442143705357707661965927585351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_
rw_with_rand_reset.90059446336839697186273114110426183886829809807442143705357707661965927585351
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.90818558460245025625791724583292395222448303999906859556946807444997167917498
Short name T219
Test name
Test status
Simulation time 19547230 ps
CPU time 0.64 seconds
Started Nov 22 01:19:35 PM PST 23
Finished Nov 22 01:19:41 PM PST 23
Peak memory 202116 kb
Host smart-43eed223-9a40-4e75-887d-75fd15870930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90818558460245025625791724583292395222448303999906859556946807444997
167917498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.908185584602450256257917245832923952224483039999068595
56946807444997167917498
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.82624350122360606170428538691719982108343155043264777863178543041131849273587
Short name T214
Test name
Test status
Simulation time 362187346 ps
CPU time 2.99 seconds
Started Nov 22 01:19:37 PM PST 23
Finished Nov 22 01:19:46 PM PST 23
Peak memory 202408 kb
Host smart-41fae76e-f2b1-4952-87b8-004827ba1a1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82624350122360606170428538691719982108343155043264777863
178543041131849273587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.826243501223606061704285
38691719982108343155043264777863178543041131849273587
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.77874049004641549340748128826576162104263097216942166022604341399284091122360
Short name T176
Test name
Test status
Simulation time 23886481 ps
CPU time 0.65 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 202000 kb
Host smart-8c6b4316-da46-4b52-afcf-5b9b00fe0438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77874049004641549340748128826576162104263097216942
166022604341399284091122360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.7787404900464154934074
8128826576162104263097216942166022604341399284091122360
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.15211662017431585364535629708835902467614254252500294838708123661185820905453
Short name T168
Test name
Test status
Simulation time 117100021 ps
CPU time 2.4 seconds
Started Nov 22 01:19:53 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 202376 kb
Host smart-ba517845-02f6-4ccd-92c7-87aee883db99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15211662017431585364535629708835902467614254252500294838708123661185820
905453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.152116620174315853645356297088359024676142542525002948
38708123661185820905453
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.49256534505087259564197923704178608151190783820590900983820043443483782817306
Short name T207
Test name
Test status
Simulation time 163313937 ps
CPU time 1.51 seconds
Started Nov 22 01:20:05 PM PST 23
Finished Nov 22 01:20:08 PM PST 23
Peak memory 202280 kb
Host smart-35cd38b8-af1a-49fa-a105-fb2615e7c9cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49256534505087259564197923704178608151190783820590900983820
043443483782817306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_intg_err.4925653450508725956419792370417860815119
0783820590900983820043443483782817306
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.108287363851949525233282096048095334682194873719609682232769984482063781932991
Short name T206
Test name
Test status
Simulation time 42439904 ps
CPU time 0.85 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 202084 kb
Host smart-145ec780-339c-4e38-b07b-4b0bde853061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108287363851949
525233282096048095334682194873719609682232769984482063781932991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem
_rw_with_rand_reset.108287363851949525233282096048095334682194873719609682232769984482063781932991
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.65643416318912618310359095735841338186243567193020076755603593738925666711011
Short name T172
Test name
Test status
Simulation time 19547230 ps
CPU time 0.65 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:39 PM PST 23
Peak memory 201552 kb
Host smart-77a8094f-a285-42ce-856c-f48c733f36aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65643416318912618310359095735841338186243567193020076755603593738925
666711011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.656434163189126183103590957358413381862435671930200767
55603593738925666711011
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4952281565772374971364403492063121619677453345316802155191118673957273890692
Short name T201
Test name
Test status
Simulation time 362187346 ps
CPU time 2.89 seconds
Started Nov 22 01:20:14 PM PST 23
Finished Nov 22 01:20:18 PM PST 23
Peak memory 202464 kb
Host smart-2947ad06-06e0-40e4-8316-48d89a43f874
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49522815657723749713644034920631216196774533453168021551
91118673957273890692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.4952281565772374971364403
492063121619677453345316802155191118673957273890692
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.22294918024732629444918098361867153935773056161130822463521931732998582518191
Short name T174
Test name
Test status
Simulation time 23886481 ps
CPU time 0.65 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 202036 kb
Host smart-394aba42-1b19-4e6a-9d1c-ea9a24d2247a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22294918024732629444918098361867153935773056161130
822463521931732998582518191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.2229491802473262944491
8098361867153935773056161130822463521931732998582518191
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.59665042744600541065684859679911134965175284675250136785855129836557911303087
Short name T53
Test name
Test status
Simulation time 117100021 ps
CPU time 2.48 seconds
Started Nov 22 01:19:38 PM PST 23
Finished Nov 22 01:19:47 PM PST 23
Peak memory 202352 kb
Host smart-07ef2817-2c10-4f18-bd2d-d1621c9fe5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59665042744600541065684859679911134965175284675250136785855129836557911
303087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.596650427446005410656848596799111349651752846752501367
85855129836557911303087
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.100946209906833150035105828388771806891278535773644823935880487181859205223373
Short name T208
Test name
Test status
Simulation time 163313937 ps
CPU time 1.54 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 202228 kb
Host smart-184e6027-d972-4d43-b41e-7449d148570b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10094620990683315003510582838877180689127853577364482393588
0487181859205223373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_intg_err.100946209906833150035105828388771806891
278535773644823935880487181859205223373
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.6632676054407902281624500598923414337871904708311143215904300810004289922875
Short name T250
Test name
Test status
Simulation time 42439904 ps
CPU time 0.87 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:40 PM PST 23
Peak memory 201728 kb
Host smart-b454df5b-fc01-4a89-8d57-926b04f99e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663267605440790
2281624500598923414337871904708311143215904300810004289922875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_r
w_with_rand_reset.6632676054407902281624500598923414337871904708311143215904300810004289922875
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.78586549581909820618534686109347446536629475475842355247167863385393907839789
Short name T196
Test name
Test status
Simulation time 19547230 ps
CPU time 0.62 seconds
Started Nov 22 01:19:51 PM PST 23
Finished Nov 22 01:19:56 PM PST 23
Peak memory 202032 kb
Host smart-62fd6848-eee8-4416-93a7-1ac42a81476a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78586549581909820618534686109347446536629475475842355247167863385393
907839789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.785865495819098206185346861093474465366294754758423552
47167863385393907839789
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.86793776140405380349804962695242621025578467860231218679351110454014416055608
Short name T45
Test name
Test status
Simulation time 362187346 ps
CPU time 2.76 seconds
Started Nov 22 01:20:30 PM PST 23
Finished Nov 22 01:20:39 PM PST 23
Peak memory 201464 kb
Host smart-9164b920-53fe-4dc1-851d-b785e33ab458
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86793776140405380349804962695242621025578467860231218679
351110454014416055608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.867937761404053803498049
62695242621025578467860231218679351110454014416055608
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.80585766776139879244547785125294070702538034109677707899276212015461580218576
Short name T75
Test name
Test status
Simulation time 23886481 ps
CPU time 0.64 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:39 PM PST 23
Peak memory 201520 kb
Host smart-0aabb3db-265a-40d5-b572-bc2d31fed773
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80585766776139879244547785125294070702538034109677
707899276212015461580218576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.8058576677613987924454
7785125294070702538034109677707899276212015461580218576
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.42713458726106725733624044128965830514467489613102541026401300231023683200700
Short name T164
Test name
Test status
Simulation time 117100021 ps
CPU time 2.28 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 202312 kb
Host smart-1ef1ff8d-c8be-4900-9823-c1ef1a6411eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42713458726106725733624044128965830514467489613102541026401300231023683
200700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.427134587261067257336240441289658305144674896131025410
26401300231023683200700
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.13343786748517112141492097102901448899442007070416335946101062795258882982384
Short name T235
Test name
Test status
Simulation time 163313937 ps
CPU time 1.46 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:58 PM PST 23
Peak memory 202296 kb
Host smart-2827e875-8045-4d27-8019-fa062a4b6034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343786748517112141492097102901448899442007070416335946101
062795258882982384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_intg_err.1334378674851711214149209710290144889944
2007070416335946101062795258882982384
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.98365029655841680483814258931055833498605232204890498110704517979504855497174
Short name T52
Test name
Test status
Simulation time 42439904 ps
CPU time 0.85 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 201976 kb
Host smart-0cf725b9-233e-4c9d-a81d-aadca98c65fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983650296558416
80483814258931055833498605232204890498110704517979504855497174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_
rw_with_rand_reset.98365029655841680483814258931055833498605232204890498110704517979504855497174
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.107870060953486115357208480003383135328912769371980218661743960182855103324267
Short name T163
Test name
Test status
Simulation time 19547230 ps
CPU time 0.68 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 201976 kb
Host smart-458fbb67-e196-4f6c-8014-a57be9a2de73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10787006095348611535720848000338313532891276937198021866174396018285
5103324267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.10787006095348611535720848000338313532891276937198021
8661743960182855103324267
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.74900152034940443375455228517145841793743098805172123440607142961595195054735
Short name T234
Test name
Test status
Simulation time 362187346 ps
CPU time 2.82 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:42 PM PST 23
Peak memory 202044 kb
Host smart-2a2d7a68-fdca-47d7-a8bc-9b3b52e83fd7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74900152034940443375455228517145841793743098805172123440
607142961595195054735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.749001520349404433754552
28517145841793743098805172123440607142961595195054735
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.36078525296484828726883768991909655906158929168061338682417267949849031923278
Short name T97
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 201892 kb
Host smart-8f13b0ad-14a1-4cbd-a66b-fb89789c5d43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36078525296484828726883768991909655906158929168061
338682417267949849031923278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3607852529648482872688
3768991909655906158929168061338682417267949849031923278
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.69789340410008118413719121965151022080863013649126365144053674210526764945686
Short name T56
Test name
Test status
Simulation time 117100021 ps
CPU time 2.42 seconds
Started Nov 22 01:19:51 PM PST 23
Finished Nov 22 01:19:57 PM PST 23
Peak memory 202364 kb
Host smart-5d037774-6e56-4537-86b4-74e5da6333ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69789340410008118413719121965151022080863013649126365144053674210526764
945686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.697893404100081184137191219651510220808630136491263651
44053674210526764945686
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.39179649918412738471865900625200888079209204192908336468170868406043619592045
Short name T236
Test name
Test status
Simulation time 163313937 ps
CPU time 1.37 seconds
Started Nov 22 01:20:51 PM PST 23
Finished Nov 22 01:20:57 PM PST 23
Peak memory 202176 kb
Host smart-638c3ad7-3da4-4ae8-80d9-a738aedfbcf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39179649918412738471865900625200888079209204192908336468170
868406043619592045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_intg_err.3917964991841273847186590062520088807920
9204192908336468170868406043619592045
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.55329315694734598663475181334013306814871239446796792077829656215045239680324
Short name T167
Test name
Test status
Simulation time 42439904 ps
CPU time 0.89 seconds
Started Nov 22 01:19:55 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 202168 kb
Host smart-73b76a9c-6edc-4c7a-bed7-245c7a8591f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553293156947345
98663475181334013306814871239446796792077829656215045239680324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_
rw_with_rand_reset.55329315694734598663475181334013306814871239446796792077829656215045239680324
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.24277553946059041994574079648469257146304958222502586918990466516895007726065
Short name T231
Test name
Test status
Simulation time 19547230 ps
CPU time 0.6 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 202020 kb
Host smart-96f04d0f-26e7-482f-9df5-ae3b2f544671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24277553946059041994574079648469257146304958222502586918990466516895
007726065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.242775539460590419945740796484692571463049582225025869
18990466516895007726065
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.91097627221304618887338730079719624684597797198583968009709546570378284237156
Short name T89
Test name
Test status
Simulation time 362187346 ps
CPU time 2.91 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:07 PM PST 23
Peak memory 202504 kb
Host smart-202b8539-0dd4-49df-a24f-6bf3f633d77b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91097627221304618887338730079719624684597797198583968009
709546570378284237156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.910976272213046188873387
30079719624684597797198583968009709546570378284237156
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.35187209078562973305188023473699524581470278395362206790508749494948030322192
Short name T28
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:19:55 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 201908 kb
Host smart-2d53f1ae-cb9b-413e-b5e9-98cbcf73808c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35187209078562973305188023473699524581470278395362
206790508749494948030322192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3518720907856297330518
8023473699524581470278395362206790508749494948030322192
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.7190704105138391620292676973648826525904276986573908481804581040222611027995
Short name T212
Test name
Test status
Simulation time 117100021 ps
CPU time 2.24 seconds
Started Nov 22 01:19:38 PM PST 23
Finished Nov 22 01:19:47 PM PST 23
Peak memory 202164 kb
Host smart-59516143-347c-4e65-9db3-4c9df4fb3e28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71907041051383916202926769736488265259042769865739084818045810402226110
27995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.7190704105138391620292676973648826525904276986573908481
804581040222611027995
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.50759051981567218529258820871050158729869386663658695554762341024464412478504
Short name T227
Test name
Test status
Simulation time 163313937 ps
CPU time 1.46 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 202248 kb
Host smart-fa7b9704-de4c-447b-b214-9f4d9ae81a98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50759051981567218529258820871050158729869386663658695554762
341024464412478504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_intg_err.5075905198156721852925882087105015872986
9386663658695554762341024464412478504
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.60648195364381642068265103469963512380757351676543998012437296067259743556540
Short name T230
Test name
Test status
Simulation time 42439904 ps
CPU time 0.85 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 202112 kb
Host smart-7401acfc-da94-4c71-8fbd-c515d420ab47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606481953643816
42068265103469963512380757351676543998012437296067259743556540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_
rw_with_rand_reset.60648195364381642068265103469963512380757351676543998012437296067259743556540
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.94931798977536815209088238339862429778411480317236600409383817374719816370076
Short name T86
Test name
Test status
Simulation time 19547230 ps
CPU time 0.63 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 202084 kb
Host smart-a3b16cde-238f-452c-8730-def71c040f81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94931798977536815209088238339862429778411480317236600409383817374719
816370076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.949317989775368152090882383398624297784114803172366004
09383817374719816370076
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.25304744869156778984002077273703143279954259253185906177654924953765359329273
Short name T65
Test name
Test status
Simulation time 362187346 ps
CPU time 2.84 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:20:02 PM PST 23
Peak memory 202416 kb
Host smart-ed02b053-e76e-48d3-9c2b-0169702ea2f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25304744869156778984002077273703143279954259253185906177
654924953765359329273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.253047448691567789840020
77273703143279954259253185906177654924953765359329273
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.78450693560108860370145682862155610238955982728097626319459689198986703065705
Short name T190
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 202028 kb
Host smart-8dae6574-48c9-46b4-8aec-33b14eaaa0c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78450693560108860370145682862155610238955982728097
626319459689198986703065705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.7845069356010886037014
5682862155610238955982728097626319459689198986703065705
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.108106366045324679377376630169498307392023806530581927602515208833343821551411
Short name T173
Test name
Test status
Simulation time 117100021 ps
CPU time 2.37 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:07 PM PST 23
Peak memory 202392 kb
Host smart-34c3ac95-1d1c-4339-850b-6a5956f537f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810636604532467937737663016949830739202380653058192760251520883334382
1551411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.10810636604532467937737663016949830739202380653058192
7602515208833343821551411
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.33523699205170255826840903290509896875304609488642452149441176261702024192901
Short name T205
Test name
Test status
Simulation time 163313937 ps
CPU time 1.48 seconds
Started Nov 22 01:19:37 PM PST 23
Finished Nov 22 01:19:44 PM PST 23
Peak memory 202208 kb
Host smart-d2bc8a6a-e5d2-4710-a54e-f1d7d9a3780d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33523699205170255826840903290509896875304609488642452149441
176261702024192901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_intg_err.3352369920517025582684090329050989687530
4609488642452149441176261702024192901
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.13460307893174736278521491480544455202872249865895222189998915334498267957559
Short name T181
Test name
Test status
Simulation time 42439904 ps
CPU time 0.89 seconds
Started Nov 22 01:19:55 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 201992 kb
Host smart-9a12201f-b481-49aa-a430-e4762c838037
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134603078931747
36278521491480544455202872249865895222189998915334498267957559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_
rw_with_rand_reset.13460307893174736278521491480544455202872249865895222189998915334498267957559
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.111280950271447359915840902270051363950117758937660693331248210120567825348776
Short name T228
Test name
Test status
Simulation time 19547230 ps
CPU time 0.62 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:06 PM PST 23
Peak memory 201972 kb
Host smart-7b0c969e-3696-403c-a9fd-26a8fdec2a4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11128095027144735991584090227005136395011775893766069333124821012056
7825348776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.11128095027144735991584090227005136395011775893766069
3331248210120567825348776
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.50868298478002042238990009199070756765420572877837268249586639266757208535063
Short name T88
Test name
Test status
Simulation time 362187346 ps
CPU time 2.99 seconds
Started Nov 22 01:19:53 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 202492 kb
Host smart-44cebd10-e285-488b-b59b-2a3ec3427523
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50868298478002042238990009199070756765420572877837268249
586639266757208535063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.508682984780020422389900
09199070756765420572877837268249586639266757208535063
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.85942580501429618612513271456591972090175670803830137390028762629140392573014
Short name T193
Test name
Test status
Simulation time 23886481 ps
CPU time 0.7 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:06 PM PST 23
Peak memory 202024 kb
Host smart-697e117a-d137-4402-9e1c-e361c184091b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85942580501429618612513271456591972090175670803830
137390028762629140392573014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.8594258050142961861251
3271456591972090175670803830137390028762629140392573014
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.62669910071930551012923352123261333564177086043599812189776906835195186013989
Short name T55
Test name
Test status
Simulation time 117100021 ps
CPU time 2.38 seconds
Started Nov 22 01:20:03 PM PST 23
Finished Nov 22 01:20:07 PM PST 23
Peak memory 202252 kb
Host smart-d179b41d-9bbf-46b4-a494-bd623f2ae1ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62669910071930551012923352123261333564177086043599812189776906835195186
013989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.626699100719305510129233521232613335641770860435998121
89776906835195186013989
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.64160278501570190306527199776494444244281014462557859675940307942228258366982
Short name T222
Test name
Test status
Simulation time 163313937 ps
CPU time 1.39 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:58 PM PST 23
Peak memory 202344 kb
Host smart-4b7fbbb0-0f4a-4438-956a-68dede91e2c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64160278501570190306527199776494444244281014462557859675940
307942228258366982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_intg_err.6416027850157019030652719977649444424428
1014462557859675940307942228258366982
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.53180419778975071364283293831653782841260203529571507450259356556664257831644
Short name T170
Test name
Test status
Simulation time 22582920 ps
CPU time 0.71 seconds
Started Nov 22 01:19:34 PM PST 23
Finished Nov 22 01:19:38 PM PST 23
Peak memory 201904 kb
Host smart-639fca31-d1e5-4b65-a403-1aaaf9a4c038
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53180419778975071364283293831653782841260203529571507450259356
556664257831644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_aliasing.5318041977897507136428329383165378284126020
3529571507450259356556664257831644
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.100051716487575780650022725079094994464326346870175960131770326848503565094189
Short name T165
Test name
Test status
Simulation time 122117838 ps
CPU time 1.3 seconds
Started Nov 22 01:19:36 PM PST 23
Finished Nov 22 01:19:43 PM PST 23
Peak memory 202272 kb
Host smart-98818f2b-a381-4d38-bcb7-9d482f462ccf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10005171648757578065002272507909499446432634687017596013177032
6848503565094189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.100051716487575780650022725079094994464326
346870175960131770326848503565094189
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.95640057402110074813327865964712316369342173334040905636566494252551596878894
Short name T200
Test name
Test status
Simulation time 23779339 ps
CPU time 0.65 seconds
Started Nov 22 01:19:39 PM PST 23
Finished Nov 22 01:19:46 PM PST 23
Peak memory 202088 kb
Host smart-52dc541f-6f60-4a4d-86ed-af4f15b77076
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95640057402110074813327865964712316369342173334040905636566494
252551596878894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_reset.9564005740211007481332786596471231636934217
3334040905636566494252551596878894
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.102349189713756331358131079442395675906747499653870346972303421228342895266906
Short name T154
Test name
Test status
Simulation time 42439904 ps
CPU time 0.9 seconds
Started Nov 22 01:19:37 PM PST 23
Finished Nov 22 01:19:45 PM PST 23
Peak memory 202052 kb
Host smart-d0627bd8-ff3b-4cb3-99f4-cd09943ebeba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102349189713756
331358131079442395675906747499653870346972303421228342895266906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_
rw_with_rand_reset.102349189713756331358131079442395675906747499653870346972303421228342895266906
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.53633432324803528356072323311113587320942053632634015162192578828894113614914
Short name T245
Test name
Test status
Simulation time 19547230 ps
CPU time 0.6 seconds
Started Nov 22 01:19:36 PM PST 23
Finished Nov 22 01:19:43 PM PST 23
Peak memory 201884 kb
Host smart-e73ae462-fd69-4ae8-801c-bc575100a117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53633432324803528356072323311113587320942053632634015162192578828894
113614914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.5363343232480352835607232331111358732094205363263401516
2192578828894113614914
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.99751429085359762324550072986149616624546979552585163912277138612780724798515
Short name T90
Test name
Test status
Simulation time 362187346 ps
CPU time 2.85 seconds
Started Nov 22 01:19:38 PM PST 23
Finished Nov 22 01:19:47 PM PST 23
Peak memory 202344 kb
Host smart-0330354a-9e59-478a-b766-fea7d0265538
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99751429085359762324550072986149616624546979552585163912
277138612780724798515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.9975142908535976232455007
2986149616624546979552585163912277138612780724798515
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.58859936774628914698744903493003146760979568234880843441778055124142550293231
Short name T159
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:49 PM PST 23
Peak memory 201952 kb
Host smart-9a630fd6-9762-4dd8-a350-883c67d22f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58859936774628914698744903493003146760979568234880
843441778055124142550293231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.58859936774628914698744
903493003146760979568234880843441778055124142550293231
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.7799886262796051734291511660442707757798024725687995963000403088678728394176
Short name T187
Test name
Test status
Simulation time 117100021 ps
CPU time 2.42 seconds
Started Nov 22 01:19:40 PM PST 23
Finished Nov 22 01:19:48 PM PST 23
Peak memory 202248 kb
Host smart-b09163f9-f1ee-4b7b-ada2-0a8b2743c999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77998862627960517342915116604427077577980247256879959630004030886787283
94176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.77998862627960517342915116604427077577980247256879959630
00403088678728394176
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.24050586511191575009595924559966590137989167047775248875306916224932277518340
Short name T251
Test name
Test status
Simulation time 163313937 ps
CPU time 1.45 seconds
Started Nov 22 01:19:37 PM PST 23
Finished Nov 22 01:19:45 PM PST 23
Peak memory 202180 kb
Host smart-6a60b4ac-448d-48d6-a65f-02af1ebb54b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24050586511191575009595924559966590137989167047775248875306
916224932277518340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_intg_err.24050586511191575009595924559966590137989
167047775248875306916224932277518340
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.72511336078264838835267305913811948868526514398123593360543743968238307266866
Short name T218
Test name
Test status
Simulation time 22582920 ps
CPU time 0.67 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:49 PM PST 23
Peak memory 202036 kb
Host smart-f6b4159e-4615-472d-9ccd-f87a856e52e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72511336078264838835267305913811948868526514398123593360543743
968238307266866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.7251133607826483883526730591381194886852651
4398123593360543743968238307266866
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.80845694221042498276157310337051289823797659341661083341507075224076969663304
Short name T98
Test name
Test status
Simulation time 122117838 ps
CPU time 1.3 seconds
Started Nov 22 01:19:43 PM PST 23
Finished Nov 22 01:19:50 PM PST 23
Peak memory 202280 kb
Host smart-6b518944-49a6-48d3-968c-4a7c7dfcf8f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80845694221042498276157310337051289823797659341661083341507075
224076969663304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_bash.8084569422104249827615731033705128982379765
9341661083341507075224076969663304
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.106182215045913259645322009484090501728935375629439490979857249152051239443137
Short name T60
Test name
Test status
Simulation time 23779339 ps
CPU time 0.65 seconds
Started Nov 22 01:19:33 PM PST 23
Finished Nov 22 01:19:38 PM PST 23
Peak memory 202020 kb
Host smart-04d70f49-06e0-48af-a2f8-74eff64643b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10618221504591325964532200948409050172893537562943949097985724
9152051239443137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_reset.106182215045913259645322009484090501728935
375629439490979857249152051239443137
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.21640118229439219877363616122331570999554874256961973391992505770295316489899
Short name T204
Test name
Test status
Simulation time 42439904 ps
CPU time 0.87 seconds
Started Nov 22 01:19:43 PM PST 23
Finished Nov 22 01:19:50 PM PST 23
Peak memory 202136 kb
Host smart-504a01e7-f5b7-4edc-9ed2-8bf19747348c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216401182294392
19877363616122331570999554874256961973391992505770295316489899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_r
w_with_rand_reset.21640118229439219877363616122331570999554874256961973391992505770295316489899
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.32713107188382023981128645458664489758232668494015094760433659875430258864137
Short name T83
Test name
Test status
Simulation time 19547230 ps
CPU time 0.61 seconds
Started Nov 22 01:20:26 PM PST 23
Finished Nov 22 01:20:32 PM PST 23
Peak memory 201596 kb
Host smart-59d4e5c2-9f3f-4b29-9fae-6cc8963edcad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32713107188382023981128645458664489758232668494015094760433659875430
258864137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.3271310718838202398112864545866448975823266849401509476
0433659875430258864137
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.23858426251058180779394930813434412184856677952699525264910230410862585625859
Short name T87
Test name
Test status
Simulation time 362187346 ps
CPU time 2.94 seconds
Started Nov 22 01:19:35 PM PST 23
Finished Nov 22 01:19:44 PM PST 23
Peak memory 202480 kb
Host smart-628e0e6f-1f54-44e2-852a-bd68a4eed49d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23858426251058180779394930813434412184856677952699525264
910230410862585625859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2385842625105818077939493
0813434412184856677952699525264910230410862585625859
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.26889952378642977356383144985300320980985792024862453531753806874008866743622
Short name T73
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:19:41 PM PST 23
Finished Nov 22 01:19:48 PM PST 23
Peak memory 202060 kb
Host smart-03276ae7-2179-4b8e-8771-48449923586a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26889952378642977356383144985300320980985792024862
453531753806874008866743622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.26889952378642977356383
144985300320980985792024862453531753806874008866743622
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.10462093361811655468994795252755977272324110622387823712884553035129469151170
Short name T241
Test name
Test status
Simulation time 117100021 ps
CPU time 2.35 seconds
Started Nov 22 01:19:32 PM PST 23
Finished Nov 22 01:19:38 PM PST 23
Peak memory 202380 kb
Host smart-565882a1-9379-4297-9201-62ed8190f8ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10462093361811655468994795252755977272324110622387823712884553035129469
151170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.1046209336181165546899479525275597727232411062238782371
2884553035129469151170
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.21732394286800125878744038453361801069101376832758347929573463090994560991866
Short name T160
Test name
Test status
Simulation time 163313937 ps
CPU time 1.39 seconds
Started Nov 22 01:20:25 PM PST 23
Finished Nov 22 01:20:31 PM PST 23
Peak memory 201708 kb
Host smart-6b9d019d-e97b-4869-8e8b-e5a83c02362f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21732394286800125878744038453361801069101376832758347929573
463090994560991866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_intg_err.21732394286800125878744038453361801069101
376832758347929573463090994560991866
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.8033925667778401842906047243551842324431270901201728570436920948721699322952
Short name T67
Test name
Test status
Simulation time 22582920 ps
CPU time 0.63 seconds
Started Nov 22 01:19:45 PM PST 23
Finished Nov 22 01:19:51 PM PST 23
Peak memory 202032 kb
Host smart-de77c10f-3478-4e34-a26a-1c216053c7ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80339256677784018429060472435518423244312709012017285704369209
48721699322952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_aliasing.80339256677784018429060472435518423244312709
01201728570436920948721699322952
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.57083606263436282980166676028534201387376253986714166928351978894845757276708
Short name T183
Test name
Test status
Simulation time 122117838 ps
CPU time 1.25 seconds
Started Nov 22 01:19:46 PM PST 23
Finished Nov 22 01:19:52 PM PST 23
Peak memory 202276 kb
Host smart-41a19c0a-1c3e-4910-b42f-491d4aa4f5f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57083606263436282980166676028534201387376253986714166928351978
894845757276708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_bash.5708360626343628298016667602853420138737625
3986714166928351978894845757276708
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.23628624064854758990016792227812837816431860152939784685050966417037407052026
Short name T249
Test name
Test status
Simulation time 23779339 ps
CPU time 0.63 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:48 PM PST 23
Peak memory 202076 kb
Host smart-84fa8a12-af14-42f0-95f5-a307ce8cd6e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23628624064854758990016792227812837816431860152939784685050966
417037407052026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_reset.2362862406485475899001679222781283781643186
0152939784685050966417037407052026
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.93474778451182895297773937242661576864511363687139393191408742508636100894350
Short name T72
Test name
Test status
Simulation time 42439904 ps
CPU time 0.9 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 201972 kb
Host smart-b60d4d3d-90db-4f74-ba7b-f69c11d60ac5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934747784511828
95297773937242661576864511363687139393191408742508636100894350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_r
w_with_rand_reset.93474778451182895297773937242661576864511363687139393191408742508636100894350
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.626104292125315831209195327102928935112207535075574790823985474304025829028
Short name T166
Test name
Test status
Simulation time 19547230 ps
CPU time 0.61 seconds
Started Nov 22 01:19:39 PM PST 23
Finished Nov 22 01:19:46 PM PST 23
Peak memory 201988 kb
Host smart-464154d3-a427-44a0-8e5b-88495968ab7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62610429212531583120919532710292893511220753507557479082398547430402
5829028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.626104292125315831209195327102928935112207535075574790823
985474304025829028
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.58969973353480329515814286958066324674812560451051286682482706429255090289086
Short name T237
Test name
Test status
Simulation time 362187346 ps
CPU time 2.98 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 202444 kb
Host smart-e665a3fb-4ed0-4ef1-8a80-bff56da1fb5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58969973353480329515814286958066324674812560451051286682
482706429255090289086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.5896997335348032951581428
6958066324674812560451051286682482706429255090289086
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.111210369144860121794658045227355623083039400868727287079697250494112976732892
Short name T203
Test name
Test status
Simulation time 23886481 ps
CPU time 0.69 seconds
Started Nov 22 01:19:36 PM PST 23
Finished Nov 22 01:19:43 PM PST 23
Peak memory 202068 kb
Host smart-d361ab20-12b8-4656-9abd-8e5b5754a5d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11121036914486012179465804522735562308303940086872
7287079697250494112976732892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1112103691448601217946
58045227355623083039400868727287079697250494112976732892
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.47302549845687521596771126527653938110672295168872168612144572873769122199420
Short name T198
Test name
Test status
Simulation time 117100021 ps
CPU time 2.37 seconds
Started Nov 22 01:19:46 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 202328 kb
Host smart-f412e226-8862-4c87-8196-1e8ffa7cfa93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47302549845687521596771126527653938110672295168872168612144572873769122
199420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.4730254984568752159677112652765393811067229516887216861
2144572873769122199420
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.57313488391632244647572808924139893156423026155190141354656729664165713032870
Short name T169
Test name
Test status
Simulation time 163313937 ps
CPU time 1.48 seconds
Started Nov 22 01:19:42 PM PST 23
Finished Nov 22 01:19:50 PM PST 23
Peak memory 202276 kb
Host smart-29944dd1-aa4a-49c9-abd1-a230660ccf2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57313488391632244647572808924139893156423026155190141354656
729664165713032870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_intg_err.57313488391632244647572808924139893156423
026155190141354656729664165713032870
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.31916764269661440356930809867431894549953244732369838650090498708899093002276
Short name T197
Test name
Test status
Simulation time 42439904 ps
CPU time 0.89 seconds
Started Nov 22 01:20:16 PM PST 23
Finished Nov 22 01:20:19 PM PST 23
Peak memory 202192 kb
Host smart-718ebe53-b26d-4fa4-8794-f45f0b5ee88e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319167642696614
40356930809867431894549953244732369838650090498708899093002276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_r
w_with_rand_reset.31916764269661440356930809867431894549953244732369838650090498708899093002276
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.68608819790509165515271702181415115516236423302636973523250428793907017275614
Short name T177
Test name
Test status
Simulation time 19547230 ps
CPU time 0.66 seconds
Started Nov 22 01:20:07 PM PST 23
Finished Nov 22 01:20:09 PM PST 23
Peak memory 202060 kb
Host smart-94468850-b486-4d9b-a7bd-4ba940a868d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68608819790509165515271702181415115516236423302636973523250428793907
017275614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.6860881979050916551527170218141511551623642330263697352
3250428793907017275614
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.69942723639798080629715708021615230350159237451298812709067389995574076926023
Short name T242
Test name
Test status
Simulation time 362187346 ps
CPU time 2.88 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 202424 kb
Host smart-b1a1a6b9-b1d8-47f2-b087-d4935ca11001
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69942723639798080629715708021615230350159237451298812709
067389995574076926023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.6994272363979808062971570
8021615230350159237451298812709067389995574076926023
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.18716060142495409737566430933026701520618836480064421868332228477369656965940
Short name T61
Test name
Test status
Simulation time 23886481 ps
CPU time 0.67 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 202028 kb
Host smart-500cb88d-50c4-4514-bb63-43a53d40abdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18716060142495409737566430933026701520618836480064
421868332228477369656965940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.18716060142495409737566
430933026701520618836480064421868332228477369656965940
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.63855570339184262154659509973109289362154607956795081038163077828500545018481
Short name T209
Test name
Test status
Simulation time 117100021 ps
CPU time 2.39 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:56 PM PST 23
Peak memory 202312 kb
Host smart-6f5e3f16-4924-4085-b4b1-7e44cb97607c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63855570339184262154659509973109289362154607956795081038163077828500545
018481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.6385557033918426215465950997310928936215460795679508103
8163077828500545018481
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.106957958567402580378057557253322338171521885144715149095019738158883280806093
Short name T47
Test name
Test status
Simulation time 163313937 ps
CPU time 1.48 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:07 PM PST 23
Peak memory 202160 kb
Host smart-0ca73ffe-4492-471f-9584-b05033d944aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10695795856740258037805755725332233817152188514471514909501
9738158883280806093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_intg_err.1069579585674025803780575572533223381715
21885144715149095019738158883280806093
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.83413491760130699562782313817689138558399676828566439614408417985041186345874
Short name T51
Test name
Test status
Simulation time 42439904 ps
CPU time 0.88 seconds
Started Nov 22 01:20:15 PM PST 23
Finished Nov 22 01:20:17 PM PST 23
Peak memory 202160 kb
Host smart-12ea26fd-2a9b-414e-8e54-ed76739d9030
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834134917601306
99562782313817689138558399676828566439614408417985041186345874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_r
w_with_rand_reset.83413491760130699562782313817689138558399676828566439614408417985041186345874
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.68183484612849079572279673268941195921520271529618783676271859369065941062298
Short name T225
Test name
Test status
Simulation time 19547230 ps
CPU time 0.62 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 201992 kb
Host smart-4a2e5447-1b87-4d67-8113-386377aaadb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68183484612849079572279673268941195921520271529618783676271859369065
941062298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.6818348461284907957227967326894119592152027152961878367
6271859369065941062298
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.48524306730817817944516454866364573553210036923141126819382376293211297360530
Short name T82
Test name
Test status
Simulation time 362187346 ps
CPU time 2.87 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:20:01 PM PST 23
Peak memory 201424 kb
Host smart-adc2e380-9a1a-4bb6-9b03-8cc0e6a5d719
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48524306730817817944516454866364573553210036923141126819
382376293211297360530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.4852430673081781794451645
4866364573553210036923141126819382376293211297360530
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.28675151604462895937258019502856669953315675621985994696356394948549822384390
Short name T186
Test name
Test status
Simulation time 23886481 ps
CPU time 0.65 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 202036 kb
Host smart-c64ffb3f-04c6-4caf-a6e5-1ae8e6171174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28675151604462895937258019502856669953315675621985
994696356394948549822384390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.28675151604462895937258
019502856669953315675621985994696356394948549822384390
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.47505195566816822580491020547172797199721610283604245364732007200592733386450
Short name T233
Test name
Test status
Simulation time 117100021 ps
CPU time 2.35 seconds
Started Nov 22 01:19:52 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 202396 kb
Host smart-fd573da0-2749-46be-8235-b39c316c2ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47505195566816822580491020547172797199721610283604245364732007200592733
386450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.4750519556681682258049102054717279719972161028360424536
4732007200592733386450
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.24370843579216515922702902163989431918213337622858669242229970258834085770601
Short name T238
Test name
Test status
Simulation time 163313937 ps
CPU time 1.45 seconds
Started Nov 22 01:20:04 PM PST 23
Finished Nov 22 01:20:06 PM PST 23
Peak memory 202168 kb
Host smart-d799c83d-6de7-42e5-b80b-2068c45dd517
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24370843579216515922702902163989431918213337622858669242229
970258834085770601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_intg_err.24370843579216515922702902163989431918213
337622858669242229970258834085770601
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.14703981804557102239583425229499104529573789725395596918334097324356243948692
Short name T180
Test name
Test status
Simulation time 42439904 ps
CPU time 0.85 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 201224 kb
Host smart-b31f3229-8f87-4573-af47-b5f9e2788d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147039818045571
02239583425229499104529573789725395596918334097324356243948692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_r
w_with_rand_reset.14703981804557102239583425229499104529573789725395596918334097324356243948692
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.29220996456221265758839240398726218984108044088738677804971015539964230107438
Short name T84
Test name
Test status
Simulation time 19547230 ps
CPU time 0.61 seconds
Started Nov 22 01:19:54 PM PST 23
Finished Nov 22 01:19:59 PM PST 23
Peak memory 202028 kb
Host smart-be84c051-5b9f-4166-a42e-3955c12adca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29220996456221265758839240398726218984108044088738677804971015539964
230107438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.2922099645622126575883924039872621898410804408873867780
4971015539964230107438
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1696246166583056704524131801291413612178399226332775800005543207710844718136
Short name T85
Test name
Test status
Simulation time 362187346 ps
CPU time 2.92 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:57 PM PST 23
Peak memory 202384 kb
Host smart-3276d52f-4f63-4053-93fe-67d072fd3268
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16962461665830567045241318012914136121783992263327758000
05543207710844718136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.16962461665830567045241318
01291413612178399226332775800005543207710844718136
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.17648985734186358509472668800300882605273184405523035884879801081764024376778
Short name T175
Test name
Test status
Simulation time 23886481 ps
CPU time 0.63 seconds
Started Nov 22 01:19:49 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 202000 kb
Host smart-00567375-8f6e-4660-b896-1e4ccc93b333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17648985734186358509472668800300882605273184405523
035884879801081764024376778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.17648985734186358509472
668800300882605273184405523035884879801081764024376778
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2839806213832825161358966831483789252032173554728401016141796045669979231167
Short name T50
Test name
Test status
Simulation time 117100021 ps
CPU time 2.37 seconds
Started Nov 22 01:19:51 PM PST 23
Finished Nov 22 01:19:57 PM PST 23
Peak memory 202280 kb
Host smart-4396efe0-7166-40a3-b550-e6ffd5c77b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28398062138328251613589668314837892520321735547284010161417960456699792
31167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.28398062138328251613589668314837892520321735547284010161
41796045669979231167
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.114374424884706676693231115448081590557432780757282686099599854400923633807698
Short name T161
Test name
Test status
Simulation time 163313937 ps
CPU time 1.44 seconds
Started Nov 22 01:19:53 PM PST 23
Finished Nov 22 01:20:00 PM PST 23
Peak memory 202256 kb
Host smart-06e7de0c-993b-49f9-a97c-08cc587bb1d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437442488470667669323111544808159055743278075728268609959
9854400923633807698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_intg_err.1143744248847066766932311154480815905574
32780757282686099599854400923633807698
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.17048960809256976100334684237507470711898493728764594884669815066503580024518
Short name T185
Test name
Test status
Simulation time 42439904 ps
CPU time 0.84 seconds
Started Nov 22 01:20:33 PM PST 23
Finished Nov 22 01:20:39 PM PST 23
Peak memory 201592 kb
Host smart-e5c87c9f-8f57-4b92-83dc-1ab115125001
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170489608092569
76100334684237507470711898493728764594884669815066503580024518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_r
w_with_rand_reset.17048960809256976100334684237507470711898493728764594884669815066503580024518
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.9079604700174297859347022185518914214272644802222401413400694952754153652101
Short name T171
Test name
Test status
Simulation time 19547230 ps
CPU time 0.63 seconds
Started Nov 22 01:19:50 PM PST 23
Finished Nov 22 01:19:54 PM PST 23
Peak memory 202088 kb
Host smart-4dc6e10e-8b1d-4635-b8c5-626c30fc23ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90796047001742978593470221855189142142726448022224014134006949527541
53652101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.90796047001742978593470221855189142142726448022224014134
00694952754153652101
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.97515405803305319841668511738335796956704522241451346420001341830053168766184
Short name T217
Test name
Test status
Simulation time 362187346 ps
CPU time 2.84 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:56 PM PST 23
Peak memory 202356 kb
Host smart-392a5f00-e50f-4391-a4bf-28e520291429
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97515405803305319841668511738335796956704522241451346420
001341830053168766184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.9751540580330531984166851
1738335796956704522241451346420001341830053168766184
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.9358300372537806581393293375813618115561137567384768453991164881981374036858
Short name T178
Test name
Test status
Simulation time 23886481 ps
CPU time 0.66 seconds
Started Nov 22 01:19:38 PM PST 23
Finished Nov 22 01:19:45 PM PST 23
Peak memory 202040 kb
Host smart-e8f7a30c-f55a-4b8f-a76d-912c345c0015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93583003725378065813932933758136181155611375673847
68453991164881981374036858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.935830037253780658139329
3375813618115561137567384768453991164881981374036858
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.13575901262756486693475263335955232307713430700163133913953506075160308509105
Short name T156
Test name
Test status
Simulation time 117100021 ps
CPU time 2.43 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:41 PM PST 23
Peak memory 201844 kb
Host smart-c54dd9d4-329d-4e30-a18d-43f4eed708bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13575901262756486693475263335955232307713430700163133913953506075160308
509105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.1357590126275648669347526333595523230771343070016313391
3953506075160308509105
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.67264480903026655255466949596630840545447085453312986157208223342994958119851
Short name T158
Test name
Test status
Simulation time 163313937 ps
CPU time 1.44 seconds
Started Nov 22 01:20:34 PM PST 23
Finished Nov 22 01:20:40 PM PST 23
Peak memory 201788 kb
Host smart-a39ae523-f605-4240-9578-6fb437532f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67264480903026655255466949596630840545447085453312986157208
223342994958119851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_intg_err.67264480903026655255466949596630840545447
085453312986157208223342994958119851
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.105327857447680993510959674168553836142711518776224635272306954909959884598002
Short name T210
Test name
Test status
Simulation time 42439904 ps
CPU time 0.88 seconds
Started Nov 22 01:19:36 PM PST 23
Finished Nov 22 01:19:42 PM PST 23
Peak memory 202012 kb
Host smart-41670246-cf49-4c9b-b06b-3680af751fca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105327857447680
993510959674168553836142711518776224635272306954909959884598002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_
rw_with_rand_reset.105327857447680993510959674168553836142711518776224635272306954909959884598002
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.72502567380272654881013522069965146751478717453616474846321090254846015083960
Short name T59
Test name
Test status
Simulation time 19547230 ps
CPU time 0.6 seconds
Started Nov 22 01:19:47 PM PST 23
Finished Nov 22 01:19:53 PM PST 23
Peak memory 201868 kb
Host smart-88607e20-c1df-4db1-b5a7-f5b363e9af4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72502567380272654881013522069965146751478717453616474846321090254846
015083960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.7250256738027265488101352206996514675147871745361647484
6321090254846015083960
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.612558875123317269398136336060669028747683589780663873965967708302732884735
Short name T224
Test name
Test status
Simulation time 362187346 ps
CPU time 2.89 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:56 PM PST 23
Peak memory 202284 kb
Host smart-5435737a-953c-4acd-a3e6-cd086709fc35
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61255887512331726939813633606066902874768358978066387396
5967708302732884735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.612558875123317269398136336
060669028747683589780663873965967708302732884735
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.76641068878155866624610009332486907675865094359053871416737178231338383138552
Short name T220
Test name
Test status
Simulation time 23886481 ps
CPU time 0.7 seconds
Started Nov 22 01:20:25 PM PST 23
Finished Nov 22 01:20:30 PM PST 23
Peak memory 200780 kb
Host smart-903ae4eb-9484-45ef-8ecd-08815f96c6f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76641068878155866624610009332486907675865094359053
871416737178231338383138552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.76641068878155866624610
009332486907675865094359053871416737178231338383138552
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.92873400841861889455525243785530824656581686666167109728287423579071578384636
Short name T243
Test name
Test status
Simulation time 117100021 ps
CPU time 2.34 seconds
Started Nov 22 01:19:48 PM PST 23
Finished Nov 22 01:19:55 PM PST 23
Peak memory 202180 kb
Host smart-5e5797c1-e1c0-4a3c-b788-87eff9275f79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92873400841861889455525243785530824656581686666167109728287423579071578
384636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.9287340084186188945552524378553082465658168666616710972
8287423579071578384636
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.6564553950016888280673923475027132074337206502856219140905683145381489323901
Short name T102
Test name
Test status
Simulation time 163313937 ps
CPU time 1.49 seconds
Started Nov 22 01:19:51 PM PST 23
Finished Nov 22 01:19:57 PM PST 23
Peak memory 202196 kb
Host smart-ae372908-8aa1-45c3-b516-e30d2dbd6022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65645539500168882806739234750271320743372065028562191409056
83145381489323901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_intg_err.656455395001688828067392347502713207433720
6502856219140905683145381489323901
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1841652938538626042803360387768412780273897722076785689335828703877000008321
Short name T705
Test name
Test status
Simulation time 4471404472 ps
CPU time 615 seconds
Started Nov 22 01:20:48 PM PST 23
Finished Nov 22 01:31:07 PM PST 23
Peak memory 375380 kb
Host smart-05a5f721-4eaa-45b0-b6c1-e70845314a2e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841652938538626042803360387768412780273897722076785689335828703877000008321
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_key_req.18416529385386260428033603877684127802738
97722076785689335828703877000008321
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.24075098194029623788211001002485949201512845765496266033602947147462055852768
Short name T1009
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:21:29 PM PST 23
Finished Nov 22 01:21:37 PM PST 23
Peak memory 202064 kb
Host smart-45201607-a7e5-418b-a118-e7f8d665603a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240750981940296237882110010024859492015128457654962660336029471474
62055852768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.2407509819402962378821100100248594920151284576549626603
3602947147462055852768
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.11293505109248720737582106340439300472468898320071051153237861322937071652159
Short name T603
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.47 seconds
Started Nov 22 01:21:20 PM PST 23
Finished Nov 22 01:22:47 PM PST 23
Peak memory 202532 kb
Host smart-71b97c68-1857-45cc-a868-153b29ab97e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11293505109248720737582106340439300472468898320071051153237861322937071652159 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.11293505109248720737582106340439300472468898320071051153237861322937071652159
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.2465952893156957538020488903831061171606324251150705904211714091143130941933
Short name T620
Test name
Test status
Simulation time 23162112088 ps
CPU time 667.83 seconds
Started Nov 22 01:21:01 PM PST 23
Finished Nov 22 01:32:13 PM PST 23
Peak memory 364440 kb
Host smart-082fde07-9e95-44a6-9539-9eaf930c34eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465952893156957538020488903831061171606324251150705904211714091143130941933 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.2465952893156957538020488903831061171606324251150705904211714091143130941933
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.25392333695349327588501154078251371154535908483965248084387793395332942629203
Short name T778
Test name
Test status
Simulation time 985753786 ps
CPU time 7.15 seconds
Started Nov 22 01:20:57 PM PST 23
Finished Nov 22 01:21:10 PM PST 23
Peak memory 212984 kb
Host smart-e5a06246-aaf2-4808-963b-a0a39214cafe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25392333695349327588501154078251371154535908483965248084387793395332942629203 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.25392333695349327588501154078251371154535908483965248084387793395332942629203
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.33957541668400020569517363942578767592289877519388977039243942950027388773836
Short name T986
Test name
Test status
Simulation time 209242141 ps
CPU time 72.5 seconds
Started Nov 22 01:20:43 PM PST 23
Finished Nov 22 01:21:58 PM PST 23
Peak memory 351172 kb
Host smart-ed6348ee-5343-4541-9776-e15b6e2261e2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395754166840002056951736394257876759228987751938897703
9243942950027388773836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max_throughput.339575416684000205695173639425787675
92289877519388977039243942950027388773836
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.83061103824926915966961457663259795137968081326522290766550154086773983334497
Short name T80
Test name
Test status
Simulation time 166171057 ps
CPU time 3.06 seconds
Started Nov 22 01:20:51 PM PST 23
Finished Nov 22 01:20:59 PM PST 23
Peak memory 215672 kb
Host smart-f153ae56-7d8f-471f-af30-b6c9943d5fce
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83061103824926915966961457663259795137968081326522290766550154086773
983334497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.8306110382492691596696145766325979513796808132652
2290766550154086773983334497
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.21229173386004056760287564690110312428490189432505177886667654133585569260096
Short name T68
Test name
Test status
Simulation time 590810517 ps
CPU time 5.22 seconds
Started Nov 22 01:20:52 PM PST 23
Finished Nov 22 01:21:02 PM PST 23
Peak memory 202572 kb
Host smart-6ab55f02-1ef7-40d7-bedf-fe5df3514249
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21229173386004056760287564690110312428490189432505177886667654133585569260096
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.21229173386004056760287564690110312428490189432505177886667654133585569260096
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.56375683127001933306015994105872124222253410930596234098489466744116128531729
Short name T377
Test name
Test status
Simulation time 21947461091 ps
CPU time 826.56 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:35:24 PM PST 23
Peak memory 371384 kb
Host smart-d5fba49f-4245-46b7-b8c6-f0dcdfb93374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56375683127001933306015994105872124222253410930596234098489466744116128531729 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.56375683127001933306015994105872124222253410930596234098489466744116128531729
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.90648988034187229100865771627781314291149326127396628153838853330478484169605
Short name T260
Test name
Test status
Simulation time 445204539 ps
CPU time 12.39 seconds
Started Nov 22 01:21:26 PM PST 23
Finished Nov 22 01:21:49 PM PST 23
Peak memory 246540 kb
Host smart-76815e98-1cbc-4ee4-a03f-19c81ddd137e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906489880341872291008657716277813142911493261273966281538388533304784
84169605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.9064898803418722910086577162778131429114932612739662815
3838853330478484169605
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.64001526337935721462561958768208278722373215825362015279288846433018213296601
Short name T92
Test name
Test status
Simulation time 42305619653 ps
CPU time 541.3 seconds
Started Nov 22 01:21:25 PM PST 23
Finished Nov 22 01:30:36 PM PST 23
Peak memory 202684 kb
Host smart-5b10fe59-f6e6-4319-83aa-757f4dbcd4b3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640015263379357214625619587682082787223732158253620152792888464330182
13296601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access_b2b.64001526337935721462561958768208278722373
215825362015279288846433018213296601
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.1477827698200789526909523852237566627122907642215976744960545875469382650862
Short name T892
Test name
Test status
Simulation time 40672061 ps
CPU time 0.83 seconds
Started Nov 22 01:20:53 PM PST 23
Finished Nov 22 01:21:00 PM PST 23
Peak memory 202600 kb
Host smart-74eab9fe-c82f-4ce8-98c8-fb18fbc7ae8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477827698200789526909523852237566627122907642215976744960545875469382650862 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1477827698200789526909523852237566627122907642215976744960545875469382650862
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.4475447817154333348361899754315957863567778444503658288829567654041364900639
Short name T269
Test name
Test status
Simulation time 19383553031 ps
CPU time 527.91 seconds
Started Nov 22 01:21:26 PM PST 23
Finished Nov 22 01:30:23 PM PST 23
Peak memory 371768 kb
Host smart-e120285a-cc2c-43e9-9a3a-bea23b61121b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4475447817154333348361899754315957863567778444503658288829567654041364900639 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.4475447817154333348361899754315957863567778444503658288829567654041364900639
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.16566756496039585742432328253740532533122801855974305908554147087810027484430
Short name T448
Test name
Test status
Simulation time 427865392 ps
CPU time 11.75 seconds
Started Nov 22 01:21:25 PM PST 23
Finished Nov 22 01:21:46 PM PST 23
Peak memory 246560 kb
Host smart-64353755-65f4-40a8-b968-ce4158175e68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16566756496039585742432328253740532533122801855974305908554147087810027484430 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.16566756496039585742432328253740532533122801855974305908554147087810027484430
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.42570385845434014528322010843689705894502004247752466480837443023324630326267
Short name T841
Test name
Test status
Simulation time 121463254244 ps
CPU time 3154.26 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 02:14:12 PM PST 23
Peak memory 375148 kb
Host smart-ba1fb799-c830-48de-8d01-cd18574c448b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425703858454340145283220108436897058945020042477524664808374430
23324630326267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.425703858454340145283220108436897058945020042477
52466480837443023324630326267
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.48846053286086386630487035575201343753613865770533446172867095561887621951181
Short name T571
Test name
Test status
Simulation time 624328106 ps
CPU time 1154.4 seconds
Started Nov 22 01:20:50 PM PST 23
Finished Nov 22 01:40:08 PM PST 23
Peak memory 401840 kb
Host smart-f3f82da5-2953-435f-bc3b-e8f74f8fb27d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=48846053286086386630487035575201343753613865770533446172867095561887621951181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sra
m_ctrl_stress_all_with_rand_reset.48846053286086386630487035575201343753613865770533446172867095561887621951181
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.81832978110922828766861885344702076803132209652862901812568038265497178350428
Short name T823
Test name
Test status
Simulation time 6491370455 ps
CPU time 359.53 seconds
Started Nov 22 01:21:25 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 202604 kb
Host smart-1124d7c0-b21c-48bc-b729-97b99ffaf29e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81832978110922828766861885344702076803132209652862901812568038265497178350428
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.8183297811092282876686188534470207680313220965286290
1812568038265497178350428
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.55377621655837192092038021956546150825788861748313678562550196139649939864261
Short name T126
Test name
Test status
Simulation time 237420487 ps
CPU time 81.39 seconds
Started Nov 22 01:20:47 PM PST 23
Finished Nov 22 01:22:11 PM PST 23
Peak memory 351232 kb
Host smart-1b97658e-0eaa-4559-b1ee-a42dd844b879
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553776216558371920920380219565461508257888617483136785
62550196139649939864261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.55377621655837192092038
021956546150825788861748313678562550196139649939864261
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.84352338884672114961306165606696335247673590330400477491337908204805247852587
Short name T471
Test name
Test status
Simulation time 4471404472 ps
CPU time 776.3 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:34:47 PM PST 23
Peak memory 375512 kb
Host smart-36e68106-73df-41b5-a52c-6e9c8d6804b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84352338884672114961306165606696335247673590330400477491337908204805247852587
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_key_req.8435233888467211496130616560669633524767
3590330400477491337908204805247852587
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.82044129991705919558432374258767450864615196462794922340729626481493399133175
Short name T299
Test name
Test status
Simulation time 9249473390 ps
CPU time 85.32 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:23:28 PM PST 23
Peak memory 202640 kb
Host smart-e7fbf941-fd7b-422d-88d8-2242483fa6c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82044129991705919558432374258767450864615196462794922340729626481493399133175 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.82044129991705919558432374258767450864615196462794922340729626481493399133175
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.278336284309972885597980142078713666268028551645506373814622718845143085165
Short name T350
Test name
Test status
Simulation time 23162112088 ps
CPU time 638.82 seconds
Started Nov 22 01:21:20 PM PST 23
Finished Nov 22 01:32:03 PM PST 23
Peak memory 364652 kb
Host smart-163d7669-1f89-44f9-9c36-611cd506eca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278336284309972885597980142078713666268028551645506373814622718845143085165 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.278336284309972885597980142078713666268028551645506373814622718845143085165
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.95779764928548695347269301491459743081850219460620698378895054308151097522924
Short name T408
Test name
Test status
Simulation time 209242141 ps
CPU time 90.1 seconds
Started Nov 22 01:21:06 PM PST 23
Finished Nov 22 01:22:38 PM PST 23
Peak memory 351332 kb
Host smart-d291d373-390a-429f-b774-f8448f91f09a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9577976492854869534726930149145974308185021946062069837
8895054308151097522924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max_throughput.957797649285486953472693014914597430
81850219460620698378895054308151097522924
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.26494615968880891574161962757657705407107643788837703559055052544997739803483
Short name T703
Test name
Test status
Simulation time 166171057 ps
CPU time 3.09 seconds
Started Nov 22 01:21:13 PM PST 23
Finished Nov 22 01:21:18 PM PST 23
Peak memory 215716 kb
Host smart-59f68d5c-904b-4866-8258-baa2a96e1aa3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494615968880891574161962757657705407107643788837703559055052544997
739803483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.2649461596888089157416196275765770540710764378883
7703559055052544997739803483
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.40786041682036373801791997422915705208095415993338762022056590520513625723125
Short name T316
Test name
Test status
Simulation time 590810517 ps
CPU time 5.44 seconds
Started Nov 22 01:21:02 PM PST 23
Finished Nov 22 01:21:12 PM PST 23
Peak memory 202596 kb
Host smart-ac1ce5d1-bf37-40a4-ad97-20078458f855
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40786041682036373801791997422915705208095415993338762022056590520513625723125
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.40786041682036373801791997422915705208095415993338762022056590520513625723125
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.112362349929923883263202478061372884857655688014381090851465920144363270322518
Short name T119
Test name
Test status
Simulation time 21947461091 ps
CPU time 579.89 seconds
Started Nov 22 01:20:49 PM PST 23
Finished Nov 22 01:30:33 PM PST 23
Peak memory 371460 kb
Host smart-dcfc3672-bd95-45c9-9885-d6f9b46bba0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112362349929923883263202478061372884857655688014381090851465920144363270322518 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.112362349929923883263202478061372884857655688014381090851465920144363270322518
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.30880946945318422708268369211646607514241870973750913185084869898883784542035
Short name T761
Test name
Test status
Simulation time 445204539 ps
CPU time 10.81 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:22:06 PM PST 23
Peak memory 246168 kb
Host smart-bd03481c-7861-4530-9192-18e4f5b21418
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308809469453184227082683692116466075142418709737509131850848698988837
84542035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.3088094694531842270826836921164660751424187097375091318
5084869898883784542035
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.27475230922498097585526843940949529726268814734092022017439696784080063721569
Short name T738
Test name
Test status
Simulation time 42305619653 ps
CPU time 541.43 seconds
Started Nov 22 01:21:03 PM PST 23
Finished Nov 22 01:30:08 PM PST 23
Peak memory 202692 kb
Host smart-c41badc3-804b-4126-a3f9-ad7e38bc1e28
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274752309224980975855268439409495297262688147340920220174396967840800
63721569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access_b2b.27475230922498097585526843940949529726268
814734092022017439696784080063721569
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.32059088676509345032985690368491256035417463996244658535726853839659909817419
Short name T38
Test name
Test status
Simulation time 40672061 ps
CPU time 0.79 seconds
Started Nov 22 01:22:45 PM PST 23
Finished Nov 22 01:22:59 PM PST 23
Peak memory 202124 kb
Host smart-d1d487d5-8a31-4ae0-9a55-99b1e816f038
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32059088676509345032985690368491256035417463996244658535726853839659909817419 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.32059088676509345032985690368491256035417463996244658535726853839659909817419
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.86192131635851343923358514393058795744492742351365429744480422948177636077370
Short name T26
Test name
Test status
Simulation time 216402798 ps
CPU time 2 seconds
Started Nov 22 01:21:09 PM PST 23
Finished Nov 22 01:21:13 PM PST 23
Peak memory 220892 kb
Host smart-af21b451-dda7-456b-8cbb-559bfe257fc5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8619213163585134392335851439305879574449274235136542974448042294817
7636077370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.861921316358513439233585143930587957444927423513654297444804
22948177636077370
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.8045312985717938567681586340681018668201213591189830798897681127477921078267
Short name T743
Test name
Test status
Simulation time 427865392 ps
CPU time 12.73 seconds
Started Nov 22 01:21:08 PM PST 23
Finished Nov 22 01:21:22 PM PST 23
Peak memory 246596 kb
Host smart-00076d69-0cc1-4117-be12-e5066004600f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8045312985717938567681586340681018668201213591189830798897681127477921078267 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.8045312985717938567681586340681018668201213591189830798897681127477921078267
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.110204961738435288483722509038603680767240436000489913203029791414017645820081
Short name T348
Test name
Test status
Simulation time 121463254244 ps
CPU time 2802.43 seconds
Started Nov 22 01:20:59 PM PST 23
Finished Nov 22 02:07:47 PM PST 23
Peak memory 375480 kb
Host smart-63c6f80e-851f-4587-8ae8-756340e8d03c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110204961738435288483722509038603680767240436000489913203029791
414017645820081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.11020496173843528848372250903860368076724043600
0489913203029791414017645820081
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.114475108214266024144170532478041371290125723232701870271739532005347351838319
Short name T843
Test name
Test status
Simulation time 624328106 ps
CPU time 913.87 seconds
Started Nov 22 01:22:46 PM PST 23
Finished Nov 22 01:38:13 PM PST 23
Peak memory 401408 kb
Host smart-4131e2c2-6ae5-4620-87c0-307cd444f8be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=114475108214266024144170532478041371290125723232701870271739532005347351838319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sr
am_ctrl_stress_all_with_rand_reset.114475108214266024144170532478041371290125723232701870271739532005347351838319
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.28999100618211065672659462377050796759790961734027462464267924379331627609235
Short name T716
Test name
Test status
Simulation time 6491370455 ps
CPU time 360.72 seconds
Started Nov 22 01:21:28 PM PST 23
Finished Nov 22 01:27:38 PM PST 23
Peak memory 202660 kb
Host smart-4066e9c6-c70a-4620-acd4-427c2b63c2d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28999100618211065672659462377050796759790961734027462464267924379331627609235
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.2899910061821106567265946237705079675979096173402746
2464267924379331627609235
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.110863275581622348683284640787404624776860561587855294979679807986608753964197
Short name T540
Test name
Test status
Simulation time 237420487 ps
CPU time 102.82 seconds
Started Nov 22 01:21:20 PM PST 23
Finished Nov 22 01:23:07 PM PST 23
Peak memory 351352 kb
Host smart-60733da7-6e9e-4b48-9c5a-369ed46bcb78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110863275581622348683284640787404624776860561587855294
979679807986608753964197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1108632755816223486832
84640787404624776860561587855294979679807986608753964197
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.69442594607772778090447509053815426944943885116556748978984080764977418825344
Short name T508
Test name
Test status
Simulation time 4471404472 ps
CPU time 872.94 seconds
Started Nov 22 01:22:11 PM PST 23
Finished Nov 22 01:36:47 PM PST 23
Peak memory 375520 kb
Host smart-87570d7c-f24a-4f83-9d25-03d09674c31e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69442594607772778090447509053815426944943885116556748978984080764977418825344
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during_key_req.694425946077727780904475090538154269449
43885116556748978984080764977418825344
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.58450543397002673872023920012556687025057109939288449978408876851833923719954
Short name T420
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 01:21:21 PM PST 23
Finished Nov 22 01:21:26 PM PST 23
Peak memory 202172 kb
Host smart-4a4f13d2-55b3-431b-b214-c3e767188b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584505433970026738720239200125566870250571099392884499784088768518
33923719954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.584505433970026738720239200125566870250571099392884499
78408876851833923719954
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.115411313124365479517346108826013996866640495613298900445950805610760908543624
Short name T457
Test name
Test status
Simulation time 9249473390 ps
CPU time 86.68 seconds
Started Nov 22 01:21:21 PM PST 23
Finished Nov 22 01:22:52 PM PST 23
Peak memory 202488 kb
Host smart-6375a215-a32d-4f1b-91a6-570d7ecc7532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115411313124365479517346108826013996866640495613298900445950805610760908543624 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.115411313124365479517346108826013996866640495613298900445950805610760908543624
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.43981064454737590352666334944910001086258496992053971820155644136165661450197
Short name T443
Test name
Test status
Simulation time 23162112088 ps
CPU time 740.47 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:34:50 PM PST 23
Peak memory 364668 kb
Host smart-462490d9-ecdb-4d1a-b56c-efbe903a06a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43981064454737590352666334944910001086258496992053971820155644136165661450197 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.43981064454737590352666334944910001086258496992053971820155644136165661450197
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.90872380840858391219159665013181286968861086935184236665862193144457048404973
Short name T441
Test name
Test status
Simulation time 985753786 ps
CPU time 7.02 seconds
Started Nov 22 01:21:14 PM PST 23
Finished Nov 22 01:21:22 PM PST 23
Peak memory 213192 kb
Host smart-0f587d99-8fc1-4537-841b-4d8019f7a197
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90872380840858391219159665013181286968861086935184236665862193144457048404973 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.90872380840858391219159665013181286968861086935184236665862193144457048404973
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.79996356163147849731568771648368798597298276646234365274191169577618728107912
Short name T617
Test name
Test status
Simulation time 209242141 ps
CPU time 73.35 seconds
Started Nov 22 01:22:02 PM PST 23
Finished Nov 22 01:23:21 PM PST 23
Peak memory 351156 kb
Host smart-f03a3cbe-7348-4a8f-802b-5622b60cf7c8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7999635616314784973156877164836879859729827664623436527
4191169577618728107912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_max_throughput.79996356163147849731568771648368798
597298276646234365274191169577618728107912
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.28086931277205972209792860367983170074763157194299703945729890989858029521950
Short name T153
Test name
Test status
Simulation time 166171057 ps
CPU time 3.05 seconds
Started Nov 22 01:21:16 PM PST 23
Finished Nov 22 01:21:21 PM PST 23
Peak memory 215740 kb
Host smart-a4cb4048-50ca-4791-85b7-4af05884656c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28086931277205972209792860367983170074763157194299703945729890989858
029521950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.280869312772059722097928603679831700747631571942
99703945729890989858029521950
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.36327333554016499108492860779973527216535503269378842475712275524871332637676
Short name T753
Test name
Test status
Simulation time 590810517 ps
CPU time 5.43 seconds
Started Nov 22 01:21:23 PM PST 23
Finished Nov 22 01:21:38 PM PST 23
Peak memory 202572 kb
Host smart-9153e55c-7e94-4b8d-ad6d-dfd4be33c433
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36327333554016499108492860779973527216535503269378842475712275524871332637676
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.36327333554016499108492860779973527216535503269378842475712275524871332637676
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.24408679609093420411205288711853771916212188820478183905683082634744869127528
Short name T335
Test name
Test status
Simulation time 21947461091 ps
CPU time 792.18 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 371208 kb
Host smart-a3637f3a-45b3-4e7a-98f0-a28da57a7600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24408679609093420411205288711853771916212188820478183905683082634744869127528 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.24408679609093420411205288711853771916212188820478183905683082634744869127528
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.34558858233920666983673089601770351694212793793948905081778983565695106242844
Short name T268
Test name
Test status
Simulation time 445204539 ps
CPU time 14.56 seconds
Started Nov 22 01:21:27 PM PST 23
Finished Nov 22 01:21:58 PM PST 23
Peak memory 246624 kb
Host smart-ca4582b2-096f-4172-9914-c1daf19f9fbe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345588582339206669836730896017703516942127937939489050817789835656951
06242844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.345588582339206669836730896017703516942127937939489050
81778983565695106242844
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.38640458821519656715149155645384059585585275293897385162937937932027584441214
Short name T614
Test name
Test status
Simulation time 42305619653 ps
CPU time 547.02 seconds
Started Nov 22 01:21:14 PM PST 23
Finished Nov 22 01:30:22 PM PST 23
Peak memory 202712 kb
Host smart-4bb76371-af49-4b26-8c2c-389dc5516cda
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386404588215196567151491556453840595855852752938973851629379379320275
84441214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access_b2b.3864045882151965671514915564538405958558
5275293897385162937937932027584441214
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.7465951270134390842507776696398044633391991412074414669900758010711846835548
Short name T780
Test name
Test status
Simulation time 40672061 ps
CPU time 0.84 seconds
Started Nov 22 01:21:22 PM PST 23
Finished Nov 22 01:21:31 PM PST 23
Peak memory 202612 kb
Host smart-0ee6738b-3260-4e23-891c-b3ca92fc4aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7465951270134390842507776696398044633391991412074414669900758010711846835548 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.7465951270134390842507776696398044633391991412074414669900758010711846835548
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.67421804564003883180116698904592415654448025189765673017835411645729149618909
Short name T741
Test name
Test status
Simulation time 19383553031 ps
CPU time 595.19 seconds
Started Nov 22 01:21:23 PM PST 23
Finished Nov 22 01:31:27 PM PST 23
Peak memory 371652 kb
Host smart-bfbe0edd-18fe-48fc-b057-c81e4df14cb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67421804564003883180116698904592415654448025189765673017835411645729149618909 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.67421804564003883180116698904592415654448025189765673017835411645729149618909
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.66363172091608892694837861189932473834187081098052177767034039791412045346232
Short name T893
Test name
Test status
Simulation time 427865392 ps
CPU time 11.09 seconds
Started Nov 22 01:21:22 PM PST 23
Finished Nov 22 01:21:37 PM PST 23
Peak memory 246564 kb
Host smart-20e85f10-2f9e-4391-ade9-0c5d506165fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66363172091608892694837861189932473834187081098052177767034039791412045346232 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.66363172091608892694837861189932473834187081098052177767034039791412045346232
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.113736029631638892891855970276168019797279711996006835346231489146480822306603
Short name T368
Test name
Test status
Simulation time 121463254244 ps
CPU time 4012.14 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 02:29:19 PM PST 23
Peak memory 375408 kb
Host smart-62c3f764-2d27-48f5-b4ac-1b96df27a38d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113736029631638892891855970276168019797279711996006835346231489
146480822306603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.1137360296316388928918559702761680197972797119
96006835346231489146480822306603
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.72238388631071133961959453753812244013044158003728049017564169195047285826488
Short name T699
Test name
Test status
Simulation time 624328106 ps
CPU time 1151.76 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:40:49 PM PST 23
Peak memory 401868 kb
Host smart-cf9320c4-53c3-4903-bd9e-b1a2066cbf41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=72238388631071133961959453753812244013044158003728049017564169195047285826488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sr
am_ctrl_stress_all_with_rand_reset.72238388631071133961959453753812244013044158003728049017564169195047285826488
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.58654754683464040166717971937004413750956784629956059066629887418621280289822
Short name T676
Test name
Test status
Simulation time 6491370455 ps
CPU time 366.27 seconds
Started Nov 22 01:21:20 PM PST 23
Finished Nov 22 01:27:30 PM PST 23
Peak memory 202568 kb
Host smart-bfd4f4ad-7301-416b-b7b7-da5a4b5c787b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58654754683464040166717971937004413750956784629956059066629887418621280289822
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.586547546834640401667179719370044137509567846299560
59066629887418621280289822
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.25207936666425423340096434468671813611095599120741563237597588553468056636456
Short name T580
Test name
Test status
Simulation time 237420487 ps
CPU time 84.34 seconds
Started Nov 22 01:23:04 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 351268 kb
Host smart-9a8f6858-05f9-4747-931e-7bd05e20edbe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252079366664254233400964344686718136110955991207415632
37597588553468056636456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2520793666642542334009
6434468671813611095599120741563237597588553468056636456
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.88658527771449893843546683024107881752597769619790464095624576760554681508715
Short name T270
Test name
Test status
Simulation time 4471404472 ps
CPU time 809.17 seconds
Started Nov 22 01:21:47 PM PST 23
Finished Nov 22 01:35:21 PM PST 23
Peak memory 375528 kb
Host smart-f7491caa-fbb2-4969-a4c1-85f30f05ac3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88658527771449893843546683024107881752597769619790464095624576760554681508715
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during_key_req.886585277714498938435466830241078817525
97769619790464095624576760554681508715
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.74449216470032021222578212542569905091402816575202130583538514343836247377917
Short name T324
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:22:00 PM PST 23
Peak memory 202184 kb
Host smart-c94e601c-42d7-4a58-a617-dd79717c5f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744492164700320212225782125425699050914028165752021305835385143438
36247377917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.744492164700320212225782125425699050914028165752021305
83538514343836247377917
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.6111591823252585861404162947124404504049212752821998852768013173050579918703
Short name T358
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.75 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 202464 kb
Host smart-778b981d-a206-4a78-ac0b-09930657b03b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6111591823252585861404162947124404504049212752821998852768013173050579918703 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.6111591823252585861404162947124404504049212752821998852768013173050579918703
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.92478772865952499766929663163820921903740450907318414442759183928136295985067
Short name T569
Test name
Test status
Simulation time 23162112088 ps
CPU time 816.78 seconds
Started Nov 22 01:21:55 PM PST 23
Finished Nov 22 01:35:38 PM PST 23
Peak memory 364676 kb
Host smart-ec31e132-be69-4624-a99a-8817be2a73e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92478772865952499766929663163820921903740450907318414442759183928136295985067 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.92478772865952499766929663163820921903740450907318414442759183928136295985067
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.44742003966853512871562851048817234616186258361182237635647878697146689424467
Short name T1033
Test name
Test status
Simulation time 985753786 ps
CPU time 7.35 seconds
Started Nov 22 01:21:39 PM PST 23
Finished Nov 22 01:21:54 PM PST 23
Peak memory 213076 kb
Host smart-c962e251-a332-4d1c-9bc7-41f03edf3c0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44742003966853512871562851048817234616186258361182237635647878697146689424467 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.44742003966853512871562851048817234616186258361182237635647878697146689424467
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.52725015345021298434606412263531151542367032381282272528909670027933414898451
Short name T404
Test name
Test status
Simulation time 209242141 ps
CPU time 70.87 seconds
Started Nov 22 01:21:38 PM PST 23
Finished Nov 22 01:22:56 PM PST 23
Peak memory 351244 kb
Host smart-33171046-6e26-493f-872b-b73814f0fdac
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5272501534502129843460641226353115154236703238128227252
8909670027933414898451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_max_throughput.52725015345021298434606412263531151
542367032381282272528909670027933414898451
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.62220971276999120234531364785433479875394905998326791909685912450283431600989
Short name T833
Test name
Test status
Simulation time 166171057 ps
CPU time 3.07 seconds
Started Nov 22 01:22:05 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 215676 kb
Host smart-0120d9ba-7ace-4cab-b4f6-725fa30e07c4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62220971276999120234531364785433479875394905998326791909685912450283
431600989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.622209712769991202345313647854334798753949059983
26791909685912450283431600989
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.57215075783307014582116403029038659230539527025605789680163735517394428935835
Short name T255
Test name
Test status
Simulation time 590810517 ps
CPU time 5.42 seconds
Started Nov 22 01:21:52 PM PST 23
Finished Nov 22 01:22:03 PM PST 23
Peak memory 202584 kb
Host smart-a6642c92-7b17-42dc-b341-47eff99f509e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57215075783307014582116403029038659230539527025605789680163735517394428935835
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.57215075783307014582116403029038659230539527025605789680163735517394428935835
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.102771210836058477581414671315099908107562843521203834560335942614355372361606
Short name T567
Test name
Test status
Simulation time 21947461091 ps
CPU time 793.4 seconds
Started Nov 22 01:21:26 PM PST 23
Finished Nov 22 01:34:50 PM PST 23
Peak memory 371264 kb
Host smart-ba353428-70ee-47cf-ad13-3fd9016077ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102771210836058477581414671315099908107562843521203834560335942614355372361606 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.102771210836058477581414671315099908107562843521203834560335942614355372361606
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.79086528893541392635544345878460963118420001727611065526997656137335209135306
Short name T771
Test name
Test status
Simulation time 445204539 ps
CPU time 13.94 seconds
Started Nov 22 01:21:47 PM PST 23
Finished Nov 22 01:22:06 PM PST 23
Peak memory 246564 kb
Host smart-80a6eeaa-23f6-4e22-b91f-d6274df58bb8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790865288935413926355443458784609631184200017276110655269976561373352
09135306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.790865288935413926355443458784609631184200017276110655
26997656137335209135306
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.51118509641109110146341703358360493391260860205816778076262894544299209365235
Short name T775
Test name
Test status
Simulation time 42305619653 ps
CPU time 543.69 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:30:58 PM PST 23
Peak memory 202704 kb
Host smart-8de380f5-3763-49a8-9c67-c24690064b12
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511185096411091101463417033583604933912608602058167780762628945442992
09365235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access_b2b.5111850964110911014634170335836049339126
0860205816778076262894544299209365235
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.105360495796018429541510771609364008999666029221390812149560339191879705024804
Short name T344
Test name
Test status
Simulation time 40672061 ps
CPU time 0.81 seconds
Started Nov 22 01:21:40 PM PST 23
Finished Nov 22 01:21:47 PM PST 23
Peak memory 202616 kb
Host smart-5af3f210-fdb0-46da-b90d-320f8280fb1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105360495796018429541510771609364008999666029221390812149560339191879705024804 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.105360495796018429541510771609364008999666029221390812149560339191879705024804
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.83785679671362013710330333094352804565657366239774262799543821437415036565477
Short name T504
Test name
Test status
Simulation time 19383553031 ps
CPU time 572.89 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:31:38 PM PST 23
Peak memory 371832 kb
Host smart-39e21df7-e43d-4697-9cc6-ae85f10b5d1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83785679671362013710330333094352804565657366239774262799543821437415036565477 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.83785679671362013710330333094352804565657366239774262799543821437415036565477
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.32292288687668905591476760634030675140952831647386127591408999860428553045575
Short name T334
Test name
Test status
Simulation time 427865392 ps
CPU time 12.1 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:22:15 PM PST 23
Peak memory 246392 kb
Host smart-ac35d614-608f-48c4-ba9f-ce499f872148
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32292288687668905591476760634030675140952831647386127591408999860428553045575 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.32292288687668905591476760634030675140952831647386127591408999860428553045575
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.15475269301219659698010844858147668887947964915549412933477677806057272746903
Short name T562
Test name
Test status
Simulation time 121463254244 ps
CPU time 3300.88 seconds
Started Nov 22 01:21:42 PM PST 23
Finished Nov 22 02:16:49 PM PST 23
Peak memory 375444 kb
Host smart-2914a26d-ff9e-42d5-8425-3059343801a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154752693012196596980108448581476688879479649155494129334776778
06057272746903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.15475269301219659698010844858147668887947964915
549412933477677806057272746903
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.82147531321548394820446167581553689864773103157597655371307500105582614309349
Short name T551
Test name
Test status
Simulation time 624328106 ps
CPU time 1064.25 seconds
Started Nov 22 01:21:56 PM PST 23
Finished Nov 22 01:39:46 PM PST 23
Peak memory 401712 kb
Host smart-193842f1-75aa-41b1-aaa7-98475c16aff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=82147531321548394820446167581553689864773103157597655371307500105582614309349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sr
am_ctrl_stress_all_with_rand_reset.82147531321548394820446167581553689864773103157597655371307500105582614309349
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.22038144857113809458848243787070763416727039045949407495926908931470884819514
Short name T607
Test name
Test status
Simulation time 6491370455 ps
CPU time 355.66 seconds
Started Nov 22 01:23:11 PM PST 23
Finished Nov 22 01:29:16 PM PST 23
Peak memory 202548 kb
Host smart-8ce5b30b-ea34-40bc-8faf-28f6d036cdad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22038144857113809458848243787070763416727039045949407495926908931470884819514
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.220381448571138094588482437870707634167270390459494
07495926908931470884819514
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.60580673045336201741790926655082543768434986297883959446546342477342752289993
Short name T633
Test name
Test status
Simulation time 237420487 ps
CPU time 65.09 seconds
Started Nov 22 01:21:33 PM PST 23
Finished Nov 22 01:22:44 PM PST 23
Peak memory 351200 kb
Host smart-8d544044-3df7-440d-8682-f43aad358b47
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605806730453362017417909266550825437684349862978839594
46546342477342752289993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.6058067304533620174179
0926655082543768434986297883959446546342477342752289993
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.67286139237205928666886822123549972695840183721745152721748017816814735848270
Short name T553
Test name
Test status
Simulation time 4471404472 ps
CPU time 569.26 seconds
Started Nov 22 01:21:33 PM PST 23
Finished Nov 22 01:31:08 PM PST 23
Peak memory 375348 kb
Host smart-472d20f2-3062-437a-a920-b85dd6652d4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67286139237205928666886822123549972695840183721745152721748017816814735848270
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during_key_req.672861392372059286668868221235499726958
40183721745152721748017816814735848270
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.2801019541896381091869805996285639334933963732269679901440336230103585443829
Short name T627
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:21:31 PM PST 23
Finished Nov 22 01:21:38 PM PST 23
Peak memory 202176 kb
Host smart-7db5f450-a9d4-4a1a-9d43-5e3043436e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280101954189638109186980599628563933493396373226967990144033623010
3585443829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.2801019541896381091869805996285639334933963732269679901
440336230103585443829
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.67760993987709421709762512733753328932304314726197225202146971322160334332212
Short name T391
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.55 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:23:23 PM PST 23
Peak memory 202636 kb
Host smart-afc99743-9af1-4f05-9c29-83c5483a6776
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67760993987709421709762512733753328932304314726197225202146971322160334332212 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.67760993987709421709762512733753328932304314726197225202146971322160334332212
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.54185235171956254911680610667361151690226975922496285365309882977773998800943
Short name T695
Test name
Test status
Simulation time 23162112088 ps
CPU time 622.24 seconds
Started Nov 22 01:22:26 PM PST 23
Finished Nov 22 01:32:54 PM PST 23
Peak memory 364500 kb
Host smart-eb967f0c-fe0b-4511-b491-7aaadda26906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54185235171956254911680610667361151690226975922496285365309882977773998800943 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.54185235171956254911680610667361151690226975922496285365309882977773998800943
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.70873012881117298159867285624482513328469533651455441918469250574843186513715
Short name T694
Test name
Test status
Simulation time 985753786 ps
CPU time 7.28 seconds
Started Nov 22 01:21:37 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 213168 kb
Host smart-080cb9eb-9d08-42c2-893f-4bb0c5e103b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70873012881117298159867285624482513328469533651455441918469250574843186513715 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.70873012881117298159867285624482513328469533651455441918469250574843186513715
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.69305616796043918050977563891015114996432233889317242189548638234611716887295
Short name T717
Test name
Test status
Simulation time 209242141 ps
CPU time 84.62 seconds
Started Nov 22 01:22:33 PM PST 23
Finished Nov 22 01:24:02 PM PST 23
Peak memory 351348 kb
Host smart-11bef1fe-3f36-496f-aa5f-d57d1c1c586e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6930561679604391805097756389101511499643223388931724218
9548638234611716887295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_max_throughput.69305616796043918050977563891015114
996432233889317242189548638234611716887295
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.78106253706552084859486058649466330033060836354345865707738547989927601820716
Short name T1018
Test name
Test status
Simulation time 166171057 ps
CPU time 3.13 seconds
Started Nov 22 01:21:27 PM PST 23
Finished Nov 22 01:21:40 PM PST 23
Peak memory 215724 kb
Host smart-abee4bde-78d4-437d-a975-a4c5cead0dd2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78106253706552084859486058649466330033060836354345865707738547989927
601820716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.781062537065520848594860586494663300330608363543
45865707738547989927601820716
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.62633630876266494338717751995137336238682631121011276589843416502124836962858
Short name T947
Test name
Test status
Simulation time 590810517 ps
CPU time 5.31 seconds
Started Nov 22 01:21:34 PM PST 23
Finished Nov 22 01:21:49 PM PST 23
Peak memory 202616 kb
Host smart-d680b633-22d5-4a37-bd1d-2b940736be57
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62633630876266494338717751995137336238682631121011276589843416502124836962858
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.62633630876266494338717751995137336238682631121011276589843416502124836962858
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.37940158310945776577956868835062623501569479786206099635401537181771884440570
Short name T570
Test name
Test status
Simulation time 21947461091 ps
CPU time 621.13 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:33:11 PM PST 23
Peak memory 370124 kb
Host smart-a4922af1-a666-415d-b361-764c7c6f0f13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37940158310945776577956868835062623501569479786206099635401537181771884440570 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.37940158310945776577956868835062623501569479786206099635401537181771884440570
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.38935772364887323100128738322600650147034397919993328571963136403218255084918
Short name T979
Test name
Test status
Simulation time 445204539 ps
CPU time 11.88 seconds
Started Nov 22 01:22:47 PM PST 23
Finished Nov 22 01:23:12 PM PST 23
Peak memory 246152 kb
Host smart-76a6e00a-e55e-4a29-b681-c805a1da0b55
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389357723648873231001287383226006501470343979199933285719631364032182
55084918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.389357723648873231001287383226006501470343979199933285
71963136403218255084918
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4567952212228803595039675957035309356253736147153845707176150290528100703002
Short name T547
Test name
Test status
Simulation time 42305619653 ps
CPU time 538.41 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:31:01 PM PST 23
Peak memory 202652 kb
Host smart-a4a50467-7cd1-45de-9f0b-19ac9cfeaa31
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456795221222880359503967595703530935625373614715384570717615029052810
0703002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access_b2b.45679522122288035950396759570353093562537
36147153845707176150290528100703002
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.107444977533972123586056613076129867218931447910442443332358121074047948091265
Short name T1013
Test name
Test status
Simulation time 40672061 ps
CPU time 0.84 seconds
Started Nov 22 01:21:12 PM PST 23
Finished Nov 22 01:21:14 PM PST 23
Peak memory 202604 kb
Host smart-916acec1-14dc-4141-8d02-75adc2e4983d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107444977533972123586056613076129867218931447910442443332358121074047948091265 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.107444977533972123586056613076129867218931447910442443332358121074047948091265
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.55076244288153306388721788441798439368109248056576636846264608507873904994234
Short name T722
Test name
Test status
Simulation time 19383553031 ps
CPU time 690.62 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:33:26 PM PST 23
Peak memory 371784 kb
Host smart-baae5ea7-242e-45b8-bbe4-737d65c24933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55076244288153306388721788441798439368109248056576636846264608507873904994234 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.55076244288153306388721788441798439368109248056576636846264608507873904994234
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.98923680135182801760187372702703066548585812385306492058214701269664099637535
Short name T993
Test name
Test status
Simulation time 427865392 ps
CPU time 11.33 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:23:01 PM PST 23
Peak memory 246600 kb
Host smart-b61ad56c-829e-4f2e-9e12-038cae6f7cd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98923680135182801760187372702703066548585812385306492058214701269664099637535 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.98923680135182801760187372702703066548585812385306492058214701269664099637535
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.112074328696367563735649780080150085875121002630202196253984063838137686088825
Short name T649
Test name
Test status
Simulation time 121463254244 ps
CPU time 3857.52 seconds
Started Nov 22 01:21:31 PM PST 23
Finished Nov 22 02:25:55 PM PST 23
Peak memory 375456 kb
Host smart-220f93a5-f04f-407f-9b32-010e339b1d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112074328696367563735649780080150085875121002630202196253984063
838137686088825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.1120743286963675637356497800801500858751210026
30202196253984063838137686088825
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.45349818723076232925598691574082139909973811951422266286092803972068869566066
Short name T827
Test name
Test status
Simulation time 624328106 ps
CPU time 1241.79 seconds
Started Nov 22 01:21:33 PM PST 23
Finished Nov 22 01:42:23 PM PST 23
Peak memory 401692 kb
Host smart-65990555-5191-4998-99bf-24966f55b73a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=45349818723076232925598691574082139909973811951422266286092803972068869566066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sr
am_ctrl_stress_all_with_rand_reset.45349818723076232925598691574082139909973811951422266286092803972068869566066
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.27654331729933046758561559545183098659917819580224003610188938306819700801942
Short name T997
Test name
Test status
Simulation time 6491370455 ps
CPU time 361.21 seconds
Started Nov 22 01:21:55 PM PST 23
Finished Nov 22 01:28:02 PM PST 23
Peak memory 202604 kb
Host smart-4632e621-c7d5-44fd-8e25-70337f905bf8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27654331729933046758561559545183098659917819580224003610188938306819700801942
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.276543317299330467585615595451830986599178195802240
03610188938306819700801942
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.105123144245960877602989862161302445449823025326601389081685411817317160281517
Short name T615
Test name
Test status
Simulation time 237420487 ps
CPU time 101.83 seconds
Started Nov 22 01:21:47 PM PST 23
Finished Nov 22 01:23:35 PM PST 23
Peak memory 350428 kb
Host smart-1e91788e-e572-47f7-9c5a-79b39f16d2e7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105123144245960877602989862161302445449823025326601389
081685411817317160281517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.105123144245960877602
989862161302445449823025326601389081685411817317160281517
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.34257683314446790986608652804869788465695533575766518242253984625554228330053
Short name T359
Test name
Test status
Simulation time 4471404472 ps
CPU time 754.69 seconds
Started Nov 22 01:21:59 PM PST 23
Finished Nov 22 01:34:39 PM PST 23
Peak memory 375448 kb
Host smart-053d6a77-f384-4a7e-bdc0-1249f4def984
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34257683314446790986608652804869788465695533575766518242253984625554228330053
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during_key_req.342576833144467909866086528048697884656
95533575766518242253984625554228330053
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.59391692174432697692130610185256394209430956999849849711262438229466940172622
Short name T1040
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:21:39 PM PST 23
Finished Nov 22 01:21:46 PM PST 23
Peak memory 202184 kb
Host smart-cdb0e898-8ce9-47b4-b359-825d88a4ade2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593916921744326976921306101852563942094309569998498497112624382294
66940172622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.593916921744326976921306101852563942094309569998498497
11262438229466940172622
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.66360636004211471477870297614632580008694153381215844366269387673514796196465
Short name T407
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.97 seconds
Started Nov 22 01:21:44 PM PST 23
Finished Nov 22 01:23:13 PM PST 23
Peak memory 202528 kb
Host smart-95ff6724-e58a-4729-a4af-635286ed2d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66360636004211471477870297614632580008694153381215844366269387673514796196465 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.66360636004211471477870297614632580008694153381215844366269387673514796196465
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.11770980817098740344192368344571038357180599469533347190363401592032257910372
Short name T876
Test name
Test status
Simulation time 985753786 ps
CPU time 7.15 seconds
Started Nov 22 01:21:55 PM PST 23
Finished Nov 22 01:22:08 PM PST 23
Peak memory 213236 kb
Host smart-17a4c561-4389-43c8-bdb2-f0a60743efb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11770980817098740344192368344571038357180599469533347190363401592032257910372 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.11770980817098740344192368344571038357180599469533347190363401592032257910372
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.72074197084346800743591083957041485001534054286597534624869091568326750746708
Short name T301
Test name
Test status
Simulation time 209242141 ps
CPU time 95.79 seconds
Started Nov 22 01:21:56 PM PST 23
Finished Nov 22 01:23:38 PM PST 23
Peak memory 351380 kb
Host smart-411878a6-d5a1-40de-9a06-1be11ee3818b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7207419708434680074359108395704148500153405428659753462
4869091568326750746708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_max_throughput.72074197084346800743591083957041485
001534054286597534624869091568326750746708
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.67379237743417261418462273933678209261678930813760344559883415190230126312933
Short name T623
Test name
Test status
Simulation time 166171057 ps
CPU time 2.98 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:21:59 PM PST 23
Peak memory 215684 kb
Host smart-4d163972-5e0f-4cc0-9a3d-07a0e0429c34
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67379237743417261418462273933678209261678930813760344559883415190230
126312933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.673792377434172614184622739336782092616789308137
60344559883415190230126312933
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.84098982112482972361686355016350585827006029356037586316864626477731430724272
Short name T314
Test name
Test status
Simulation time 590810517 ps
CPU time 5.5 seconds
Started Nov 22 01:21:36 PM PST 23
Finished Nov 22 01:21:50 PM PST 23
Peak memory 202604 kb
Host smart-cb5e5c83-5a86-4007-9700-96e143bed5e9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84098982112482972361686355016350585827006029356037586316864626477731430724272
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.84098982112482972361686355016350585827006029356037586316864626477731430724272
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.19440191093434778619377624670869087643226761747047639525390511014892691561156
Short name T130
Test name
Test status
Simulation time 21947461091 ps
CPU time 779.76 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:35:35 PM PST 23
Peak memory 371260 kb
Host smart-47852d47-a955-4c9b-847a-a5e7b79d29a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19440191093434778619377624670869087643226761747047639525390511014892691561156 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.19440191093434778619377624670869087643226761747047639525390511014892691561156
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.10177835613722140044783150520485194852243306574783121143104597475602301238033
Short name T809
Test name
Test status
Simulation time 445204539 ps
CPU time 13.46 seconds
Started Nov 22 01:21:35 PM PST 23
Finished Nov 22 01:21:57 PM PST 23
Peak memory 246572 kb
Host smart-18129811-df8d-4f79-953b-d4bc48fd5dc8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101778356137221400447831505204851948522433065747831211431045974756023
01238033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.101778356137221400447831505204851948522433065747831211
43104597475602301238033
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.59861898299974127967295583543584415163545879520941176497386171747282780017368
Short name T573
Test name
Test status
Simulation time 42305619653 ps
CPU time 533.67 seconds
Started Nov 22 01:21:48 PM PST 23
Finished Nov 22 01:30:47 PM PST 23
Peak memory 202656 kb
Host smart-8d536f3a-5dff-447a-bdd0-9108f27a392c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598618982999741279672955835435844151635458795209411764973861717472827
80017368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access_b2b.5986189829997412796729558354358441516354
5879520941176497386171747282780017368
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.68796066301281891997257129654265011107241846176522279773946279551737691510133
Short name T341
Test name
Test status
Simulation time 40672061 ps
CPU time 0.81 seconds
Started Nov 22 01:21:39 PM PST 23
Finished Nov 22 01:21:47 PM PST 23
Peak memory 202468 kb
Host smart-0762d1a2-75b5-402b-89d2-e2238dd6d672
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68796066301281891997257129654265011107241846176522279773946279551737691510133 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.68796066301281891997257129654265011107241846176522279773946279551737691510133
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.99975872992975943058864142080853874690720568715994823547035847398825608836588
Short name T588
Test name
Test status
Simulation time 19383553031 ps
CPU time 573.66 seconds
Started Nov 22 01:21:35 PM PST 23
Finished Nov 22 01:31:18 PM PST 23
Peak memory 371720 kb
Host smart-08cafa2f-eed2-4834-a100-711092d43f44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99975872992975943058864142080853874690720568715994823547035847398825608836588 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.99975872992975943058864142080853874690720568715994823547035847398825608836588
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.104399096995988127339294919561358189516809149674567582678354513640940896460600
Short name T429
Test name
Test status
Simulation time 427865392 ps
CPU time 12.24 seconds
Started Nov 22 01:21:33 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 246616 kb
Host smart-a6be6777-69e0-45b5-903d-d9a2b97e34f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104399096995988127339294919561358189516809149674567582678354513640940896460600 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.104399096995988127339294919561358189516809149674567582678354513640940896460600
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.16982800844537607551565588376108127378908682547646239627566960384131150959347
Short name T519
Test name
Test status
Simulation time 121463254244 ps
CPU time 3622.42 seconds
Started Nov 22 01:21:43 PM PST 23
Finished Nov 22 02:22:11 PM PST 23
Peak memory 375456 kb
Host smart-6f4b9805-0203-4f4e-8cb9-1caec5dbf7f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169828008445376075515655883761081273789086825476462396275669603
84131150959347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.16982800844537607551565588376108127378908682547
646239627566960384131150959347
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.39583552860548497613186906400491591281472792811352326209416470918231743270034
Short name T347
Test name
Test status
Simulation time 624328106 ps
CPU time 956.58 seconds
Started Nov 22 01:22:26 PM PST 23
Finished Nov 22 01:38:27 PM PST 23
Peak memory 401680 kb
Host smart-5b9bf533-3870-4d2a-be20-5222d17eaa9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=39583552860548497613186906400491591281472792811352326209416470918231743270034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sr
am_ctrl_stress_all_with_rand_reset.39583552860548497613186906400491591281472792811352326209416470918231743270034
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.75148722955087650989014049119775823749217636236003368704917042256898194187212
Short name T132
Test name
Test status
Simulation time 6491370455 ps
CPU time 350.16 seconds
Started Nov 22 01:22:42 PM PST 23
Finished Nov 22 01:28:38 PM PST 23
Peak memory 202496 kb
Host smart-182f7182-b737-42af-a417-9c63e8cfe346
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75148722955087650989014049119775823749217636236003368704917042256898194187212
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.751487229550876509890140491197758237492176362360033
68704917042256898194187212
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.76582240957513955320920515812871682730806969517157615611762132969880372990905
Short name T959
Test name
Test status
Simulation time 237420487 ps
CPU time 146.29 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:24:22 PM PST 23
Peak memory 351336 kb
Host smart-1877c1b0-f082-434a-b190-a43f322d97e1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765822409575139553209205158128716827308069695171576156
11762132969880372990905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.7658224095751395532092
0515812871682730806969517157615611762132969880372990905
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.57382446269742480382752547540165202039666630852705679878897062787408493252967
Short name T655
Test name
Test status
Simulation time 4471404472 ps
CPU time 814.69 seconds
Started Nov 22 01:21:59 PM PST 23
Finished Nov 22 01:35:39 PM PST 23
Peak memory 375448 kb
Host smart-5a5b9d7d-e10e-46f8-8fa5-65f03689a2d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57382446269742480382752547540165202039666630852705679878897062787408493252967
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during_key_req.573824462697424803827525475401652020396
66630852705679878897062787408493252967
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.110956867298953943336076351425990844343770550031169108862225852772842251751363
Short name T994
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:21:52 PM PST 23
Finished Nov 22 01:21:58 PM PST 23
Peak memory 202192 kb
Host smart-860cbad8-363f-48a2-849d-7ee5d7ee1fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110956867298953943336076351425990844343770550031169108862225852772
842251751363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.11095686729895394333607635142599084434377055003116910
8862225852772842251751363
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.62469204876627672622945248411276991544278499755381468501405636521931542063129
Short name T354
Test name
Test status
Simulation time 9249473390 ps
CPU time 81.91 seconds
Started Nov 22 01:21:37 PM PST 23
Finished Nov 22 01:23:07 PM PST 23
Peak memory 202640 kb
Host smart-c6c4ce02-3506-48b0-b444-b7e057489990
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62469204876627672622945248411276991544278499755381468501405636521931542063129 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.62469204876627672622945248411276991544278499755381468501405636521931542063129
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.84332259452224024536321920816991316341951354597656512039768948974676599026250
Short name T788
Test name
Test status
Simulation time 23162112088 ps
CPU time 721.15 seconds
Started Nov 22 01:21:34 PM PST 23
Finished Nov 22 01:33:45 PM PST 23
Peak memory 364588 kb
Host smart-2ab19c82-d39e-4694-9807-15a5d3777d54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84332259452224024536321920816991316341951354597656512039768948974676599026250 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.84332259452224024536321920816991316341951354597656512039768948974676599026250
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.46762912403832486045111457076159011517802850785961005334389200176693592292762
Short name T523
Test name
Test status
Simulation time 985753786 ps
CPU time 6.91 seconds
Started Nov 22 01:21:47 PM PST 23
Finished Nov 22 01:21:59 PM PST 23
Peak memory 213204 kb
Host smart-09edf34e-1e62-40f7-8199-64d795397bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46762912403832486045111457076159011517802850785961005334389200176693592292762 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.46762912403832486045111457076159011517802850785961005334389200176693592292762
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.50901994908705924988090367828625332457804547392304619173044582149146044801589
Short name T636
Test name
Test status
Simulation time 209242141 ps
CPU time 87.07 seconds
Started Nov 22 01:21:58 PM PST 23
Finished Nov 22 01:23:31 PM PST 23
Peak memory 351252 kb
Host smart-9afb3110-7f4e-4356-b298-6d46deac50a4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5090199490870592498809036782862533245780454739230461917
3044582149146044801589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_max_throughput.50901994908705924988090367828625332
457804547392304619173044582149146044801589
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.64975335749360059353145611575501865263697745450072621350459337334937146856609
Short name T622
Test name
Test status
Simulation time 166171057 ps
CPU time 2.99 seconds
Started Nov 22 01:21:38 PM PST 23
Finished Nov 22 01:21:48 PM PST 23
Peak memory 215736 kb
Host smart-530c5ed9-a271-4ad8-9897-1c59e89d0ac5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64975335749360059353145611575501865263697745450072621350459337334937
146856609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.649753357493600593531456115755018652636977454500
72621350459337334937146856609
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.86947706303331933530346040589280890027896678113172788419395830629720547453973
Short name T136
Test name
Test status
Simulation time 590810517 ps
CPU time 5.5 seconds
Started Nov 22 01:21:42 PM PST 23
Finished Nov 22 01:21:53 PM PST 23
Peak memory 202432 kb
Host smart-af447611-1b24-48dc-b63b-def12d170343
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86947706303331933530346040589280890027896678113172788419395830629720547453973
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.86947706303331933530346040589280890027896678113172788419395830629720547453973
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.26615849542336070826525820066739816012294193591051192209360664806920953339069
Short name T147
Test name
Test status
Simulation time 21947461091 ps
CPU time 724.04 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:33:59 PM PST 23
Peak memory 371412 kb
Host smart-69387632-e89e-4109-b825-5955f52e819c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26615849542336070826525820066739816012294193591051192209360664806920953339069 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.26615849542336070826525820066739816012294193591051192209360664806920953339069
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.30680950572749343353462793400127722538690430362001751539433840850252270386136
Short name T772
Test name
Test status
Simulation time 445204539 ps
CPU time 11.72 seconds
Started Nov 22 01:21:38 PM PST 23
Finished Nov 22 01:21:57 PM PST 23
Peak memory 246516 kb
Host smart-9e61c03c-5cb2-40c5-b0f2-299fccc00609
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306809505727493433534627934001277225386904303620017515394338408502522
70386136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.306809505727493433534627934001277225386904303620017515
39433840850252270386136
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.89295612533940830866940960316650210888898258651576111245482824728733273376759
Short name T498
Test name
Test status
Simulation time 42305619653 ps
CPU time 545.34 seconds
Started Nov 22 01:21:48 PM PST 23
Finished Nov 22 01:30:59 PM PST 23
Peak memory 202608 kb
Host smart-292511c2-c6f7-40a5-9286-ab2058fcf026
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892956125339408308669409603166502108888982586515761112454828247287332
73376759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access_b2b.8929561253394083086694096031665021088889
8258651576111245482824728733273376759
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.39155771914233427187057714865587262039689948044588915151081086539682273996869
Short name T396
Test name
Test status
Simulation time 19383553031 ps
CPU time 667.91 seconds
Started Nov 22 01:21:56 PM PST 23
Finished Nov 22 01:33:10 PM PST 23
Peak memory 371824 kb
Host smart-bc6c25ad-4d17-472f-8b3b-de7ab6f52e8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39155771914233427187057714865587262039689948044588915151081086539682273996869 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.39155771914233427187057714865587262039689948044588915151081086539682273996869
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.18547058055186603045543758241266779878068056227891896423100372499356997522739
Short name T265
Test name
Test status
Simulation time 427865392 ps
CPU time 12.54 seconds
Started Nov 22 01:21:37 PM PST 23
Finished Nov 22 01:21:58 PM PST 23
Peak memory 246664 kb
Host smart-de2f2752-58dd-4067-b88a-9ea111545172
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547058055186603045543758241266779878068056227891896423100372499356997522739 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.18547058055186603045543758241266779878068056227891896423100372499356997522739
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.60208606097386086684209088521857528112778447296708624575272214355109914250890
Short name T863
Test name
Test status
Simulation time 121463254244 ps
CPU time 3093.66 seconds
Started Nov 22 01:21:38 PM PST 23
Finished Nov 22 02:13:19 PM PST 23
Peak memory 375472 kb
Host smart-c2a16351-84bb-4b88-a93c-1fdedad95bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602086060973860866842090885218575281127784472967086245752722143
55109914250890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.60208606097386086684209088521857528112778447296
708624575272214355109914250890
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.113165107112381082210067274309672067472244957002143286821569810990311565313102
Short name T49
Test name
Test status
Simulation time 624328106 ps
CPU time 1446.71 seconds
Started Nov 22 01:21:31 PM PST 23
Finished Nov 22 01:45:44 PM PST 23
Peak memory 401628 kb
Host smart-87bf33f0-4924-42f3-b9ff-c6276bbf0acd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=113165107112381082210067274309672067472244957002143286821569810990311565313102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s
ram_ctrl_stress_all_with_rand_reset.113165107112381082210067274309672067472244957002143286821569810990311565313102
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.63306541173194214754825385982966507643115684830359179481183834307214677708319
Short name T744
Test name
Test status
Simulation time 237420487 ps
CPU time 100.61 seconds
Started Nov 22 01:21:46 PM PST 23
Finished Nov 22 01:23:32 PM PST 23
Peak memory 351348 kb
Host smart-a165164e-72f4-4f38-aebc-625d146365f6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633065411731942147548253859829665076431156848303591794
81183834307214677708319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.6330654117319421475482
5385982966507643115684830359179481183834307214677708319
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.21211726724441446994586687327878687795861294226338902432674178313222042582639
Short name T579
Test name
Test status
Simulation time 4471404472 ps
CPU time 705.79 seconds
Started Nov 22 01:21:55 PM PST 23
Finished Nov 22 01:33:47 PM PST 23
Peak memory 375520 kb
Host smart-5e4cdc53-3672-4ae0-a67e-7c6b061617b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21211726724441446994586687327878687795861294226338902432674178313222042582639
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during_key_req.212117267244414469945866873278786877958
61294226338902432674178313222042582639
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.30916484230119050035315820006209914393725595207409627855786939270097490620351
Short name T608
Test name
Test status
Simulation time 16600825 ps
CPU time 0.64 seconds
Started Nov 22 01:21:58 PM PST 23
Finished Nov 22 01:22:05 PM PST 23
Peak memory 202000 kb
Host smart-ff9d6041-d78c-4b4e-a08c-9807544316fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309164842301190500353158200062099143937255952074096278557869392700
97490620351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.309164842301190500353158200062099143937255952074096278
55786939270097490620351
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.91603864804516889946022657933481296393328664531852114304839583310459484025769
Short name T817
Test name
Test status
Simulation time 9249473390 ps
CPU time 80.03 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:23:23 PM PST 23
Peak memory 202452 kb
Host smart-5683e1f1-f50f-4758-9ea9-35ee6137d7b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91603864804516889946022657933481296393328664531852114304839583310459484025769 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.91603864804516889946022657933481296393328664531852114304839583310459484025769
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.53109468032943466214160597510344816076365816539536273104422329153052756823036
Short name T919
Test name
Test status
Simulation time 23162112088 ps
CPU time 820.15 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:35:47 PM PST 23
Peak memory 364668 kb
Host smart-ceb56621-2814-4f8c-ba62-45b0f1406206
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53109468032943466214160597510344816076365816539536273104422329153052756823036 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.53109468032943466214160597510344816076365816539536273104422329153052756823036
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.55712891620812098623027123419619677409140789540665561824147314554666594682356
Short name T889
Test name
Test status
Simulation time 985753786 ps
CPU time 6.95 seconds
Started Nov 22 01:21:35 PM PST 23
Finished Nov 22 01:21:53 PM PST 23
Peak memory 213220 kb
Host smart-8171d1d9-c8d8-4227-a27b-a49d667926a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55712891620812098623027123419619677409140789540665561824147314554666594682356 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.55712891620812098623027123419619677409140789540665561824147314554666594682356
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.54343624843619572752550349372430973824737636370305380592565507802860398480130
Short name T400
Test name
Test status
Simulation time 209242141 ps
CPU time 65.36 seconds
Started Nov 22 01:21:43 PM PST 23
Finished Nov 22 01:22:53 PM PST 23
Peak memory 351336 kb
Host smart-3b3d81bd-801c-4147-bacc-c1abbeedd363
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5434362484361957275255034937243097382473763637030538059
2565507802860398480130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_max_throughput.54343624843619572752550349372430973
824737636370305380592565507802860398480130
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.13764800011716197698539528365256024385031003850726376700372287973810442928940
Short name T854
Test name
Test status
Simulation time 166171057 ps
CPU time 3.39 seconds
Started Nov 22 01:21:33 PM PST 23
Finished Nov 22 01:21:43 PM PST 23
Peak memory 215668 kb
Host smart-e47fddb2-63f1-4e44-bcfc-7803f6741517
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13764800011716197698539528365256024385031003850726376700372287973810
442928940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.137648000117161976985395283652560243850310038507
26376700372287973810442928940
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.568158243830308119997389809715560420835544670179033805352875460077757214606
Short name T273
Test name
Test status
Simulation time 590810517 ps
CPU time 5.68 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 202432 kb
Host smart-54dfaf94-8bbe-4248-a785-d4ef0ce70a49
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568158243830308119997389809715560420835544670179033805352875460077757214606 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.568158243830308119997389809715560420835544670179033805352875460077757214606
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.28002074782692551462345172597411753839213427632021362935063167968492910522640
Short name T329
Test name
Test status
Simulation time 21947461091 ps
CPU time 866.65 seconds
Started Nov 22 01:21:37 PM PST 23
Finished Nov 22 01:36:12 PM PST 23
Peak memory 371360 kb
Host smart-da4853b6-0c39-44dd-adf0-58d83142046f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28002074782692551462345172597411753839213427632021362935063167968492910522640 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.28002074782692551462345172597411753839213427632021362935063167968492910522640
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.76288097925044242034237106468219445622898971826945278153037690946960706574509
Short name T593
Test name
Test status
Simulation time 445204539 ps
CPU time 13.74 seconds
Started Nov 22 01:21:42 PM PST 23
Finished Nov 22 01:22:01 PM PST 23
Peak memory 246520 kb
Host smart-3273ce0f-cd81-4738-bdef-f9b74bd4625f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762880979250442420342371064682194456228989718269452781530376909469607
06574509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.762880979250442420342371064682194456228989718269452781
53037690946960706574509
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.11947247816718605715782528128297688188368230043547981002978656563197847215163
Short name T584
Test name
Test status
Simulation time 42305619653 ps
CPU time 531.62 seconds
Started Nov 22 01:21:56 PM PST 23
Finished Nov 22 01:30:54 PM PST 23
Peak memory 202556 kb
Host smart-5442b0d2-e0d1-4a93-8411-a56f3332916d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119472478167186057157825281282976881883682300435479810029786565631978
47215163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access_b2b.1194724781671860571578252812829768818836
8230043547981002978656563197847215163
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.104008750587819827030250625083966814781499842016617281340404914405058019658836
Short name T283
Test name
Test status
Simulation time 40672061 ps
CPU time 0.82 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 202532 kb
Host smart-e89a8020-b5f1-49d5-9a39-273a7397fb0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104008750587819827030250625083966814781499842016617281340404914405058019658836 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.104008750587819827030250625083966814781499842016617281340404914405058019658836
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.28034890174639158803595156921488375616954204400473706366286747148687732051326
Short name T529
Test name
Test status
Simulation time 19383553031 ps
CPU time 601.04 seconds
Started Nov 22 01:21:41 PM PST 23
Finished Nov 22 01:31:48 PM PST 23
Peak memory 371840 kb
Host smart-1196ecf6-bfc7-48c2-91ff-bed6095cf282
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28034890174639158803595156921488375616954204400473706366286747148687732051326 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.28034890174639158803595156921488375616954204400473706366286747148687732051326
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.28104048214485103566839702292304010121226976365032916442630265330470486043416
Short name T690
Test name
Test status
Simulation time 427865392 ps
CPU time 11.82 seconds
Started Nov 22 01:21:44 PM PST 23
Finished Nov 22 01:22:01 PM PST 23
Peak memory 246604 kb
Host smart-7a9f1ee2-7f67-4971-a1e1-ad205c8211f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28104048214485103566839702292304010121226976365032916442630265330470486043416 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.28104048214485103566839702292304010121226976365032916442630265330470486043416
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.9360838981923430215292335240639610711851900166076719291296038606036213789415
Short name T842
Test name
Test status
Simulation time 121463254244 ps
CPU time 3232.51 seconds
Started Nov 22 01:21:39 PM PST 23
Finished Nov 22 02:15:39 PM PST 23
Peak memory 375380 kb
Host smart-c6040e68-9bfe-4e4e-a035-394ac9690670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936083898192343021529233524063961071185190016607671929129603860
6036213789415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.936083898192343021529233524063961071185190016607
6719291296038606036213789415
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.28342679084446201512968261716123970431905285300927493476157934709727378690667
Short name T432
Test name
Test status
Simulation time 6491370455 ps
CPU time 355.87 seconds
Started Nov 22 01:21:59 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 202668 kb
Host smart-3f1771f6-790c-439f-8ffb-d9ac8ae50977
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28342679084446201512968261716123970431905285300927493476157934709727378690667
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.283426790844462015129682617161239704319052853009274
93476157934709727378690667
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.48219836865544681991865627965046317702651748044311684427237537950507776953998
Short name T894
Test name
Test status
Simulation time 237420487 ps
CPU time 92.59 seconds
Started Nov 22 01:21:52 PM PST 23
Finished Nov 22 01:23:30 PM PST 23
Peak memory 351360 kb
Host smart-9a338665-7577-4f5c-96e8-83d124c95cf1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482198368655446819918656279650463177026517480443116844
27237537950507776953998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.4821983686554468199186
5627965046317702651748044311684427237537950507776953998
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.12479697714721868190479839705827581993675011301953390807745092886270682781867
Short name T859
Test name
Test status
Simulation time 4471404472 ps
CPU time 805.73 seconds
Started Nov 22 01:21:46 PM PST 23
Finished Nov 22 01:35:18 PM PST 23
Peak memory 375552 kb
Host smart-6005dbea-a512-4255-9b13-7d06279a0d52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12479697714721868190479839705827581993675011301953390807745092886270682781867
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during_key_req.124796977147218681904798397058275819936
75011301953390807745092886270682781867
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.94144587954022426040774526627949975339617599036768096835714585916430440076105
Short name T21
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:21:51 PM PST 23
Peak memory 202220 kb
Host smart-1127dbc9-ca1c-4d1b-8274-ff2debabde77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941445879540224260407745266279499753396175990367680968357145859164
30440076105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.941445879540224260407745266279499753396175990367680968
35714585916430440076105
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1847812102232623498666662265582957592214618725025800866507778629621498026189
Short name T924
Test name
Test status
Simulation time 9249473390 ps
CPU time 81.03 seconds
Started Nov 22 01:22:48 PM PST 23
Finished Nov 22 01:24:22 PM PST 23
Peak memory 202576 kb
Host smart-e482ee35-44ef-4a1f-83dc-380e1ad181d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847812102232623498666662265582957592214618725025800866507778629621498026189 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.1847812102232623498666662265582957592214618725025800866507778629621498026189
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.1265166489056857458447762318616672440674267016167454286793016338233567345644
Short name T490
Test name
Test status
Simulation time 23162112088 ps
CPU time 695.57 seconds
Started Nov 22 01:21:44 PM PST 23
Finished Nov 22 01:33:24 PM PST 23
Peak memory 364508 kb
Host smart-58e0c2e5-6f6f-4091-952b-d6334013ecac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265166489056857458447762318616672440674267016167454286793016338233567345644 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.1265166489056857458447762318616672440674267016167454286793016338233567345644
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.41076834867122674005209344390924928037198562516821546784242880326617208111146
Short name T868
Test name
Test status
Simulation time 985753786 ps
CPU time 7.09 seconds
Started Nov 22 01:22:16 PM PST 23
Finished Nov 22 01:22:25 PM PST 23
Peak memory 213204 kb
Host smart-86df0dd3-acc6-4114-89be-0f1478ce3d89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41076834867122674005209344390924928037198562516821546784242880326617208111146 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.41076834867122674005209344390924928037198562516821546784242880326617208111146
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.108585879890942967653849109386649387548380623835853722684734460753932613803881
Short name T436
Test name
Test status
Simulation time 209242141 ps
CPU time 105.67 seconds
Started Nov 22 01:21:52 PM PST 23
Finished Nov 22 01:23:44 PM PST 23
Peak memory 351256 kb
Host smart-be9736ff-8888-42ee-b3ca-bd7bf94b24fb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085858798909429676538491093866493875483806238358537226
84734460753932613803881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_max_throughput.1085858798909429676538491093866493
87548380623835853722684734460753932613803881
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.70843986896915916673619192395212100323634065015669960483527906280131480247400
Short name T278
Test name
Test status
Simulation time 166171057 ps
CPU time 3.04 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 01:22:10 PM PST 23
Peak memory 215724 kb
Host smart-25745514-d2cc-4740-b176-fce640b1cb76
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70843986896915916673619192395212100323634065015669960483527906280131
480247400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.708439868969159166736191923952121003236340650156
69960483527906280131480247400
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.92057940945574498015172537531544081655176744745358545207246189222079919368893
Short name T1026
Test name
Test status
Simulation time 590810517 ps
CPU time 5.3 seconds
Started Nov 22 01:22:49 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 202180 kb
Host smart-e102bc29-59fa-40ba-9178-f5a817a1182f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92057940945574498015172537531544081655176744745358545207246189222079919368893
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.92057940945574498015172537531544081655176744745358545207246189222079919368893
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.73767337934092775718752454216162975260471607964634597498538906787653042094918
Short name T666
Test name
Test status
Simulation time 21947461091 ps
CPU time 881.9 seconds
Started Nov 22 01:21:47 PM PST 23
Finished Nov 22 01:36:35 PM PST 23
Peak memory 371296 kb
Host smart-38bae8a5-3ae0-436a-b8ed-47aee334a01c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73767337934092775718752454216162975260471607964634597498538906787653042094918 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.73767337934092775718752454216162975260471607964634597498538906787653042094918
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.12354287966296133732925938993310635151362968892417953147655342391310153576304
Short name T748
Test name
Test status
Simulation time 445204539 ps
CPU time 11.14 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:22:02 PM PST 23
Peak memory 246568 kb
Host smart-2e2ad451-fe0e-4080-bc58-8626effbfe82
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123542879662961337329259389933106351513629688924179531476553423913101
53576304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.123542879662961337329259389933106351513629688924179531
47655342391310153576304
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.38911795029532664793361650179383120055424379261461432949663163640164016994897
Short name T93
Test name
Test status
Simulation time 42305619653 ps
CPU time 535.28 seconds
Started Nov 22 01:21:38 PM PST 23
Finished Nov 22 01:30:41 PM PST 23
Peak memory 202716 kb
Host smart-6ad9bdf6-29f9-455a-a9ce-dd485080de21
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389117950295326647933616501793831200554243792614614329496631636401640
16994897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access_b2b.3891179502953266479336165017938312005542
4379261461432949663163640164016994897
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.101964114374607823675480393261376739251172461384729754663772049843064148775899
Short name T912
Test name
Test status
Simulation time 40672061 ps
CPU time 0.84 seconds
Started Nov 22 01:21:40 PM PST 23
Finished Nov 22 01:21:47 PM PST 23
Peak memory 202616 kb
Host smart-748c028c-2313-4cf3-aa5c-c403c663b791
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101964114374607823675480393261376739251172461384729754663772049843064148775899 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.101964114374607823675480393261376739251172461384729754663772049843064148775899
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.72994366006509465993318891549357510486188456932232867133699311172959014876683
Short name T1007
Test name
Test status
Simulation time 19383553031 ps
CPU time 553.52 seconds
Started Nov 22 01:21:47 PM PST 23
Finished Nov 22 01:31:06 PM PST 23
Peak memory 370976 kb
Host smart-6af6b337-fded-4fc0-a07d-c8dd3d27a32d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72994366006509465993318891549357510486188456932232867133699311172959014876683 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.72994366006509465993318891549357510486188456932232867133699311172959014876683
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.114517560193747830872824350199539694834347346766866417795547220869858962520261
Short name T915
Test name
Test status
Simulation time 427865392 ps
CPU time 10.01 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 246412 kb
Host smart-177e2588-e8e9-4f36-b6fa-8a2549140da4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114517560193747830872824350199539694834347346766866417795547220869858962520261 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.114517560193747830872824350199539694834347346766866417795547220869858962520261
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.101287602045850688823431423951813950846039706634087281946204558051168783264883
Short name T563
Test name
Test status
Simulation time 121463254244 ps
CPU time 2973.96 seconds
Started Nov 22 01:22:48 PM PST 23
Finished Nov 22 02:12:36 PM PST 23
Peak memory 375068 kb
Host smart-8e74fd84-6925-4ec7-942b-a53ec564fa0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101287602045850688823431423951813950846039706634087281946204558
051168783264883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.1012876020458506888234314239518139508460397066
34087281946204558051168783264883
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.394108886655264563839910541711247020109034715106605004660392877300166304482
Short name T442
Test name
Test status
Simulation time 624328106 ps
CPU time 1121.52 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:40:44 PM PST 23
Peak memory 401728 kb
Host smart-20595240-9790-4e19-af45-5f9a234aeb4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=394108886655264563839910541711247020109034715106605004660392877300166304482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_
SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram
_ctrl_stress_all_with_rand_reset.394108886655264563839910541711247020109034715106605004660392877300166304482
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.92284802697577301389095709666097279891228093489062043474358990207884189823467
Short name T734
Test name
Test status
Simulation time 6491370455 ps
CPU time 359.95 seconds
Started Nov 22 01:21:47 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 202668 kb
Host smart-31c52869-a94b-47b4-b9bb-9b4e1c918efa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92284802697577301389095709666097279891228093489062043474358990207884189823467
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.922848026975773013890957096660972798912280934890620
43474358990207884189823467
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.7085468572106307587970087018408426773240761767889266961049037800559352489796
Short name T69
Test name
Test status
Simulation time 237420487 ps
CPU time 92.97 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:23:10 PM PST 23
Peak memory 351296 kb
Host smart-ac669b52-325e-4b2b-9591-18093aa46b1e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708546857210630758797008701840842677324076176788926696
1049037800559352489796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.70854685721063075879700
87018408426773240761767889266961049037800559352489796
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.65572548638653306316950012114939424836467340530122502906236211890345331850540
Short name T670
Test name
Test status
Simulation time 4471404472 ps
CPU time 743.05 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:34:14 PM PST 23
Peak memory 375336 kb
Host smart-b290af5d-8272-4146-8daa-541834b1210a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65572548638653306316950012114939424836467340530122502906236211890345331850540
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during_key_req.655725486386533063169500121149394248364
67340530122502906236211890345331850540
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.41564026927933519347433138053643931858412032159462014946602413157369915214364
Short name T548
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:22:00 PM PST 23
Peak memory 202184 kb
Host smart-496c1215-1508-404e-ba35-b200e92e3249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415640269279335193474331380536439318584120321594620149466024131573
69915214364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.415640269279335193474331380536439318584120321594620149
46602413157369915214364
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.50038686750229537124527131593666672173483921414089449194579557413186881091348
Short name T323
Test name
Test status
Simulation time 9249473390 ps
CPU time 81.28 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 202496 kb
Host smart-7b3eb6e5-ceae-4e93-b4d4-fe87d11cc319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50038686750229537124527131593666672173483921414089449194579557413186881091348 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.50038686750229537124527131593666672173483921414089449194579557413186881091348
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.91575050799390135557249665496349166810490958723916188809187726150568905293838
Short name T905
Test name
Test status
Simulation time 23162112088 ps
CPU time 685.81 seconds
Started Nov 22 01:21:55 PM PST 23
Finished Nov 22 01:33:27 PM PST 23
Peak memory 364584 kb
Host smart-cd526ef3-e015-47de-b11e-b5d7269b0710
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91575050799390135557249665496349166810490958723916188809187726150568905293838 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.91575050799390135557249665496349166810490958723916188809187726150568905293838
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.62071036621695895190201306694704766830790414009149291717504924799124282130050
Short name T883
Test name
Test status
Simulation time 985753786 ps
CPU time 7.45 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:23:15 PM PST 23
Peak memory 213104 kb
Host smart-757fa462-0199-409a-a215-9d817d4edfae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62071036621695895190201306694704766830790414009149291717504924799124282130050 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.62071036621695895190201306694704766830790414009149291717504924799124282130050
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.95845152773911888495191930291709149548090954053370264464952856854275104688868
Short name T658
Test name
Test status
Simulation time 209242141 ps
CPU time 77.33 seconds
Started Nov 22 01:22:02 PM PST 23
Finished Nov 22 01:23:25 PM PST 23
Peak memory 351332 kb
Host smart-1f0bc0a2-f177-4749-8b78-7019458e5313
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9584515277391188849519193029170914954809095405337026446
4952856854275104688868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_max_throughput.95845152773911888495191930291709149
548090954053370264464952856854275104688868
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.100536932845631692405587559369055264153803457635814978867039995448939158875404
Short name T776
Test name
Test status
Simulation time 166171057 ps
CPU time 3.13 seconds
Started Nov 22 01:22:50 PM PST 23
Finished Nov 22 01:23:07 PM PST 23
Peak memory 215656 kb
Host smart-02aba0ea-ee44-4dd6-bd26-9bdbf669f475
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10053693284563169240558755936905526415380345763581497886703999544893
9158875404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.10053693284563169240558755936905526415380345763
5814978867039995448939158875404
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.40765324927558144750933252607269737647302258551792824299826256812744053974339
Short name T595
Test name
Test status
Simulation time 590810517 ps
CPU time 5.46 seconds
Started Nov 22 01:22:04 PM PST 23
Finished Nov 22 01:22:15 PM PST 23
Peak memory 202592 kb
Host smart-c0a4430c-dd27-4a11-9ada-b93678354709
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40765324927558144750933252607269737647302258551792824299826256812744053974339
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.40765324927558144750933252607269737647302258551792824299826256812744053974339
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.29184151703745639376592776102856749591780519957317193535951014331812116616476
Short name T355
Test name
Test status
Simulation time 21947461091 ps
CPU time 839.96 seconds
Started Nov 22 01:21:58 PM PST 23
Finished Nov 22 01:36:04 PM PST 23
Peak memory 371348 kb
Host smart-06020918-e475-45aa-82e8-ca41023fde71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29184151703745639376592776102856749591780519957317193535951014331812116616476 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.29184151703745639376592776102856749591780519957317193535951014331812116616476
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.41288863882074972327144900746153597300043765820904028584399618951074650836591
Short name T683
Test name
Test status
Simulation time 445204539 ps
CPU time 14.52 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 01:22:21 PM PST 23
Peak memory 246520 kb
Host smart-9808e951-377d-4feb-a6ae-e8c0fcb7cb81
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412888638820749723271449007461535973000437658209040285843996189510746
50836591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.412888638820749723271449007461535973000437658209040285
84399618951074650836591
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.97663489366829331861784367953798855649744643661220400831923281639289676752962
Short name T312
Test name
Test status
Simulation time 42305619653 ps
CPU time 551 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:31:14 PM PST 23
Peak memory 202728 kb
Host smart-cf320a5a-f047-4a33-a963-47909b171c86
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976634893668293318617843679537988556497446436612204008319232816392896
76752962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access_b2b.9766348936682933186178436795379885564974
4643661220400831923281639289676752962
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.6191388656602179445076446254801906373734248297513072467940461902162091655621
Short name T309
Test name
Test status
Simulation time 40672061 ps
CPU time 0.83 seconds
Started Nov 22 01:22:07 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 202628 kb
Host smart-ec8b8491-1a19-4a3e-b8da-e3556f0ab251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6191388656602179445076446254801906373734248297513072467940461902162091655621 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.6191388656602179445076446254801906373734248297513072467940461902162091655621
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.18286737136245666413712220071252248642946165754415425176302924974988174796589
Short name T535
Test name
Test status
Simulation time 19383553031 ps
CPU time 487.63 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:30:33 PM PST 23
Peak memory 371856 kb
Host smart-59c3f564-027e-4077-bb46-742bef27a09d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18286737136245666413712220071252248642946165754415425176302924974988174796589 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.18286737136245666413712220071252248642946165754415425176302924974988174796589
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.47872642094625117982458851826668886198942304430708508486649350521257839327880
Short name T976
Test name
Test status
Simulation time 427865392 ps
CPU time 9.45 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:22:59 PM PST 23
Peak memory 245416 kb
Host smart-a4df8383-0d70-4c99-b59b-e3562ef9017d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47872642094625117982458851826668886198942304430708508486649350521257839327880 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.47872642094625117982458851826668886198942304430708508486649350521257839327880
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.25864859139772063132160036128970448861492219336427027017892718521186888490647
Short name T413
Test name
Test status
Simulation time 121463254244 ps
CPU time 2848.99 seconds
Started Nov 22 01:22:02 PM PST 23
Finished Nov 22 02:09:37 PM PST 23
Peak memory 375264 kb
Host smart-8341e1fa-74b4-46b0-a7d6-2628b38571b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258648591397720631321600361289704488614922193364270270178927185
21186888490647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.25864859139772063132160036128970448861492219336
427027017892718521186888490647
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.109448178781807594974700921784520452032221007628891670062208206883960142715225
Short name T779
Test name
Test status
Simulation time 624328106 ps
CPU time 1015.74 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:38:51 PM PST 23
Peak memory 401692 kb
Host smart-1e38239f-989c-433e-86d0-e8a9b82bdb2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=109448178781807594974700921784520452032221007628891670062208206883960142715225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.s
ram_ctrl_stress_all_with_rand_reset.109448178781807594974700921784520452032221007628891670062208206883960142715225
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.110497778170917441657276488549948018703895273929777106595607362586271361461311
Short name T849
Test name
Test status
Simulation time 6491370455 ps
CPU time 358.76 seconds
Started Nov 22 01:22:03 PM PST 23
Finished Nov 22 01:28:07 PM PST 23
Peak memory 202496 kb
Host smart-2f7d82e7-bd39-4059-af69-13ec4743b96b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11049777817091744165727648854994801870389527392977710659560736258627136146131
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.11049777817091744165727648854994801870389527392977
7106595607362586271361461311
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.74961015367579663032371719452050356279523567233570566776407612386285501567382
Short name T500
Test name
Test status
Simulation time 237420487 ps
CPU time 96.26 seconds
Started Nov 22 01:22:13 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 351184 kb
Host smart-3d636b81-47e8-4abd-aeb4-d85f6f70ced5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749610153675796630323717194520503562795235672335705667
76407612386285501567382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.7496101536757966303237
1719452050356279523567233570566776407612386285501567382
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.23550842518040113039248439450659965561777587950688524374295423142254762646284
Short name T568
Test name
Test status
Simulation time 4471404472 ps
CPU time 618.87 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:32:09 PM PST 23
Peak memory 375500 kb
Host smart-b111435d-412f-4f18-a154-786d08da8eb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23550842518040113039248439450659965561777587950688524374295423142254762646284
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during_key_req.235508425180401130392484394506599655617
77587950688524374295423142254762646284
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.115748097112794557432921841725862711577207794312791853585244987648468402611961
Short name T992
Test name
Test status
Simulation time 16600825 ps
CPU time 0.66 seconds
Started Nov 22 01:22:26 PM PST 23
Finished Nov 22 01:22:32 PM PST 23
Peak memory 202104 kb
Host smart-a1e76c48-24ac-4a29-bec6-4a686d0e9aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115748097112794557432921841725862711577207794312791853585244987648
468402611961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.11574809711279455743292184172586271157720779431279185
3585244987648468402611961
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.9728140080238061126875884068275791666014629565111995224045911103306107003528
Short name T839
Test name
Test status
Simulation time 9249473390 ps
CPU time 80.21 seconds
Started Nov 22 01:21:46 PM PST 23
Finished Nov 22 01:23:12 PM PST 23
Peak memory 202616 kb
Host smart-498b1dd4-5ca1-4154-b951-d491963502b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9728140080238061126875884068275791666014629565111995224045911103306107003528 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.9728140080238061126875884068275791666014629565111995224045911103306107003528
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.26144618633198586054224793750577464067636892670124073921583915663779136208157
Short name T589
Test name
Test status
Simulation time 23162112088 ps
CPU time 719.54 seconds
Started Nov 22 01:21:46 PM PST 23
Finished Nov 22 01:33:51 PM PST 23
Peak memory 364644 kb
Host smart-0da49b37-334e-4b7a-901e-bc0d5fb1e897
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26144618633198586054224793750577464067636892670124073921583915663779136208157 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.26144618633198586054224793750577464067636892670124073921583915663779136208157
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.115394247350098383292459935575650323598580321063537324586942268521645826163053
Short name T598
Test name
Test status
Simulation time 985753786 ps
CPU time 7.1 seconds
Started Nov 22 01:21:36 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 213092 kb
Host smart-632063dd-00ed-4fbb-8ead-1250401f2333
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115394247350098383292459935575650323598580321063537324586942268521645826163053 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.115394247350098383292459935575650323598580321063537324586942268521645826163053
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.20198148913107495986476585031709840596628897990089825525220545557799700729409
Short name T318
Test name
Test status
Simulation time 209242141 ps
CPU time 111.01 seconds
Started Nov 22 01:21:37 PM PST 23
Finished Nov 22 01:23:36 PM PST 23
Peak memory 351368 kb
Host smart-e4ca1288-b16e-467a-9492-1aa386639a6d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019814891310749598647658503170984059662889799008982552
5220545557799700729409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_max_throughput.20198148913107495986476585031709840
596628897990089825525220545557799700729409
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.16923095561621497078946918929918179465177402839688722066446213042694922805864
Short name T621
Test name
Test status
Simulation time 166171057 ps
CPU time 2.97 seconds
Started Nov 22 01:21:35 PM PST 23
Finished Nov 22 01:21:47 PM PST 23
Peak memory 215724 kb
Host smart-67ddd498-11ed-400f-af65-85363ae90512
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16923095561621497078946918929918179465177402839688722066446213042694
922805864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.169230955616214970789469189299181794651774028396
88722066446213042694922805864
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.59201025641653762648010064969138126861918541232015463078891931931880336085297
Short name T281
Test name
Test status
Simulation time 590810517 ps
CPU time 5.83 seconds
Started Nov 22 01:21:43 PM PST 23
Finished Nov 22 01:21:54 PM PST 23
Peak memory 202616 kb
Host smart-850ba275-1ecf-4f7e-aa8b-3a8f52781bfa
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59201025641653762648010064969138126861918541232015463078891931931880336085297
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.59201025641653762648010064969138126861918541232015463078891931931880336085297
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.81494504121456117192905829003175215915444263994496856060528853521568059949528
Short name T134
Test name
Test status
Simulation time 21947461091 ps
CPU time 901.22 seconds
Started Nov 22 01:21:39 PM PST 23
Finished Nov 22 01:36:47 PM PST 23
Peak memory 371380 kb
Host smart-4dfb996e-c006-43c9-bb3c-24f07fcb0b1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81494504121456117192905829003175215915444263994496856060528853521568059949528 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.81494504121456117192905829003175215915444263994496856060528853521568059949528
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.41030970525511755788505205098364390573955946369915514416586547203104892354729
Short name T601
Test name
Test status
Simulation time 445204539 ps
CPU time 11.43 seconds
Started Nov 22 01:21:35 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 246580 kb
Host smart-e9275f25-a283-4c15-b352-f12a13d303b7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410309705255117557885052050983643905739559463699155144165865472031048
92354729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.410309705255117557885052050983643905739559463699155144
16586547203104892354729
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3420903167008046249130934732423653252658937877092644614278626837936135512139
Short name T1032
Test name
Test status
Simulation time 42305619653 ps
CPU time 552.43 seconds
Started Nov 22 01:22:15 PM PST 23
Finished Nov 22 01:31:30 PM PST 23
Peak memory 202576 kb
Host smart-fe0d47cb-43a6-4fa6-b442-eefcf6af7b9d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342090316700804624913093473242365325265893787709264461427862683793613
5512139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access_b2b.34209031670080462491309347324236532526589
37877092644614278626837936135512139
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.51059367189292262110108058086184725852909759341371879776505211686023955429239
Short name T832
Test name
Test status
Simulation time 40672061 ps
CPU time 0.81 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 202560 kb
Host smart-73ad965c-9f06-4351-ac5f-0f52901c8858
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51059367189292262110108058086184725852909759341371879776505211686023955429239 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.51059367189292262110108058086184725852909759341371879776505211686023955429239
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.3614202651724422734375150310462886266211124796180954746934055572987097650298
Short name T668
Test name
Test status
Simulation time 19383553031 ps
CPU time 596.41 seconds
Started Nov 22 01:21:58 PM PST 23
Finished Nov 22 01:32:00 PM PST 23
Peak memory 371616 kb
Host smart-fc23f46d-71e3-49da-9ab0-9c521aefa5e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614202651724422734375150310462886266211124796180954746934055572987097650298 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3614202651724422734375150310462886266211124796180954746934055572987097650298
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.68262733975029780565802827467722933627238992004573215392786554364996392440404
Short name T395
Test name
Test status
Simulation time 427865392 ps
CPU time 10.74 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:22:01 PM PST 23
Peak memory 246596 kb
Host smart-8b691249-081c-4184-ac67-54096e8f0907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68262733975029780565802827467722933627238992004573215392786554364996392440404 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.68262733975029780565802827467722933627238992004573215392786554364996392440404
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.108055151186544684042541479581795616737494031175339431523933930313292878046950
Short name T426
Test name
Test status
Simulation time 121463254244 ps
CPU time 3019.52 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 02:12:55 PM PST 23
Peak memory 375328 kb
Host smart-cb81ad33-607a-4f3d-8261-918d5c57bb43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108055151186544684042541479581795616737494031175339431523933930
313292878046950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.1080551511865446840425414795817956167374940311
75339431523933930313292878046950
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.32545732069695554145920612679857925875279604761319881951500406934579601821327
Short name T300
Test name
Test status
Simulation time 624328106 ps
CPU time 1359.19 seconds
Started Nov 22 01:21:40 PM PST 23
Finished Nov 22 01:44:26 PM PST 23
Peak memory 401828 kb
Host smart-6acd8d34-5d85-4bc7-a270-2c0f16ee6be0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=32545732069695554145920612679857925875279604761319881951500406934579601821327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sr
am_ctrl_stress_all_with_rand_reset.32545732069695554145920612679857925875279604761319881951500406934579601821327
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.99527174854215018202017088810251513551035366661808562179564156265018391351732
Short name T644
Test name
Test status
Simulation time 6491370455 ps
CPU time 353.25 seconds
Started Nov 22 01:21:39 PM PST 23
Finished Nov 22 01:27:39 PM PST 23
Peak memory 202668 kb
Host smart-dc4a08b3-b718-4394-94ce-d427107b76b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99527174854215018202017088810251513551035366661808562179564156265018391351732
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.995271748542150182020170888102515135510353666618085
62179564156265018391351732
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.71476032282298857630388016945555846955470153435068769060796972101694587750392
Short name T757
Test name
Test status
Simulation time 237420487 ps
CPU time 101.81 seconds
Started Nov 22 01:21:38 PM PST 23
Finished Nov 22 01:23:27 PM PST 23
Peak memory 351368 kb
Host smart-00ecf826-0a50-4224-ab4f-ad474cb8165a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714760322822988576303880169455558469554701534350687690
60796972101694587750392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.7147603228229885763038
8016945555846955470153435068769060796972101694587750392
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.78731589042752078815323364747295896677998032055850025483742077052957655731254
Short name T513
Test name
Test status
Simulation time 4471404472 ps
CPU time 686.46 seconds
Started Nov 22 01:21:46 PM PST 23
Finished Nov 22 01:33:18 PM PST 23
Peak memory 375412 kb
Host smart-d355e259-daca-49e9-b032-e0124d1ca60f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78731589042752078815323364747295896677998032055850025483742077052957655731254
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during_key_req.787315890427520788153233647472958966779
98032055850025483742077052957655731254
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.51788294147936980998851524000119956578374809612948511374039148538705787426953
Short name T864
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:21:48 PM PST 23
Finished Nov 22 01:21:54 PM PST 23
Peak memory 202200 kb
Host smart-acad8087-1e8c-47a8-8dea-a5b6ce62c8da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517882941479369809988515240001199565783748096129485113740391485387
05787426953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.517882941479369809988515240001199565783748096129485113
74039148538705787426953
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.96353594786783526303627679987569574547116864642572552865166765731803603594050
Short name T913
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.52 seconds
Started Nov 22 01:21:39 PM PST 23
Finished Nov 22 01:23:10 PM PST 23
Peak memory 202632 kb
Host smart-54bd6e18-870d-4b1a-9f5b-92481cdcb8d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96353594786783526303627679987569574547116864642572552865166765731803603594050 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.96353594786783526303627679987569574547116864642572552865166765731803603594050
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.15419834223867358337495901979218048238569654910169746686718116369555421288059
Short name T360
Test name
Test status
Simulation time 23162112088 ps
CPU time 751.38 seconds
Started Nov 22 01:22:46 PM PST 23
Finished Nov 22 01:35:30 PM PST 23
Peak memory 364676 kb
Host smart-30428785-675c-4433-ab8f-44d7b2d850f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15419834223867358337495901979218048238569654910169746686718116369555421288059 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.15419834223867358337495901979218048238569654910169746686718116369555421288059
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.52474413591430268079992298837689666487812619830607654715809131452477542321112
Short name T1035
Test name
Test status
Simulation time 985753786 ps
CPU time 7.44 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:22:36 PM PST 23
Peak memory 213216 kb
Host smart-4f28f7aa-9224-479e-9be7-eb6b5a53d515
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52474413591430268079992298837689666487812619830607654715809131452477542321112 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.52474413591430268079992298837689666487812619830607654715809131452477542321112
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.102676048895807797360642450420715112242212212011129938853182037233537985400418
Short name T1034
Test name
Test status
Simulation time 209242141 ps
CPU time 102.64 seconds
Started Nov 22 01:22:08 PM PST 23
Finished Nov 22 01:23:54 PM PST 23
Peak memory 351232 kb
Host smart-970e6c0f-0961-4c74-8c16-2ce755c2af31
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026760488958077973606424504207151122422122120111299388
53182037233537985400418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_max_throughput.1026760488958077973606424504207151
12242212212011129938853182037233537985400418
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.62547208545546264182742007887346715613419373262151750855250337158766044156
Short name T381
Test name
Test status
Simulation time 166171057 ps
CPU time 2.9 seconds
Started Nov 22 01:21:56 PM PST 23
Finished Nov 22 01:22:05 PM PST 23
Peak memory 215628 kb
Host smart-fef634c9-928d-4b83-a48f-f28eab5fe5ef
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62547208545546264182742007887346715613419373262151750855250337158766
044156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.625472085455462641827420078873467156134193732621517
50855250337158766044156
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.55510460954328258621492647125175573645004459613774595269528502750048232113452
Short name T521
Test name
Test status
Simulation time 590810517 ps
CPU time 5.63 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:22:04 PM PST 23
Peak memory 202500 kb
Host smart-f305ca80-1644-4c1b-8f6e-98636fc6c513
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55510460954328258621492647125175573645004459613774595269528502750048232113452
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.55510460954328258621492647125175573645004459613774595269528502750048232113452
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.61789951420248180503814899596344337014834025558107815322045129422247170283698
Short name T2
Test name
Test status
Simulation time 21947461091 ps
CPU time 834.83 seconds
Started Nov 22 01:22:04 PM PST 23
Finished Nov 22 01:36:04 PM PST 23
Peak memory 371220 kb
Host smart-54f62167-cbec-460d-a48e-138ee7a372e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61789951420248180503814899596344337014834025558107815322045129422247170283698 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.61789951420248180503814899596344337014834025558107815322045129422247170283698
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.26300940395071985988576441121084486297571050263525888165540225036977702463774
Short name T599
Test name
Test status
Simulation time 445204539 ps
CPU time 13.96 seconds
Started Nov 22 01:21:54 PM PST 23
Finished Nov 22 01:22:14 PM PST 23
Peak memory 246532 kb
Host smart-fd75ef9a-a0cb-47e8-b4fe-c73b685cf5d5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263009403950719859885764411210844862975710502635258881655402250369777
02463774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.263009403950719859885764411210844862975710502635258881
65540225036977702463774
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.46997020474322374877447972280918510062712098529169811757035658126175299952273
Short name T874
Test name
Test status
Simulation time 42305619653 ps
CPU time 530.59 seconds
Started Nov 22 01:21:36 PM PST 23
Finished Nov 22 01:30:35 PM PST 23
Peak memory 202548 kb
Host smart-2dda486a-2f73-46bf-a67a-0a9617bd41ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469970204743223748774479722809185100627120985291698117570356581261752
99952273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access_b2b.4699702047432237487744797228091851006271
2098529169811757035658126175299952273
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.59552647376619705122685392823707360179197178579893463325515741461946964900892
Short name T34
Test name
Test status
Simulation time 40672061 ps
CPU time 0.82 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:21:59 PM PST 23
Peak memory 202604 kb
Host smart-31461a01-568b-4153-8512-874c090f6ba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59552647376619705122685392823707360179197178579893463325515741461946964900892 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.59552647376619705122685392823707360179197178579893463325515741461946964900892
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.35928090958571562955030502953902969685359870896075656167110712625282902089325
Short name T386
Test name
Test status
Simulation time 19383553031 ps
CPU time 577.2 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 01:32:13 PM PST 23
Peak memory 371684 kb
Host smart-0a5da349-eebc-4461-a493-8fde5d8a1974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35928090958571562955030502953902969685359870896075656167110712625282902089325 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.35928090958571562955030502953902969685359870896075656167110712625282902089325
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.8316601590486891411299887368415991551150083182271299650702418126619021078654
Short name T510
Test name
Test status
Simulation time 427865392 ps
CPU time 11.53 seconds
Started Nov 22 01:21:44 PM PST 23
Finished Nov 22 01:22:00 PM PST 23
Peak memory 246596 kb
Host smart-005c395e-43a1-43fa-a78d-9af158787e5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8316601590486891411299887368415991551150083182271299650702418126619021078654 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.8316601590486891411299887368415991551150083182271299650702418126619021078654
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.85678672079212412004273863052183140880560789971700401061832014566059755096708
Short name T43
Test name
Test status
Simulation time 121463254244 ps
CPU time 3077.72 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 02:13:24 PM PST 23
Peak memory 373836 kb
Host smart-623b690a-3f34-4b4d-91a7-6725446a56f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856786720792124120042738630521831408805607899717004010618320145
66059755096708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.85678672079212412004273863052183140880560789971
700401061832014566059755096708
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.10846161846055321170062633115153549547081931061567017687853609807646967961407
Short name T922
Test name
Test status
Simulation time 624328106 ps
CPU time 1202.03 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:41:57 PM PST 23
Peak memory 401708 kb
Host smart-b46eb566-00cb-41fe-baaf-fd781fef459c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=10846161846055321170062633115153549547081931061567017687853609807646967961407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sr
am_ctrl_stress_all_with_rand_reset.10846161846055321170062633115153549547081931061567017687853609807646967961407
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.46408165431337003949849655362289382907890986544315483541562598662705761048019
Short name T628
Test name
Test status
Simulation time 6491370455 ps
CPU time 358.92 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 202704 kb
Host smart-c9f3d1c5-1704-4132-99b5-c5f97e08458f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46408165431337003949849655362289382907890986544315483541562598662705761048019
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.464081654313370039498496553622893829078909865443154
83541562598662705761048019
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.100004758865317015440791377602550780221685082074805937629889746180717376239421
Short name T131
Test name
Test status
Simulation time 237420487 ps
CPU time 89.48 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:23:20 PM PST 23
Peak memory 351400 kb
Host smart-b3803a35-9e4c-4547-bb0c-01d7d454c177
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100004758865317015440791377602550780221685082074805937
629889746180717376239421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.100004758865317015440
791377602550780221685082074805937629889746180717376239421
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.72351756966655140523783188537745026609092249271091996777488592491633421297252
Short name T835
Test name
Test status
Simulation time 4471404472 ps
CPU time 850.42 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:36:36 PM PST 23
Peak memory 375484 kb
Host smart-e9256bf9-a028-4bf2-9abe-edd3811ea30d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72351756966655140523783188537745026609092249271091996777488592491633421297252
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_key_req.7235175696665514052378318853774502660909
2249271091996777488592491633421297252
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.62653208073682573185892534357099773147630468185354882140386442747943171200266
Short name T899
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:20:54 PM PST 23
Finished Nov 22 01:20:59 PM PST 23
Peak memory 202080 kb
Host smart-9f6efa9f-f90c-4ccf-a450-52ac17190e6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626532080736825731858925343570997731476304681853548821403864427479
43171200266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.6265320807368257318589253435709977314763046818535488214
0386442747943171200266
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.90757663485290541801335396896659039584571858243545434999286021560389526895398
Short name T724
Test name
Test status
Simulation time 9249473390 ps
CPU time 79.42 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:22:58 PM PST 23
Peak memory 202484 kb
Host smart-e7c60b0f-3dc6-4903-a16c-c3107a5fa340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90757663485290541801335396896659039584571858243545434999286021560389526895398 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.90757663485290541801335396896659039584571858243545434999286021560389526895398
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.94793268114377114657518359847755171276732431238019939971879531755434666279014
Short name T797
Test name
Test status
Simulation time 23162112088 ps
CPU time 734.63 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:34:10 PM PST 23
Peak memory 364632 kb
Host smart-ed17c4cf-56b7-4415-bf71-e2d976a600e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94793268114377114657518359847755171276732431238019939971879531755434666279014 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.94793268114377114657518359847755171276732431238019939971879531755434666279014
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.82952622582655739324410474817945075906226515194210661551792286223297883088862
Short name T850
Test name
Test status
Simulation time 985753786 ps
CPU time 7.06 seconds
Started Nov 22 01:22:21 PM PST 23
Finished Nov 22 01:22:30 PM PST 23
Peak memory 213216 kb
Host smart-59c8f608-2a92-491d-8bc0-b323fdc5152c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82952622582655739324410474817945075906226515194210661551792286223297883088862 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.82952622582655739324410474817945075906226515194210661551792286223297883088862
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.98085324003626337686912353884013499418741928881907064694724611455954112715930
Short name T736
Test name
Test status
Simulation time 209242141 ps
CPU time 84.85 seconds
Started Nov 22 01:21:34 PM PST 23
Finished Nov 22 01:23:07 PM PST 23
Peak memory 351168 kb
Host smart-1e1c2d3c-35ad-49e2-b5e1-27fb8a4f7cc1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9808532400362633768691235388401349941874192888190706469
4724611455954112715930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max_throughput.980853240036263376869123538840134994
18741928881907064694724611455954112715930
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.58737502949079809769615277474357179721309505965864261613456690858168679357342
Short name T564
Test name
Test status
Simulation time 166171057 ps
CPU time 3.06 seconds
Started Nov 22 01:21:16 PM PST 23
Finished Nov 22 01:21:20 PM PST 23
Peak memory 215544 kb
Host smart-6c0ed423-41f4-45f7-9496-86a773f1d17c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58737502949079809769615277474357179721309505965864261613456690858168
679357342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.5873750294907980976961527747435717972130950596586
4261613456690858168679357342
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.35329958257491795212175862471460019540777118895629742546725769184107733283616
Short name T401
Test name
Test status
Simulation time 590810517 ps
CPU time 5.65 seconds
Started Nov 22 01:21:07 PM PST 23
Finished Nov 22 01:21:14 PM PST 23
Peak memory 202604 kb
Host smart-bd95e9f7-9c8d-4526-9d0a-282e7ebb1862
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35329958257491795212175862471460019540777118895629742546725769184107733283616
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.35329958257491795212175862471460019540777118895629742546725769184107733283616
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.83870478963435254945146231065335145747533587703130294166425729671604750272598
Short name T557
Test name
Test status
Simulation time 21947461091 ps
CPU time 886.44 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:36:25 PM PST 23
Peak memory 371364 kb
Host smart-661ea6e4-df15-45df-9b84-d5638d8716fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83870478963435254945146231065335145747533587703130294166425729671604750272598 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.83870478963435254945146231065335145747533587703130294166425729671604750272598
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.13842986444399713122539428047059097028572823730783521025580623920329520652865
Short name T411
Test name
Test status
Simulation time 445204539 ps
CPU time 11.34 seconds
Started Nov 22 01:21:17 PM PST 23
Finished Nov 22 01:21:30 PM PST 23
Peak memory 246388 kb
Host smart-83779da2-5153-49be-868b-2da32b53ccd4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138429864443997131225394280470590970285728237307835210255806239203295
20652865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.1384298644439971312253942804705909702857282373078352102
5580623920329520652865
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.9187533895604004838098505881131094625513989162640490661888475263113836849677
Short name T469
Test name
Test status
Simulation time 42305619653 ps
CPU time 538.86 seconds
Started Nov 22 01:21:56 PM PST 23
Finished Nov 22 01:31:00 PM PST 23
Peak memory 202680 kb
Host smart-b851e8fa-0430-4975-bf05-5aa72af140c0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918753389560400483809850588113109462551398916264049066188847526311383
6849677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access_b2b.918753389560400483809850588113109462551398
9162640490661888475263113836849677
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.35766321607381949150757208891947718857800376017880257008384330730536773031083
Short name T252
Test name
Test status
Simulation time 40672061 ps
CPU time 0.81 seconds
Started Nov 22 01:21:17 PM PST 23
Finished Nov 22 01:21:19 PM PST 23
Peak memory 202616 kb
Host smart-b407182d-5c2f-4ded-9cc2-78d047ead862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35766321607381949150757208891947718857800376017880257008384330730536773031083 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.35766321607381949150757208891947718857800376017880257008384330730536773031083
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.46985623550464506111748495671937820300493045904389123124858722597770928726769
Short name T729
Test name
Test status
Simulation time 19383553031 ps
CPU time 581.56 seconds
Started Nov 22 01:21:12 PM PST 23
Finished Nov 22 01:30:55 PM PST 23
Peak memory 371724 kb
Host smart-5e6ab52c-12c8-46ab-94a6-a5094b186c5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46985623550464506111748495671937820300493045904389123124858722597770928726769 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.46985623550464506111748495671937820300493045904389123124858722597770928726769
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.78234893032765485781182879195705033659514577066937459000542609645314798573624
Short name T36
Test name
Test status
Simulation time 216402798 ps
CPU time 1.86 seconds
Started Nov 22 01:20:49 PM PST 23
Finished Nov 22 01:20:54 PM PST 23
Peak memory 220716 kb
Host smart-c405247a-1bae-4c72-92cf-a7dd619bff4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7823489303276548578118287919570503365951457706693745900054260964531
4798573624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.782348930327654857811828791957050336595145770669374590005426
09645314798573624
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.5276619532238468980862459131470326965737696341235931257528563046001057833271
Short name T137
Test name
Test status
Simulation time 427865392 ps
CPU time 11.52 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:22:06 PM PST 23
Peak memory 246532 kb
Host smart-ae728847-716d-49b9-9015-016bd9b07480
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5276619532238468980862459131470326965737696341235931257528563046001057833271 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.5276619532238468980862459131470326965737696341235931257528563046001057833271
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.15310263608153630895258250638502633789395170658816139124134620233555096077883
Short name T31
Test name
Test status
Simulation time 121463254244 ps
CPU time 3665.96 seconds
Started Nov 22 01:21:11 PM PST 23
Finished Nov 22 02:22:19 PM PST 23
Peak memory 375468 kb
Host smart-2b0a2528-e703-40ef-afd0-4fe035cded2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153102636081536308952582506385026337893951706588161391241346202
33555096077883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.153102636081536308952582506385026337893951706588
16139124134620233555096077883
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.29305148285215871147569547397229365741158251523821831803661037039247431935889
Short name T745
Test name
Test status
Simulation time 624328106 ps
CPU time 958.95 seconds
Started Nov 22 01:21:34 PM PST 23
Finished Nov 22 01:37:41 PM PST 23
Peak memory 401632 kb
Host smart-7c8edec2-9ca1-4c82-86dc-daac9097700f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=29305148285215871147569547397229365741158251523821831803661037039247431935889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sra
m_ctrl_stress_all_with_rand_reset.29305148285215871147569547397229365741158251523821831803661037039247431935889
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.51067229256599184505604681155853168134314733595496670260600485632475424859302
Short name T867
Test name
Test status
Simulation time 6491370455 ps
CPU time 354.64 seconds
Started Nov 22 01:21:10 PM PST 23
Finished Nov 22 01:27:07 PM PST 23
Peak memory 202616 kb
Host smart-78f8f2d5-ddb7-448c-9ceb-9c45f6d050c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51067229256599184505604681155853168134314733595496670260600485632475424859302
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.5106722925659918450560468115585316813431473359549667
0260600485632475424859302
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.104894917897399804860665354449160359313789471616081514404225247173192849627931
Short name T346
Test name
Test status
Simulation time 237420487 ps
CPU time 103.56 seconds
Started Nov 22 01:21:16 PM PST 23
Finished Nov 22 01:23:01 PM PST 23
Peak memory 351356 kb
Host smart-68e9bb64-848e-4f87-8abb-4da729f57fb9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104894917897399804860665354449160359313789471616081514
404225247173192849627931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1048949178973998048606
65354449160359313789471616081514404225247173192849627931
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.14582673230296905898051161416450768878203093757622752429164165915461624906986
Short name T840
Test name
Test status
Simulation time 4471404472 ps
CPU time 777.69 seconds
Started Nov 22 01:22:54 PM PST 23
Finished Nov 22 01:36:04 PM PST 23
Peak memory 375508 kb
Host smart-b640e30b-9ade-48ab-aa5a-da15fd0fb53c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14582673230296905898051161416450768878203093757622752429164165915461624906986
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during_key_req.145826732302969058980511614164507688782
03093757622752429164165915461624906986
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.71880384621748407562544915762371843102681347484233602601090319965484397853223
Short name T828
Test name
Test status
Simulation time 16600825 ps
CPU time 0.59 seconds
Started Nov 22 01:21:48 PM PST 23
Finished Nov 22 01:21:54 PM PST 23
Peak memory 202200 kb
Host smart-2be53b4e-cd41-4917-a4ca-cc9d49a14b75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718803846217484075625449157623718431026813474842336026010903199654
84397853223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.718803846217484075625449157623718431026813474842336026
01090319965484397853223
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.40946404032880063853591223213119516683556317921724456626203374205604966595370
Short name T536
Test name
Test status
Simulation time 9249473390 ps
CPU time 85.43 seconds
Started Nov 22 01:22:22 PM PST 23
Finished Nov 22 01:23:49 PM PST 23
Peak memory 202616 kb
Host smart-49ceefcd-5989-4ff3-a7f7-138db8ad5856
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40946404032880063853591223213119516683556317921724456626203374205604966595370 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.40946404032880063853591223213119516683556317921724456626203374205604966595370
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.5635154803531977303780983509346266963551223325958228365403067963182894380995
Short name T522
Test name
Test status
Simulation time 23162112088 ps
CPU time 738.75 seconds
Started Nov 22 01:21:59 PM PST 23
Finished Nov 22 01:34:23 PM PST 23
Peak memory 364640 kb
Host smart-fd6e6ed5-5577-430f-8c7f-1e9de670a272
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5635154803531977303780983509346266963551223325958228365403067963182894380995 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.5635154803531977303780983509346266963551223325958228365403067963182894380995
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.53904776118985137970736001636137440608364920014769311809502660083098389837554
Short name T935
Test name
Test status
Simulation time 985753786 ps
CPU time 7.1 seconds
Started Nov 22 01:21:43 PM PST 23
Finished Nov 22 01:21:55 PM PST 23
Peak memory 213204 kb
Host smart-df0580fe-ff2d-4357-9e49-aea8520e1b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53904776118985137970736001636137440608364920014769311809502660083098389837554 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.53904776118985137970736001636137440608364920014769311809502660083098389837554
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.81879563543607576421396466929131987140957218170135355006124319848321476545362
Short name T692
Test name
Test status
Simulation time 209242141 ps
CPU time 93.13 seconds
Started Nov 22 01:22:22 PM PST 23
Finished Nov 22 01:23:57 PM PST 23
Peak memory 351352 kb
Host smart-4562630d-ddc3-4256-a9df-3b2646299066
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8187956354360757642139646692913198714095721817013535500
6124319848321476545362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_max_throughput.81879563543607576421396466929131987
140957218170135355006124319848321476545362
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.22251018936695658722309689048376031784427711703137884692166855274226151905306
Short name T820
Test name
Test status
Simulation time 166171057 ps
CPU time 3.06 seconds
Started Nov 22 01:21:59 PM PST 23
Finished Nov 22 01:22:07 PM PST 23
Peak memory 215704 kb
Host smart-68edc223-f339-4633-91c0-6d15c042682f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22251018936695658722309689048376031784427711703137884692166855274226
151905306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.222510189366956587223096890483760317844277117031
37884692166855274226151905306
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.111720747883655502581594112230197452023152295797288537532160774457926873968395
Short name T118
Test name
Test status
Simulation time 590810517 ps
CPU time 5.51 seconds
Started Nov 22 01:23:05 PM PST 23
Finished Nov 22 01:23:21 PM PST 23
Peak memory 202504 kb
Host smart-815a8c50-8558-4fae-aaf8-c0223f6851f7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111720747883655502581594112230197452023152295797288537532160774457926873968395
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.111720747883655502581594112230197452023152295797288537532160774457926873968395
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.55965346759576978187713794508801670879012617291871930787451284328591529490578
Short name T987
Test name
Test status
Simulation time 21947461091 ps
CPU time 741.29 seconds
Started Nov 22 01:22:03 PM PST 23
Finished Nov 22 01:34:30 PM PST 23
Peak memory 371368 kb
Host smart-76f7aa11-5d9e-48fa-8648-a581522e29b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55965346759576978187713794508801670879012617291871930787451284328591529490578 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.55965346759576978187713794508801670879012617291871930787451284328591529490578
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.12172085112120321244838645807896127395131617079037303900523599671150426851106
Short name T5
Test name
Test status
Simulation time 445204539 ps
CPU time 13.1 seconds
Started Nov 22 01:21:58 PM PST 23
Finished Nov 22 01:22:17 PM PST 23
Peak memory 246520 kb
Host smart-c1fcc84b-9926-4fe9-a08a-3e9c6443c7cc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121720851121203212448386458078961273951316170790373039005235996711504
26851106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.121720851121203212448386458078961273951316170790373039
00523599671150426851106
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.61356899195948145609633024850401178326531010678475141442275039781796926236825
Short name T261
Test name
Test status
Simulation time 40672061 ps
CPU time 0.84 seconds
Started Nov 22 01:22:03 PM PST 23
Finished Nov 22 01:22:09 PM PST 23
Peak memory 202656 kb
Host smart-217eefe1-bb05-4f31-9adf-63aa11172eed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61356899195948145609633024850401178326531010678475141442275039781796926236825 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.61356899195948145609633024850401178326531010678475141442275039781796926236825
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.24419242215727041997140615097843236593222569478661520169593515042449475062827
Short name T1036
Test name
Test status
Simulation time 19383553031 ps
CPU time 465.54 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:30:11 PM PST 23
Peak memory 371856 kb
Host smart-084a6296-62a7-4259-b700-6d2e075539a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24419242215727041997140615097843236593222569478661520169593515042449475062827 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.24419242215727041997140615097843236593222569478661520169593515042449475062827
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.49967792714422598490773494020797842492347836496830494862849127152336497298364
Short name T613
Test name
Test status
Simulation time 427865392 ps
CPU time 11.04 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:22:02 PM PST 23
Peak memory 246596 kb
Host smart-8f27afa8-2802-4cb2-acf0-bb776e59b6ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49967792714422598490773494020797842492347836496830494862849127152336497298364 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.49967792714422598490773494020797842492347836496830494862849127152336497298364
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.97141024816147043238977155064032059663240454008700431492471871691132950664492
Short name T926
Test name
Test status
Simulation time 121463254244 ps
CPU time 3689.06 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 02:23:36 PM PST 23
Peak memory 375444 kb
Host smart-4ff696ed-cd57-4a99-9513-159aec573e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971410248161470432389771550640320596632404540087004314924718716
91132950664492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.97141024816147043238977155064032059663240454008
700431492471871691132950664492
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.81750182083227784240805645644329707157151750767181823661915112625539715229122
Short name T412
Test name
Test status
Simulation time 624328106 ps
CPU time 1018.87 seconds
Started Nov 22 01:21:55 PM PST 23
Finished Nov 22 01:39:00 PM PST 23
Peak memory 401796 kb
Host smart-5ebc5703-90a6-4b6f-8c4a-f8017d3b9c2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=81750182083227784240805645644329707157151750767181823661915112625539715229122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sr
am_ctrl_stress_all_with_rand_reset.81750182083227784240805645644329707157151750767181823661915112625539715229122
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.67335005843994664961113096364353396711013030666178967429650266259298663071024
Short name T937
Test name
Test status
Simulation time 6491370455 ps
CPU time 354.49 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 202616 kb
Host smart-ba72a547-d533-47a5-99a5-b400d0573bde
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67335005843994664961113096364353396711013030666178967429650266259298663071024
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.673350058439946649611130963643533967110130306661789
67429650266259298663071024
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.65936130382686112628006844842700256867641005406601896368991287620794773421148
Short name T629
Test name
Test status
Simulation time 237420487 ps
CPU time 114.13 seconds
Started Nov 22 01:22:02 PM PST 23
Finished Nov 22 01:24:02 PM PST 23
Peak memory 351184 kb
Host smart-1c44b7be-36d6-40e8-b5a6-5105975e8763
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659361303826861126280068448427002568676410054066018963
68991287620794773421148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.6593613038268611262800
6844842700256867641005406601896368991287620794773421148
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.26096919518615889859965023329319932972936950421564796579652146880553139283215
Short name T559
Test name
Test status
Simulation time 4471404472 ps
CPU time 800.5 seconds
Started Nov 22 01:21:43 PM PST 23
Finished Nov 22 01:35:09 PM PST 23
Peak memory 375520 kb
Host smart-ab2626f8-42d0-412e-81ee-e5356b9ca144
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26096919518615889859965023329319932972936950421564796579652146880553139283215
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during_key_req.260969195186158898599650233293199329729
36950421564796579652146880553139283215
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.94724930932818024819440465083767853005591893726351285608058791069990574877267
Short name T1023
Test name
Test status
Simulation time 16600825 ps
CPU time 0.63 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 202152 kb
Host smart-da795d1c-9d69-480a-afff-fa7fbfcb0a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947249309328180248194404650837678530055918937263512856080587910699
90574877267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.947249309328180248194404650837678530055918937263512856
08058791069990574877267
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.55985661758311689086775878590755089395193157028963567776948493798304325203003
Short name T1008
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.55 seconds
Started Nov 22 01:23:22 PM PST 23
Finished Nov 22 01:24:55 PM PST 23
Peak memory 202596 kb
Host smart-6e44b70b-2a51-4ce1-8858-728bc7c9f283
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55985661758311689086775878590755089395193157028963567776948493798304325203003 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.55985661758311689086775878590755089395193157028963567776948493798304325203003
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.109346962945522177357223374122393354029911836165803090737333205945195750005606
Short name T816
Test name
Test status
Simulation time 23162112088 ps
CPU time 788.81 seconds
Started Nov 22 01:21:54 PM PST 23
Finished Nov 22 01:35:09 PM PST 23
Peak memory 364560 kb
Host smart-0e88adff-a4d7-4b40-b251-f91887c4f1e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109346962945522177357223374122393354029911836165803090737333205945195750005606 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.109346962945522177357223374122393354029911836165803090737333205945195750005606
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.108112435844168509553568275631332546000754279670061291825839377670209044033289
Short name T537
Test name
Test status
Simulation time 985753786 ps
CPU time 7.34 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:22:46 PM PST 23
Peak memory 213232 kb
Host smart-12c0c11f-eebd-492a-bbde-7fac65fbfa04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108112435844168509553568275631332546000754279670061291825839377670209044033289 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.108112435844168509553568275631332546000754279670061291825839377670209044033289
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.37270497210281529782388457466159263067974379829157676008835264731191184352234
Short name T276
Test name
Test status
Simulation time 209242141 ps
CPU time 110.1 seconds
Started Nov 22 01:21:55 PM PST 23
Finished Nov 22 01:23:51 PM PST 23
Peak memory 351268 kb
Host smart-7183e5c2-0920-42fa-91af-c427759cc155
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727049721028152978238845746615926306797437982915767600
8835264731191184352234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_max_throughput.37270497210281529782388457466159263
067974379829157676008835264731191184352234
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.44693390756000589728867917356156251924930870169070542367202107694008094107543
Short name T906
Test name
Test status
Simulation time 166171057 ps
CPU time 3.13 seconds
Started Nov 22 01:22:17 PM PST 23
Finished Nov 22 01:22:22 PM PST 23
Peak memory 215700 kb
Host smart-30cb5087-b1cf-4b2d-a811-5cb673eaa878
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44693390756000589728867917356156251924930870169070542367202107694008
094107543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.446933907560005897288679173561562519249308701690
70542367202107694008094107543
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.48780612681691963611874762578071176141171056464908781300244715508990686378399
Short name T455
Test name
Test status
Simulation time 590810517 ps
CPU time 5.64 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:22:05 PM PST 23
Peak memory 202508 kb
Host smart-6bf2228f-bf88-4198-b82c-02c1c0a4cfbb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48780612681691963611874762578071176141171056464908781300244715508990686378399
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.48780612681691963611874762578071176141171056464908781300244715508990686378399
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.114428426342734089422113678215040696782797408169662995091057143238381278500526
Short name T929
Test name
Test status
Simulation time 21947461091 ps
CPU time 845.82 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:36:00 PM PST 23
Peak memory 371332 kb
Host smart-964cfa81-ad68-449b-908e-769de1fa46d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114428426342734089422113678215040696782797408169662995091057143238381278500526 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.114428426342734089422113678215040696782797408169662995091057143238381278500526
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.2104540818804549046350492351188292892522631660329554840298269535324234326114
Short name T421
Test name
Test status
Simulation time 445204539 ps
CPU time 12.01 seconds
Started Nov 22 01:22:02 PM PST 23
Finished Nov 22 01:22:20 PM PST 23
Peak memory 246596 kb
Host smart-30482ae9-ca07-4e68-9fb5-9089a12224d2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210454081880454904635049235118829289252263166032955484029826953532423
4326114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.2104540818804549046350492351188292892522631660329554840
298269535324234326114
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.74455139782275209988555315316271641587060704829595054234964247875453553263116
Short name T435
Test name
Test status
Simulation time 42305619653 ps
CPU time 529.11 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:31:56 PM PST 23
Peak memory 202456 kb
Host smart-2db6c8b7-eeca-4ff9-96bd-3ccf584c17d4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744551397822752099885553153162716415870607048295950542349642478754535
53263116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access_b2b.7445513978227520998855531531627164158706
0704829595054234964247875453553263116
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.99662862604975131596840090609241093817595104749556147513513735239796107794899
Short name T691
Test name
Test status
Simulation time 40672061 ps
CPU time 0.86 seconds
Started Nov 22 01:22:19 PM PST 23
Finished Nov 22 01:22:22 PM PST 23
Peak memory 202560 kb
Host smart-aa5e8639-ea51-46e7-9d16-34bd3caab467
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99662862604975131596840090609241093817595104749556147513513735239796107794899 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.99662862604975131596840090609241093817595104749556147513513735239796107794899
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.75305517772000075968689788747654645238368254324098458542026054890742871159929
Short name T686
Test name
Test status
Simulation time 19383553031 ps
CPU time 543.01 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:31:06 PM PST 23
Peak memory 371784 kb
Host smart-0e4cdd18-bdb1-47de-b67b-5cdec071c9d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75305517772000075968689788747654645238368254324098458542026054890742871159929 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.75305517772000075968689788747654645238368254324098458542026054890742871159929
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.88527670457682773418134953649272979339750641752728773930270147478151335265639
Short name T952
Test name
Test status
Simulation time 427865392 ps
CPU time 11.34 seconds
Started Nov 22 01:22:53 PM PST 23
Finished Nov 22 01:23:18 PM PST 23
Peak memory 246428 kb
Host smart-2ad3695b-a74b-4413-9669-1cfe5f39ca47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88527670457682773418134953649272979339750641752728773930270147478151335265639 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.88527670457682773418134953649272979339750641752728773930270147478151335265639
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.86095156115589149991287797661278670043651508400597454786357703571092773815182
Short name T516
Test name
Test status
Simulation time 121463254244 ps
CPU time 3479.62 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 02:20:06 PM PST 23
Peak memory 375456 kb
Host smart-597a9025-8c0b-411e-a6df-f9e6840fa37d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860951561155891499912877976612786700436515084005974547863577035
71092773815182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.86095156115589149991287797661278670043651508400
597454786357703571092773815182
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.38123470379995163990774185323463573599666342431782476451387397376416170858539
Short name T310
Test name
Test status
Simulation time 624328106 ps
CPU time 1364.22 seconds
Started Nov 22 01:21:51 PM PST 23
Finished Nov 22 01:44:41 PM PST 23
Peak memory 401780 kb
Host smart-94540c6c-7b68-4a99-84d2-b674cbf6f419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=38123470379995163990774185323463573599666342431782476451387397376416170858539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sr
am_ctrl_stress_all_with_rand_reset.38123470379995163990774185323463573599666342431782476451387397376416170858539
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.47010988574759073180651075625701843791460113622092947739554439091478265808140
Short name T652
Test name
Test status
Simulation time 6491370455 ps
CPU time 361 seconds
Started Nov 22 01:21:47 PM PST 23
Finished Nov 22 01:27:53 PM PST 23
Peak memory 202668 kb
Host smart-c67addf2-9f8b-4258-a595-df784aec6e60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47010988574759073180651075625701843791460113622092947739554439091478265808140
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.470109885747590731806510756257018437914601136220929
47739554439091478265808140
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.13924615036190669072907888429593199946704472719776065087602016433715898161589
Short name T139
Test name
Test status
Simulation time 237420487 ps
CPU time 122.43 seconds
Started Nov 22 01:21:52 PM PST 23
Finished Nov 22 01:24:00 PM PST 23
Peak memory 351304 kb
Host smart-9614f140-225a-47c9-b9fa-a00c353b46ea
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139246150361906690729078884295931999467044727197760650
87602016433715898161589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.1392461503619066907290
7888429593199946704472719776065087602016433715898161589
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.59258095105850146559593560279398031793341505617154017791293352409219656069796
Short name T671
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:21:56 PM PST 23
Finished Nov 22 01:22:03 PM PST 23
Peak memory 202236 kb
Host smart-f15ff2af-e0ee-43fe-8e6b-953514198054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592580951058501465595935602793980317933415056171540177912933524092
19656069796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.592580951058501465595935602793980317933415056171540177
91293352409219656069796
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.26762825465311560634885004407943158239189373892385629643784361854146155462791
Short name T980
Test name
Test status
Simulation time 9249473390 ps
CPU time 87.61 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:23:31 PM PST 23
Peak memory 202448 kb
Host smart-54aba406-3f5b-4127-b654-2d45a2ad6d40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26762825465311560634885004407943158239189373892385629643784361854146155462791 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.26762825465311560634885004407943158239189373892385629643784361854146155462791
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.53107608293228398825969024305637552740974284708315816142636901183959172710973
Short name T882
Test name
Test status
Simulation time 23162112088 ps
CPU time 728.16 seconds
Started Nov 22 01:22:53 PM PST 23
Finished Nov 22 01:35:15 PM PST 23
Peak memory 364592 kb
Host smart-c14e0cb4-6536-429f-9820-02ef9ddc7271
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53107608293228398825969024305637552740974284708315816142636901183959172710973 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.53107608293228398825969024305637552740974284708315816142636901183959172710973
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.54080479405124034563655053727741292576535566043793349751170584090229963129277
Short name T458
Test name
Test status
Simulation time 985753786 ps
CPU time 7.1 seconds
Started Nov 22 01:21:59 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 213172 kb
Host smart-b432ab44-4e1f-4836-95cd-555b5d027d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54080479405124034563655053727741292576535566043793349751170584090229963129277 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.54080479405124034563655053727741292576535566043793349751170584090229963129277
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.31793508273385508230350587520172694696960380399334107199328551807415950149392
Short name T549
Test name
Test status
Simulation time 209242141 ps
CPU time 105.27 seconds
Started Nov 22 01:21:54 PM PST 23
Finished Nov 22 01:23:45 PM PST 23
Peak memory 351268 kb
Host smart-85de504b-83a0-4c09-8155-222375a2e3be
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179350827338550823035058752017269469696038039933410719
9328551807415950149392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_max_throughput.31793508273385508230350587520172694
696960380399334107199328551807415950149392
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.111906826186446590067947010435964210965517161332928240532762976412391006159143
Short name T884
Test name
Test status
Simulation time 166171057 ps
CPU time 3.09 seconds
Started Nov 22 01:22:54 PM PST 23
Finished Nov 22 01:23:10 PM PST 23
Peak memory 215676 kb
Host smart-a9cc6918-f7b2-4f98-b5a3-74d65b6a8bf7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11190682618644659006794701043596421096551716133292824053276297641239
1006159143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.11190682618644659006794701043596421096551716133
2928240532762976412391006159143
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.19573790247283447321976364651411823382763154257215432113649364166644387902864
Short name T576
Test name
Test status
Simulation time 590810517 ps
CPU time 5.24 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:22:08 PM PST 23
Peak memory 202624 kb
Host smart-b4fad991-4fe6-452a-a77b-80f0735bd509
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19573790247283447321976364651411823382763154257215432113649364166644387902864
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.19573790247283447321976364651411823382763154257215432113649364166644387902864
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.94200518776035004485292260284537089585803803014889723154521631618802520437753
Short name T984
Test name
Test status
Simulation time 21947461091 ps
CPU time 768.43 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:34:40 PM PST 23
Peak memory 371412 kb
Host smart-fcd89dfb-83e3-4c48-b7e6-238edec266bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94200518776035004485292260284537089585803803014889723154521631618802520437753 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.94200518776035004485292260284537089585803803014889723154521631618802520437753
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.85526506594079661754157316178290349030028586666438602273408199647281839244470
Short name T1000
Test name
Test status
Simulation time 445204539 ps
CPU time 11.52 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:23:01 PM PST 23
Peak memory 246392 kb
Host smart-49426e58-dcca-47b3-93ab-92fc7dc6caa5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855265065940796617541573161782903490300285866664386022734081996472818
39244470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.855265065940796617541573161782903490300285866664386022
73408199647281839244470
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.76049913753719172470144617710156748121745300676945726189469638380393959404796
Short name T534
Test name
Test status
Simulation time 42305619653 ps
CPU time 548.85 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:31:15 PM PST 23
Peak memory 202680 kb
Host smart-c918e4fc-16ec-4f4c-8cc7-cdd85a4edf73
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760499137537191724701446177101567481217453006769457261894696383803939
59404796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access_b2b.7604991375371917247014461771015674812174
5300676945726189469638380393959404796
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.34901146269398373628592926690924257587663475134627277866987319316019863205487
Short name T900
Test name
Test status
Simulation time 40672061 ps
CPU time 0.81 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:22:26 PM PST 23
Peak memory 202656 kb
Host smart-84325f58-95ee-4816-aa12-a1aa8ad5696c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34901146269398373628592926690924257587663475134627277866987319316019863205487 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.34901146269398373628592926690924257587663475134627277866987319316019863205487
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.24373593290285335485804482932245070834323301713396040386009110963185584381868
Short name T101
Test name
Test status
Simulation time 19383553031 ps
CPU time 594.04 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:31:54 PM PST 23
Peak memory 371764 kb
Host smart-d32f6c66-4ebc-410e-9473-dd65235c8db8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373593290285335485804482932245070834323301713396040386009110963185584381868 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.24373593290285335485804482932245070834323301713396040386009110963185584381868
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.6063536473414437932862596536473886806400844333505554729515063842050471746681
Short name T1005
Test name
Test status
Simulation time 427865392 ps
CPU time 10.25 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:22:40 PM PST 23
Peak memory 246456 kb
Host smart-fffeb798-0fba-4c8b-93ca-94cd27afe351
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6063536473414437932862596536473886806400844333505554729515063842050471746681 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.6063536473414437932862596536473886806400844333505554729515063842050471746681
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.106020343157674789080050407748154920336572218845993801591545697351487844609558
Short name T847
Test name
Test status
Simulation time 121463254244 ps
CPU time 3060.73 seconds
Started Nov 22 01:22:53 PM PST 23
Finished Nov 22 02:14:08 PM PST 23
Peak memory 375480 kb
Host smart-40c72290-047a-45ce-83c4-a31ce3c7214b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106020343157674789080050407748154920336572218845993801591545697
351487844609558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.1060203431576747890800504077481549203365722188
45993801591545697351487844609558
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.18742152825620717125140258077422983296474771098036421286222804918739620709298
Short name T17
Test name
Test status
Simulation time 624328106 ps
CPU time 1150.85 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:41:06 PM PST 23
Peak memory 401708 kb
Host smart-5360db1c-3158-4ba2-a795-be6f11b1b950
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=18742152825620717125140258077422983296474771098036421286222804918739620709298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sr
am_ctrl_stress_all_with_rand_reset.18742152825620717125140258077422983296474771098036421286222804918739620709298
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.53666240741821479582149312139653054195205656500532930680340669002154338502262
Short name T978
Test name
Test status
Simulation time 6491370455 ps
CPU time 355 seconds
Started Nov 22 01:22:04 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 202484 kb
Host smart-599a1467-1df9-4fc8-aa8a-a41aeef4e2ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53666240741821479582149312139653054195205656500532930680340669002154338502262
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.536662407418214795821493121396530541952056565005329
30680340669002154338502262
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.56662053032729541331180685530730310515963357424191292307072348521776650295960
Short name T897
Test name
Test status
Simulation time 237420487 ps
CPU time 91.26 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:23:34 PM PST 23
Peak memory 351304 kb
Host smart-c6553986-84ab-41db-9eec-aff1529a15f4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566620530327295413311806855307303105159633574241912923
07072348521776650295960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.5666205303272954133118
0685530730310515963357424191292307072348521776650295960
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.10315948033648406850401567193449642887607965920260139580420637224740254005507
Short name T1030
Test name
Test status
Simulation time 4471404472 ps
CPU time 756.77 seconds
Started Nov 22 01:21:56 PM PST 23
Finished Nov 22 01:34:39 PM PST 23
Peak memory 375464 kb
Host smart-95ab8961-3d53-4ead-b49f-8d0d5bc4fa55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10315948033648406850401567193449642887607965920260139580420637224740254005507
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during_key_req.103159480336484068504015671934496428876
07965920260139580420637224740254005507
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.24576796542352142606933617204540553271988327042209760082576666622016759363595
Short name T23
Test name
Test status
Simulation time 16600825 ps
CPU time 0.63 seconds
Started Nov 22 01:22:38 PM PST 23
Finished Nov 22 01:22:44 PM PST 23
Peak memory 202172 kb
Host smart-9a2e30b6-bd99-4a3a-9721-7db23b242ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245767965423521426069336172045405532719883270422097600825766666220
16759363595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.245767965423521426069336172045405532719883270422097600
82576666622016759363595
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.85454447141973971052888751494180590453873148496160262706764675172282771246829
Short name T910
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.31 seconds
Started Nov 22 01:22:11 PM PST 23
Finished Nov 22 01:23:36 PM PST 23
Peak memory 202640 kb
Host smart-059443e5-cb60-4d45-bdc7-37f36279ac93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85454447141973971052888751494180590453873148496160262706764675172282771246829 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.85454447141973971052888751494180590453873148496160262706764675172282771246829
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.69017219523143160810153691403483047891435463566528334322154292666241483331984
Short name T124
Test name
Test status
Simulation time 23162112088 ps
CPU time 842.37 seconds
Started Nov 22 01:22:45 PM PST 23
Finished Nov 22 01:37:00 PM PST 23
Peak memory 364532 kb
Host smart-be172cb4-8161-4102-a837-484afa7fc3c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69017219523143160810153691403483047891435463566528334322154292666241483331984 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.69017219523143160810153691403483047891435463566528334322154292666241483331984
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.88925613948173227497262257573019998352871080092018888076982599440082962560584
Short name T271
Test name
Test status
Simulation time 985753786 ps
CPU time 7.33 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 01:22:15 PM PST 23
Peak memory 213184 kb
Host smart-aa4ad09c-09fb-4818-8ba4-d40824166ee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88925613948173227497262257573019998352871080092018888076982599440082962560584 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.88925613948173227497262257573019998352871080092018888076982599440082962560584
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.109978642132389260745485708013245882858947859091439834707256984523990408396747
Short name T787
Test name
Test status
Simulation time 209242141 ps
CPU time 86.99 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 351336 kb
Host smart-bacbe8f2-de4d-4c1e-9d73-bc480df84173
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099786421323892607454857080132458828589478590914398347
07256984523990408396747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_max_throughput.1099786421323892607454857080132458
82858947859091439834707256984523990408396747
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.55535587830135771762195911574442532352008834932809203937225104449225979757655
Short name T1038
Test name
Test status
Simulation time 166171057 ps
CPU time 2.98 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 01:22:10 PM PST 23
Peak memory 215724 kb
Host smart-ff5bf689-d9d1-4060-a901-ab94632fac80
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55535587830135771762195911574442532352008834932809203937225104449225
979757655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.555355878301357717621959115744425323520088349328
09203937225104449225979757655
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.79501753183397826702350219343154962296337124938820423372450168051116285224221
Short name T365
Test name
Test status
Simulation time 590810517 ps
CPU time 5.31 seconds
Started Nov 22 01:21:54 PM PST 23
Finished Nov 22 01:22:05 PM PST 23
Peak memory 202496 kb
Host smart-2c0bf37f-ef62-4cac-bfb5-0e09cbfe7f11
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79501753183397826702350219343154962296337124938820423372450168051116285224221
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.79501753183397826702350219343154962296337124938820423372450168051116285224221
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.86824711280584181114870777528222599844432013641000964516905181317253589225468
Short name T485
Test name
Test status
Simulation time 21947461091 ps
CPU time 811.64 seconds
Started Nov 22 01:21:46 PM PST 23
Finished Nov 22 01:35:23 PM PST 23
Peak memory 371292 kb
Host smart-dcaa388f-b9b9-409a-83d0-46c0c62774d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86824711280584181114870777528222599844432013641000964516905181317253589225468 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.86824711280584181114870777528222599844432013641000964516905181317253589225468
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.60698303538172742137549888419376752112666491489156966380283557857686686544029
Short name T414
Test name
Test status
Simulation time 445204539 ps
CPU time 13.44 seconds
Started Nov 22 01:21:58 PM PST 23
Finished Nov 22 01:22:17 PM PST 23
Peak memory 246552 kb
Host smart-a1cda803-01ed-4eab-a8f9-99a47cf8581e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606983035381727421375498884193767521126664914891569663802835578576866
86544029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.606983035381727421375498884193767521126664914891569663
80283557857686686544029
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.6885793558999361404925562737723758309008424986253964991414318079273724239528
Short name T642
Test name
Test status
Simulation time 42305619653 ps
CPU time 540.3 seconds
Started Nov 22 01:21:55 PM PST 23
Finished Nov 22 01:31:01 PM PST 23
Peak memory 202572 kb
Host smart-a46dbace-6318-42ed-8f12-692686f09c9d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688579355899936140492556273772375830900842498625396499141431807927372
4239528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access_b2b.68857935589993614049255627377237583090084
24986253964991414318079273724239528
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.71430735988235233880238058256180454947882893116992627251014074137158537324419
Short name T437
Test name
Test status
Simulation time 40672061 ps
CPU time 0.9 seconds
Started Nov 22 01:22:08 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 202600 kb
Host smart-90aed826-3cf4-4e35-930e-c1532bfd79bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71430735988235233880238058256180454947882893116992627251014074137158537324419 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.71430735988235233880238058256180454947882893116992627251014074137158537324419
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.59579589077780271655019092999962827779753502371707735311141182808373580079766
Short name T463
Test name
Test status
Simulation time 19383553031 ps
CPU time 455.66 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:29:41 PM PST 23
Peak memory 371808 kb
Host smart-cf0e4b0f-c20a-4715-8b10-924edecd701e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59579589077780271655019092999962827779753502371707735311141182808373580079766 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.59579589077780271655019092999962827779753502371707735311141182808373580079766
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.5103503325686767163628782977558769838155806170908870673211049359907110684493
Short name T275
Test name
Test status
Simulation time 427865392 ps
CPU time 11.1 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 01:22:18 PM PST 23
Peak memory 246652 kb
Host smart-c2f8bfec-5ea5-4902-a793-71128b151f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5103503325686767163628782977558769838155806170908870673211049359907110684493 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.5103503325686767163628782977558769838155806170908870673211049359907110684493
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.52070791235600633497154068306967930027790899749912937765655760285582302253145
Short name T855
Test name
Test status
Simulation time 121463254244 ps
CPU time 3417.24 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 02:19:04 PM PST 23
Peak memory 375380 kb
Host smart-f27a9d69-f47f-46de-b887-c96f5ba89c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520707912356006334971540683069679300277908997499129377656557602
85582302253145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.52070791235600633497154068306967930027790899749
912937765655760285582302253145
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.92642165513155314230708237373206249162877385935602583488046139231911126449686
Short name T423
Test name
Test status
Simulation time 624328106 ps
CPU time 1343.03 seconds
Started Nov 22 01:21:54 PM PST 23
Finished Nov 22 01:44:23 PM PST 23
Peak memory 401780 kb
Host smart-82dcf0f9-9793-44b1-904a-2190c7026837
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=92642165513155314230708237373206249162877385935602583488046139231911126449686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sr
am_ctrl_stress_all_with_rand_reset.92642165513155314230708237373206249162877385935602583488046139231911126449686
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.19815221445423473872768134740267653587783349794897050866611557183449035791432
Short name T294
Test name
Test status
Simulation time 6491370455 ps
CPU time 353.33 seconds
Started Nov 22 01:21:59 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 202648 kb
Host smart-00e47314-3f62-4950-8aba-687f37b09392
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815221445423473872768134740267653587783349794897050866611557183449035791432
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.198152214454234738727681347402676535877833497948970
50866611557183449035791432
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.15288796339778948189200304615729265379664510655118788943282638146038959685168
Short name T565
Test name
Test status
Simulation time 237420487 ps
CPU time 82.19 seconds
Started Nov 22 01:22:22 PM PST 23
Finished Nov 22 01:23:47 PM PST 23
Peak memory 351348 kb
Host smart-da7d265d-bbfd-4ce3-8160-7c41d49c309c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152887963397789481892003046157292653796645106551187889
43282638146038959685168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1528879633977894818920
0304615729265379664510655118788943282638146038959685168
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.98237377282029226941288917057623908599488946214609198771209103573606304014318
Short name T680
Test name
Test status
Simulation time 4471404472 ps
CPU time 702.62 seconds
Started Nov 22 01:22:11 PM PST 23
Finished Nov 22 01:33:57 PM PST 23
Peak memory 375528 kb
Host smart-5ddcbfac-8efc-4ad9-8ce9-0635a2aab5eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98237377282029226941288917057623908599488946214609198771209103573606304014318
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during_key_req.982373772820292269412889170576239085994
88946214609198771209103573606304014318
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.19032327846817040215435595105615108638588303634665095667829405569017738764819
Short name T749
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 202220 kb
Host smart-bf00de20-ed63-4b9b-b6f1-1706ee0d6ec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190323278468170402154355951056151086385883036346650956678294055690
17738764819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.190323278468170402154355951056151086385883036346650956
67829405569017738764819
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.10470468831180446620107906630515880551767915117129322381951308154104668518220
Short name T371
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.71 seconds
Started Nov 22 01:22:36 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 202580 kb
Host smart-4e72ecae-9834-4cc0-aab0-a722fce0d34e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10470468831180446620107906630515880551767915117129322381951308154104668518220 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.10470468831180446620107906630515880551767915117129322381951308154104668518220
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.19013534387680855534547191089397367527864497645710905983060881419247465859468
Short name T486
Test name
Test status
Simulation time 23162112088 ps
CPU time 772.63 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:34:48 PM PST 23
Peak memory 364660 kb
Host smart-1f0c3bc3-f40f-41f9-85d7-1404be55c5d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19013534387680855534547191089397367527864497645710905983060881419247465859468 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.19013534387680855534547191089397367527864497645710905983060881419247465859468
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.15519132094590431357526690611229138699763862301084716311519304601082618703875
Short name T907
Test name
Test status
Simulation time 985753786 ps
CPU time 7.11 seconds
Started Nov 22 01:22:18 PM PST 23
Finished Nov 22 01:22:27 PM PST 23
Peak memory 213132 kb
Host smart-b37757ad-44b8-4dfc-9760-e2e02bcddc5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15519132094590431357526690611229138699763862301084716311519304601082618703875 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.15519132094590431357526690611229138699763862301084716311519304601082618703875
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.27446311223524050238848137631915945707902701748315288539362636843727857427640
Short name T616
Test name
Test status
Simulation time 209242141 ps
CPU time 96.45 seconds
Started Nov 22 01:22:36 PM PST 23
Finished Nov 22 01:24:18 PM PST 23
Peak memory 351192 kb
Host smart-f272e34e-7633-4561-b2f7-3ecb35569f89
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744631122352405023884813763191594570790270174831528853
9362636843727857427640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_max_throughput.27446311223524050238848137631915945
707902701748315288539362636843727857427640
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.56278749709228532248327132687351197262289842169004446641856246862663355101268
Short name T496
Test name
Test status
Simulation time 166171057 ps
CPU time 3.34 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:21:57 PM PST 23
Peak memory 215720 kb
Host smart-bb81f034-d81d-48f8-98eb-d1c4f642f65a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56278749709228532248327132687351197262289842169004446641856246862663
355101268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.562787497092285322483271326873511972622898421690
04446641856246862663355101268
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.100098812624745739691197539041902428531566843658549589735108504149441004661109
Short name T767
Test name
Test status
Simulation time 590810517 ps
CPU time 5.67 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:22:09 PM PST 23
Peak memory 202592 kb
Host smart-531e9d27-4247-4563-ac7a-5737d0c05b6a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100098812624745739691197539041902428531566843658549589735108504149441004661109
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.100098812624745739691197539041902428531566843658549589735108504149441004661109
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.27269958847225988646964786544732805117393514964378952754911186052963049411122
Short name T546
Test name
Test status
Simulation time 21947461091 ps
CPU time 804.05 seconds
Started Nov 22 01:22:03 PM PST 23
Finished Nov 22 01:35:32 PM PST 23
Peak memory 371412 kb
Host smart-d79130d7-8dcb-4acd-846e-8714cdb2511c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27269958847225988646964786544732805117393514964378952754911186052963049411122 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.27269958847225988646964786544732805117393514964378952754911186052963049411122
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.113215889974427208529674451176406364633775407798424077524086144735899871318964
Short name T735
Test name
Test status
Simulation time 445204539 ps
CPU time 14.71 seconds
Started Nov 22 01:22:03 PM PST 23
Finished Nov 22 01:22:23 PM PST 23
Peak memory 246588 kb
Host smart-a4c58e34-8bc7-4573-ae88-bac6657f303f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113215889974427208529674451176406364633775407798424077524086144735899
871318964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.11321588997442720852967445117640636463377540779842407
7524086144735899871318964
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.70434836700295125973024175335339584540482820044753010895244845461977082391578
Short name T879
Test name
Test status
Simulation time 42305619653 ps
CPU time 544.56 seconds
Started Nov 22 01:21:51 PM PST 23
Finished Nov 22 01:31:01 PM PST 23
Peak memory 202612 kb
Host smart-99cc3872-f2b2-468b-89b5-82b20116becc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704348367002951259730241753353395845404828200447530108952448454619770
82391578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access_b2b.7043483670029512597302417533533958454048
2820044753010895244845461977082391578
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.88023063000885308863248325642619401135304416976092243271710608800942355109451
Short name T33
Test name
Test status
Simulation time 40672061 ps
CPU time 0.79 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:22:37 PM PST 23
Peak memory 202440 kb
Host smart-ca0d60d5-b9cb-4cfa-b04d-e29c2ed7a99a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88023063000885308863248325642619401135304416976092243271710608800942355109451 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.88023063000885308863248325642619401135304416976092243271710608800942355109451
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.5947785946782101797468622900514023409659849297330294596861105838128994275039
Short name T338
Test name
Test status
Simulation time 19383553031 ps
CPU time 579.02 seconds
Started Nov 22 01:22:05 PM PST 23
Finished Nov 22 01:31:49 PM PST 23
Peak memory 371840 kb
Host smart-0e1d55b8-df66-45d3-bb70-1ff900ba8ac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5947785946782101797468622900514023409659849297330294596861105838128994275039 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.5947785946782101797468622900514023409659849297330294596861105838128994275039
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.98231332777830734755349980196037756832971937096868875285384744680546251920037
Short name T638
Test name
Test status
Simulation time 427865392 ps
CPU time 11.32 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:22:17 PM PST 23
Peak memory 246408 kb
Host smart-d652867f-124b-4831-9cde-272b71dbf22c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98231332777830734755349980196037756832971937096868875285384744680546251920037 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.98231332777830734755349980196037756832971937096868875285384744680546251920037
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.53834202077257754467198175043584327529597252178042769185864207582877039318195
Short name T306
Test name
Test status
Simulation time 121463254244 ps
CPU time 3423.42 seconds
Started Nov 22 01:21:52 PM PST 23
Finished Nov 22 02:19:01 PM PST 23
Peak memory 375448 kb
Host smart-a0fa71e3-ff88-4e38-a314-fe161fc1ff7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538342020772577544671981750435843275295972521780427691858642075
82877039318195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.53834202077257754467198175043584327529597252178
042769185864207582877039318195
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.42588906523244881160578604965495533415738011137157864469063351701556311291152
Short name T873
Test name
Test status
Simulation time 624328106 ps
CPU time 1036.15 seconds
Started Nov 22 01:21:56 PM PST 23
Finished Nov 22 01:39:18 PM PST 23
Peak memory 401628 kb
Host smart-3eee19bb-ab59-464a-ad0c-6e3a01fc3a7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=42588906523244881160578604965495533415738011137157864469063351701556311291152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sr
am_ctrl_stress_all_with_rand_reset.42588906523244881160578604965495533415738011137157864469063351701556311291152
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.88561664911560483681431121203465115449917075427347680459944487919040209671938
Short name T801
Test name
Test status
Simulation time 6491370455 ps
CPU time 355.17 seconds
Started Nov 22 01:21:58 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 202668 kb
Host smart-3a38d4bb-b578-4cfc-a603-593746a36ce2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88561664911560483681431121203465115449917075427347680459944487919040209671938
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.885616649115604836814311212034651154499170754273476
80459944487919040209671938
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.112143713743989859011033012870695097719564174347638682913654123251446595024293
Short name T1
Test name
Test status
Simulation time 237420487 ps
CPU time 94.01 seconds
Started Nov 22 01:21:52 PM PST 23
Finished Nov 22 01:23:31 PM PST 23
Peak memory 351348 kb
Host smart-bae35d44-71db-4ea6-bfda-561cddf5c92b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112143713743989859011033012870695097719564174347638682
913654123251446595024293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.112143713743989859011
033012870695097719564174347638682913654123251446595024293
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.38287368371536759719237716905514664913565274815754844348185897835387143015718
Short name T822
Test name
Test status
Simulation time 4471404472 ps
CPU time 791.72 seconds
Started Nov 22 01:21:50 PM PST 23
Finished Nov 22 01:35:07 PM PST 23
Peak memory 375456 kb
Host smart-2bf026d5-0fa4-46b1-9cf9-9d1abdcc3630
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38287368371536759719237716905514664913565274815754844348185897835387143015718
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during_key_req.382873683715367597192377169055146649135
65274815754844348185897835387143015718
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.63708960170196924191829095544440866951600339852832783229657464500852936811882
Short name T325
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:22:06 PM PST 23
Peak memory 202024 kb
Host smart-d6cff63a-9f70-4e30-bda6-441f4dedc5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637089601701969241918290955444408669516003398528327832296574645008
52936811882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.637089601701969241918290955444408669516003398528327832
29657464500852936811882
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.91352774758251672138090159897835776370902467723453826392312229166092340367139
Short name T650
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.86 seconds
Started Nov 22 01:22:19 PM PST 23
Finished Nov 22 01:23:45 PM PST 23
Peak memory 202612 kb
Host smart-e2827aec-c341-48a4-95df-3889448b7f7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91352774758251672138090159897835776370902467723453826392312229166092340367139 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.91352774758251672138090159897835776370902467723453826392312229166092340367139
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.111678546122232439107088084693183785393039514608625575169084546774774620932319
Short name T518
Test name
Test status
Simulation time 23162112088 ps
CPU time 707.84 seconds
Started Nov 22 01:21:57 PM PST 23
Finished Nov 22 01:33:51 PM PST 23
Peak memory 364584 kb
Host smart-9cb74d95-2a54-4c5f-9e7a-772a7f608f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111678546122232439107088084693183785393039514608625575169084546774774620932319 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.111678546122232439107088084693183785393039514608625575169084546774774620932319
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.47040977288825319334560947122291793954184902997786475893715067910772454543081
Short name T1039
Test name
Test status
Simulation time 985753786 ps
CPU time 7.13 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 213264 kb
Host smart-a79d6059-af92-407c-83cb-fd19f899bbbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47040977288825319334560947122291793954184902997786475893715067910772454543081 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.47040977288825319334560947122291793954184902997786475893715067910772454543081
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.50119466975866136682615816780052130013110550469577119117521598856075020926887
Short name T539
Test name
Test status
Simulation time 209242141 ps
CPU time 89.36 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:23:35 PM PST 23
Peak memory 349668 kb
Host smart-988f1e6a-e161-495e-bfbb-723387b4d059
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5011946697586613668261581678005213001311055046957711911
7521598856075020926887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_max_throughput.50119466975866136682615816780052130
013110550469577119117521598856075020926887
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.100262168089083653715369359869739734791012886361977802512417658366160562479327
Short name T958
Test name
Test status
Simulation time 166171057 ps
CPU time 3.12 seconds
Started Nov 22 01:22:08 PM PST 23
Finished Nov 22 01:22:15 PM PST 23
Peak memory 215792 kb
Host smart-8f73bc14-dcf4-49ad-b5cf-835e67e5de77
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10026216808908365371536935986973973479101288636197780251241765836616
0562479327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.10026216808908365371536935986973973479101288636
1977802512417658366160562479327
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.31897856240368533464266675938247745637738164040022529278456341882327756625673
Short name T135
Test name
Test status
Simulation time 590810517 ps
CPU time 5.28 seconds
Started Nov 22 01:22:21 PM PST 23
Finished Nov 22 01:22:28 PM PST 23
Peak memory 202608 kb
Host smart-b4cff9a0-5352-468d-87e1-1458318be6a0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31897856240368533464266675938247745637738164040022529278456341882327756625673
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.31897856240368533464266675938247745637738164040022529278456341882327756625673
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.63322585421125347162001054994640140764799093619787378004383385382291975578916
Short name T612
Test name
Test status
Simulation time 21947461091 ps
CPU time 969.68 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:38:08 PM PST 23
Peak memory 371380 kb
Host smart-7432580a-de05-4efb-9eaf-b1874e14704e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63322585421125347162001054994640140764799093619787378004383385382291975578916 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.63322585421125347162001054994640140764799093619787378004383385382291975578916
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.57762249797376042914293698209315901698510146616011037583407753993974630195843
Short name T898
Test name
Test status
Simulation time 445204539 ps
CPU time 13.42 seconds
Started Nov 22 01:22:39 PM PST 23
Finished Nov 22 01:22:59 PM PST 23
Peak memory 246532 kb
Host smart-3e33943d-ba11-4633-a6fd-be72a0674e70
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577622497973760429142936982093159016985101466160110375834077539939746
30195843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.577622497973760429142936982093159016985101466160110375
83407753993974630195843
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.60596284763876425057843826164363179800950453798668294375762457707170657766338
Short name T66
Test name
Test status
Simulation time 42305619653 ps
CPU time 530.02 seconds
Started Nov 22 01:21:54 PM PST 23
Finished Nov 22 01:30:50 PM PST 23
Peak memory 202688 kb
Host smart-ce15977c-25b9-4155-87a6-1c8ac10a25ae
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605962847638764250578438261643631798009504537986682943757624577071706
57766338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access_b2b.6059628476387642505784382616436317980095
0453798668294375762457707170657766338
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.45264526321721683960778969934740367020962446007579983458459911130612657942820
Short name T995
Test name
Test status
Simulation time 40672061 ps
CPU time 0.85 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:22:07 PM PST 23
Peak memory 202564 kb
Host smart-4f037778-9b5e-40f2-85cf-dbc88583d23e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45264526321721683960778969934740367020962446007579983458459911130612657942820 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.45264526321721683960778969934740367020962446007579983458459911130612657942820
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.80904033700446338511234909506129096514002981350221606336068792006142003859199
Short name T352
Test name
Test status
Simulation time 19383553031 ps
CPU time 536.64 seconds
Started Nov 22 01:22:54 PM PST 23
Finished Nov 22 01:32:03 PM PST 23
Peak memory 371788 kb
Host smart-7915ddcc-ff1c-4d2e-ac75-a4afc5286f21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80904033700446338511234909506129096514002981350221606336068792006142003859199 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.80904033700446338511234909506129096514002981350221606336068792006142003859199
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.109132189863527251415557103711210727772827452708910733217039656236672004123004
Short name T253
Test name
Test status
Simulation time 427865392 ps
CPU time 10.22 seconds
Started Nov 22 01:22:02 PM PST 23
Finished Nov 22 01:22:18 PM PST 23
Peak memory 246412 kb
Host smart-86259456-6b4b-45bc-8b70-61f554da4adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109132189863527251415557103711210727772827452708910733217039656236672004123004 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.109132189863527251415557103711210727772827452708910733217039656236672004123004
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.6744945384187902270058012584317506908614765649569877827374375846132511128536
Short name T574
Test name
Test status
Simulation time 121463254244 ps
CPU time 3023.01 seconds
Started Nov 22 01:22:24 PM PST 23
Finished Nov 22 02:12:52 PM PST 23
Peak memory 375288 kb
Host smart-89801c94-896d-4c49-bf51-27b1552c8898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674494538418790227005801258431750690861476564956987782737437584
6132511128536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.674494538418790227005801258431750690861476564956
9877827374375846132511128536
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.49746362967807542156736647118714417937470891359009462363666859675958381374930
Short name T974
Test name
Test status
Simulation time 624328106 ps
CPU time 1011.41 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 01:38:59 PM PST 23
Peak memory 401628 kb
Host smart-9ba6e494-2455-449f-b500-e0ee4e16b83a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=49746362967807542156736647118714417937470891359009462363666859675958381374930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sr
am_ctrl_stress_all_with_rand_reset.49746362967807542156736647118714417937470891359009462363666859675958381374930
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.63278542981218018898464963124534747204230488440479700846790714098843120549110
Short name T1006
Test name
Test status
Simulation time 6491370455 ps
CPU time 347.44 seconds
Started Nov 22 01:21:58 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 202472 kb
Host smart-a4a5dac6-eb6e-44fe-a848-fd8e20d14a96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63278542981218018898464963124534747204230488440479700846790714098843120549110
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.632785429812180188984649631245347472042304884404797
00846790714098843120549110
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.91254959293074726312168495686570764731063359233046959074657873368846802406164
Short name T985
Test name
Test status
Simulation time 237420487 ps
CPU time 83.19 seconds
Started Nov 22 01:22:03 PM PST 23
Finished Nov 22 01:23:31 PM PST 23
Peak memory 351184 kb
Host smart-db4300c7-7c20-415d-90d2-595c47eed6a3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912549592930747263121684956865707647310633592330469590
74657873368846802406164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.9125495929307472631216
8495686570764731063359233046959074657873368846802406164
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.67968070440807378102792631631493065477508540186141283538383057659322885900482
Short name T333
Test name
Test status
Simulation time 4471404472 ps
CPU time 676.01 seconds
Started Nov 22 01:21:59 PM PST 23
Finished Nov 22 01:33:21 PM PST 23
Peak memory 375464 kb
Host smart-1b3ebe08-f1eb-4009-85a0-53399f33a9ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67968070440807378102792631631493065477508540186141283538383057659322885900482
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during_key_req.679680704408073781027926316314930654775
08540186141283538383057659322885900482
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.24987119232295643748463824859125172570751492985295211578652735519426081597163
Short name T424
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 01:22:13 PM PST 23
Finished Nov 22 01:22:17 PM PST 23
Peak memory 202200 kb
Host smart-51679bde-8fb5-4d1c-a8f1-d6d566ac4794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249871192322956437484638248591251725707514929852952115786527355194
26081597163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.249871192322956437484638248591251725707514929852952115
78652735519426081597163
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.75906025886555239239706063200995618107270343822511257973061770951902237251716
Short name T292
Test name
Test status
Simulation time 9249473390 ps
CPU time 81.25 seconds
Started Nov 22 01:23:32 PM PST 23
Finished Nov 22 01:25:06 PM PST 23
Peak memory 202640 kb
Host smart-34095f09-5c44-41c7-aa0e-82a327a017fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75906025886555239239706063200995618107270343822511257973061770951902237251716 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.75906025886555239239706063200995618107270343822511257973061770951902237251716
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.25418432842965597840366745533953709618896521748716921966949465057789620268238
Short name T955
Test name
Test status
Simulation time 23162112088 ps
CPU time 782.83 seconds
Started Nov 22 01:22:06 PM PST 23
Finished Nov 22 01:35:13 PM PST 23
Peak memory 364540 kb
Host smart-960d65fa-5d34-4f64-b578-238500d2a924
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25418432842965597840366745533953709618896521748716921966949465057789620268238 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.25418432842965597840366745533953709618896521748716921966949465057789620268238
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.81739448994769522940815919931829558910139278932362931001729786774332723823538
Short name T808
Test name
Test status
Simulation time 985753786 ps
CPU time 7.33 seconds
Started Nov 22 01:22:40 PM PST 23
Finished Nov 22 01:22:53 PM PST 23
Peak memory 213216 kb
Host smart-54ccab46-3868-46f2-8bf3-fca90a8ca945
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81739448994769522940815919931829558910139278932362931001729786774332723823538 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.81739448994769522940815919931829558910139278932362931001729786774332723823538
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.3927906530146779319837771979229813388839929404120532785928597892519568622824
Short name T1019
Test name
Test status
Simulation time 209242141 ps
CPU time 82.01 seconds
Started Nov 22 01:22:36 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 351360 kb
Host smart-8d15fa88-7dff-47a5-ace0-c5fe4cad8e5a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927906530146779319837771979229813388839929404120532785
928597892519568622824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_max_throughput.392790653014677931983777197922981338
8839929404120532785928597892519568622824
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.84261187450861594786276704158230136763570879875193095331611899586517206074832
Short name T1021
Test name
Test status
Simulation time 166171057 ps
CPU time 3.05 seconds
Started Nov 22 01:22:10 PM PST 23
Finished Nov 22 01:22:17 PM PST 23
Peak memory 215736 kb
Host smart-86ecea5f-b5cc-4590-b4d2-c651c850b0ff
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84261187450861594786276704158230136763570879875193095331611899586517
206074832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.842611874508615947862767041582301367635708798751
93095331611899586517206074832
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.111740155389369561842965408861079439097528201077264153013644191162971976212459
Short name T343
Test name
Test status
Simulation time 590810517 ps
CPU time 5.78 seconds
Started Nov 22 01:22:11 PM PST 23
Finished Nov 22 01:22:20 PM PST 23
Peak memory 202616 kb
Host smart-9d88b9f4-4c44-44b3-8566-7e618173e168
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111740155389369561842965408861079439097528201077264153013644191162971976212459
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.111740155389369561842965408861079439097528201077264153013644191162971976212459
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.42089285885019755939992509936469425588651956797050797181943405157523413391756
Short name T725
Test name
Test status
Simulation time 21947461091 ps
CPU time 655.32 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 01:33:03 PM PST 23
Peak memory 371416 kb
Host smart-bd61ceb4-8df8-47c7-838d-001a7796a5e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42089285885019755939992509936469425588651956797050797181943405157523413391756 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.42089285885019755939992509936469425588651956797050797181943405157523413391756
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.29025617488157645871125297708213814008505587821126439041252255254707109604549
Short name T830
Test name
Test status
Simulation time 445204539 ps
CPU time 11.18 seconds
Started Nov 22 01:23:32 PM PST 23
Finished Nov 22 01:23:56 PM PST 23
Peak memory 246580 kb
Host smart-89f08718-df61-4e1e-ba4c-4434a90ce28d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290256174881576458711252977082138140085055878211264390412522552547071
09604549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.290256174881576458711252977082138140085055878211264390
41252255254707109604549
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.40059544860614573453037209590399869759232835250782124867057585092078427863344
Short name T560
Test name
Test status
Simulation time 42305619653 ps
CPU time 550.38 seconds
Started Nov 22 01:22:07 PM PST 23
Finished Nov 22 01:31:21 PM PST 23
Peak memory 202724 kb
Host smart-aa9b94a3-fc7e-461f-b5a2-3497ec0e248c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400595448606145734530372095903998697592328352507821248670575850920784
27863344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access_b2b.4005954486061457345303720959039986975923
2835250782124867057585092078427863344
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.2489872445264126813967033031374526279483698132321110652280418157175587996998
Short name T466
Test name
Test status
Simulation time 40672061 ps
CPU time 0.82 seconds
Started Nov 22 01:22:08 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 202440 kb
Host smart-6961b790-1510-4fe8-a3ea-53b9b116f20c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489872445264126813967033031374526279483698132321110652280418157175587996998 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2489872445264126813967033031374526279483698132321110652280418157175587996998
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.117025491091673981731458421396490865908422833477080518835638727103636213389
Short name T769
Test name
Test status
Simulation time 19383553031 ps
CPU time 533.64 seconds
Started Nov 22 01:22:59 PM PST 23
Finished Nov 22 01:32:02 PM PST 23
Peak memory 371816 kb
Host smart-c9931fab-ba82-4e96-be86-1cbc8fa0285e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117025491091673981731458421396490865908422833477080518835638727103636213389 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.117025491091673981731458421396490865908422833477080518835638727103636213389
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.1329892229905264131109143371794254047600053402651739960335463564583410000052
Short name T783
Test name
Test status
Simulation time 427865392 ps
CPU time 12.48 seconds
Started Nov 22 01:21:59 PM PST 23
Finished Nov 22 01:22:17 PM PST 23
Peak memory 246472 kb
Host smart-4bbcdf52-af4b-4f60-be99-20f624b7c7ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329892229905264131109143371794254047600053402651739960335463564583410000052 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1329892229905264131109143371794254047600053402651739960335463564583410000052
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.12607617627645419091746244395734214693589389022675674010014643040958630191836
Short name T30
Test name
Test status
Simulation time 121463254244 ps
CPU time 3062.09 seconds
Started Nov 22 01:23:25 PM PST 23
Finished Nov 22 02:14:42 PM PST 23
Peak memory 375448 kb
Host smart-1d9acb76-3b42-494f-8c37-5d8035edfd9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126076176276454190917462443957342146935893890226756740100146430
40958630191836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.12607617627645419091746244395734214693589389022
675674010014643040958630191836
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1828985353508639838636560758326309364327849460923219764295413009056989881663
Short name T48
Test name
Test status
Simulation time 624328106 ps
CPU time 1228.35 seconds
Started Nov 22 01:22:12 PM PST 23
Finished Nov 22 01:42:44 PM PST 23
Peak memory 401832 kb
Host smart-66ba8772-c324-4261-8e33-20aed21e76c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1828985353508639838636560758326309364327849460923219764295413009056989881663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sra
m_ctrl_stress_all_with_rand_reset.1828985353508639838636560758326309364327849460923219764295413009056989881663
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.92211947135522550392152630487936040063724653830320843157100705426841197496069
Short name T861
Test name
Test status
Simulation time 6491370455 ps
CPU time 347.7 seconds
Started Nov 22 01:22:11 PM PST 23
Finished Nov 22 01:28:02 PM PST 23
Peak memory 202672 kb
Host smart-58813e26-878e-4c8a-afca-c52d483981c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92211947135522550392152630487936040063724653830320843157100705426841197496069
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.922119471355225503921526304879360400637246538303208
43157100705426841197496069
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.59118502712578046963950480561576072436480744631500755687798935964983170818954
Short name T285
Test name
Test status
Simulation time 237420487 ps
CPU time 103.02 seconds
Started Nov 22 01:23:32 PM PST 23
Finished Nov 22 01:25:28 PM PST 23
Peak memory 351384 kb
Host smart-3f4f3aaf-5274-49b7-a83d-bc55f051573d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591185027125780469639504805615760724364807446315007556
87798935964983170818954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.5911850271257804696395
0480561576072436480744631500755687798935964983170818954
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.34416117097049423429081878222168926318002376749334695313517359229418744790470
Short name T452
Test name
Test status
Simulation time 4471404472 ps
CPU time 784.23 seconds
Started Nov 22 01:23:22 PM PST 23
Finished Nov 22 01:36:37 PM PST 23
Peak memory 375480 kb
Host smart-3f422003-0720-46f1-a023-4f4110d0348b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34416117097049423429081878222168926318002376749334695313517359229418744790470
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during_key_req.344161170970494234290818782221689263180
02376749334695313517359229418744790470
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.58684858784016101846332309784763920398352762867005487704991780420312821597791
Short name T288
Test name
Test status
Simulation time 16600825 ps
CPU time 0.64 seconds
Started Nov 22 01:22:03 PM PST 23
Finished Nov 22 01:22:09 PM PST 23
Peak memory 202108 kb
Host smart-4b83ed3b-58dc-4db5-8785-e8f24ba545ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586848587840161018463323097847639203983527628670054877049917804203
12821597791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.586848587840161018463323097847639203983527628670054877
04991780420312821597791
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.17819049025391216405370851944927900538941563851745672714468895831784093053483
Short name T313
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.07 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:23:29 PM PST 23
Peak memory 202628 kb
Host smart-b8b72781-63aa-4f06-8a65-0e3a6248bec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819049025391216405370851944927900538941563851745672714468895831784093053483 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.17819049025391216405370851944927900538941563851745672714468895831784093053483
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.80846146577615822881418928147045792156230186067850062840403302067304612805862
Short name T495
Test name
Test status
Simulation time 23162112088 ps
CPU time 700.52 seconds
Started Nov 22 01:22:04 PM PST 23
Finished Nov 22 01:33:50 PM PST 23
Peak memory 364636 kb
Host smart-7d00947d-4315-4679-81fb-420233cbda10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80846146577615822881418928147045792156230186067850062840403302067304612805862 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.80846146577615822881418928147045792156230186067850062840403302067304612805862
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.100422980700716799987006678124412649455312357740389207568512204806464814166617
Short name T287
Test name
Test status
Simulation time 985753786 ps
CPU time 7.08 seconds
Started Nov 22 01:22:58 PM PST 23
Finished Nov 22 01:23:15 PM PST 23
Peak memory 213200 kb
Host smart-6d334841-1b76-4988-b023-1057052124b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100422980700716799987006678124412649455312357740389207568512204806464814166617 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.100422980700716799987006678124412649455312357740389207568512204806464814166617
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.41269102707212847844725691702677557924707461014960007085037009182358628272006
Short name T286
Test name
Test status
Simulation time 209242141 ps
CPU time 101.26 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 01:23:48 PM PST 23
Peak memory 351240 kb
Host smart-6b496087-4d9f-4259-8bf2-7521754e8f27
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126910270721284784472569170267755792470746101496000708
5037009182358628272006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_max_throughput.41269102707212847844725691702677557
924707461014960007085037009182358628272006
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1980347256926081547487536655518175738053831500739308263741012364283422148607
Short name T796
Test name
Test status
Simulation time 166171057 ps
CPU time 3.13 seconds
Started Nov 22 01:22:01 PM PST 23
Finished Nov 22 01:22:10 PM PST 23
Peak memory 215604 kb
Host smart-04b11591-e0b3-40e9-8fd7-9795b530a7ec
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803472569260815474875366555181757380538315007393082637410123642834
22148607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.1980347256926081547487536655518175738053831500739
308263741012364283422148607
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.19439901605094666804050846574529442141250967992016353408514804411077474555997
Short name T637
Test name
Test status
Simulation time 590810517 ps
CPU time 5.66 seconds
Started Nov 22 01:22:05 PM PST 23
Finished Nov 22 01:22:19 PM PST 23
Peak memory 202616 kb
Host smart-7876ff35-374b-4e39-a144-292a3b261062
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19439901605094666804050846574529442141250967992016353408514804411077474555997
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.19439901605094666804050846574529442141250967992016353408514804411077474555997
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.105086523562028213040328711520876805015566120481067810256897042425303896460042
Short name T555
Test name
Test status
Simulation time 21947461091 ps
CPU time 770.19 seconds
Started Nov 22 01:22:16 PM PST 23
Finished Nov 22 01:35:08 PM PST 23
Peak memory 371380 kb
Host smart-be3b609f-28e7-4d41-8aaa-901ee65785ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105086523562028213040328711520876805015566120481067810256897042425303896460042 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.105086523562028213040328711520876805015566120481067810256897042425303896460042
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.111295384242529868180451790565679535189660573261074046265742476294835509706558
Short name T626
Test name
Test status
Simulation time 445204539 ps
CPU time 12.79 seconds
Started Nov 22 01:22:04 PM PST 23
Finished Nov 22 01:22:22 PM PST 23
Peak memory 246476 kb
Host smart-d00a51eb-4795-4dd1-8076-cb62f0912594
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111295384242529868180451790565679535189660573261074046265742476294835
509706558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.11129538424252986818045179056567953518966057326107404
6265742476294835509706558
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.30294014216060535721808470786423769991093856719385043723296547117145036142654
Short name T762
Test name
Test status
Simulation time 42305619653 ps
CPU time 563.02 seconds
Started Nov 22 01:22:04 PM PST 23
Finished Nov 22 01:31:32 PM PST 23
Peak memory 202716 kb
Host smart-cfe2814f-bcba-49d1-9ccb-5df4feb3795f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302940142160605357218084707864237699910938567193850437232965471171450
36142654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access_b2b.3029401421606053572180847078642376999109
3856719385043723296547117145036142654
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.73351094351514731781885578376732813497002593415056181247456300403400741725557
Short name T148
Test name
Test status
Simulation time 40672061 ps
CPU time 0.82 seconds
Started Nov 22 01:23:23 PM PST 23
Finished Nov 22 01:23:35 PM PST 23
Peak memory 202596 kb
Host smart-8db7c30c-f976-4938-954e-4b2f74ab828e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73351094351514731781885578376732813497002593415056181247456300403400741725557 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.73351094351514731781885578376732813497002593415056181247456300403400741725557
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.39844845131640816048226203779187022299694747594340744551674539286471651363712
Short name T444
Test name
Test status
Simulation time 19383553031 ps
CPU time 463.46 seconds
Started Nov 22 01:23:01 PM PST 23
Finished Nov 22 01:30:56 PM PST 23
Peak memory 371820 kb
Host smart-7e86d94a-566a-4ab2-96bf-16da6344adb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39844845131640816048226203779187022299694747594340744551674539286471651363712 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.39844845131640816048226203779187022299694747594340744551674539286471651363712
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.54309977251195579813466209492556886571323989250452591849592246919812997104548
Short name T366
Test name
Test status
Simulation time 427865392 ps
CPU time 11.59 seconds
Started Nov 22 01:23:34 PM PST 23
Finished Nov 22 01:23:58 PM PST 23
Peak memory 246616 kb
Host smart-a37ff0ed-e705-4e3f-81e2-710894f1f18b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54309977251195579813466209492556886571323989250452591849592246919812997104548 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.54309977251195579813466209492556886571323989250452591849592246919812997104548
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.8534889157657062857609951604860279623950934353644604729621134073807287586878
Short name T403
Test name
Test status
Simulation time 121463254244 ps
CPU time 3301.16 seconds
Started Nov 22 01:22:29 PM PST 23
Finished Nov 22 02:17:35 PM PST 23
Peak memory 374800 kb
Host smart-4b2a71d4-590d-4127-aaec-08b4efd0c5fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853488915765706285760995160486027962395093435364460472962113407
3807287586878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.853488915765706285760995160486027962395093435364
4604729621134073807287586878
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.7909056555143456118223271645164128975816695203205498652619767357139711017363
Short name T857
Test name
Test status
Simulation time 624328106 ps
CPU time 1087.74 seconds
Started Nov 22 01:22:04 PM PST 23
Finished Nov 22 01:40:17 PM PST 23
Peak memory 401692 kb
Host smart-a97d5c0b-345c-449d-bbb9-da82f51d52cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=7909056555143456118223271645164128975816695203205498652619767357139711017363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sra
m_ctrl_stress_all_with_rand_reset.7909056555143456118223271645164128975816695203205498652619767357139711017363
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.73103885418266391479221257643274312602695324380218314567267029749870552235663
Short name T951
Test name
Test status
Simulation time 6491370455 ps
CPU time 350.96 seconds
Started Nov 22 01:22:47 PM PST 23
Finished Nov 22 01:28:51 PM PST 23
Peak memory 202668 kb
Host smart-c01cce5c-c3d4-4dbd-80cc-c7b3b5d0fd9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73103885418266391479221257643274312602695324380218314567267029749870552235663
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.731038854182663914792212576432743126026953243802183
14567267029749870552235663
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.17020313600907395829092436105276042510160113604744431982977231169786135520294
Short name T550
Test name
Test status
Simulation time 237420487 ps
CPU time 85.61 seconds
Started Nov 22 01:22:10 PM PST 23
Finished Nov 22 01:23:39 PM PST 23
Peak memory 351384 kb
Host smart-20fb33b8-3383-4b52-9e87-c43bb2a1bfd5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170203136009073958290924361052760425101601136047444319
82977231169786135520294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1702031360090739582909
2436105276042510160113604744431982977231169786135520294
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.31564923962581501935493118878237777986843202760704094704560995073551744363253
Short name T425
Test name
Test status
Simulation time 4471404472 ps
CPU time 609.64 seconds
Started Nov 22 01:24:12 PM PST 23
Finished Nov 22 01:34:26 PM PST 23
Peak memory 375008 kb
Host smart-b440ef1d-c47e-4ee6-9b36-59b0d74e7e23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31564923962581501935493118878237777986843202760704094704560995073551744363253
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during_key_req.315649239625815019354931188782377779868
43202760704094704560995073551744363253
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.58602967464169964596623410230023422027158434291091059774900796464195749252207
Short name T895
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:22:05 PM PST 23
Finished Nov 22 01:22:11 PM PST 23
Peak memory 202216 kb
Host smart-2ceb7b56-c3dd-473b-b3cc-9be8c11cdc22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586029674641699645966234102300234220271584342910910597749007964641
95749252207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.586029674641699645966234102300234220271584342910910597
74900796464195749252207
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.38143317090544258330935272428958268971564820081938305472104857059888107839332
Short name T42
Test name
Test status
Simulation time 9249473390 ps
CPU time 85.18 seconds
Started Nov 22 01:22:07 PM PST 23
Finished Nov 22 01:23:36 PM PST 23
Peak memory 202636 kb
Host smart-7da74ece-f706-4f71-a9af-9b01c397637d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38143317090544258330935272428958268971564820081938305472104857059888107839332 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.38143317090544258330935272428958268971564820081938305472104857059888107839332
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.42375984090776429069506654485708972917730023123997919561511986223463535698503
Short name T479
Test name
Test status
Simulation time 23162112088 ps
CPU time 699.06 seconds
Started Nov 22 01:22:04 PM PST 23
Finished Nov 22 01:33:48 PM PST 23
Peak memory 364436 kb
Host smart-cc0e5b08-dc8b-4b59-bec2-f19472c41c2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42375984090776429069506654485708972917730023123997919561511986223463535698503 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.42375984090776429069506654485708972917730023123997919561511986223463535698503
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.86444939092589841085728520730181556951282997669858202841261884994455733260507
Short name T257
Test name
Test status
Simulation time 985753786 ps
CPU time 7.18 seconds
Started Nov 22 01:22:03 PM PST 23
Finished Nov 22 01:22:16 PM PST 23
Peak memory 213224 kb
Host smart-fe682bf6-ece9-499f-80f3-be9ef0b394ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86444939092589841085728520730181556951282997669858202841261884994455733260507 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.86444939092589841085728520730181556951282997669858202841261884994455733260507
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.103197265519528553486701415013950878700699555370593931783337723850639789151439
Short name T405
Test name
Test status
Simulation time 209242141 ps
CPU time 94.7 seconds
Started Nov 22 01:24:10 PM PST 23
Finished Nov 22 01:25:49 PM PST 23
Peak memory 350168 kb
Host smart-184a4b43-1cca-4482-96d3-cb4c40d78fbe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031972655195285534867014150139508787006995553705939317
83337723850639789151439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_max_throughput.1031972655195285534867014150139508
78700699555370593931783337723850639789151439
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.32080709189762270589071028455430180884781450078491915175300131675449803089275
Short name T375
Test name
Test status
Simulation time 166171057 ps
CPU time 3.15 seconds
Started Nov 22 01:22:09 PM PST 23
Finished Nov 22 01:22:15 PM PST 23
Peak memory 215652 kb
Host smart-2858e104-3145-4f79-9a1e-96422e14c673
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32080709189762270589071028455430180884781450078491915175300131675449
803089275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.320807091897622705890710284554301808847814500784
91915175300131675449803089275
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.8379731663808512499682408493329142923316114021011187415862530765398379653105
Short name T575
Test name
Test status
Simulation time 590810517 ps
CPU time 5.11 seconds
Started Nov 22 01:24:11 PM PST 23
Finished Nov 22 01:24:19 PM PST 23
Peak memory 201660 kb
Host smart-c0689dd5-8c86-4ad7-9072-c6737e38de63
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8379731663808512499682408493329142923316114021011187415862530765398379653105 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.8379731663808512499682408493329142923316114021011187415862530765398379653105
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.101455597974810602425995611681992568350488905525716371398228553372793860601568
Short name T862
Test name
Test status
Simulation time 21947461091 ps
CPU time 650.17 seconds
Started Nov 22 01:23:00 PM PST 23
Finished Nov 22 01:34:01 PM PST 23
Peak memory 371272 kb
Host smart-61b3e143-6a5c-4020-b6f4-0f92e4f922cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101455597974810602425995611681992568350488905525716371398228553372793860601568 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.101455597974810602425995611681992568350488905525716371398228553372793860601568
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.29648555928088584321704118021679278934436693380971047907186429514118704015658
Short name T127
Test name
Test status
Simulation time 445204539 ps
CPU time 12.73 seconds
Started Nov 22 01:22:14 PM PST 23
Finished Nov 22 01:22:29 PM PST 23
Peak memory 246580 kb
Host smart-af04eb93-5ed5-410e-950b-1411297705d8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296485559280885843217041180216792789344366933809710479071864295141187
04015658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.296485559280885843217041180216792789344366933809710479
07186429514118704015658
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.13903408617780760771046638753693444723458046349074207262676404061605770791083
Short name T451
Test name
Test status
Simulation time 42305619653 ps
CPU time 535.44 seconds
Started Nov 22 01:22:13 PM PST 23
Finished Nov 22 01:31:12 PM PST 23
Peak memory 202712 kb
Host smart-4a3f4cb9-03a4-48ba-924b-d91c274601d2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139034086177807607710466387536934447234580463490742072626764040616057
70791083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access_b2b.1390340861778076077104663875369344472345
8046349074207262676404061605770791083
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.113816947058349316865769640655134204436988779489211379679602640095042525272192
Short name T954
Test name
Test status
Simulation time 40672061 ps
CPU time 0.87 seconds
Started Nov 22 01:23:23 PM PST 23
Finished Nov 22 01:23:36 PM PST 23
Peak memory 202600 kb
Host smart-848b3290-2ef0-43ad-9777-104d39cce871
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113816947058349316865769640655134204436988779489211379679602640095042525272192 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.113816947058349316865769640655134204436988779489211379679602640095042525272192
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.89246541396164360042788591805853185417678142698248966214585981430068104065318
Short name T681
Test name
Test status
Simulation time 19383553031 ps
CPU time 460.21 seconds
Started Nov 22 01:24:10 PM PST 23
Finished Nov 22 01:31:54 PM PST 23
Peak memory 370088 kb
Host smart-764d9cc8-31cd-490d-b3fc-e1afc6af0b71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89246541396164360042788591805853185417678142698248966214585981430068104065318 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.89246541396164360042788591805853185417678142698248966214585981430068104065318
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.59123655645937336625412507304573813468148404748144096724305021291029007637101
Short name T872
Test name
Test status
Simulation time 427865392 ps
CPU time 11.33 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:22:17 PM PST 23
Peak memory 246540 kb
Host smart-c2ca1ce2-7f66-4508-aace-0e5985e3403f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59123655645937336625412507304573813468148404748144096724305021291029007637101 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.59123655645937336625412507304573813468148404748144096724305021291029007637101
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.72400854488576152824533428044769779805398717950991977974340764539542073926779
Short name T434
Test name
Test status
Simulation time 121463254244 ps
CPU time 3708.09 seconds
Started Nov 22 01:22:38 PM PST 23
Finished Nov 22 02:24:32 PM PST 23
Peak memory 375308 kb
Host smart-14017e20-7232-46ec-b5fd-5525087a3fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724008544885761528245334280447697798053987179509919779743407645
39542073926779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.72400854488576152824533428044769779805398717950
991977974340764539542073926779
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1906671492047171774867015152152532660194828478658898651143510021526297041782
Short name T858
Test name
Test status
Simulation time 624328106 ps
CPU time 1114.46 seconds
Started Nov 22 01:22:12 PM PST 23
Finished Nov 22 01:40:49 PM PST 23
Peak memory 401824 kb
Host smart-6e916756-762a-4068-b874-13c497f5c394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1906671492047171774867015152152532660194828478658898651143510021526297041782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sra
m_ctrl_stress_all_with_rand_reset.1906671492047171774867015152152532660194828478658898651143510021526297041782
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.55680301074800501304394191407986437043839195336904758794029590172882115515934
Short name T91
Test name
Test status
Simulation time 6491370455 ps
CPU time 363.69 seconds
Started Nov 22 01:22:35 PM PST 23
Finished Nov 22 01:28:43 PM PST 23
Peak memory 202616 kb
Host smart-9168dbbb-3d1b-471c-80e8-4ef3140ce4c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55680301074800501304394191407986437043839195336904758794029590172882115515934
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.556803010748005013043941914079864370438391953369047
58794029590172882115515934
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4820659454883046737869942918410880640381327967671834364591452796694246109309
Short name T852
Test name
Test status
Simulation time 237420487 ps
CPU time 100.02 seconds
Started Nov 22 01:23:13 PM PST 23
Finished Nov 22 01:25:01 PM PST 23
Peak memory 351180 kb
Host smart-13e830ba-5fb9-4bab-bf55-f8a6551c6366
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482065945488304673786994291841088064038132796767183436
4591452796694246109309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.48206594548830467378699
42918410880640381327967671834364591452796694246109309
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1257295573244114658685340631845696318018631294334084203086830364227912889195
Short name T528
Test name
Test status
Simulation time 4471404472 ps
CPU time 719.68 seconds
Started Nov 22 01:22:18 PM PST 23
Finished Nov 22 01:34:20 PM PST 23
Peak memory 375504 kb
Host smart-2bb8111d-d95a-4538-9449-530b8893c37e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257295573244114658685340631845696318018631294334084203086830364227912889195
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during_key_req.1257295573244114658685340631845696318018
631294334084203086830364227912889195
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.6920490553983461572322697695781885693327477900841337525171508411648349294266
Short name T647
Test name
Test status
Simulation time 16600825 ps
CPU time 0.59 seconds
Started Nov 22 01:22:18 PM PST 23
Finished Nov 22 01:22:20 PM PST 23
Peak memory 202016 kb
Host smart-0ff56a81-df20-4493-a206-3b0b74e909d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692049055398346157232269769578188569332747790084133752517150841164
8349294266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.6920490553983461572322697695781885693327477900841337525
171508411648349294266
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.44832574429843675629438997093514091438137855885244640575056412494393414933574
Short name T641
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.3 seconds
Started Nov 22 01:22:10 PM PST 23
Finished Nov 22 01:23:37 PM PST 23
Peak memory 202600 kb
Host smart-1ffdada3-bf26-495b-830f-1cbfa7f070a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44832574429843675629438997093514091438137855885244640575056412494393414933574 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.44832574429843675629438997093514091438137855885244640575056412494393414933574
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.96287018328772306924553169795680313797215616659710831250540640238886812430188
Short name T122
Test name
Test status
Simulation time 23162112088 ps
CPU time 1133.58 seconds
Started Nov 22 01:22:13 PM PST 23
Finished Nov 22 01:41:09 PM PST 23
Peak memory 364616 kb
Host smart-4d6d0f1c-6a2a-4467-b037-cecebd4db2a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96287018328772306924553169795680313797215616659710831250540640238886812430188 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.96287018328772306924553169795680313797215616659710831250540640238886812430188
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.18712676115304527042195782572484960401299519260653489382339872615574857090427
Short name T785
Test name
Test status
Simulation time 985753786 ps
CPU time 6.95 seconds
Started Nov 22 01:22:13 PM PST 23
Finished Nov 22 01:22:23 PM PST 23
Peak memory 213188 kb
Host smart-314a95ff-f1dd-4371-b9de-f005cf3acba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18712676115304527042195782572484960401299519260653489382339872615574857090427 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.18712676115304527042195782572484960401299519260653489382339872615574857090427
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.19777354255259153583606094269396743452801890962490918104058262539598578040090
Short name T307
Test name
Test status
Simulation time 209242141 ps
CPU time 95.12 seconds
Started Nov 22 01:22:09 PM PST 23
Finished Nov 22 01:23:48 PM PST 23
Peak memory 351364 kb
Host smart-2a458235-4aec-4f38-af0a-0a12d6966214
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977735425525915358360609426939674345280189096249091810
4058262539598578040090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_max_throughput.19777354255259153583606094269396743
452801890962490918104058262539598578040090
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.24267759238678880586699732099875785724484909201745079663340507550222982856576
Short name T321
Test name
Test status
Simulation time 166171057 ps
CPU time 3.06 seconds
Started Nov 22 01:22:26 PM PST 23
Finished Nov 22 01:22:34 PM PST 23
Peak memory 215584 kb
Host smart-ea24a020-2a00-4c29-bcb2-1ddf0749ba01
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24267759238678880586699732099875785724484909201745079663340507550222
982856576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.242677592386788805866997320998757857244849092017
45079663340507550222982856576
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.105863781429238092730966095407721720307526246163741490518231968526915375847451
Short name T558
Test name
Test status
Simulation time 590810517 ps
CPU time 5.48 seconds
Started Nov 22 01:22:18 PM PST 23
Finished Nov 22 01:22:25 PM PST 23
Peak memory 202532 kb
Host smart-65b745a5-9b91-4ea1-a1f7-5076720096e9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105863781429238092730966095407721720307526246163741490518231968526915375847451
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.105863781429238092730966095407721720307526246163741490518231968526915375847451
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.93445375608957181691842287320470800223408091037366255365038261728687606386934
Short name T860
Test name
Test status
Simulation time 21947461091 ps
CPU time 769.24 seconds
Started Nov 22 01:22:19 PM PST 23
Finished Nov 22 01:35:11 PM PST 23
Peak memory 371220 kb
Host smart-b7e25a5f-a416-4e5f-bbd0-ef8af92384f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93445375608957181691842287320470800223408091037366255365038261728687606386934 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.93445375608957181691842287320470800223408091037366255365038261728687606386934
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.40666737399595951957750871431559455632620760509617608057379767797065725198522
Short name T357
Test name
Test status
Simulation time 445204539 ps
CPU time 14.07 seconds
Started Nov 22 01:22:05 PM PST 23
Finished Nov 22 01:22:24 PM PST 23
Peak memory 246564 kb
Host smart-fae5a546-8f34-4c76-a200-020b5a726a84
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406667373995959519577508714315594556326207605096176080573797677970657
25198522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.406667373995959519577508714315594556326207605096176080
57379767797065725198522
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.35055463217127148148857119907080821397615838283628509306826008521422817451140
Short name T878
Test name
Test status
Simulation time 42305619653 ps
CPU time 534.43 seconds
Started Nov 22 01:22:16 PM PST 23
Finished Nov 22 01:31:13 PM PST 23
Peak memory 202728 kb
Host smart-70bedc94-ad7f-4f1d-85b2-5c0658a4d555
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350554632171271481488571199070808213976158382836285093068260085214228
17451140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access_b2b.3505546321712714814885711990708082139761
5838283628509306826008521422817451140
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.31015990354002846304485019737698002850185134050043163071654231187896977474701
Short name T465
Test name
Test status
Simulation time 40672061 ps
CPU time 0.85 seconds
Started Nov 22 01:22:07 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 202632 kb
Host smart-9d7daba6-f125-4b04-8df2-9568cc0a17af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31015990354002846304485019737698002850185134050043163071654231187896977474701 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.31015990354002846304485019737698002850185134050043163071654231187896977474701
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.37679145472523666571799787572414993857439498120255072803614233663751156802808
Short name T921
Test name
Test status
Simulation time 19383553031 ps
CPU time 515.58 seconds
Started Nov 22 01:22:19 PM PST 23
Finished Nov 22 01:30:57 PM PST 23
Peak memory 371844 kb
Host smart-257608ab-25e7-4d72-ae02-f4dc2ddb2468
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37679145472523666571799787572414993857439498120255072803614233663751156802808 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.37679145472523666571799787572414993857439498120255072803614233663751156802808
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.16058947075567396008448477271423625561762336590300926193848442167762604889429
Short name T279
Test name
Test status
Simulation time 427865392 ps
CPU time 12.21 seconds
Started Nov 22 01:22:15 PM PST 23
Finished Nov 22 01:22:30 PM PST 23
Peak memory 246628 kb
Host smart-ba1cac41-aae1-444a-9ab9-12212801812d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16058947075567396008448477271423625561762336590300926193848442167762604889429 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.16058947075567396008448477271423625561762336590300926193848442167762604889429
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.44954429478169682118941313980481568007470133151353676984022902554051383307967
Short name T115
Test name
Test status
Simulation time 121463254244 ps
CPU time 3887.63 seconds
Started Nov 22 01:22:22 PM PST 23
Finished Nov 22 02:27:11 PM PST 23
Peak memory 375412 kb
Host smart-d77e2ab5-8090-4eb9-b5a7-053cf23651dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449544294781696821189413139804815680074701331513536769840229025
54051383307967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.44954429478169682118941313980481568007470133151
353676984022902554051383307967
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.52175711279610703611177863377192346055927995062280291848776657458626914561074
Short name T656
Test name
Test status
Simulation time 624328106 ps
CPU time 1306.57 seconds
Started Nov 22 01:22:15 PM PST 23
Finished Nov 22 01:44:04 PM PST 23
Peak memory 401708 kb
Host smart-e138f796-662a-48d0-b73b-a4476f7c9b83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=52175711279610703611177863377192346055927995062280291848776657458626914561074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sr
am_ctrl_stress_all_with_rand_reset.52175711279610703611177863377192346055927995062280291848776657458626914561074
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.21604106477201952070399193998285670358864892911229437644761230546283052210554
Short name T826
Test name
Test status
Simulation time 6491370455 ps
CPU time 338.35 seconds
Started Nov 22 01:24:13 PM PST 23
Finished Nov 22 01:29:55 PM PST 23
Peak memory 202192 kb
Host smart-fbbe0be5-3643-4d00-87d1-ff6c717f1015
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21604106477201952070399193998285670358864892911229437644761230546283052210554
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.216041064772019520703991939982856703588648929112294
37644761230546283052210554
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.97241822706274935514310403147633536675252650753919441651932112957302899781940
Short name T577
Test name
Test status
Simulation time 237420487 ps
CPU time 82.07 seconds
Started Nov 22 01:22:04 PM PST 23
Finished Nov 22 01:23:31 PM PST 23
Peak memory 351260 kb
Host smart-1d43cb1f-d14d-4da0-bfb9-1be13d6c2127
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972418227062749355143104031476335366752526507539194416
51932112957302899781940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.9724182270627493551431
0403147633536675252650753919441651932112957302899781940
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.96735809454164945566782552529305135350479828436213741031839035237174766239814
Short name T328
Test name
Test status
Simulation time 4471404472 ps
CPU time 827.34 seconds
Started Nov 22 01:21:28 PM PST 23
Finished Nov 22 01:35:24 PM PST 23
Peak memory 375496 kb
Host smart-367c19ee-62fb-4ff2-96f8-03a759b4a03a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96735809454164945566782552529305135350479828436213741031839035237174766239814
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_key_req.9673580945416494556678255252930513535047
9828436213741031839035237174766239814
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.105672312474726149877280895662723156162305709291310755540292631705697613754786
Short name T777
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 01:21:09 PM PST 23
Finished Nov 22 01:21:11 PM PST 23
Peak memory 202168 kb
Host smart-81f3e8d3-0864-488a-b76a-733b41936d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105672312474726149877280895662723156162305709291310755540292631705
697613754786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.105672312474726149877280895662723156162305709291310755
540292631705697613754786
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.75679624866838646689707607381781304499324220017302134359485518523600543711976
Short name T965
Test name
Test status
Simulation time 9249473390 ps
CPU time 79.46 seconds
Started Nov 22 01:20:52 PM PST 23
Finished Nov 22 01:22:16 PM PST 23
Peak memory 202560 kb
Host smart-940cf0c9-eab1-4acf-bac7-7fb5ea5ba2d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75679624866838646689707607381781304499324220017302134359485518523600543711976 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.75679624866838646689707607381781304499324220017302134359485518523600543711976
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.79988985918015173778150929008437944723397952386898363334386441198166365531591
Short name T545
Test name
Test status
Simulation time 23162112088 ps
CPU time 824.71 seconds
Started Nov 22 01:21:21 PM PST 23
Finished Nov 22 01:35:10 PM PST 23
Peak memory 364624 kb
Host smart-fdab5564-d299-41c2-bbc3-b2bae8b757f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79988985918015173778150929008437944723397952386898363334386441198166365531591 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.79988985918015173778150929008437944723397952386898363334386441198166365531591
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.66994285236785778622539584124901701101804409258609260929839803973519614106871
Short name T949
Test name
Test status
Simulation time 985753786 ps
CPU time 7.07 seconds
Started Nov 22 01:20:55 PM PST 23
Finished Nov 22 01:21:07 PM PST 23
Peak memory 213136 kb
Host smart-02389f9e-4d4c-42cd-9940-dcf7d7bb24bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66994285236785778622539584124901701101804409258609260929839803973519614106871 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.66994285236785778622539584124901701101804409258609260929839803973519614106871
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.6755474641088016919451192744583140257212865248369548404264843654387710132036
Short name T805
Test name
Test status
Simulation time 209242141 ps
CPU time 105.18 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:24:21 PM PST 23
Peak memory 351316 kb
Host smart-cba52228-2794-4156-bafb-5be1c1ea4bc2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6755474641088016919451192744583140257212865248369548404
264843654387710132036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max_throughput.6755474641088016919451192744583140257
212865248369548404264843654387710132036
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.13510526361221151424701902077379227678341356426960540368495302768486168949076
Short name T754
Test name
Test status
Simulation time 166171057 ps
CPU time 2.79 seconds
Started Nov 22 01:21:46 PM PST 23
Finished Nov 22 01:21:55 PM PST 23
Peak memory 215256 kb
Host smart-d24fe08f-e33e-4f60-a04f-4035ac54a89d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13510526361221151424701902077379227678341356426960540368495302768486
168949076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.1351052636122115142470190207737922767834135642696
0540368495302768486168949076
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.44342730148360012273335441633753263664095782860852531043831109968648259609638
Short name T758
Test name
Test status
Simulation time 590810517 ps
CPU time 5.65 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 202560 kb
Host smart-adfe0e57-6892-4d57-bb3f-1e4088c873f5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44342730148360012273335441633753263664095782860852531043831109968648259609638
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.44342730148360012273335441633753263664095782860852531043831109968648259609638
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.75320626026595857965232643305916155196676761366095854972820599258473304301518
Short name T382
Test name
Test status
Simulation time 21947461091 ps
CPU time 583.79 seconds
Started Nov 22 01:23:14 PM PST 23
Finished Nov 22 01:33:06 PM PST 23
Peak memory 371352 kb
Host smart-b96e7912-47ce-4874-b448-e26098160b72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75320626026595857965232643305916155196676761366095854972820599258473304301518 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.75320626026595857965232643305916155196676761366095854972820599258473304301518
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.67159750566313413841843390613611481498127892983067505115039822991657277224216
Short name T819
Test name
Test status
Simulation time 445204539 ps
CPU time 12.63 seconds
Started Nov 22 01:20:52 PM PST 23
Finished Nov 22 01:21:10 PM PST 23
Peak memory 246572 kb
Host smart-8cf03944-8bf3-4404-ace5-9e39e289ad7f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671597505663134138418433906136114814981278929830675051150398229916572
77224216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.6715975056631341384184339061361148149812789298306750511
5039822991657277224216
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.32763204743636201630839606011321713426683539616208660915130700152995996750488
Short name T998
Test name
Test status
Simulation time 42305619653 ps
CPU time 533.96 seconds
Started Nov 22 01:21:29 PM PST 23
Finished Nov 22 01:30:31 PM PST 23
Peak memory 202560 kb
Host smart-189c03ea-9973-44f0-88b3-152c21359518
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327632047436362016308396060113217134266835396162086609151307001529959
96750488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access_b2b.32763204743636201630839606011321713426683
539616208660915130700152995996750488
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.11828548536874172478924429321075210953542155756738961234939645572722719853916
Short name T266
Test name
Test status
Simulation time 40672061 ps
CPU time 0.84 seconds
Started Nov 22 01:21:06 PM PST 23
Finished Nov 22 01:21:09 PM PST 23
Peak memory 202612 kb
Host smart-b37c2a65-2046-4171-a113-9d09be490e74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11828548536874172478924429321075210953542155756738961234939645572722719853916 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.11828548536874172478924429321075210953542155756738961234939645572722719853916
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.45482692570671442147622260403438847152842269438387518170428662836435303545552
Short name T272
Test name
Test status
Simulation time 19383553031 ps
CPU time 503.44 seconds
Started Nov 22 01:20:54 PM PST 23
Finished Nov 22 01:29:23 PM PST 23
Peak memory 371840 kb
Host smart-75700d32-af93-4eb5-a318-fb3603956b73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45482692570671442147622260403438847152842269438387518170428662836435303545552 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.45482692570671442147622260403438847152842269438387518170428662836435303545552
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.90018739862516877329874270694872479676441507245956452353135153887618078208937
Short name T35
Test name
Test status
Simulation time 216402798 ps
CPU time 1.88 seconds
Started Nov 22 01:21:54 PM PST 23
Finished Nov 22 01:22:02 PM PST 23
Peak memory 220524 kb
Host smart-df925fa8-6f92-4232-81c0-caa5070ac39c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9001873986251687732987427069487247967644150724595645235313515388761
8078208937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.900187398625168773298742706948724796764415072459564523531351
53887618078208937
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.47165421386263485042414683117419161830623341712199046905524031919490301911135
Short name T41
Test name
Test status
Simulation time 427865392 ps
CPU time 11.66 seconds
Started Nov 22 01:20:54 PM PST 23
Finished Nov 22 01:21:11 PM PST 23
Peak memory 246608 kb
Host smart-2dd9601f-8aaf-44e7-878c-0dd9da000641
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47165421386263485042414683117419161830623341712199046905524031919490301911135 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.47165421386263485042414683117419161830623341712199046905524031919490301911135
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.90712573587014992942685948139094912368587370919395573338469649691831713416824
Short name T597
Test name
Test status
Simulation time 121463254244 ps
CPU time 2809.87 seconds
Started Nov 22 01:22:07 PM PST 23
Finished Nov 22 02:09:01 PM PST 23
Peak memory 375412 kb
Host smart-1aaa0992-61d7-4721-b2ea-9890da794b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907125735870149929426859481390949123685873709193955733384696496
91831713416824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.907125735870149929426859481390949123685873709193
95573338469649691831713416824
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.55031850908518188580003611162846253625983512526461652057230589159530174017027
Short name T927
Test name
Test status
Simulation time 624328106 ps
CPU time 1214.15 seconds
Started Nov 22 01:21:25 PM PST 23
Finished Nov 22 01:41:49 PM PST 23
Peak memory 401816 kb
Host smart-9e137362-5e97-44e6-b92e-6200247142bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=55031850908518188580003611162846253625983512526461652057230589159530174017027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sra
m_ctrl_stress_all_with_rand_reset.55031850908518188580003611162846253625983512526461652057230589159530174017027
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.71975708857813270318076952666631986990487965885374242689231707803081212711645
Short name T94
Test name
Test status
Simulation time 6491370455 ps
CPU time 359.24 seconds
Started Nov 22 01:20:57 PM PST 23
Finished Nov 22 01:27:01 PM PST 23
Peak memory 202680 kb
Host smart-740f10e4-d7e8-40d5-a056-2a0b8ce6cc7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71975708857813270318076952666631986990487965885374242689231707803081212711645
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.7197570885781327031807695266663198699048796588537424
2689231707803081212711645
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1840685081289534506975679063620551289631008694571309617799203808170180902206
Short name T297
Test name
Test status
Simulation time 237420487 ps
CPU time 85.71 seconds
Started Nov 22 01:20:55 PM PST 23
Finished Nov 22 01:22:26 PM PST 23
Peak memory 351340 kb
Host smart-088ba319-2fdd-4993-a279-b535477b4f2c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184068508128953450697567906362055128963100869457130961
7799203808170180902206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.184068508128953450697567
9063620551289631008694571309617799203808170180902206
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.67153761160578804632134823821817324137960030686327270864636546973494354808008
Short name T885
Test name
Test status
Simulation time 4471404472 ps
CPU time 731.25 seconds
Started Nov 22 01:22:40 PM PST 23
Finished Nov 22 01:34:57 PM PST 23
Peak memory 375504 kb
Host smart-03fab401-5150-44cf-87aa-d0be685ee3fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67153761160578804632134823821817324137960030686327270864636546973494354808008
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during_key_req.671537611605788046321348238218173241379
60030686327270864636546973494354808008
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.42716853479593261098580305445395997404190190288626340074637123742798868512778
Short name T870
Test name
Test status
Simulation time 16600825 ps
CPU time 0.59 seconds
Started Nov 22 01:22:42 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 202028 kb
Host smart-b009020f-4c90-45b4-b00e-f7b8f972b4bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427168534795932610985803054453959974041901902886263400746371237427
98868512778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.427168534795932610985803054453959974041901902886263400
74637123742798868512778
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.66209698887082511809704356090624787733562885592663455565796702218232319511791
Short name T114
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.95 seconds
Started Nov 22 01:22:08 PM PST 23
Finished Nov 22 01:23:35 PM PST 23
Peak memory 202640 kb
Host smart-a4e452e4-348e-4552-a3f6-f6ff3e923249
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66209698887082511809704356090624787733562885592663455565796702218232319511791 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.66209698887082511809704356090624787733562885592663455565796702218232319511791
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.81370272792579631566324389520701432651883299742492073476851101002518394578588
Short name T501
Test name
Test status
Simulation time 23162112088 ps
CPU time 813.56 seconds
Started Nov 22 01:22:28 PM PST 23
Finished Nov 22 01:36:06 PM PST 23
Peak memory 364660 kb
Host smart-157e1872-5b33-451f-bbfe-65bc705fdbf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81370272792579631566324389520701432651883299742492073476851101002518394578588 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.81370272792579631566324389520701432651883299742492073476851101002518394578588
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.100608547352060358925212440525064701983471475693909643577729233219688161577659
Short name T470
Test name
Test status
Simulation time 985753786 ps
CPU time 7.13 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 01:22:42 PM PST 23
Peak memory 213216 kb
Host smart-e1d5c5f8-1a85-4270-8e5e-52bd42fa3e65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100608547352060358925212440525064701983471475693909643577729233219688161577659 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.100608547352060358925212440525064701983471475693909643577729233219688161577659
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.1682619950175460338251678222671897948100600280052365166137558888210683934148
Short name T583
Test name
Test status
Simulation time 209242141 ps
CPU time 83.97 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 01:23:59 PM PST 23
Peak memory 351320 kb
Host smart-90b17dfb-f71b-49e5-a334-8141aeb4996d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682619950175460338251678222671897948100600280052365166
137558888210683934148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_max_throughput.168261995017546033825167822267189794
8100600280052365166137558888210683934148
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.394629778744663590191570621761763002412891541964378858056019700688494043163
Short name T320
Test name
Test status
Simulation time 166171057 ps
CPU time 3.24 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:22:28 PM PST 23
Peak memory 215728 kb
Host smart-db8484f5-82d7-48b8-8b8a-110b8a3982be
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39462977874466359019157062176176300241289154196437885805601970068849
4043163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.39462977874466359019157062176176300241289154196437
8858056019700688494043163
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.111227614850802910914050852502854554546887390312619558583261237739808123782806
Short name T353
Test name
Test status
Simulation time 590810517 ps
CPU time 5.66 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:22:32 PM PST 23
Peak memory 202552 kb
Host smart-58efd459-171e-4fd3-a3ba-01d463435f1d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111227614850802910914050852502854554546887390312619558583261237739808123782806
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.111227614850802910914050852502854554546887390312619558583261237739808123782806
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.99844583640225190388798048961368711758540233195375959469498349394162814113943
Short name T418
Test name
Test status
Simulation time 21947461091 ps
CPU time 659.45 seconds
Started Nov 22 01:22:18 PM PST 23
Finished Nov 22 01:33:20 PM PST 23
Peak memory 371272 kb
Host smart-0ac02bf8-341e-4f21-91ce-f82bab52d960
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99844583640225190388798048961368711758540233195375959469498349394162814113943 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.99844583640225190388798048961368711758540233195375959469498349394162814113943
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.26083631682655643198577306331909751048223474205500945505079701343028547901895
Short name T945
Test name
Test status
Simulation time 445204539 ps
CPU time 13.3 seconds
Started Nov 22 01:22:14 PM PST 23
Finished Nov 22 01:22:31 PM PST 23
Peak memory 246464 kb
Host smart-926f967d-afd1-4375-907f-e3166b9f2af2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260836316826556431985773063319097510482234742055009455050797013430285
47901895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.260836316826556431985773063319097510482234742055009455
05079701343028547901895
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.48141037378607230231127326729417631484600290717465877257236560469631153408555
Short name T917
Test name
Test status
Simulation time 42305619653 ps
CPU time 522.54 seconds
Started Nov 22 01:22:18 PM PST 23
Finished Nov 22 01:31:02 PM PST 23
Peak memory 202512 kb
Host smart-82aa64c1-03e3-40fe-ad97-35d70ddae571
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481410373786072302311273267294176314846002907174658772572365604696311
53408555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access_b2b.4814103737860723023112732672941763148460
0290717465877257236560469631153408555
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.26558155975833782653535466823795475469807422658685915519128665965079107759550
Short name T963
Test name
Test status
Simulation time 40672061 ps
CPU time 0.84 seconds
Started Nov 22 01:22:28 PM PST 23
Finished Nov 22 01:22:33 PM PST 23
Peak memory 202508 kb
Host smart-3dc282ac-fd92-4fa2-b0b5-b4230cca443d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26558155975833782653535466823795475469807422658685915519128665965079107759550 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.26558155975833782653535466823795475469807422658685915519128665965079107759550
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.19563222813730350586617621394072789511432722273562758979585873136252675141589
Short name T891
Test name
Test status
Simulation time 19383553031 ps
CPU time 493.8 seconds
Started Nov 22 01:22:36 PM PST 23
Finished Nov 22 01:30:55 PM PST 23
Peak memory 371764 kb
Host smart-0e259b36-ec11-4aae-b56a-5cf282b0f2c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19563222813730350586617621394072789511432722273562758979585873136252675141589 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.19563222813730350586617621394072789511432722273562758979585873136252675141589
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.30225773853225428726493512982221888225768401267029482574133331795931875374599
Short name T13
Test name
Test status
Simulation time 427865392 ps
CPU time 9.9 seconds
Started Nov 22 01:22:07 PM PST 23
Finished Nov 22 01:22:21 PM PST 23
Peak memory 246408 kb
Host smart-3219104e-299f-41d8-8064-cc150703650d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30225773853225428726493512982221888225768401267029482574133331795931875374599 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.30225773853225428726493512982221888225768401267029482574133331795931875374599
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.107371363673409180732562289059650466338623965486129749047486014317922008374665
Short name T402
Test name
Test status
Simulation time 121463254244 ps
CPU time 3372.79 seconds
Started Nov 22 01:22:49 PM PST 23
Finished Nov 22 02:19:16 PM PST 23
Peak memory 375464 kb
Host smart-a57d376f-ab3b-451f-8d38-e3c631a3ed8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107371363673409180732562289059650466338623965486129749047486014
317922008374665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.1073713636734091807325622890596504663386239654
86129749047486014317922008374665
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.64470667560178848035296263788710915799266219309296207854258209575258188808788
Short name T752
Test name
Test status
Simulation time 624328106 ps
CPU time 1009.04 seconds
Started Nov 22 01:22:22 PM PST 23
Finished Nov 22 01:39:13 PM PST 23
Peak memory 401788 kb
Host smart-ea7bd548-a082-4786-bdf4-9dfaca5c1d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=64470667560178848035296263788710915799266219309296207854258209575258188808788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sr
am_ctrl_stress_all_with_rand_reset.64470667560178848035296263788710915799266219309296207854258209575258188808788
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.47108113471646906402218163036120442095927677697565694481955708109346474255182
Short name T807
Test name
Test status
Simulation time 6491370455 ps
CPU time 368.94 seconds
Started Nov 22 01:22:19 PM PST 23
Finished Nov 22 01:28:30 PM PST 23
Peak memory 202632 kb
Host smart-0243186f-be24-4a66-8b57-bfad3f0a096e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47108113471646906402218163036120442095927677697565694481955708109346474255182
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.471081134716469064022181630361204420959276776975656
94481955708109346474255182
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.82997659036543847213273394015830681374989114152764316710165079075390422914508
Short name T791
Test name
Test status
Simulation time 237420487 ps
CPU time 81.77 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:23:48 PM PST 23
Peak memory 351296 kb
Host smart-0c203bab-ebb8-4bc9-bd70-911d2744fa96
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829976590365438472132733940158306813749891141527643167
10165079075390422914508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.8299765903654384721327
3394015830681374989114152764316710165079075390422914508
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.18027951393465319001445348507806117290274921925303412721847907726356538560467
Short name T715
Test name
Test status
Simulation time 4471404472 ps
CPU time 701.39 seconds
Started Nov 22 01:22:29 PM PST 23
Finished Nov 22 01:34:16 PM PST 23
Peak memory 375412 kb
Host smart-1342019c-c76d-4455-af30-ff0d9ea074b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18027951393465319001445348507806117290274921925303412721847907726356538560467
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during_key_req.180279513934653190014453485078061172902
74921925303412721847907726356538560467
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.30601382610315449133389715521942001200164827292855907766943785225867444369586
Short name T387
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 01:22:41 PM PST 23
Finished Nov 22 01:22:49 PM PST 23
Peak memory 202224 kb
Host smart-b7be786a-2614-4d5a-9354-8f9d1e9fa064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306013826103154491333897155219420012001648272928559077669437852258
67444369586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.306013826103154491333897155219420012001648272928559077
66943785225867444369586
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.13094114611336336255354568972446814458085717930528965784365576867104801457409
Short name T981
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.81 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:23:49 PM PST 23
Peak memory 202640 kb
Host smart-4cafdec0-a220-4f44-a28f-84ac4af89f3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13094114611336336255354568972446814458085717930528965784365576867104801457409 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.13094114611336336255354568972446814458085717930528965784365576867104801457409
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.43719911351554592105283918203265863446236256624424621647543694302589751152927
Short name T682
Test name
Test status
Simulation time 23162112088 ps
CPU time 815.33 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 01:36:10 PM PST 23
Peak memory 364660 kb
Host smart-7c78ab45-953f-4c5b-9c95-876474008aad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43719911351554592105283918203265863446236256624424621647543694302589751152927 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.43719911351554592105283918203265863446236256624424621647543694302589751152927
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.4874724070778952191539540442066464034596680587573624267055479885653078207039
Short name T419
Test name
Test status
Simulation time 985753786 ps
CPU time 7.13 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:22:43 PM PST 23
Peak memory 213184 kb
Host smart-c53277f2-87bd-4faa-8388-334ad810374d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4874724070778952191539540442066464034596680587573624267055479885653078207039 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.4874724070778952191539540442066464034596680587573624267055479885653078207039
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.102276814261736180976045509627409995138463027362705076460034719981756842487071
Short name T384
Test name
Test status
Simulation time 209242141 ps
CPU time 108.46 seconds
Started Nov 22 01:22:28 PM PST 23
Finished Nov 22 01:24:21 PM PST 23
Peak memory 351244 kb
Host smart-6af838d0-87de-4243-ba70-750ea585f91a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022768142617361809760455096274099951384630273627050764
60034719981756842487071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_max_throughput.1022768142617361809760455096274099
95138463027362705076460034719981756842487071
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.70958695650704793236443990014780495674490055794610668283547750797719118017062
Short name T345
Test name
Test status
Simulation time 166171057 ps
CPU time 3.12 seconds
Started Nov 22 01:22:24 PM PST 23
Finished Nov 22 01:22:30 PM PST 23
Peak memory 215712 kb
Host smart-cd37ec15-ec61-4472-8da1-bc86dfc03ff7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70958695650704793236443990014780495674490055794610668283547750797719
118017062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.709586956507047932364439900147804956744900557946
10668283547750797719118017062
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.47089482314085837834927337148067265204741201656980449045224425306678883519790
Short name T133
Test name
Test status
Simulation time 590810517 ps
CPU time 5.31 seconds
Started Nov 22 01:24:13 PM PST 23
Finished Nov 22 01:24:22 PM PST 23
Peak memory 202104 kb
Host smart-424d10b2-99d1-4567-9d70-c932430c738a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47089482314085837834927337148067265204741201656980449045224425306678883519790
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.47089482314085837834927337148067265204741201656980449045224425306678883519790
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.41955097194110280930358204614542211765641798002545504078585769130120086484576
Short name T544
Test name
Test status
Simulation time 21947461091 ps
CPU time 773.42 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:35:29 PM PST 23
Peak memory 371412 kb
Host smart-86f45b03-c29f-41ae-a153-7a3038667705
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41955097194110280930358204614542211765641798002545504078585769130120086484576 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.41955097194110280930358204614542211765641798002545504078585769130120086484576
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.99612169851617651241484630015006931101874383736797794821984665451481882486160
Short name T14
Test name
Test status
Simulation time 445204539 ps
CPU time 13.8 seconds
Started Nov 22 01:22:28 PM PST 23
Finished Nov 22 01:22:47 PM PST 23
Peak memory 246584 kb
Host smart-5c8eaf7c-5180-4004-996e-520cee459f2d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996121698516176512414846300150069311018743837367977948219846654514818
82486160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.996121698516176512414846300150069311018743837367977948
21984665451481882486160
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.108501634093600549896264117295391849352094156490731532437216202419874938412268
Short name T1014
Test name
Test status
Simulation time 42305619653 ps
CPU time 535.93 seconds
Started Nov 22 01:22:22 PM PST 23
Finished Nov 22 01:31:20 PM PST 23
Peak memory 202680 kb
Host smart-ee3426f1-ba60-41f2-93c6-4ac0266ccb2b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108501634093600549896264117295391849352094156490731532437216202419874
938412268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access_b2b.108501634093600549896264117295391849352
094156490731532437216202419874938412268
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.108398352542827453207660639241258583111054006077525867886337815456415659383711
Short name T515
Test name
Test status
Simulation time 40672061 ps
CPU time 0.93 seconds
Started Nov 22 01:22:24 PM PST 23
Finished Nov 22 01:22:29 PM PST 23
Peak memory 202400 kb
Host smart-bc88bcb6-f3e0-4236-b916-8c00fd32ecdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108398352542827453207660639241258583111054006077525867886337815456415659383711 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.108398352542827453207660639241258583111054006077525867886337815456415659383711
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.38964484276615915237315991827491519459532187448286639800404315383332851959651
Short name T877
Test name
Test status
Simulation time 19383553031 ps
CPU time 609.29 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:32:35 PM PST 23
Peak memory 371700 kb
Host smart-7aac5c48-1960-4b39-89c0-b9c2e4b8e915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38964484276615915237315991827491519459532187448286639800404315383332851959651 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.38964484276615915237315991827491519459532187448286639800404315383332851959651
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.24886929557943644580275989602934648888053886256782835391982286231730729214419
Short name T916
Test name
Test status
Simulation time 427865392 ps
CPU time 12.28 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:22:41 PM PST 23
Peak memory 246552 kb
Host smart-c8d9e8cf-1b2a-4612-a7b3-80e99100ab4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24886929557943644580275989602934648888053886256782835391982286231730729214419 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.24886929557943644580275989602934648888053886256782835391982286231730729214419
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.113516623056935847429676479844138386318176478545174517255353131331659848684764
Short name T950
Test name
Test status
Simulation time 121463254244 ps
CPU time 3685.85 seconds
Started Nov 22 01:22:24 PM PST 23
Finished Nov 22 02:23:55 PM PST 23
Peak memory 375380 kb
Host smart-880b13d5-03ff-4fa2-82f8-ab23e26ccf2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113516623056935847429676479844138386318176478545174517255353131
331659848684764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.1135166230569358474296764798441383863181764785
45174517255353131331659848684764
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.16776838060477523121894537745347088066982635387990412622831157766561225621437
Short name T439
Test name
Test status
Simulation time 624328106 ps
CPU time 1326.67 seconds
Started Nov 22 01:22:22 PM PST 23
Finished Nov 22 01:44:31 PM PST 23
Peak memory 401760 kb
Host smart-ac1daac3-68f2-4cff-b5ca-4661ceca49ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=16776838060477523121894537745347088066982635387990412622831157766561225621437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sr
am_ctrl_stress_all_with_rand_reset.16776838060477523121894537745347088066982635387990412622831157766561225621437
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.69819206460832710346729696302604204843889773269420574387068926832847262571980
Short name T972
Test name
Test status
Simulation time 6491370455 ps
CPU time 361.41 seconds
Started Nov 22 01:22:27 PM PST 23
Finished Nov 22 01:28:33 PM PST 23
Peak memory 202596 kb
Host smart-e2275c6d-8940-498d-abfd-f081b213a23d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69819206460832710346729696302604204843889773269420574387068926832847262571980
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.698192064608327103467296963026042048438897732694205
74387068926832847262571980
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.35310341992366259437045443541697629940348295780820108620636002864853065333015
Short name T664
Test name
Test status
Simulation time 237420487 ps
CPU time 93.94 seconds
Started Nov 22 01:23:10 PM PST 23
Finished Nov 22 01:24:53 PM PST 23
Peak memory 351360 kb
Host smart-6509912b-1078-4d66-a3a8-0ab4599e34ed
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353103419923662594370454435416976299403482957808201086
20636002864853065333015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.3531034199236625943704
5443541697629940348295780820108620636002864853065333015
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.33778926271562918523284838347564528490678464293331796185108228485265616920329
Short name T1029
Test name
Test status
Simulation time 4471404472 ps
CPU time 867.47 seconds
Started Nov 22 01:22:24 PM PST 23
Finished Nov 22 01:36:56 PM PST 23
Peak memory 375504 kb
Host smart-361167cc-3d81-4271-9293-a685ca6aea77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33778926271562918523284838347564528490678464293331796185108228485265616920329
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during_key_req.337789262715629185232848383475645284906
78464293331796185108228485265616920329
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.10681104689051060778361663770339244701424206261986950917248696583233716972715
Short name T726
Test name
Test status
Simulation time 16600825 ps
CPU time 0.63 seconds
Started Nov 22 01:22:56 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 202224 kb
Host smart-be3ede4d-d5bb-41a8-b3ba-c2fb494f9892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106811046890510607783616637703392447014242062619869509172486965832
33716972715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.106811046890510607783616637703392447014242062619869509
17248696583233716972715
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.85418018533006769086944640541789746968001124895756132365728881546875650633666
Short name T406
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.35 seconds
Started Nov 22 01:22:40 PM PST 23
Finished Nov 22 01:24:09 PM PST 23
Peak memory 202636 kb
Host smart-0f1533db-91c6-4acc-8058-a5aaf8601ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85418018533006769086944640541789746968001124895756132365728881546875650633666 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.85418018533006769086944640541789746968001124895756132365728881546875650633666
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.9740382114373206947392754368835889072663368179262818855709027234917308199746
Short name T489
Test name
Test status
Simulation time 23162112088 ps
CPU time 790.4 seconds
Started Nov 22 01:22:58 PM PST 23
Finished Nov 22 01:36:18 PM PST 23
Peak memory 364620 kb
Host smart-be46667a-227a-4f53-8fc2-97cb06406015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9740382114373206947392754368835889072663368179262818855709027234917308199746 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.9740382114373206947392754368835889072663368179262818855709027234917308199746
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.94552566641777646367871917346045292006632130303539846895427696015603914447212
Short name T319
Test name
Test status
Simulation time 985753786 ps
CPU time 7.15 seconds
Started Nov 22 01:22:50 PM PST 23
Finished Nov 22 01:23:12 PM PST 23
Peak memory 213188 kb
Host smart-cd0c1b6b-51a1-4fc5-9734-e25c3d0597fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94552566641777646367871917346045292006632130303539846895427696015603914447212 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.94552566641777646367871917346045292006632130303539846895427696015603914447212
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.114479491557244038488223571421644361871069708808181856485568894221096399802528
Short name T517
Test name
Test status
Simulation time 209242141 ps
CPU time 97.72 seconds
Started Nov 22 01:22:23 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 351232 kb
Host smart-32ff52ce-25ea-4b24-9951-41149c695480
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144794915572440384882235714216443618710697088081818564
85568894221096399802528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_max_throughput.1144794915572440384882235714216443
61871069708808181856485568894221096399802528
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.83887632815976751157831823402889388460388218462482823374113481564565805529564
Short name T918
Test name
Test status
Simulation time 166171057 ps
CPU time 3.13 seconds
Started Nov 22 01:23:11 PM PST 23
Finished Nov 22 01:23:22 PM PST 23
Peak memory 215712 kb
Host smart-cfcef5c1-ad04-4cd2-bccd-0b2c58f4d7f7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83887632815976751157831823402889388460388218462482823374113481564565
805529564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.838876328159767511578318234028893884603882184624
82823374113481564565805529564
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.3695186736745291917591193907881032441571415887874615391691883095563508857402
Short name T107
Test name
Test status
Simulation time 590810517 ps
CPU time 5.62 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 01:22:41 PM PST 23
Peak memory 202592 kb
Host smart-e2aa762f-9759-436f-9e37-463dcd6c9a63
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695186736745291917591193907881032441571415887874615391691883095563508857402 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.3695186736745291917591193907881032441571415887874615391691883095563508857402
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.108173441743873041969335034732688561403679586825091594601181319952905914570170
Short name T766
Test name
Test status
Simulation time 21947461091 ps
CPU time 626.94 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:32:56 PM PST 23
Peak memory 371240 kb
Host smart-7a45a8d6-3470-478c-b0e9-5ab32b1007a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108173441743873041969335034732688561403679586825091594601181319952905914570170 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.108173441743873041969335034732688561403679586825091594601181319952905914570170
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.56498444243400963256161289005055183535808963979515645890393715943096095526068
Short name T389
Test name
Test status
Simulation time 445204539 ps
CPU time 11.64 seconds
Started Nov 22 01:22:26 PM PST 23
Finished Nov 22 01:22:42 PM PST 23
Peak memory 246424 kb
Host smart-fbc8e5af-a3cb-4755-8823-8f7b7a960c31
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564984442434009632561612890050551835358089639795156458903937159430960
95526068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.564984442434009632561612890050551835358089639795156458
90393715943096095526068
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.80959526538269950109321416831678405088832592401596050511323708158539244527382
Short name T374
Test name
Test status
Simulation time 42305619653 ps
CPU time 538.68 seconds
Started Nov 22 01:22:19 PM PST 23
Finished Nov 22 01:31:20 PM PST 23
Peak memory 202556 kb
Host smart-c6033fca-2307-4187-bfca-9e62143ec209
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809595265382699501093214168316784050888325924015960505113237081585392
44527382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access_b2b.8095952653826995010932141683167840508883
2592401596050511323708158539244527382
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.26448548979429278671909339371304218001755400605874039942941990086730360286881
Short name T315
Test name
Test status
Simulation time 40672061 ps
CPU time 0.81 seconds
Started Nov 22 01:22:45 PM PST 23
Finished Nov 22 01:22:58 PM PST 23
Peak memory 202488 kb
Host smart-acd393bf-dcbf-4fca-aa80-788186dcbb82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26448548979429278671909339371304218001755400605874039942941990086730360286881 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.26448548979429278671909339371304218001755400605874039942941990086730360286881
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.78400590524365406715718855517060390005463933443412169110034547007782981705387
Short name T611
Test name
Test status
Simulation time 19383553031 ps
CPU time 594.74 seconds
Started Nov 22 01:22:21 PM PST 23
Finished Nov 22 01:32:18 PM PST 23
Peak memory 371776 kb
Host smart-3330a2cf-a4b1-40ae-afaf-853fdef3a484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78400590524365406715718855517060390005463933443412169110034547007782981705387 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.78400590524365406715718855517060390005463933443412169110034547007782981705387
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.78356865569623951381747132859430568797923992520641395100153092436327084562948
Short name T751
Test name
Test status
Simulation time 427865392 ps
CPU time 11.25 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:23:18 PM PST 23
Peak memory 246028 kb
Host smart-7eb4dfaa-29dd-40e8-8193-54af0754d722
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78356865569623951381747132859430568797923992520641395100153092436327084562948 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.78356865569623951381747132859430568797923992520641395100153092436327084562948
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.106484967865010381324047963866373136384926946229969982434506140354842900306603
Short name T291
Test name
Test status
Simulation time 121463254244 ps
CPU time 3018.71 seconds
Started Nov 22 01:23:23 PM PST 23
Finished Nov 22 02:13:53 PM PST 23
Peak memory 375400 kb
Host smart-9d3f1d60-4671-48a0-a294-0e73f9969b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106484967865010381324047963866373136384926946229969982434506140
354842900306603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.1064849678650103813240479638663731363849269462
29969982434506140354842900306603
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.25488888257095237512278335044303526564856350236626303081084972114388428794148
Short name T475
Test name
Test status
Simulation time 624328106 ps
CPU time 1418.21 seconds
Started Nov 22 01:22:57 PM PST 23
Finished Nov 22 01:46:46 PM PST 23
Peak memory 401824 kb
Host smart-1838aeed-90e9-4a30-b18a-553171ef275a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=25488888257095237512278335044303526564856350236626303081084972114388428794148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sr
am_ctrl_stress_all_with_rand_reset.25488888257095237512278335044303526564856350236626303081084972114388428794148
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.4730286989779124310790305643566194536677240214385341487936215427795392778648
Short name T4
Test name
Test status
Simulation time 6491370455 ps
CPU time 357.2 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:28:27 PM PST 23
Peak memory 202640 kb
Host smart-cb941bef-1d4c-4ec1-bfde-6927b29af40c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4730286989779124310790305643566194536677240214385341487936215427795392778648
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.4730286989779124310790305643566194536677240214385341
487936215427795392778648
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.112453491784373488818279515682763033175080958816564734133499355161745020328539
Short name T129
Test name
Test status
Simulation time 237420487 ps
CPU time 94.42 seconds
Started Nov 22 01:22:47 PM PST 23
Finished Nov 22 01:24:35 PM PST 23
Peak memory 351384 kb
Host smart-ff7e4a7f-6c6d-487b-bd89-d6a7c40d8e21
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112453491784373488818279515682763033175080958816564734
133499355161745020328539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.112453491784373488818
279515682763033175080958816564734133499355161745020328539
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.750726238201773112868081618269998046415777230905376076281628372564614905101
Short name T804
Test name
Test status
Simulation time 4471404472 ps
CPU time 594.35 seconds
Started Nov 22 01:22:49 PM PST 23
Finished Nov 22 01:32:57 PM PST 23
Peak memory 375360 kb
Host smart-5124f115-4899-4c8a-bee0-d1d676262d1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750726238201773112868081618269998046415777230905376076281628372564614905101 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during_key_req.75072623820177311286808161826999804641577
7230905376076281628372564614905101
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.60788355655936553044825710050831141631073632728571686419453128121806706908744
Short name T674
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:23:07 PM PST 23
Peak memory 202148 kb
Host smart-305d3391-23bf-4fee-b351-876b0d0ab701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607883556559365530448257100508311416310736327285716864194531281218
06706908744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.607883556559365530448257100508311416310736327285716864
19453128121806706908744
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.110562317324218671820284544799763712243519167401066472877982970635826196051217
Short name T332
Test name
Test status
Simulation time 9249473390 ps
CPU time 81.26 seconds
Started Nov 22 01:22:29 PM PST 23
Finished Nov 22 01:23:55 PM PST 23
Peak memory 202608 kb
Host smart-bd8b5135-e587-415a-a50f-56ddc52f8736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110562317324218671820284544799763712243519167401066472877982970635826196051217 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.110562317324218671820284544799763712243519167401066472877982970635826196051217
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.50096149546003490522942320138989922796868808756130272067332254150101177781323
Short name T530
Test name
Test status
Simulation time 23162112088 ps
CPU time 727.62 seconds
Started Nov 22 01:23:20 PM PST 23
Finished Nov 22 01:35:38 PM PST 23
Peak memory 364652 kb
Host smart-9dab4323-f328-468c-8960-59c4105e3ce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50096149546003490522942320138989922796868808756130272067332254150101177781323 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.50096149546003490522942320138989922796868808756130272067332254150101177781323
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.114024474851946572366251912193020356058610571263358156273086122635342735383201
Short name T673
Test name
Test status
Simulation time 985753786 ps
CPU time 7.3 seconds
Started Nov 22 01:23:22 PM PST 23
Finished Nov 22 01:23:40 PM PST 23
Peak memory 213088 kb
Host smart-edaab31c-db84-4ddf-87a6-57cc6b7def5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114024474851946572366251912193020356058610571263358156273086122635342735383201 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.114024474851946572366251912193020356058610571263358156273086122635342735383201
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.58546374884310576947340248932801967099554961846341558211024693409617010151173
Short name T939
Test name
Test status
Simulation time 209242141 ps
CPU time 89.4 seconds
Started Nov 22 01:22:47 PM PST 23
Finished Nov 22 01:24:29 PM PST 23
Peak memory 351352 kb
Host smart-c0dfe2c8-8f37-4e60-b7b6-503daaa210fa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5854637488431057694734024893280196709955496184634155821
1024693409617010151173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_max_throughput.58546374884310576947340248932801967
099554961846341558211024693409617010151173
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.19401918232351504331144778796044188168718921776615402763767290680932502680823
Short name T957
Test name
Test status
Simulation time 166171057 ps
CPU time 3.04 seconds
Started Nov 22 01:22:42 PM PST 23
Finished Nov 22 01:22:51 PM PST 23
Peak memory 215700 kb
Host smart-0b15f7db-0a81-41cc-868c-bc0a3f370a1c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19401918232351504331144778796044188168718921776615402763767290680932
502680823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.194019182323515043311447787960441881687189217766
15402763767290680932502680823
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.17030683601486414604686960397915615393439051534478587437214733238287532896370
Short name T322
Test name
Test status
Simulation time 590810517 ps
CPU time 5.38 seconds
Started Nov 22 01:22:44 PM PST 23
Finished Nov 22 01:23:01 PM PST 23
Peak memory 202568 kb
Host smart-36b60906-a29d-4f15-91a2-dc1c0f572f51
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17030683601486414604686960397915615393439051534478587437214733238287532896370
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.17030683601486414604686960397915615393439051534478587437214733238287532896370
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.66199559407240464116415393617885577744067287214908858149374749782809656154071
Short name T798
Test name
Test status
Simulation time 21947461091 ps
CPU time 698.02 seconds
Started Nov 22 01:22:19 PM PST 23
Finished Nov 22 01:33:59 PM PST 23
Peak memory 371412 kb
Host smart-62493045-4459-4bf4-aee5-e815361a90aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66199559407240464116415393617885577744067287214908858149374749782809656154071 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.66199559407240464116415393617885577744067287214908858149374749782809656154071
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.79569967107606785559479192343080221656037861268850632040518709475123196942879
Short name T606
Test name
Test status
Simulation time 445204539 ps
CPU time 14.24 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 246624 kb
Host smart-7ce8692a-a404-4db2-b864-b0a4e8f861ce
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795699671076067855594791923430802216560378612688506320405187094751231
96942879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.795699671076067855594791923430802216560378612688506320
40518709475123196942879
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.65149939642701177838102629993834243476956089440431585632943955981393692358083
Short name T896
Test name
Test status
Simulation time 42305619653 ps
CPU time 551.65 seconds
Started Nov 22 01:23:22 PM PST 23
Finished Nov 22 01:32:44 PM PST 23
Peak memory 202692 kb
Host smart-7b678b87-5104-4cdd-9d81-952e39f870ab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651499396427011778381026299938342434769560894404315856329439559813936
92358083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access_b2b.6514993964270117783810262999383424347695
6089440431585632943955981393692358083
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.7904021141244889601683473664583552123524622161927346748431920194274815672551
Short name T790
Test name
Test status
Simulation time 40672061 ps
CPU time 0.85 seconds
Started Nov 22 01:22:42 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 202320 kb
Host smart-43acb656-4481-465e-b07f-f5fe9cb922ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7904021141244889601683473664583552123524622161927346748431920194274815672551 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.7904021141244889601683473664583552123524622161927346748431920194274815672551
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.115363977783405376774400749958068672413345126611447505898583379149611502434843
Short name T484
Test name
Test status
Simulation time 19383553031 ps
CPU time 536.64 seconds
Started Nov 22 01:23:25 PM PST 23
Finished Nov 22 01:32:37 PM PST 23
Peak memory 371812 kb
Host smart-2914a06b-84f1-4f88-96f3-ab64085ce62c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115363977783405376774400749958068672413345126611447505898583379149611502434843 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.115363977783405376774400749958068672413345126611447505898583379149611502434843
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.31010364841065641483416329330568140884094282493873061293509616062705378801322
Short name T630
Test name
Test status
Simulation time 427865392 ps
CPU time 12.46 seconds
Started Nov 22 01:22:38 PM PST 23
Finished Nov 22 01:22:56 PM PST 23
Peak memory 246580 kb
Host smart-e12f37be-b3c5-4fb5-80e3-a1b8deb39e8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31010364841065641483416329330568140884094282493873061293509616062705378801322 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.31010364841065641483416329330568140884094282493873061293509616062705378801322
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.50693594166069433349667626457425129305586475398550601882138746181231857170639
Short name T800
Test name
Test status
Simulation time 121463254244 ps
CPU time 3086.3 seconds
Started Nov 22 01:22:42 PM PST 23
Finished Nov 22 02:14:15 PM PST 23
Peak memory 375444 kb
Host smart-2b719e4b-8218-4d57-944f-c600a2319a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506935941660694333496676264574251293055864753985506018821387461
81231857170639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.50693594166069433349667626457425129305586475398
550601882138746181231857170639
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.52198656579954140436613595283778747906094485706062031237091449206326738432012
Short name T887
Test name
Test status
Simulation time 624328106 ps
CPU time 1325.38 seconds
Started Nov 22 01:22:37 PM PST 23
Finished Nov 22 01:44:47 PM PST 23
Peak memory 401816 kb
Host smart-d5e88cf6-c66e-4a00-b5c5-d64797d1490f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=52198656579954140436613595283778747906094485706062031237091449206326738432012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sr
am_ctrl_stress_all_with_rand_reset.52198656579954140436613595283778747906094485706062031237091449206326738432012
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.56523156200027603815593174863264181581553642497011912080510432891995352766306
Short name T376
Test name
Test status
Simulation time 6491370455 ps
CPU time 360.46 seconds
Started Nov 22 01:22:58 PM PST 23
Finished Nov 22 01:29:08 PM PST 23
Peak memory 202584 kb
Host smart-55bb71a8-ee61-419e-b776-273a0c0b83bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56523156200027603815593174863264181581553642497011912080510432891995352766306
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.565231562000276038155931748632641815815536424970119
12080510432891995352766306
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.60532744262632131955456028347931623453296497322954179499971869502501373599321
Short name T445
Test name
Test status
Simulation time 237420487 ps
CPU time 82.57 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:23:58 PM PST 23
Peak memory 351380 kb
Host smart-f8d32c4e-f7d6-4fca-8616-0cb5a3c1f865
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605327442626321319554560283479316234532964973229541794
99971869502501373599321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.6053274426263213195545
6028347931623453296497322954179499971869502501373599321
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.35044528018834678205149351381305418368950485118888792083548601488788182677430
Short name T459
Test name
Test status
Simulation time 4471404472 ps
CPU time 740.05 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:34:59 PM PST 23
Peak memory 375472 kb
Host smart-7357a291-8c0d-4d87-a02d-4807968aa26d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35044528018834678205149351381305418368950485118888792083548601488788182677430
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during_key_req.350445280188346782051493513813054183689
50485118888792083548601488788182677430
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.98251949966227117981264513696724253338603835171511312170706441236066639146076
Short name T639
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:22:53 PM PST 23
Finished Nov 22 01:23:07 PM PST 23
Peak memory 202148 kb
Host smart-d8cd2952-c4c9-463c-897a-5053cedf1a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982519499662271179812645136967242533386038351715113121707064412360
66639146076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.982519499662271179812645136967242533386038351715113121
70706441236066639146076
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.76314536683121692714600170033167113323721011238055957502355653740613124298411
Short name T720
Test name
Test status
Simulation time 9249473390 ps
CPU time 78.98 seconds
Started Nov 22 01:24:11 PM PST 23
Finished Nov 22 01:25:33 PM PST 23
Peak memory 202016 kb
Host smart-25219963-27e1-4ff1-bcff-beca7f8e7950
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76314536683121692714600170033167113323721011238055957502355653740613124298411 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.76314536683121692714600170033167113323721011238055957502355653740613124298411
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.37756277380668475842236878787661931887598927597764397957932836330432028863309
Short name T763
Test name
Test status
Simulation time 23162112088 ps
CPU time 835.8 seconds
Started Nov 22 01:22:47 PM PST 23
Finished Nov 22 01:36:56 PM PST 23
Peak memory 364652 kb
Host smart-d86d34a3-c711-4592-8726-5e08621de9f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37756277380668475842236878787661931887598927597764397957932836330432028863309 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.37756277380668475842236878787661931887598927597764397957932836330432028863309
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.67688649650792343254566134228176713078101181672836226540055281658710153999071
Short name T1015
Test name
Test status
Simulation time 985753786 ps
CPU time 7.12 seconds
Started Nov 22 01:22:44 PM PST 23
Finished Nov 22 01:23:03 PM PST 23
Peak memory 213256 kb
Host smart-5bad3d88-f760-4a03-bd63-856aba8b7c4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67688649650792343254566134228176713078101181672836226540055281658710153999071 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.67688649650792343254566134228176713078101181672836226540055281658710153999071
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.5358985461164627858230636576545334499186449072788200265595269604149130596804
Short name T713
Test name
Test status
Simulation time 209242141 ps
CPU time 82.13 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:24:29 PM PST 23
Peak memory 351292 kb
Host smart-2a6c8969-fddc-4fa1-8822-5fd34cffb7a3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5358985461164627858230636576545334499186449072788200265
595269604149130596804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_max_throughput.535898546116462785823063657654533449
9186449072788200265595269604149130596804
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.28438211409806528256579038732720439522451830108492414824961956279665883188259
Short name T675
Test name
Test status
Simulation time 166171057 ps
CPU time 3.14 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:22:42 PM PST 23
Peak memory 215680 kb
Host smart-0eb5aa1a-4d4a-411e-ab08-f4c42c2173fd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28438211409806528256579038732720439522451830108492414824961956279665
883188259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.284382114098065282565790387327204395224518301084
92414824961956279665883188259
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.79223280595900798028099715990592356156559300528436205376167134330267448365762
Short name T665
Test name
Test status
Simulation time 590810517 ps
CPU time 5.6 seconds
Started Nov 22 01:23:00 PM PST 23
Finished Nov 22 01:23:14 PM PST 23
Peak memory 202604 kb
Host smart-f1acebd0-c59a-488d-b2b9-1c579739e0ab
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79223280595900798028099715990592356156559300528436205376167134330267448365762
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.79223280595900798028099715990592356156559300528436205376167134330267448365762
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.34815341044358832274682557015148299281969762016986168853571594308001785683659
Short name T339
Test name
Test status
Simulation time 21947461091 ps
CPU time 642.7 seconds
Started Nov 22 01:22:47 PM PST 23
Finished Nov 22 01:33:43 PM PST 23
Peak memory 371416 kb
Host smart-91c9c3c4-6c0e-439f-98f4-cda0c6ccbfbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34815341044358832274682557015148299281969762016986168853571594308001785683659 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.34815341044358832274682557015148299281969762016986168853571594308001785683659
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.52433966414737516580767683778943899571776501980585084027828815698700330499300
Short name T150
Test name
Test status
Simulation time 445204539 ps
CPU time 12.17 seconds
Started Nov 22 01:22:45 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 246560 kb
Host smart-9777e78c-8f55-4db9-8fe6-2bf09751fbd0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524339664147375165807676837789438995717765019805850840278288156987003
30499300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.524339664147375165807676837789438995717765019805850840
27828815698700330499300
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.90145997611871418822248867415660319695113508391604106499273235597780277257566
Short name T701
Test name
Test status
Simulation time 42305619653 ps
CPU time 564.81 seconds
Started Nov 22 01:22:32 PM PST 23
Finished Nov 22 01:32:02 PM PST 23
Peak memory 202700 kb
Host smart-7342e4bc-bde2-43c7-85ec-0071f84011c1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901459976118714188222488674156603196951135083916041064992732355977802
77257566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access_b2b.9014599761187141882224886741566031969511
3508391604106499273235597780277257566
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.106243136098803284204000774060179770924046347143393499410558769166267447103131
Short name T351
Test name
Test status
Simulation time 40672061 ps
CPU time 0.89 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:22:39 PM PST 23
Peak memory 202600 kb
Host smart-886e07fb-2988-41b5-b51f-f4ca72003c81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106243136098803284204000774060179770924046347143393499410558769166267447103131 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.106243136098803284204000774060179770924046347143393499410558769166267447103131
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.31807621435651125834722439861106135366215431055911163163631542214316909816602
Short name T152
Test name
Test status
Simulation time 19383553031 ps
CPU time 600.02 seconds
Started Nov 22 01:22:32 PM PST 23
Finished Nov 22 01:32:37 PM PST 23
Peak memory 371768 kb
Host smart-f1d9fed1-c75d-4671-bd6e-d3ab3d33d89e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31807621435651125834722439861106135366215431055911163163631542214316909816602 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.31807621435651125834722439861106135366215431055911163163631542214316909816602
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.61102022262247404845750284576660796616547138537705329176478009264464244241086
Short name T596
Test name
Test status
Simulation time 427865392 ps
CPU time 12.44 seconds
Started Nov 22 01:22:37 PM PST 23
Finished Nov 22 01:22:55 PM PST 23
Peak memory 246508 kb
Host smart-e0833d5c-9502-4da3-96b4-983459d63d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61102022262247404845750284576660796616547138537705329176478009264464244241086 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.61102022262247404845750284576660796616547138537705329176478009264464244241086
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.92744116103353450062971321839681899922454455333280157711181240589892396509829
Short name T109
Test name
Test status
Simulation time 121463254244 ps
CPU time 3210.08 seconds
Started Nov 22 01:22:32 PM PST 23
Finished Nov 22 02:16:07 PM PST 23
Peak memory 375336 kb
Host smart-6c73c8a0-141b-4d94-8c8b-b3b520502b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927441161033534500629713218396818999224544553332801577111812405
89892396509829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.92744116103353450062971321839681899922454455333
280157711181240589892396509829
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.33561590909934377835522065292997824064731776961381281864509325435192773725234
Short name T975
Test name
Test status
Simulation time 624328106 ps
CPU time 1519.95 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:47:59 PM PST 23
Peak memory 401664 kb
Host smart-a9d7cf8d-ed28-4d75-90a3-bcc878c17035
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=33561590909934377835522065292997824064731776961381281864509325435192773725234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sr
am_ctrl_stress_all_with_rand_reset.33561590909934377835522065292997824064731776961381281864509325435192773725234
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.11204306131049716749283977840898019315505108176360410649097374680929466967442
Short name T657
Test name
Test status
Simulation time 6491370455 ps
CPU time 353.96 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:28:29 PM PST 23
Peak memory 202660 kb
Host smart-9b3794ca-8707-4022-bd3d-a34e5b3c2b82
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11204306131049716749283977840898019315505108176360410649097374680929466967442
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.112043061310497167492839778408980193155051081763604
10649097374680929466967442
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.96762256270381210423387389987967582881329460046326292336488352425331113439312
Short name T1025
Test name
Test status
Simulation time 237420487 ps
CPU time 92.02 seconds
Started Nov 22 01:24:14 PM PST 23
Finished Nov 22 01:25:50 PM PST 23
Peak memory 350912 kb
Host smart-03f39f2c-21db-4cea-b7a5-20512487caff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967622562703812104233873899879675828813294600463262923
36488352425331113439312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.9676225627038121042338
7389987967582881329460046326292336488352425331113439312
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.26377771903489215886551583531834456193072900353333222119431512868679713461288
Short name T40
Test name
Test status
Simulation time 4471404472 ps
CPU time 736.13 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:34:54 PM PST 23
Peak memory 375392 kb
Host smart-954e1559-af27-42d1-9d55-50b4f209b975
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26377771903489215886551583531834456193072900353333222119431512868679713461288
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during_key_req.263777719034892158865515835318344561930
72900353333222119431512868679713461288
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.55105659205311265277289162767016342878791143991530192131908483291057430744527
Short name T481
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 01:22:26 PM PST 23
Finished Nov 22 01:22:31 PM PST 23
Peak memory 202196 kb
Host smart-67f71139-dfb9-4cc2-a475-302cbbd84d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551056592053112652772891627670163428787911439915301921319084832910
57430744527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.551056592053112652772891627670163428787911439915301921
31908483291057430744527
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.83500284151962537116580790347970478867522264251580528418159881813882658373496
Short name T308
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.97 seconds
Started Nov 22 01:23:20 PM PST 23
Finished Nov 22 01:24:54 PM PST 23
Peak memory 202544 kb
Host smart-1d302d9a-29b4-4906-90be-b423cfdbd6e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83500284151962537116580790347970478867522264251580528418159881813882658373496 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.83500284151962537116580790347970478867522264251580528418159881813882658373496
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.109185983377408610459475570940596737302762759409493312485696327382012070829989
Short name T618
Test name
Test status
Simulation time 23162112088 ps
CPU time 602.35 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:33:09 PM PST 23
Peak memory 364452 kb
Host smart-49bec08c-6932-48fc-820e-1fac1b76940f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109185983377408610459475570940596737302762759409493312485696327382012070829989 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.109185983377408610459475570940596737302762759409493312485696327382012070829989
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.3348131799982806050124791055071728071212107280019231492148172698151609558623
Short name T1003
Test name
Test status
Simulation time 985753786 ps
CPU time 7.14 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:22:46 PM PST 23
Peak memory 213180 kb
Host smart-980f1e65-84a0-4a10-92c4-8183f6527559
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348131799982806050124791055071728071212107280019231492148172698151609558623 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.3348131799982806050124791055071728071212107280019231492148172698151609558623
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.114383390920561889927765382945401389305224296248043221776564271318330349935924
Short name T541
Test name
Test status
Simulation time 209242141 ps
CPU time 88.07 seconds
Started Nov 22 01:22:32 PM PST 23
Finished Nov 22 01:24:05 PM PST 23
Peak memory 351200 kb
Host smart-ddf50f12-28ef-4faa-bdee-4147fb1796ed
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143833909205618899277653829454013893052242962480432217
76564271318330349935924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_max_throughput.1143833909205618899277653829454013
89305224296248043221776564271318330349935924
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.39415071113318390485594695358111428985223224253251700154616898348486725314936
Short name T77
Test name
Test status
Simulation time 166171057 ps
CPU time 3.1 seconds
Started Nov 22 01:22:53 PM PST 23
Finished Nov 22 01:23:10 PM PST 23
Peak memory 215724 kb
Host smart-4821b2fb-e80f-440c-8bac-a2511a8c6817
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39415071113318390485594695358111428985223224253251700154616898348486
725314936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.394150711133183904855946953581114289852232242532
51700154616898348486725314936
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.51637838686432947917744620621324318388394414264860535499659512638772464896279
Short name T144
Test name
Test status
Simulation time 590810517 ps
CPU time 5.22 seconds
Started Nov 22 01:22:54 PM PST 23
Finished Nov 22 01:23:12 PM PST 23
Peak memory 202388 kb
Host smart-b8cec6b5-4e96-42cb-bda4-33f9a4b3322b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51637838686432947917744620621324318388394414264860535499659512638772464896279
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.51637838686432947917744620621324318388394414264860535499659512638772464896279
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.102072246504059541037868422005406045608962049124403184226794568159836268653101
Short name T851
Test name
Test status
Simulation time 21947461091 ps
CPU time 821.92 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:36:18 PM PST 23
Peak memory 371412 kb
Host smart-3b086638-4a1e-46c3-9e10-079273c9988e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102072246504059541037868422005406045608962049124403184226794568159836268653101 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.102072246504059541037868422005406045608962049124403184226794568159836268653101
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.103790349648990122657807741320204510966676822664335966933655555037089693233948
Short name T393
Test name
Test status
Simulation time 445204539 ps
CPU time 14.34 seconds
Started Nov 22 01:22:56 PM PST 23
Finished Nov 22 01:23:21 PM PST 23
Peak memory 246580 kb
Host smart-03432e24-acb1-41e5-921c-c43f713bb981
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103790349648990122657807741320204510966676822664335966933655555037089
693233948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.10379034964899012265780774132020451096667682266433596
6933655555037089693233948
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.58279606444210658401672301114993192688080187342875499706461460279002645853531
Short name T587
Test name
Test status
Simulation time 42305619653 ps
CPU time 549.12 seconds
Started Nov 22 01:22:26 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 202716 kb
Host smart-d00953c5-a2c9-49c8-8aa8-6e11f7fafe45
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582796064442106584016723011149931926880801873428754997064614602790026
45853531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access_b2b.5827960644421065840167230111499319268808
0187342875499706461460279002645853531
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.64297680378420833827503765600204153944295092673261478027823744724011384496383
Short name T476
Test name
Test status
Simulation time 40672061 ps
CPU time 0.79 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 202460 kb
Host smart-7ffac2d4-b4de-44c3-a81e-45ff3d0a9fc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64297680378420833827503765600204153944295092673261478027823744724011384496383 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.64297680378420833827503765600204153944295092673261478027823744724011384496383
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.53287544100307439617851248919326153641671578865330595265469153693026137623064
Short name T331
Test name
Test status
Simulation time 19383553031 ps
CPU time 531.14 seconds
Started Nov 22 01:22:32 PM PST 23
Finished Nov 22 01:31:28 PM PST 23
Peak memory 371756 kb
Host smart-0f4e3403-5b03-4d96-9328-fcdc11ff59d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53287544100307439617851248919326153641671578865330595265469153693026137623064 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.53287544100307439617851248919326153641671578865330595265469153693026137623064
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.79383791886118158408079122696954859043738329820834469964886031397122092653333
Short name T491
Test name
Test status
Simulation time 427865392 ps
CPU time 13.6 seconds
Started Nov 22 01:22:32 PM PST 23
Finished Nov 22 01:22:51 PM PST 23
Peak memory 246568 kb
Host smart-fe5b01bf-f649-4d9f-822c-38be40205600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79383791886118158408079122696954859043738329820834469964886031397122092653333 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.79383791886118158408079122696954859043738329820834469964886031397122092653333
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.49407801843101949971978524191595812203986578790868611513834368473011869104425
Short name T525
Test name
Test status
Simulation time 121463254244 ps
CPU time 3034.49 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 02:13:14 PM PST 23
Peak memory 375376 kb
Host smart-820df489-1d11-48f5-be88-ba29dc2ac06d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494078018431019499719785241915958122039865787908686115138343684
73011869104425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.49407801843101949971978524191595812203986578790
868611513834368473011869104425
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.12702468083925503948287745533259265554650469696602796276324311523211128597821
Short name T782
Test name
Test status
Simulation time 624328106 ps
CPU time 1121.19 seconds
Started Nov 22 01:22:29 PM PST 23
Finished Nov 22 01:41:15 PM PST 23
Peak memory 401188 kb
Host smart-0ba539a9-f40f-4b53-a675-084c17be2180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=12702468083925503948287745533259265554650469696602796276324311523211128597821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sr
am_ctrl_stress_all_with_rand_reset.12702468083925503948287745533259265554650469696602796276324311523211128597821
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.9885648436008766744452234270905687452403883627440813298295647884670597982834
Short name T792
Test name
Test status
Simulation time 6491370455 ps
CPU time 360.27 seconds
Started Nov 22 01:22:57 PM PST 23
Finished Nov 22 01:29:08 PM PST 23
Peak memory 202656 kb
Host smart-3de245a2-d0f0-454b-b3ef-760a9bf98e97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9885648436008766744452234270905687452403883627440813298295647884670597982834
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.9885648436008766744452234270905687452403883627440813
298295647884670597982834
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.114108166519431715987170586154967166334390599233888915703803948856961670644005
Short name T625
Test name
Test status
Simulation time 237420487 ps
CPU time 88.13 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:24:04 PM PST 23
Peak memory 351356 kb
Host smart-f6f2e1f7-8776-45c0-8f3b-26889123e7c3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114108166519431715987170586154967166334390599233888915
703803948856961670644005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.114108166519431715987
170586154967166334390599233888915703803948856961670644005
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3124715964246586349304549315119942316940900179646415688511901124181937614258
Short name T721
Test name
Test status
Simulation time 4471404472 ps
CPU time 753.92 seconds
Started Nov 22 01:22:26 PM PST 23
Finished Nov 22 01:35:04 PM PST 23
Peak memory 375472 kb
Host smart-b483d434-240f-4c49-8232-48f62561bbaf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124715964246586349304549315119942316940900179646415688511901124181937614258
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during_key_req.3124715964246586349304549315119942316940
900179646415688511901124181937614258
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.9689147253573581940979691329914600134097622170854621411026051627378834754750
Short name T385
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 01:22:56 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 202208 kb
Host smart-68bac756-87d8-4599-849a-b83e3fab1a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968914725357358194097969132991460013409762217085462141102605162737
8834754750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.9689147253573581940979691329914600134097622170854621411
026051627378834754750
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.81575895419910078421339880455477999875202491199310353549450700436746995349099
Short name T410
Test name
Test status
Simulation time 9249473390 ps
CPU time 77.9 seconds
Started Nov 22 01:22:42 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 202460 kb
Host smart-4309e4db-2f40-435b-9a7a-680868d25cb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81575895419910078421339880455477999875202491199310353549450700436746995349099 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.81575895419910078421339880455477999875202491199310353549450700436746995349099
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.14273650176880768722295117366771820869278180572942804965829715838438887036508
Short name T967
Test name
Test status
Simulation time 23162112088 ps
CPU time 637.02 seconds
Started Nov 22 01:22:28 PM PST 23
Finished Nov 22 01:33:10 PM PST 23
Peak memory 364640 kb
Host smart-3442d40b-d28d-45ed-a9ff-efffc1b9ee3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14273650176880768722295117366771820869278180572942804965829715838438887036508 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.14273650176880768722295117366771820869278180572942804965829715838438887036508
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.112773099314666308398397952219229000871074850786339356534102959560849741009124
Short name T505
Test name
Test status
Simulation time 985753786 ps
CPU time 7.33 seconds
Started Nov 22 01:22:44 PM PST 23
Finished Nov 22 01:23:02 PM PST 23
Peak memory 213204 kb
Host smart-ae26c387-2493-43d9-8e04-ac234ac72541
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112773099314666308398397952219229000871074850786339356534102959560849741009124 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.112773099314666308398397952219229000871074850786339356534102959560849741009124
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.21812162824857780218590841989776090797249153351815840570171456301834743651505
Short name T881
Test name
Test status
Simulation time 209242141 ps
CPU time 82.33 seconds
Started Nov 22 01:22:35 PM PST 23
Finished Nov 22 01:24:02 PM PST 23
Peak memory 351336 kb
Host smart-eee4937c-a8e1-4410-b091-d7d5000447aa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181216282485778021859084198977609079724915335181584057
0171456301834743651505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_max_throughput.21812162824857780218590841989776090
797249153351815840570171456301834743651505
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.109442701990148307154655538657264858216826371011370132383979323872250634534158
Short name T814
Test name
Test status
Simulation time 166171057 ps
CPU time 3.06 seconds
Started Nov 22 01:22:32 PM PST 23
Finished Nov 22 01:22:40 PM PST 23
Peak memory 215720 kb
Host smart-f5925edf-d53d-4392-ad05-3d72fd0390d2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944270199014830715465553865726485821682637101137013238397932387225
0634534158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.10944270199014830715465553865726485821682637101
1370132383979323872250634534158
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.113257187264067867832995736817464726273393669072602221372717539294943162727943
Short name T430
Test name
Test status
Simulation time 590810517 ps
CPU time 5.42 seconds
Started Nov 22 01:22:37 PM PST 23
Finished Nov 22 01:22:49 PM PST 23
Peak memory 202588 kb
Host smart-2eef075f-de87-4ec1-ae2b-1bc304af6084
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113257187264067867832995736817464726273393669072602221372717539294943162727943
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.113257187264067867832995736817464726273393669072602221372717539294943162727943
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.26997664662204035435137191612021403203763057843465854083595052298980938591733
Short name T532
Test name
Test status
Simulation time 21947461091 ps
CPU time 623.12 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:33:30 PM PST 23
Peak memory 371356 kb
Host smart-d08745a8-315a-4815-b818-02fc1d949514
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26997664662204035435137191612021403203763057843465854083595052298980938591733 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.26997664662204035435137191612021403203763057843465854083595052298980938591733
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.25881588730249523638903975690572996381837623995706560381423052756620023357681
Short name T764
Test name
Test status
Simulation time 445204539 ps
CPU time 12.04 seconds
Started Nov 22 01:22:41 PM PST 23
Finished Nov 22 01:23:00 PM PST 23
Peak memory 246468 kb
Host smart-2dcc2a56-0f14-4b0a-be5b-bb7ac4314b70
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258815887302495236389039756905729963818376239957065603814230527566200
23357681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.258815887302495236389039756905729963818376239957065603
81423052756620023357681
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.106926858489749713608544702303742343588992428335483198126956814441428559198048
Short name T506
Test name
Test status
Simulation time 42305619653 ps
CPU time 526.71 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 01:31:21 PM PST 23
Peak memory 202668 kb
Host smart-6469e667-3dee-42e1-ae55-e4f0ec0b3ba1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106926858489749713608544702303742343588992428335483198126956814441428
559198048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access_b2b.106926858489749713608544702303742343588
992428335483198126956814441428559198048
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.77314369563454514745404273404108094739569461903345734750432906004933010184752
Short name T582
Test name
Test status
Simulation time 40672061 ps
CPU time 0.86 seconds
Started Nov 22 01:22:35 PM PST 23
Finished Nov 22 01:22:41 PM PST 23
Peak memory 202548 kb
Host smart-80da6b48-0296-43d4-8eb6-60ffc587ad83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77314369563454514745404273404108094739569461903345734750432906004933010184752 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.77314369563454514745404273404108094739569461903345734750432906004933010184752
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.45336721132849854836127742703550917519271297838038247898020491288712671725425
Short name T1028
Test name
Test status
Simulation time 19383553031 ps
CPU time 539.83 seconds
Started Nov 22 01:22:57 PM PST 23
Finished Nov 22 01:32:07 PM PST 23
Peak memory 371792 kb
Host smart-b98ba0e7-cf63-45f5-8fd0-7c64aa0197e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45336721132849854836127742703550917519271297838038247898020491288712671725425 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.45336721132849854836127742703550917519271297838038247898020491288712671725425
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.72241525389844458856484716088293598989216798860220696731666536593723114032694
Short name T409
Test name
Test status
Simulation time 427865392 ps
CPU time 11.55 seconds
Started Nov 22 01:23:11 PM PST 23
Finished Nov 22 01:23:31 PM PST 23
Peak memory 246576 kb
Host smart-157f0cc2-c3d9-422d-8264-d4ca4b892495
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72241525389844458856484716088293598989216798860220696731666536593723114032694 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.72241525389844458856484716088293598989216798860220696731666536593723114032694
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.21390881496134973160230904592887631305705636064065180113088078686814794470242
Short name T645
Test name
Test status
Simulation time 121463254244 ps
CPU time 3336.64 seconds
Started Nov 22 01:23:12 PM PST 23
Finished Nov 22 02:18:58 PM PST 23
Peak memory 375348 kb
Host smart-242938b4-165e-4bb2-8e90-7dbf3ad26622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213908814961349731602309045928876313057056360640651801130880786
86814794470242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.21390881496134973160230904592887631305705636064
065180113088078686814794470242
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.27686005205632278551576811434002572536631085260232974487142374793883822529983
Short name T311
Test name
Test status
Simulation time 624328106 ps
CPU time 996.2 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:39:12 PM PST 23
Peak memory 401788 kb
Host smart-c469ca5c-82ce-46dc-bfec-5a51e7e7e44e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=27686005205632278551576811434002572536631085260232974487142374793883822529983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sr
am_ctrl_stress_all_with_rand_reset.27686005205632278551576811434002572536631085260232974487142374793883822529983
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.78795273899138123052736747058794562608606321379983668244753517580361081362178
Short name T390
Test name
Test status
Simulation time 6491370455 ps
CPU time 355.56 seconds
Started Nov 22 01:23:09 PM PST 23
Finished Nov 22 01:29:15 PM PST 23
Peak memory 202668 kb
Host smart-48ca4f55-5430-421b-aeb3-b05bf6953685
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78795273899138123052736747058794562608606321379983668244753517580361081362178
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.787952738991381230527367470587945626086063213799836
68244753517580361081362178
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.64745208372071245416321145015234894228990619928985585185445664469552711719645
Short name T770
Test name
Test status
Simulation time 237420487 ps
CPU time 98.8 seconds
Started Nov 22 01:22:29 PM PST 23
Finished Nov 22 01:24:13 PM PST 23
Peak memory 351420 kb
Host smart-9edae542-099c-400f-b0a4-df47b1365a33
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647452083720712454163211450152348942289906199289855851
85445664469552711719645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.6474520837207124541632
1145015234894228990619928985585185445664469552711719645
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.108116291724567278130914148288806841037419539889507982774033205056769375259438
Short name T646
Test name
Test status
Simulation time 4471404472 ps
CPU time 651.43 seconds
Started Nov 22 01:22:44 PM PST 23
Finished Nov 22 01:33:48 PM PST 23
Peak memory 375380 kb
Host smart-409c5a63-0753-435e-a14e-3aabc0fc5fcb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811629172456727813091414828880684103741953988950798277403320505676937525943
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_key_req.10811629172456727813091414828880684103
7419539889507982774033205056769375259438
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.10357152572450813051481619268615414962722124505294902301315685892333376611871
Short name T709
Test name
Test status
Simulation time 16600825 ps
CPU time 0.62 seconds
Started Nov 22 01:23:21 PM PST 23
Finished Nov 22 01:23:32 PM PST 23
Peak memory 202172 kb
Host smart-89493e50-4bdb-4b90-abed-908e123799dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103571525724508130514816192686154149627221245052949023013156858923
33376611871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.103571525724508130514816192686154149627221245052949023
01315685892333376611871
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.6607441549656539800362330400437994088687178759070815914651382173717240780521
Short name T110
Test name
Test status
Simulation time 9249473390 ps
CPU time 78.99 seconds
Started Nov 22 01:22:44 PM PST 23
Finished Nov 22 01:24:14 PM PST 23
Peak memory 202524 kb
Host smart-141c88aa-2e51-4244-b656-2bbcbda37a2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6607441549656539800362330400437994088687178759070815914651382173717240780521 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.6607441549656539800362330400437994088687178759070815914651382173717240780521
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.75282013266767910254394085204124889072769343310894846343725755540580602071130
Short name T373
Test name
Test status
Simulation time 23162112088 ps
CPU time 621.86 seconds
Started Nov 22 01:22:36 PM PST 23
Finished Nov 22 01:33:03 PM PST 23
Peak memory 364636 kb
Host smart-cc684f25-e3e8-4594-8750-349b87e227a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75282013266767910254394085204124889072769343310894846343725755540580602071130 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.75282013266767910254394085204124889072769343310894846343725755540580602071130
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.61474035062245003862085587005471859515240972711709091461539484162060640357266
Short name T723
Test name
Test status
Simulation time 985753786 ps
CPU time 7.18 seconds
Started Nov 22 01:23:19 PM PST 23
Finished Nov 22 01:23:36 PM PST 23
Peak memory 213168 kb
Host smart-2d239915-c4f1-4062-81c2-3a806cfe87aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61474035062245003862085587005471859515240972711709091461539484162060640357266 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.61474035062245003862085587005471859515240972711709091461539484162060640357266
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.107960666667195780244194661704106945016309546131879540656578971721298977705717
Short name T361
Test name
Test status
Simulation time 209242141 ps
CPU time 86.9 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:24:17 PM PST 23
Peak memory 351244 kb
Host smart-354ffabd-2425-498b-8bda-03c2c28c7e96
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079606666671957802441946617041069450163095461318795406
56578971721298977705717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max_throughput.1079606666671957802441946617041069
45016309546131879540656578971721298977705717
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.39424714365573770662526053318245988502451318607543204262603981100342406548192
Short name T829
Test name
Test status
Simulation time 166171057 ps
CPU time 3.1 seconds
Started Nov 22 01:22:48 PM PST 23
Finished Nov 22 01:23:05 PM PST 23
Peak memory 215588 kb
Host smart-dce21fb2-ba0b-45c2-b94d-13ef307eea1a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39424714365573770662526053318245988502451318607543204262603981100342
406548192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.394247143655737706625260533182459885024513186075
43204262603981100342406548192
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.46569213069461285162817537747235384020981531577352498961319495448346180156606
Short name T946
Test name
Test status
Simulation time 590810517 ps
CPU time 5.46 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:22:45 PM PST 23
Peak memory 202616 kb
Host smart-2ef34729-cce8-47d6-9a3d-710f0dacbbc4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46569213069461285162817537747235384020981531577352498961319495448346180156606
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.46569213069461285162817537747235384020981531577352498961319495448346180156606
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.70168707492499305809582528136429103947410895291918914007137082627665763688449
Short name T679
Test name
Test status
Simulation time 21947461091 ps
CPU time 706.55 seconds
Started Nov 22 01:22:45 PM PST 23
Finished Nov 22 01:34:44 PM PST 23
Peak memory 371332 kb
Host smart-337949b7-b35d-4a09-af1d-8e9bef1efd28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70168707492499305809582528136429103947410895291918914007137082627665763688449 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.70168707492499305809582528136429103947410895291918914007137082627665763688449
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.78468294694908108750260921206023010864639547306847363809963535417648515392197
Short name T1017
Test name
Test status
Simulation time 445204539 ps
CPU time 12.51 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:22:42 PM PST 23
Peak memory 246500 kb
Host smart-9c7ac4b2-f4ce-475e-8aa2-751a6c4fa614
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784682946949081087502609212060230108646395473068473638099635354176485
15392197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.784682946949081087502609212060230108646395473068473638
09963535417648515392197
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.14417049002531871296452114736915321686071668256165754659997505832574574392545
Short name T795
Test name
Test status
Simulation time 42305619653 ps
CPU time 527.25 seconds
Started Nov 22 01:22:54 PM PST 23
Finished Nov 22 01:31:54 PM PST 23
Peak memory 202580 kb
Host smart-51eaac39-c01f-49ea-8292-5c1d2785fe65
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144170490025318712964521147369153216860716682561657546599975058325745
74392545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access_b2b.1441704900253187129645211473691532168607
1668256165754659997505832574574392545
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.61649707334390966983082283061629988108319170145506596635331735327199562945110
Short name T342
Test name
Test status
Simulation time 40672061 ps
CPU time 0.82 seconds
Started Nov 22 01:22:36 PM PST 23
Finished Nov 22 01:22:42 PM PST 23
Peak memory 202420 kb
Host smart-7ec3736b-15c0-4b68-b7e5-2e02ab8b1d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61649707334390966983082283061629988108319170145506596635331735327199562945110 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.61649707334390966983082283061629988108319170145506596635331735327199562945110
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.60328141077723845324857642148726024442667722002424190153722903140579251538289
Short name T605
Test name
Test status
Simulation time 19383553031 ps
CPU time 501.39 seconds
Started Nov 22 01:23:09 PM PST 23
Finished Nov 22 01:31:40 PM PST 23
Peak memory 371772 kb
Host smart-c1478b44-5cf0-473c-9bce-7f47b32f4b4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60328141077723845324857642148726024442667722002424190153722903140579251538289 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.60328141077723845324857642148726024442667722002424190153722903140579251538289
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.8054993379371145049657879243397823971656107029510968093201487206125798234668
Short name T624
Test name
Test status
Simulation time 427865392 ps
CPU time 10.6 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 246560 kb
Host smart-3595a2dc-0515-42c7-9d52-5326bef5652d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8054993379371145049657879243397823971656107029510968093201487206125798234668 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.8054993379371145049657879243397823971656107029510968093201487206125798234668
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.74487219404037192388917601871586843488221188095276735781819364078929393611907
Short name T786
Test name
Test status
Simulation time 121463254244 ps
CPU time 3462.06 seconds
Started Nov 22 01:22:28 PM PST 23
Finished Nov 22 02:20:15 PM PST 23
Peak memory 375432 kb
Host smart-1ee933ec-ccee-43e6-ad6f-8d5d4f622d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744872194040371923889176018715868434882211880952767357818193640
78929393611907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.74487219404037192388917601871586843488221188095
276735781819364078929393611907
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.55145344601983509227634493189036722531301061264311761270257645246253646451228
Short name T330
Test name
Test status
Simulation time 624328106 ps
CPU time 1041.18 seconds
Started Nov 22 01:22:58 PM PST 23
Finished Nov 22 01:40:29 PM PST 23
Peak memory 401628 kb
Host smart-7c567a1f-f933-4502-bbca-ba5ed3ad8964
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=55145344601983509227634493189036722531301061264311761270257645246253646451228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sr
am_ctrl_stress_all_with_rand_reset.55145344601983509227634493189036722531301061264311761270257645246253646451228
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.91676495776561747044140572093061711019480363830324939684922621707784460602020
Short name T494
Test name
Test status
Simulation time 6491370455 ps
CPU time 361.02 seconds
Started Nov 22 01:22:25 PM PST 23
Finished Nov 22 01:28:31 PM PST 23
Peak memory 202612 kb
Host smart-68a2aac6-6296-4ea9-ba4b-b4510c2d2b72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91676495776561747044140572093061711019480363830324939684922621707784460602020
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.916764957765617470441405720930617110194803638303249
39684922621707784460602020
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.85902081824195693165396637849167053299845167359398109892642961617430376287986
Short name T774
Test name
Test status
Simulation time 237420487 ps
CPU time 106.84 seconds
Started Nov 22 01:22:57 PM PST 23
Finished Nov 22 01:24:54 PM PST 23
Peak memory 351340 kb
Host smart-fb76e947-0002-4b07-acf5-0c994f6287cf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859020818241956931653966378491670532998451673593981098
92642961617430376287986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.8590208182419569316539
6637849167053299845167359398109892642961617430376287986
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.56164817467240371536071128605834662521338536180712665937400788000654209887135
Short name T704
Test name
Test status
Simulation time 4471404472 ps
CPU time 755.82 seconds
Started Nov 22 01:23:13 PM PST 23
Finished Nov 22 01:35:58 PM PST 23
Peak memory 375472 kb
Host smart-4b59e66c-793e-4bb6-8539-657f0182fa7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56164817467240371536071128605834662521338536180712665937400788000654209887135
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during_key_req.561648174672403715360711286058346625213
38536180712665937400788000654209887135
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.31725415314929095152264168921006991938451039897222575424488999665962413577202
Short name T755
Test name
Test status
Simulation time 16600825 ps
CPU time 0.67 seconds
Started Nov 22 01:23:18 PM PST 23
Finished Nov 22 01:23:24 PM PST 23
Peak memory 202148 kb
Host smart-87f8e125-6f0a-47e4-a2f1-ef960e95a9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317254153149290951522641689210069919384510398972225754244889996659
62413577202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.317254153149290951522641689210069919384510398972225754
24488999665962413577202
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.83024158108804714427263700565746814817463884401298621193908341863503371259117
Short name T740
Test name
Test status
Simulation time 9249473390 ps
CPU time 81.27 seconds
Started Nov 22 01:23:11 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 202624 kb
Host smart-dd91884d-719f-4bb9-8638-970d17848a9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83024158108804714427263700565746814817463884401298621193908341863503371259117 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.83024158108804714427263700565746814817463884401298621193908341863503371259117
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.28913992269283784047031689626012070282226603651582791167923823898251922461434
Short name T103
Test name
Test status
Simulation time 23162112088 ps
CPU time 706.7 seconds
Started Nov 22 01:22:58 PM PST 23
Finished Nov 22 01:34:54 PM PST 23
Peak memory 364616 kb
Host smart-5799bfe1-9436-46cc-b981-286c091d9555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28913992269283784047031689626012070282226603651582791167923823898251922461434 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.28913992269283784047031689626012070282226603651582791167923823898251922461434
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.48572021091987116086387555116672762827187975751597049944173503186855543416336
Short name T8
Test name
Test status
Simulation time 985753786 ps
CPU time 7.24 seconds
Started Nov 22 01:23:22 PM PST 23
Finished Nov 22 01:23:40 PM PST 23
Peak memory 213192 kb
Host smart-fb7ddc9f-0461-475a-bd22-76cd20d6ae11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48572021091987116086387555116672762827187975751597049944173503186855543416336 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.48572021091987116086387555116672762827187975751597049944173503186855543416336
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.18342712148109825675989513267830945708715324240187419561037160173439670824650
Short name T914
Test name
Test status
Simulation time 209242141 ps
CPU time 101.01 seconds
Started Nov 22 01:23:13 PM PST 23
Finished Nov 22 01:25:03 PM PST 23
Peak memory 351308 kb
Host smart-78f85f9f-920f-4975-9edc-390bd15f04e9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834271214810982567598951326783094570871532424018741956
1037160173439670824650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_max_throughput.18342712148109825675989513267830945
708715324240187419561037160173439670824650
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.22534253794458489173011319354460174052661384204421188777275505669112454983981
Short name T836
Test name
Test status
Simulation time 166171057 ps
CPU time 3.01 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 01:22:38 PM PST 23
Peak memory 215652 kb
Host smart-3d000a36-10ad-4b6e-b8c1-820b124a527f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22534253794458489173011319354460174052661384204421188777275505669112
454983981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.225342537944584891730113193544601740526613842044
21188777275505669112454983981
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.22360764403301644660255531024136442363991581198998418259876073860111171863778
Short name T865
Test name
Test status
Simulation time 590810517 ps
CPU time 5.25 seconds
Started Nov 22 01:22:35 PM PST 23
Finished Nov 22 01:22:45 PM PST 23
Peak memory 202604 kb
Host smart-3d65f8d7-7708-4ba1-87f1-09f457a676d7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22360764403301644660255531024136442363991581198998418259876073860111171863778
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.22360764403301644660255531024136442363991581198998418259876073860111171863778
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.36782808639232374132315391901565691275527869732894476263578684379888566013066
Short name T902
Test name
Test status
Simulation time 21947461091 ps
CPU time 606.81 seconds
Started Nov 22 01:22:35 PM PST 23
Finished Nov 22 01:32:47 PM PST 23
Peak memory 371384 kb
Host smart-c373f36d-c73d-4680-8985-a8ece5427ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36782808639232374132315391901565691275527869732894476263578684379888566013066 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.36782808639232374132315391901565691275527869732894476263578684379888566013066
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.7304163662256428449555306918776343215948866847643183339541429068439486406498
Short name T813
Test name
Test status
Simulation time 445204539 ps
CPU time 13.09 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:22:52 PM PST 23
Peak memory 246560 kb
Host smart-73e528ef-4a28-4e76-ab97-d6dbf0eaf844
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730416366225642844955530691877634321594886684764318333954142906843948
6406498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.7304163662256428449555306918776343215948866847643183339
541429068439486406498
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.64551506300015103336832122947025325977804290813885825894014396248833084408924
Short name T619
Test name
Test status
Simulation time 42305619653 ps
CPU time 546.45 seconds
Started Nov 22 01:23:13 PM PST 23
Finished Nov 22 01:32:28 PM PST 23
Peak memory 202656 kb
Host smart-e11d005c-d6a1-4481-a50e-8880b4add4a7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645515063000151033368321229470253259778042908138858258940143962488330
84408924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access_b2b.6455150630001510333683212294702532597780
4290813885825894014396248833084408924
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.33077757989968268651497105399893596530894756112246428882231358871427653887328
Short name T634
Test name
Test status
Simulation time 40672061 ps
CPU time 0.85 seconds
Started Nov 22 01:22:49 PM PST 23
Finished Nov 22 01:23:04 PM PST 23
Peak memory 202488 kb
Host smart-cab561c0-dd81-415c-88df-899eca8edd56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33077757989968268651497105399893596530894756112246428882231358871427653887328 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.33077757989968268651497105399893596530894756112246428882231358871427653887328
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.94883511114815625556012184983460018210684462593326718551019020114037972346766
Short name T651
Test name
Test status
Simulation time 19383553031 ps
CPU time 545.54 seconds
Started Nov 22 01:22:28 PM PST 23
Finished Nov 22 01:31:39 PM PST 23
Peak memory 371848 kb
Host smart-3d1af8b9-62d3-49cb-9e5d-8a96ab3b9f5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94883511114815625556012184983460018210684462593326718551019020114037972346766 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.94883511114815625556012184983460018210684462593326718551019020114037972346766
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.62095490806496010839082136642227731137058881656881664131240705264076656778959
Short name T143
Test name
Test status
Simulation time 427865392 ps
CPU time 12.25 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 01:23:29 PM PST 23
Peak memory 246420 kb
Host smart-02618fa8-e5fe-4569-a1cc-d5410233a6bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62095490806496010839082136642227731137058881656881664131240705264076656778959 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.62095490806496010839082136642227731137058881656881664131240705264076656778959
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.74362740860346635986859140854800864953222183859748627561177665411982263228586
Short name T964
Test name
Test status
Simulation time 624328106 ps
CPU time 956.26 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 01:39:14 PM PST 23
Peak memory 401680 kb
Host smart-5253cc5d-c8b1-4034-98a4-256b6b4f9525
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=74362740860346635986859140854800864953222183859748627561177665411982263228586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sr
am_ctrl_stress_all_with_rand_reset.74362740860346635986859140854800864953222183859748627561177665411982263228586
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.100665002534881425114899479582572198107136907760628814611512338803230615107857
Short name T503
Test name
Test status
Simulation time 6491370455 ps
CPU time 370.64 seconds
Started Nov 22 01:22:30 PM PST 23
Finished Nov 22 01:28:46 PM PST 23
Peak memory 202628 kb
Host smart-c020eb35-cab8-4c73-9873-9cdfbeb9ed7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10066500253488142511489947958257219810713690776062881461151233880323061510785
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.10066500253488142511489947958257219810713690776062
8814611512338803230615107857
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.77074109103082526644796031612270930578122791736907335139856098615905221024379
Short name T543
Test name
Test status
Simulation time 237420487 ps
CPU time 94.96 seconds
Started Nov 22 01:23:25 PM PST 23
Finished Nov 22 01:25:15 PM PST 23
Peak memory 351192 kb
Host smart-2b01c377-0980-464e-a159-e0756e4b33d8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770741091030825266447960316122709305781227917369073351
39856098615905221024379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.7707410910308252664479
6031612270930578122791736907335139856098615905221024379
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.5934613262540088837714206057360645575349261051618831333953883031342298632455
Short name T37
Test name
Test status
Simulation time 4471404472 ps
CPU time 826.59 seconds
Started Nov 22 01:23:09 PM PST 23
Finished Nov 22 01:37:05 PM PST 23
Peak memory 375452 kb
Host smart-210abb8e-84b4-4884-8b69-338db9f379c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5934613262540088837714206057360645575349261051618831333953883031342298632455
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during_key_req.5934613262540088837714206057360645575349
261051618831333953883031342298632455
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.51247620628743797199160134537325070431901307541041935248776356265084854724016
Short name T643
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:22:58 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 202016 kb
Host smart-01623506-45f2-4b98-9a69-410549473b77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512476206287437971991601345373250704319013075410419352487763562650
84854724016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.512476206287437971991601345373250704319013075410419352
48776356265084854724016
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.105531592090625840266323253791953001084128982181281701356639021459182138852730
Short name T11
Test name
Test status
Simulation time 9249473390 ps
CPU time 81.59 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:24:28 PM PST 23
Peak memory 202136 kb
Host smart-e812dbc6-5b5c-411a-a38d-a198216ad6f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105531592090625840266323253791953001084128982181281701356639021459182138852730 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.105531592090625840266323253791953001084128982181281701356639021459182138852730
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.22990067043160669396923280437675423648765614490125624166760744486282240509818
Short name T737
Test name
Test status
Simulation time 23162112088 ps
CPU time 647.91 seconds
Started Nov 22 01:22:33 PM PST 23
Finished Nov 22 01:33:26 PM PST 23
Peak memory 364464 kb
Host smart-e02a9914-a152-41c8-bd97-4831220ace13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22990067043160669396923280437675423648765614490125624166760744486282240509818 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.22990067043160669396923280437675423648765614490125624166760744486282240509818
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.112853349799907891572780118769745020106534185141417406847447133964719569377329
Short name T999
Test name
Test status
Simulation time 985753786 ps
CPU time 7.24 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:23:14 PM PST 23
Peak memory 213028 kb
Host smart-7b0d7919-3e99-4f81-8bd3-dad41330ef85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112853349799907891572780118769745020106534185141417406847447133964719569377329 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.112853349799907891572780118769745020106534185141417406847447133964719569377329
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.102961116934249270165048711712805341800017528271010998962912653368205729971858
Short name T472
Test name
Test status
Simulation time 209242141 ps
CPU time 89.91 seconds
Started Nov 22 01:22:58 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 351168 kb
Host smart-aad7a740-323f-432b-8463-2803a7e8b8c3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029611169342492701650487117128053418000175282710109989
62912653368205729971858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_max_throughput.1029611169342492701650487117128053
41800017528271010998962912653368205729971858
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.16274004261799692852930414100667737568717663646997113870736004339023327740720
Short name T815
Test name
Test status
Simulation time 166171057 ps
CPU time 3.11 seconds
Started Nov 22 01:22:42 PM PST 23
Finished Nov 22 01:22:52 PM PST 23
Peak memory 215620 kb
Host smart-a4c72236-c28b-4230-8081-ba4f32a9626e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274004261799692852930414100667737568717663646997113870736004339023
327740720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.162740042617996928529304141006677375687176636469
97113870736004339023327740720
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.32702677743265224303351183483669348740836104532007728746220300157927313808382
Short name T631
Test name
Test status
Simulation time 590810517 ps
CPU time 5.5 seconds
Started Nov 22 01:23:21 PM PST 23
Finished Nov 22 01:23:37 PM PST 23
Peak memory 202460 kb
Host smart-ab43699b-6ea8-4aaa-bc68-04f80ac36039
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702677743265224303351183483669348740836104532007728746220300157927313808382
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.32702677743265224303351183483669348740836104532007728746220300157927313808382
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.65005965898765840292398954796169988517080453589619280032004812507746012791325
Short name T988
Test name
Test status
Simulation time 21947461091 ps
CPU time 876.16 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:37:15 PM PST 23
Peak memory 371416 kb
Host smart-a24daf9a-0309-45a3-b773-e7de3f3f24de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65005965898765840292398954796169988517080453589619280032004812507746012791325 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.65005965898765840292398954796169988517080453589619280032004812507746012791325
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.59110091668118188555520199043904042315237283036754185789258453205991569851362
Short name T417
Test name
Test status
Simulation time 445204539 ps
CPU time 12.62 seconds
Started Nov 22 01:23:21 PM PST 23
Finished Nov 22 01:23:43 PM PST 23
Peak memory 246552 kb
Host smart-bd2aa48e-49d8-490e-b2e6-689eb1eb648e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591100916681181885555201990439040423152372830367541857892584532059915
69851362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.591100916681181885555201990439040423152372830367541857
89258453205991569851362
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.98581217975778937554411116166464487229699562461513095682055171839521623911211
Short name T990
Test name
Test status
Simulation time 42305619653 ps
CPU time 569.63 seconds
Started Nov 22 01:22:41 PM PST 23
Finished Nov 22 01:32:17 PM PST 23
Peak memory 202700 kb
Host smart-25e9aa49-2232-425a-88f1-3751ed2efaee
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985812179757789375544111161664644872296995624615130956820551718395216
23911211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access_b2b.9858121797577893755441111616646448722969
9562461513095682055171839521623911211
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.78577192482608619299019951286858713886141442289037841719885389170825104050255
Short name T32
Test name
Test status
Simulation time 40672061 ps
CPU time 0.87 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:22:51 PM PST 23
Peak memory 202432 kb
Host smart-61ccc2a7-e3b0-43ad-ba56-594b6678fd2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78577192482608619299019951286858713886141442289037841719885389170825104050255 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.78577192482608619299019951286858713886141442289037841719885389170825104050255
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.100591246444763063436030432106143443645491966951193903170291764948947081014746
Short name T538
Test name
Test status
Simulation time 19383553031 ps
CPU time 593.65 seconds
Started Nov 22 01:22:33 PM PST 23
Finished Nov 22 01:32:32 PM PST 23
Peak memory 371864 kb
Host smart-45a9057d-beb2-4e6a-ad22-49a681fd09dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100591246444763063436030432106143443645491966951193903170291764948947081014746 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.100591246444763063436030432106143443645491966951193903170291764948947081014746
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.111818666043597749097172534594692906093752778394903091146261900502688071940395
Short name T659
Test name
Test status
Simulation time 427865392 ps
CPU time 11.05 seconds
Started Nov 22 01:22:41 PM PST 23
Finished Nov 22 01:22:59 PM PST 23
Peak memory 246572 kb
Host smart-4bb6663b-38ae-4be0-92ce-1013f66fda51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111818666043597749097172534594692906093752778394903091146261900502688071940395 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.111818666043597749097172534594692906093752778394903091146261900502688071940395
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.12344276389793354467350630405401572417776774706497372888118456775654843237961
Short name T923
Test name
Test status
Simulation time 121463254244 ps
CPU time 3365.08 seconds
Started Nov 22 01:22:33 PM PST 23
Finished Nov 22 02:18:44 PM PST 23
Peak memory 375492 kb
Host smart-2de7ef56-29c4-434b-9a85-004582d01510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123442763897933544673506304054015724177767747064973728881184567
75654843237961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.12344276389793354467350630405401572417776774706
497372888118456775654843237961
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.37120096152864001586172436804841763529000248915134770895543683897442750462886
Short name T290
Test name
Test status
Simulation time 624328106 ps
CPU time 943.14 seconds
Started Nov 22 01:22:26 PM PST 23
Finished Nov 22 01:38:14 PM PST 23
Peak memory 401672 kb
Host smart-e07c781e-27be-4f3d-92d1-994ffd564d85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=37120096152864001586172436804841763529000248915134770895543683897442750462886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sr
am_ctrl_stress_all_with_rand_reset.37120096152864001586172436804841763529000248915134770895543683897442750462886
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.88409666489794234881643821925602129744833700314039488219926898318824804900660
Short name T454
Test name
Test status
Simulation time 6491370455 ps
CPU time 339.87 seconds
Started Nov 22 01:23:19 PM PST 23
Finished Nov 22 01:29:09 PM PST 23
Peak memory 202536 kb
Host smart-ff558e30-37ac-4a50-87d6-4ed763eebb27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88409666489794234881643821925602129744833700314039488219926898318824804900660
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.884096664897942348816438219256021297448337003140394
88219926898318824804900660
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.13250886203394627309312519467039001432089834940093435949835378176445070951999
Short name T422
Test name
Test status
Simulation time 237420487 ps
CPU time 87.39 seconds
Started Nov 22 01:22:48 PM PST 23
Finished Nov 22 01:24:29 PM PST 23
Peak memory 351224 kb
Host smart-feb792fe-c31e-45f4-b852-f5f60a7f655d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132508862033946273093125194670390014320898349400934359
49835378176445070951999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1325088620339462730931
2519467039001432089834940093435949835378176445070951999
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.109298869775829678449642478593933509098544902544763889801916726675700959936920
Short name T660
Test name
Test status
Simulation time 4471404472 ps
CPU time 639.5 seconds
Started Nov 22 01:21:06 PM PST 23
Finished Nov 22 01:31:47 PM PST 23
Peak memory 375508 kb
Host smart-acee277f-98e2-414a-acd8-c5536637ecdd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929886977582967844964247859393350909854490254476388980191672667570095993692
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_key_req.109298869775829678449642478593933509098
544902544763889801916726675700959936920
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.103506169666329905681006936857426301638319586283446620125663036866021170900259
Short name T262
Test name
Test status
Simulation time 16600825 ps
CPU time 0.59 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:21:38 PM PST 23
Peak memory 202060 kb
Host smart-984a3a59-1567-43b9-beae-bf4dceac2f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103506169666329905681006936857426301638319586283446620125663036866
021170900259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.103506169666329905681006936857426301638319586283446620
125663036866021170900259
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.21943164358629660176046959346908482520726709677306800041606257617383097845478
Short name T880
Test name
Test status
Simulation time 9249473390 ps
CPU time 81.07 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:23:21 PM PST 23
Peak memory 202632 kb
Host smart-ddc026cd-96ee-4e58-a524-684b277513aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21943164358629660176046959346908482520726709677306800041606257617383097845478 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.21943164358629660176046959346908482520726709677306800041606257617383097845478
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.61758427030055035226451599463040541677654459985815314554294717292631117235354
Short name T380
Test name
Test status
Simulation time 23162112088 ps
CPU time 744.2 seconds
Started Nov 22 01:20:56 PM PST 23
Finished Nov 22 01:33:25 PM PST 23
Peak memory 364652 kb
Host smart-0c357f7e-5d4a-4c1e-9fa0-5a9566a26974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61758427030055035226451599463040541677654459985815314554294717292631117235354 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.61758427030055035226451599463040541677654459985815314554294717292631117235354
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.104584699389604006111110735082679735704613482170965549899738246170700012476063
Short name T258
Test name
Test status
Simulation time 985753786 ps
CPU time 7.08 seconds
Started Nov 22 01:21:33 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 213160 kb
Host smart-61ee83f1-4e81-4443-be66-c92dd0707bcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104584699389604006111110735082679735704613482170965549899738246170700012476063 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.104584699389604006111110735082679735704613482170965549899738246170700012476063
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.102101582501262828277633920558294269309759022430303168455971678185549798220763
Short name T370
Test name
Test status
Simulation time 209242141 ps
CPU time 71.74 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:23:10 PM PST 23
Peak memory 351052 kb
Host smart-5706645f-9397-400f-8938-c2a3e2aa9cf3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021015825012628282776339205582942693097590224303031684
55971678185549798220763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max_throughput.10210158250126282827763392055829426
9309759022430303168455971678185549798220763
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.11527869491607646918706355460646434643020072852430064871396886960131162447588
Short name T793
Test name
Test status
Simulation time 166171057 ps
CPU time 2.96 seconds
Started Nov 22 01:21:21 PM PST 23
Finished Nov 22 01:21:28 PM PST 23
Peak memory 215712 kb
Host smart-ff5facc3-80cd-4b38-8cce-3406291ac884
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11527869491607646918706355460646434643020072852430064871396886960131
162447588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.1152786949160764691870635546064643464302007285243
0064871396886960131162447588
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.114237115983677022646018535912072560449808644796688586618989058644678564066439
Short name T493
Test name
Test status
Simulation time 590810517 ps
CPU time 5.5 seconds
Started Nov 22 01:21:08 PM PST 23
Finished Nov 22 01:21:15 PM PST 23
Peak memory 202496 kb
Host smart-0a836996-e1eb-44f2-a7fb-57eae931ef7d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114237115983677022646018535912072560449808644796688586618989058644678564066439
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.114237115983677022646018535912072560449808644796688586618989058644678564066439
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.71595647345222049492819171507135257132161090602993901527284152972077074868240
Short name T369
Test name
Test status
Simulation time 21947461091 ps
CPU time 782.58 seconds
Started Nov 22 01:21:15 PM PST 23
Finished Nov 22 01:34:19 PM PST 23
Peak memory 371384 kb
Host smart-6a9e86d8-f0d8-473f-8ab9-7434fe8d13d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71595647345222049492819171507135257132161090602993901527284152972077074868240 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.71595647345222049492819171507135257132161090602993901527284152972077074868240
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.4940226391140546894112416985046233697431337210926695151215166443504139616827
Short name T488
Test name
Test status
Simulation time 445204539 ps
CPU time 13.87 seconds
Started Nov 22 01:20:55 PM PST 23
Finished Nov 22 01:21:14 PM PST 23
Peak memory 246540 kb
Host smart-e3f7aaed-7209-4990-a935-201de5f86484
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494022639114054689411241698504623369743133721092669515121516644350413
9616827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.49402263911405468941124169850462336974313372109266951512
15166443504139616827
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.84561377665473038285458825499755269632339656604554810582752011106176887211373
Short name T1004
Test name
Test status
Simulation time 42305619653 ps
CPU time 541.63 seconds
Started Nov 22 01:21:12 PM PST 23
Finished Nov 22 01:30:15 PM PST 23
Peak memory 202692 kb
Host smart-7488ce4b-5435-4b07-9db1-cef02168b162
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845613776654730382854588254997552696323396566045548105827520111061768
87211373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access_b2b.84561377665473038285458825499755269632339
656604554810582752011106176887211373
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.47890552067783369109805107752724097416438771819371307801209140276211436800450
Short name T478
Test name
Test status
Simulation time 40672061 ps
CPU time 0.9 seconds
Started Nov 22 01:22:27 PM PST 23
Finished Nov 22 01:22:33 PM PST 23
Peak memory 202556 kb
Host smart-89bd738d-f65d-47c3-863f-d0a54782a9eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47890552067783369109805107752724097416438771819371307801209140276211436800450 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.47890552067783369109805107752724097416438771819371307801209140276211436800450
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.111255825566961958584367828899197895228543405144048628258115805487543421881991
Short name T282
Test name
Test status
Simulation time 19383553031 ps
CPU time 499.76 seconds
Started Nov 22 01:21:06 PM PST 23
Finished Nov 22 01:29:28 PM PST 23
Peak memory 371664 kb
Host smart-7c5d137f-9c0c-4f5f-a5eb-1105ffe5c2dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111255825566961958584367828899197895228543405144048628258115805487543421881991 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.111255825566961958584367828899197895228543405144048628258115805487543421881991
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.50263457824618149287827590107672156217770018966127915562644636692475924565979
Short name T25
Test name
Test status
Simulation time 216402798 ps
CPU time 1.94 seconds
Started Nov 22 01:21:18 PM PST 23
Finished Nov 22 01:21:22 PM PST 23
Peak memory 220856 kb
Host smart-a5e2d372-665b-4390-bbc2-4ae35f65b182
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5026345782461814928782759010767215621777001896612791556264463669247
5924565979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.502634578246181492878275901076721562177700189661279155626446
36692475924565979
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.100740960478664271298602027923014316142320394829949000388938138505790257505689
Short name T554
Test name
Test status
Simulation time 427865392 ps
CPU time 9.83 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:21:48 PM PST 23
Peak memory 246448 kb
Host smart-6060dcd1-c391-4c71-a3b8-08f8ba1454ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100740960478664271298602027923014316142320394829949000388938138505790257505689 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.100740960478664271298602027923014316142320394829949000388938138505790257505689
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.69023538523044490748150602372808865639186165274740335903605399321661171464937
Short name T940
Test name
Test status
Simulation time 121463254244 ps
CPU time 3052.08 seconds
Started Nov 22 01:21:11 PM PST 23
Finished Nov 22 02:12:05 PM PST 23
Peak memory 375456 kb
Host smart-3d9d2b33-75ad-422e-b857-e936768da01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690235385230444907481506023728088656391861652747403359036053993
21661171464937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.690235385230444907481506023728088656391861652747
40335903605399321661171464937
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.75440453273503556979271545620088625204620730628311726191760143248025949370399
Short name T304
Test name
Test status
Simulation time 624328106 ps
CPU time 1194.74 seconds
Started Nov 22 01:21:06 PM PST 23
Finished Nov 22 01:41:03 PM PST 23
Peak memory 401816 kb
Host smart-83f158c2-0cbd-4fd6-8689-ab4b9d05c684
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=75440453273503556979271545620088625204620730628311726191760143248025949370399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sra
m_ctrl_stress_all_with_rand_reset.75440453273503556979271545620088625204620730628311726191760143248025949370399
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.94173569380646478398754550752922603902196434492159247001467308073382506801161
Short name T561
Test name
Test status
Simulation time 6491370455 ps
CPU time 355.18 seconds
Started Nov 22 01:21:13 PM PST 23
Finished Nov 22 01:27:10 PM PST 23
Peak memory 202560 kb
Host smart-de8334c8-9998-4ee4-936a-475d616d777c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94173569380646478398754550752922603902196434492159247001467308073382506801161
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.9417356938064647839875455075292260390219643449215924
7001467308073382506801161
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.25398933373505817592617051625917210109925141312306791509192776257599248754516
Short name T973
Test name
Test status
Simulation time 237420487 ps
CPU time 93.13 seconds
Started Nov 22 01:21:09 PM PST 23
Finished Nov 22 01:22:43 PM PST 23
Peak memory 351320 kb
Host smart-19a4f23b-82f2-4fbe-b7c2-fc3c6b5dc461
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253989333735058175926170516259172101099251413123067915
09192776257599248754516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.25398933373505817592617
051625917210109925141312306791509192776257599248754516
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.104857521467123605864724159553621512227171584080889866781953672520002456720364
Short name T79
Test name
Test status
Simulation time 4471404472 ps
CPU time 661.37 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:34:08 PM PST 23
Peak memory 375316 kb
Host smart-8c41f6c2-85a5-4dbf-ac3b-72439f674b8f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10485752146712360586472415955362151222717158408088986678195367252000245672036
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during_key_req.10485752146712360586472415955362151222
7171584080889866781953672520002456720364
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.3006556912771304803541505270527442674910501780107097128311277880993041714692
Short name T931
Test name
Test status
Simulation time 16600825 ps
CPU time 0.59 seconds
Started Nov 22 01:24:14 PM PST 23
Finished Nov 22 01:24:19 PM PST 23
Peak memory 201784 kb
Host smart-cbb66abc-a0e1-4ddf-b137-1651ee8d7210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300655691277130480354150527052744267491050178010709712831127788099
3041714692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.3006556912771304803541505270527442674910501780107097128
311277880993041714692
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.12342778663839096865418543598811458252367866417012563343391599237831791066107
Short name T531
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.52 seconds
Started Nov 22 01:23:09 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 202608 kb
Host smart-d9cc8a58-71e2-4b4e-9f64-cf6ff433403f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12342778663839096865418543598811458252367866417012563343391599237831791066107 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.12342778663839096865418543598811458252367866417012563343391599237831791066107
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.9634169939423743493074083623446345619414124693461977897247276713260867818759
Short name T121
Test name
Test status
Simulation time 23162112088 ps
CPU time 770.5 seconds
Started Nov 22 01:22:35 PM PST 23
Finished Nov 22 01:35:30 PM PST 23
Peak memory 364452 kb
Host smart-aa5e55d7-8045-4da3-9143-8bfe71b53e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9634169939423743493074083623446345619414124693461977897247276713260867818759 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.9634169939423743493074083623446345619414124693461977897247276713260867818759
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.72206890255603464320825077773407530145930620324146991706685261076975818878670
Short name T960
Test name
Test status
Simulation time 985753786 ps
CPU time 7.15 seconds
Started Nov 22 01:22:39 PM PST 23
Finished Nov 22 01:22:51 PM PST 23
Peak memory 213212 kb
Host smart-4b2ab749-42fa-47a0-8973-d43875bfd227
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72206890255603464320825077773407530145930620324146991706685261076975818878670 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.72206890255603464320825077773407530145930620324146991706685261076975818878670
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.84800644061668950723367430299929023076616218397355735256743682869811600006147
Short name T378
Test name
Test status
Simulation time 209242141 ps
CPU time 93.88 seconds
Started Nov 22 01:22:42 PM PST 23
Finished Nov 22 01:24:23 PM PST 23
Peak memory 351096 kb
Host smart-2a26c984-7e6c-425e-a493-9f4e632583a5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8480064406166895072336743029992902307661621839735573525
6743682869811600006147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_max_throughput.84800644061668950723367430299929023
076616218397355735256743682869811600006147
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.15571965833865165232415295309417857238301350416218078308993670274030180286197
Short name T497
Test name
Test status
Simulation time 166171057 ps
CPU time 3.02 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:23:10 PM PST 23
Peak memory 214908 kb
Host smart-808127a5-58c5-4d9f-a222-e1db23d5ec96
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15571965833865165232415295309417857238301350416218078308993670274030
180286197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.155719658338651652324152953094178572383013504162
18078308993670274030180286197
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.101470002379162524497357640670982288755648402880514278613236291468810426779078
Short name T108
Test name
Test status
Simulation time 590810517 ps
CPU time 5.74 seconds
Started Nov 22 01:23:08 PM PST 23
Finished Nov 22 01:23:24 PM PST 23
Peak memory 202600 kb
Host smart-baa5b07c-2c8d-4e0d-abc2-035415fe717e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101470002379162524497357640670982288755648402880514278613236291468810426779078
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.101470002379162524497357640670982288755648402880514278613236291468810426779078
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.12258485658873560493724587827199194145407398860285885607979881725011056509346
Short name T806
Test name
Test status
Simulation time 21947461091 ps
CPU time 598.48 seconds
Started Nov 22 01:22:44 PM PST 23
Finished Nov 22 01:32:54 PM PST 23
Peak memory 371304 kb
Host smart-e27e0681-ff46-4aec-b1b4-caaf4baa775a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12258485658873560493724587827199194145407398860285885607979881725011056509346 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.12258485658873560493724587827199194145407398860285885607979881725011056509346
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.76756977681367392905620162360658138149293851747502786541038190809582118844062
Short name T688
Test name
Test status
Simulation time 445204539 ps
CPU time 10.84 seconds
Started Nov 22 01:22:44 PM PST 23
Finished Nov 22 01:23:01 PM PST 23
Peak memory 246448 kb
Host smart-d5047a15-b0cf-47d8-ad17-f900e00a4cbe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767569776813673929056201623606581381492938517475027865410381908095821
18844062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.767569776813673929056201623606581381492938517475027865
41038190809582118844062
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.93834228443060382154172212107754152910248421328982303265047271474350027926400
Short name T96
Test name
Test status
Simulation time 42305619653 ps
CPU time 537.85 seconds
Started Nov 22 01:23:11 PM PST 23
Finished Nov 22 01:32:17 PM PST 23
Peak memory 202716 kb
Host smart-00123c57-0f3b-4021-95d4-44da12dee17c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938342284430603821541722121077541529102484213289823032650472714743500
27926400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access_b2b.9383422844306038215417221210775415291024
8421328982303265047271474350027926400
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.115193146684128827250321391563035048192455086644354411014180128362880417430658
Short name T677
Test name
Test status
Simulation time 40672061 ps
CPU time 0.84 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:22:51 PM PST 23
Peak memory 202440 kb
Host smart-7741718b-0cf1-46b6-aad8-9db41cd5c068
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115193146684128827250321391563035048192455086644354411014180128362880417430658 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.115193146684128827250321391563035048192455086644354411014180128362880417430658
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.111632639410096838355364380360180954847758773776191508071923447889291146762513
Short name T708
Test name
Test status
Simulation time 19383553031 ps
CPU time 464.73 seconds
Started Nov 22 01:22:48 PM PST 23
Finished Nov 22 01:30:46 PM PST 23
Peak memory 371712 kb
Host smart-f0301ed9-377f-4217-9961-587ead44487b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111632639410096838355364380360180954847758773776191508071923447889291146762513 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.111632639410096838355364380360180954847758773776191508071923447889291146762513
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.11661018894040380990518287940274669932405144802515316309467307757631794110644
Short name T362
Test name
Test status
Simulation time 427865392 ps
CPU time 11.64 seconds
Started Nov 22 01:22:37 PM PST 23
Finished Nov 22 01:22:55 PM PST 23
Peak memory 246556 kb
Host smart-c98f3683-5d56-4b85-b69b-de7ea11f04fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11661018894040380990518287940274669932405144802515316309467307757631794110644 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.11661018894040380990518287940274669932405144802515316309467307757631794110644
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.92910286816818715007728132103908394824428528942078501459506430091164094859162
Short name T869
Test name
Test status
Simulation time 121463254244 ps
CPU time 3133.22 seconds
Started Nov 22 01:22:40 PM PST 23
Finished Nov 22 02:15:01 PM PST 23
Peak memory 375460 kb
Host smart-e3938b73-b181-4a83-800a-553def2e650a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929102868168187150077281321039083948244285289420785014595064300
91164094859162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.92910286816818715007728132103908394824428528942
078501459506430091164094859162
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.102331998893834818700692746509910011232435630458320835278281173528178574029785
Short name T825
Test name
Test status
Simulation time 624328106 ps
CPU time 1268.02 seconds
Started Nov 22 01:22:35 PM PST 23
Finished Nov 22 01:43:48 PM PST 23
Peak memory 401780 kb
Host smart-406e89d7-bd27-40a1-9217-c24791f125d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=102331998893834818700692746509910011232435630458320835278281173528178574029785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s
ram_ctrl_stress_all_with_rand_reset.102331998893834818700692746509910011232435630458320835278281173528178574029785
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.54036826517843256562121107866281309010498540414334919188373013897992372110336
Short name T996
Test name
Test status
Simulation time 6491370455 ps
CPU time 338.95 seconds
Started Nov 22 01:22:31 PM PST 23
Finished Nov 22 01:28:15 PM PST 23
Peak memory 202628 kb
Host smart-f94402e5-b1ac-4611-a8f3-1a97123d1fd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54036826517843256562121107866281309010498540414334919188373013897992372110336
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.540368265178432565621211078662813090104985404143349
19188373013897992372110336
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.38327052525534646699345669085724032596427246435350178369673009574686052272377
Short name T989
Test name
Test status
Simulation time 237420487 ps
CPU time 84.39 seconds
Started Nov 22 01:22:45 PM PST 23
Finished Nov 22 01:24:22 PM PST 23
Peak memory 351368 kb
Host smart-1ba5f577-fd81-480d-9a7c-401ab70c74b2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383270525255346466993456690857240325964272464353501783
69673009574686052272377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3832705252553464669934
5669085724032596427246435350178369673009574686052272377
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.109778420959814338084909469397729645980655953703645463893103068275440510247812
Short name T698
Test name
Test status
Simulation time 4471404472 ps
CPU time 812.03 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:36:39 PM PST 23
Peak memory 375396 kb
Host smart-867d63c3-1a30-47fa-981d-47f927c82b20
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10977842095981433808490946939772964598065595370364546389310306827544051024781
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during_key_req.10977842095981433808490946939772964598
0655953703645463893103068275440510247812
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.59120846017129955808395679441941611242045413325234970168285682230983509152776
Short name T461
Test name
Test status
Simulation time 16600825 ps
CPU time 0.64 seconds
Started Nov 22 01:24:04 PM PST 23
Finished Nov 22 01:24:13 PM PST 23
Peak memory 202196 kb
Host smart-69b076f1-33ae-465b-842f-ea9140bb939b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591208460171299558083956794419416112420454133252349701682856822309
83509152776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.591208460171299558083956794419416112420454133252349701
68285682230983509152776
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.76873961743068201316389824288696298768375803638922676871255464073513352338601
Short name T44
Test name
Test status
Simulation time 9249473390 ps
CPU time 84.96 seconds
Started Nov 22 01:23:45 PM PST 23
Finished Nov 22 01:25:18 PM PST 23
Peak memory 202628 kb
Host smart-f664e607-2d44-4937-9a12-ab5b6794267a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76873961743068201316389824288696298768375803638922676871255464073513352338601 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.76873961743068201316389824288696298768375803638922676871255464073513352338601
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.34491213285703825030823342922386793951252829076850383975944971966824565451928
Short name T810
Test name
Test status
Simulation time 23162112088 ps
CPU time 725.58 seconds
Started Nov 22 01:22:51 PM PST 23
Finished Nov 22 01:35:12 PM PST 23
Peak memory 364648 kb
Host smart-c99cde60-6438-4e8a-b7a9-b5c8cefccf1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491213285703825030823342922386793951252829076850383975944971966824565451928 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.34491213285703825030823342922386793951252829076850383975944971966824565451928
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.44564150866772628454767858057299430799568866453022715199587432543390952072748
Short name T789
Test name
Test status
Simulation time 985753786 ps
CPU time 7.25 seconds
Started Nov 22 01:23:05 PM PST 23
Finished Nov 22 01:23:23 PM PST 23
Peak memory 213104 kb
Host smart-3763ff6e-8046-41f3-abd9-65a2444cb929
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44564150866772628454767858057299430799568866453022715199587432543390952072748 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.44564150866772628454767858057299430799568866453022715199587432543390952072748
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.47914591265117104521569815796036825589083969327620788926700544030378637896795
Short name T970
Test name
Test status
Simulation time 209242141 ps
CPU time 92.1 seconds
Started Nov 22 01:23:58 PM PST 23
Finished Nov 22 01:25:36 PM PST 23
Peak memory 351344 kb
Host smart-80b4c3cf-be3f-4561-8869-6011854787d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4791459126511710452156981579603682558908396932762078892
6700544030378637896795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_max_throughput.47914591265117104521569815796036825
589083969327620788926700544030378637896795
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.65852670214872912964841966869600402672036317418547815112170336275428632688826
Short name T399
Test name
Test status
Simulation time 166171057 ps
CPU time 3.15 seconds
Started Nov 22 01:23:02 PM PST 23
Finished Nov 22 01:23:16 PM PST 23
Peak memory 215720 kb
Host smart-6a3aeb5e-0b46-49a0-935b-50f7a6aa0414
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65852670214872912964841966869600402672036317418547815112170336275428
632688826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.658526702148729129648419668696004026720363174185
47815112170336275428632688826
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.54093070269691655961344569322975488617457642868227848964901269934684458590033
Short name T687
Test name
Test status
Simulation time 590810517 ps
CPU time 5.35 seconds
Started Nov 22 01:22:51 PM PST 23
Finished Nov 22 01:23:11 PM PST 23
Peak memory 202436 kb
Host smart-61b9ad93-64f1-4e84-98a9-f363b254f621
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54093070269691655961344569322975488617457642868227848964901269934684458590033
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.54093070269691655961344569322975488617457642868227848964901269934684458590033
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.16029939475893786464507491975508923668984920509790905761917193135297866428999
Short name T590
Test name
Test status
Simulation time 21947461091 ps
CPU time 782.24 seconds
Started Nov 22 01:22:49 PM PST 23
Finished Nov 22 01:36:05 PM PST 23
Peak memory 371368 kb
Host smart-cf7b3000-56e5-47ec-a08d-009e64ac3015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16029939475893786464507491975508923668984920509790905761917193135297866428999 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.16029939475893786464507491975508923668984920509790905761917193135297866428999
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.63432659133666933838326094280625862912280168260856692018388793200205693911908
Short name T711
Test name
Test status
Simulation time 445204539 ps
CPU time 12.8 seconds
Started Nov 22 01:22:47 PM PST 23
Finished Nov 22 01:23:13 PM PST 23
Peak memory 246576 kb
Host smart-666b47a9-7755-40be-bde5-664032b53d0f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634326591336669338383260942806258629122801682608566920183887932002056
93911908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.634326591336669338383260942806258629122801682608566920
18388793200205693911908
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.100376085826933028172977718233196215759210850713939604963374341388960354658690
Short name T802
Test name
Test status
Simulation time 42305619653 ps
CPU time 533.61 seconds
Started Nov 22 01:22:40 PM PST 23
Finished Nov 22 01:31:41 PM PST 23
Peak memory 202716 kb
Host smart-653a8a1d-90a3-4851-82cc-82b51f407c51
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100376085826933028172977718233196215759210850713939604963374341388960
354658690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access_b2b.100376085826933028172977718233196215759
210850713939604963374341388960354658690
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.64761054167280598574921805514805880248511894769196140996821045404820582868766
Short name T1022
Test name
Test status
Simulation time 40672061 ps
CPU time 0.9 seconds
Started Nov 22 01:25:26 PM PST 23
Finished Nov 22 01:25:36 PM PST 23
Peak memory 200784 kb
Host smart-cd9c157a-9cc8-4aa9-a8f3-2a09ff87aca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64761054167280598574921805514805880248511894769196140996821045404820582868766 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.64761054167280598574921805514805880248511894769196140996821045404820582868766
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.27851247728351297242413279217662358462029428678966569121009783301467388707501
Short name T890
Test name
Test status
Simulation time 19383553031 ps
CPU time 550.92 seconds
Started Nov 22 01:23:04 PM PST 23
Finished Nov 22 01:32:25 PM PST 23
Peak memory 371840 kb
Host smart-876aa32f-6d38-4978-8754-98d92b2c6106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27851247728351297242413279217662358462029428678966569121009783301467388707501 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.27851247728351297242413279217662358462029428678966569121009783301467388707501
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.94497412813441802338128813288486868258027172624311757809600723165039252110587
Short name T140
Test name
Test status
Simulation time 427865392 ps
CPU time 12.78 seconds
Started Nov 22 01:22:34 PM PST 23
Finished Nov 22 01:22:52 PM PST 23
Peak memory 246608 kb
Host smart-bf82d035-e19a-4182-b962-cfb33b07295d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94497412813441802338128813288486868258027172624311757809600723165039252110587 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.94497412813441802338128813288486868258027172624311757809600723165039252110587
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.99461594207613885670288294153584717626319501448597985015385359762627974913547
Short name T1027
Test name
Test status
Simulation time 121463254244 ps
CPU time 3098.47 seconds
Started Nov 22 01:23:05 PM PST 23
Finished Nov 22 02:14:55 PM PST 23
Peak memory 375380 kb
Host smart-6b8e6d2d-02b1-490c-843b-31788433f763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994615942076138856702882941535847176263195014485979850153853597
62627974913547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.99461594207613885670288294153584717626319501448
597985015385359762627974913547
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.34370102316908948492659853074304976369513694265038260593300549092267732115846
Short name T982
Test name
Test status
Simulation time 624328106 ps
CPU time 1238.49 seconds
Started Nov 22 01:23:32 PM PST 23
Finished Nov 22 01:44:24 PM PST 23
Peak memory 401816 kb
Host smart-4a06d88b-e2d4-4e4f-85af-8319fd7e3a33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=34370102316908948492659853074304976369513694265038260593300549092267732115846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sr
am_ctrl_stress_all_with_rand_reset.34370102316908948492659853074304976369513694265038260593300549092267732115846
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.110100428591535783175364237998889351330377991466775210749568897586609084751220
Short name T585
Test name
Test status
Simulation time 6491370455 ps
CPU time 369 seconds
Started Nov 22 01:22:53 PM PST 23
Finished Nov 22 01:29:16 PM PST 23
Peak memory 202732 kb
Host smart-8c288301-5c19-4c07-81cb-ffa293fee86a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11010042859153578317536423799888935133037799146677521074956889758660908475122
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.11010042859153578317536423799888935133037799146677
5210749568897586609084751220
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.50711361106685758281483707342847654371507839239646902092676739413931451376614
Short name T398
Test name
Test status
Simulation time 237420487 ps
CPU time 113.96 seconds
Started Nov 22 01:22:45 PM PST 23
Finished Nov 22 01:24:52 PM PST 23
Peak memory 351304 kb
Host smart-1a66a6a7-34a3-4eba-b2d4-6fda28a7315d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507113611066857582814837073428476543715078392396469020
92676739413931451376614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.5071136110668575828148
3707342847654371507839239646902092676739413931451376614
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.7977329683116348905288221476685830040337404588093562946150038658065719172099
Short name T527
Test name
Test status
Simulation time 4471404472 ps
CPU time 680.89 seconds
Started Nov 22 01:24:07 PM PST 23
Finished Nov 22 01:35:33 PM PST 23
Peak memory 375484 kb
Host smart-7bf1b888-9cb7-4f0f-a2f6-5577cabdf36c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7977329683116348905288221476685830040337404588093562946150038658065719172099
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during_key_req.7977329683116348905288221476685830040337
404588093562946150038658065719172099
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.38292118278574291140368809960217239175491234482992208791875134473683447264053
Short name T602
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:23:12 PM PST 23
Finished Nov 22 01:23:21 PM PST 23
Peak memory 202072 kb
Host smart-1d6b82af-176b-4e3c-96ec-068e49ddbd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382921182785742911403688099602172391754912344829922087918751344736
83447264053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.382921182785742911403688099602172391754912344829922087
91875134473683447264053
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.55129952532890587348528471461968490546657577466694412282524693002873487590036
Short name T663
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.79 seconds
Started Nov 22 01:22:40 PM PST 23
Finished Nov 22 01:24:09 PM PST 23
Peak memory 202628 kb
Host smart-ef3457da-052b-4ec3-b674-65ffae35b8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55129952532890587348528471461968490546657577466694412282524693002873487590036 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.55129952532890587348528471461968490546657577466694412282524693002873487590036
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.50398041701435396650770539777471309067119776523862136864055449202420166144406
Short name T254
Test name
Test status
Simulation time 23162112088 ps
CPU time 609.92 seconds
Started Nov 22 01:24:10 PM PST 23
Finished Nov 22 01:34:24 PM PST 23
Peak memory 362920 kb
Host smart-8ff69271-5a03-49e1-8c84-e45d32e482df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50398041701435396650770539777471309067119776523862136864055449202420166144406 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.50398041701435396650770539777471309067119776523862136864055449202420166144406
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.42473105319659600814500625253228943886084659619996042243895492118983643514628
Short name T263
Test name
Test status
Simulation time 985753786 ps
CPU time 7.22 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 213192 kb
Host smart-a38e7ecf-54bc-4660-8e57-0a811bab239e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42473105319659600814500625253228943886084659619996042243895492118983643514628 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.42473105319659600814500625253228943886084659619996042243895492118983643514628
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.86212585281785893193385345796489193405976647078628730584236094335256671474227
Short name T433
Test name
Test status
Simulation time 209242141 ps
CPU time 84.3 seconds
Started Nov 22 01:22:51 PM PST 23
Finished Nov 22 01:24:31 PM PST 23
Peak memory 351248 kb
Host smart-e7dba4c1-c793-4b7f-ab48-b1c9d5d4b645
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8621258528178589319338534579648919340597664707862873058
4236094335256671474227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_max_throughput.86212585281785893193385345796489193
405976647078628730584236094335256671474227
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.108003257046311806485875182055049267156693994753698146655033961389178618100454
Short name T57
Test name
Test status
Simulation time 166171057 ps
CPU time 2.87 seconds
Started Nov 22 01:23:12 PM PST 23
Finished Nov 22 01:23:23 PM PST 23
Peak memory 215592 kb
Host smart-c1b3e4a4-a422-4552-b82d-264539e580d3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10800325704631180648587518205504926715669399475369814665503396138917
8618100454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.10800325704631180648587518205504926715669399475
3698146655033961389178618100454
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.20448492074437971816018312519813297485942306557920626853295868560017650063307
Short name T460
Test name
Test status
Simulation time 590810517 ps
CPU time 5.45 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 01:23:23 PM PST 23
Peak memory 202520 kb
Host smart-fea8f149-8e4e-407d-b75c-239f44893dd9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448492074437971816018312519813297485942306557920626853295868560017650063307
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.20448492074437971816018312519813297485942306557920626853295868560017650063307
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.114392471580682171790527669478343165183651305134291616685340191300948155087916
Short name T886
Test name
Test status
Simulation time 21947461091 ps
CPU time 722.7 seconds
Started Nov 22 01:22:59 PM PST 23
Finished Nov 22 01:35:11 PM PST 23
Peak memory 371388 kb
Host smart-545a65e5-c118-46cd-9a01-97682b8d75a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114392471580682171790527669478343165183651305134291616685340191300948155087916 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.114392471580682171790527669478343165183651305134291616685340191300948155087916
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.74775171805250274226752301535876091195725703734648062591462658528267038432468
Short name T512
Test name
Test status
Simulation time 445204539 ps
CPU time 10.98 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:23:18 PM PST 23
Peak memory 245932 kb
Host smart-b67ec975-6b9e-43b5-8738-2d7dd61ef717
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747751718052502742267523015358760911957257037346480625914626585282670
38432468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.747751718052502742267523015358760911957257037346480625
91462658528267038432468
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.59708936186981864824136457134133140573034361233443271437023536298986028730744
Short name T844
Test name
Test status
Simulation time 42305619653 ps
CPU time 530.97 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:31:58 PM PST 23
Peak memory 202600 kb
Host smart-a1e522a3-08ad-4131-a993-9e7aada99c1c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597089361869818648241364571341331405730343612334432714370235362989860
28730744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access_b2b.5970893618698186482413645713413314057303
4361233443271437023536298986028730744
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.90460176393459172787098292149490503409594488023219925005829874380907049733246
Short name T746
Test name
Test status
Simulation time 40672061 ps
CPU time 0.86 seconds
Started Nov 22 01:22:59 PM PST 23
Finished Nov 22 01:23:10 PM PST 23
Peak memory 202632 kb
Host smart-dd1122d3-bf2e-4255-a84f-c58fa1544d5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90460176393459172787098292149490503409594488023219925005829874380907049733246 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.90460176393459172787098292149490503409594488023219925005829874380907049733246
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.77226825393390122072862267926176659362712049084486891977484653230943413981604
Short name T477
Test name
Test status
Simulation time 19383553031 ps
CPU time 482.92 seconds
Started Nov 22 01:22:45 PM PST 23
Finished Nov 22 01:31:00 PM PST 23
Peak memory 371704 kb
Host smart-a3b6a54e-de8a-44b3-8e20-a2f4e3db411a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77226825393390122072862267926176659362712049084486891977484653230943413981604 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.77226825393390122072862267926176659362712049084486891977484653230943413981604
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.105107523433331636740378296896184080295016604340040918766181362691111894917124
Short name T871
Test name
Test status
Simulation time 427865392 ps
CPU time 10.88 seconds
Started Nov 22 01:23:44 PM PST 23
Finished Nov 22 01:24:03 PM PST 23
Peak memory 246436 kb
Host smart-c54b32de-6e1f-4a21-a2ff-0ab6420535f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105107523433331636740378296896184080295016604340040918766181362691111894917124 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.105107523433331636740378296896184080295016604340040918766181362691111894917124
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.48376231920435186849904540959579573517837741670123115714646237679496333462067
Short name T123
Test name
Test status
Simulation time 121463254244 ps
CPU time 3592.47 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 02:23:10 PM PST 23
Peak memory 375444 kb
Host smart-06891bbd-7c28-47d1-8794-bbcef78d85e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483762319204351868499045409595795735178377416701231157146462376
79496333462067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.48376231920435186849904540959579573517837741670
123115714646237679496333462067
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.104817278671658295831275890835312706776675967911435575368376218050846694493029
Short name T604
Test name
Test status
Simulation time 624328106 ps
CPU time 1489.15 seconds
Started Nov 22 01:23:32 PM PST 23
Finished Nov 22 01:48:35 PM PST 23
Peak memory 401816 kb
Host smart-b5a80294-a8c9-4c1a-a00a-38345ca9f0fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=104817278671658295831275890835312706776675967911435575368376218050846694493029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s
ram_ctrl_stress_all_with_rand_reset.104817278671658295831275890835312706776675967911435575368376218050846694493029
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.6763374985681695731413341250579543217055773632363103651559902474847620438449
Short name T662
Test name
Test status
Simulation time 6491370455 ps
CPU time 343.98 seconds
Started Nov 22 01:22:51 PM PST 23
Finished Nov 22 01:28:50 PM PST 23
Peak memory 202612 kb
Host smart-30126e64-480a-4b71-911f-aa3594f542f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6763374985681695731413341250579543217055773632363103651559902474847620438449
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.6763374985681695731413341250579543217055773632363103
651559902474847620438449
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.115630001725409125248502478286125448541958504942844605329334289206543387821548
Short name T106
Test name
Test status
Simulation time 237420487 ps
CPU time 98.32 seconds
Started Nov 22 01:23:03 PM PST 23
Finished Nov 22 01:24:52 PM PST 23
Peak memory 351336 kb
Host smart-20d8beec-188d-440a-a25a-b4aa3d332f56
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115630001725409125248502478286125448541958504942844605
329334289206543387821548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.115630001725409125248
502478286125448541958504942844605329334289206543387821548
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.59568379216920488632820911349943865362507334883609411433827839009876750853380
Short name T730
Test name
Test status
Simulation time 4471404472 ps
CPU time 1032.11 seconds
Started Nov 22 01:23:32 PM PST 23
Finished Nov 22 01:40:57 PM PST 23
Peak memory 375508 kb
Host smart-e1e4ebba-9778-4453-b156-edb1af510a97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59568379216920488632820911349943865362507334883609411433827839009876750853380
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during_key_req.595683792169204886328209113499438653625
07334883609411433827839009876750853380
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.41508295274417293072349535677954434693495291405331618213941373243968860954825
Short name T667
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:24:05 PM PST 23
Finished Nov 22 01:24:12 PM PST 23
Peak memory 202016 kb
Host smart-0447164f-94e5-466c-9a49-5e8dd460c19b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415082952744172930723495356779544346934952914053316182139413732439
68860954825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.415082952744172930723495356779544346934952914053316182
13941373243968860954825
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.107085100906894759430902772723655348279585872806151728968827212313167949844562
Short name T983
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.57 seconds
Started Nov 22 01:23:10 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 202660 kb
Host smart-eb0a77c7-516a-4e2b-9d47-195cdbd0ba22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107085100906894759430902772723655348279585872806151728968827212313167949844562 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.107085100906894759430902772723655348279585872806151728968827212313167949844562
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.77573189432209705948476261367896162206063221392625883248034404843355420375184
Short name T953
Test name
Test status
Simulation time 23162112088 ps
CPU time 686.84 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:34:33 PM PST 23
Peak memory 364336 kb
Host smart-32969bd3-7483-42c2-81b7-9c623c1c5ab6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77573189432209705948476261367896162206063221392625883248034404843355420375184 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.77573189432209705948476261367896162206063221392625883248034404843355420375184
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.78800977956106845522945127624197601962503575457997370332046578685263654384083
Short name T337
Test name
Test status
Simulation time 985753786 ps
CPU time 7.02 seconds
Started Nov 22 01:23:05 PM PST 23
Finished Nov 22 01:23:23 PM PST 23
Peak memory 213188 kb
Host smart-1c431c26-50cd-4612-a2a7-445876826661
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78800977956106845522945127624197601962503575457997370332046578685263654384083 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.78800977956106845522945127624197601962503575457997370332046578685263654384083
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.108485848815304396976398805069742123405941289533044817551836031173283775371087
Short name T727
Test name
Test status
Simulation time 209242141 ps
CPU time 106.33 seconds
Started Nov 22 01:22:42 PM PST 23
Finished Nov 22 01:24:35 PM PST 23
Peak memory 351348 kb
Host smart-ab554be4-9472-4ad8-9bc6-b4d210402021
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084858488153043969763988050697421234059412895330448175
51836031173283775371087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_max_throughput.1084858488153043969763988050697421
23405941289533044817551836031173283775371087
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.64982838406137550136211884364593422904067203296746128156792534338223964523635
Short name T592
Test name
Test status
Simulation time 166171057 ps
CPU time 3.01 seconds
Started Nov 22 01:24:05 PM PST 23
Finished Nov 22 01:24:15 PM PST 23
Peak memory 215552 kb
Host smart-379c7357-48da-4317-ba19-a20ccd0ecc70
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64982838406137550136211884364593422904067203296746128156792534338223
964523635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.649828384061375501362118843645934229040672032967
46128156792534338223964523635
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.113466960442165833164512319700809024699165115480079492882139591590185470162038
Short name T689
Test name
Test status
Simulation time 590810517 ps
CPU time 5.63 seconds
Started Nov 22 01:24:14 PM PST 23
Finished Nov 22 01:24:23 PM PST 23
Peak memory 202104 kb
Host smart-da3aee37-c393-43f7-bd16-248c501efe0d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113466960442165833164512319700809024699165115480079492882139591590185470162038
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.113466960442165833164512319700809024699165115480079492882139591590185470162038
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.54752095701945943659449281108208200687001412903076724882519239103835493728839
Short name T256
Test name
Test status
Simulation time 21947461091 ps
CPU time 742.93 seconds
Started Nov 22 01:23:04 PM PST 23
Finished Nov 22 01:35:38 PM PST 23
Peak memory 371352 kb
Host smart-ed9c53b1-ed36-4b14-a723-624698d3993f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54752095701945943659449281108208200687001412903076724882519239103835493728839 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.54752095701945943659449281108208200687001412903076724882519239103835493728839
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.12404690036990706896933731769188139824336631218348425370843569041049202232871
Short name T296
Test name
Test status
Simulation time 445204539 ps
CPU time 12.57 seconds
Started Nov 22 01:23:02 PM PST 23
Finished Nov 22 01:23:26 PM PST 23
Peak memory 246448 kb
Host smart-d519d0cf-933d-4d1e-9de6-4f08313e029e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124046900369907068969337317691881398243366312183484253708435690410492
02232871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.124046900369907068969337317691881398243366312183484253
70843569041049202232871
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.7758713265249514288741464267634964043345624300066058094673666078214663636011
Short name T295
Test name
Test status
Simulation time 42305619653 ps
CPU time 525.63 seconds
Started Nov 22 01:23:06 PM PST 23
Finished Nov 22 01:32:02 PM PST 23
Peak memory 202592 kb
Host smart-646b2134-62b4-4045-be17-5aba53ee52d0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775871326524951428874146426763496404334562430006605809467366607821466
3636011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access_b2b.77587132652495142887414642676349640433456
24300066058094673666078214663636011
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.16664095586185458855442638764449985701175647123457064168800239187485746239400
Short name T773
Test name
Test status
Simulation time 40672061 ps
CPU time 0.85 seconds
Started Nov 22 01:23:00 PM PST 23
Finished Nov 22 01:23:12 PM PST 23
Peak memory 202608 kb
Host smart-81927473-1780-4d03-8faa-5a034a4d2981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16664095586185458855442638764449985701175647123457064168800239187485746239400 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.16664095586185458855442638764449985701175647123457064168800239187485746239400
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.33883016682683902559812497807717087207816021779290180610186513511621772622630
Short name T453
Test name
Test status
Simulation time 19383553031 ps
CPU time 567.26 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:32:17 PM PST 23
Peak memory 371824 kb
Host smart-8a6b2b51-6439-465b-8a43-1aefadc018f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33883016682683902559812497807717087207816021779290180610186513511621772622630 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.33883016682683902559812497807717087207816021779290180610186513511621772622630
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.39018246115942262952029611944492264685830676277662363808232053016008839576384
Short name T920
Test name
Test status
Simulation time 427865392 ps
CPU time 11.93 seconds
Started Nov 22 01:23:05 PM PST 23
Finished Nov 22 01:23:28 PM PST 23
Peak memory 246476 kb
Host smart-bc1d3395-176d-4b4c-ae52-6b39a6829caa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39018246115942262952029611944492264685830676277662363808232053016008839576384 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.39018246115942262952029611944492264685830676277662363808232053016008839576384
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.36078999479833617686386189607074263805146052684765217503944599387599772770538
Short name T379
Test name
Test status
Simulation time 121463254244 ps
CPU time 3686.02 seconds
Started Nov 22 01:23:02 PM PST 23
Finished Nov 22 02:24:40 PM PST 23
Peak memory 375456 kb
Host smart-bf9a89cc-5714-4f7b-94f0-b52f982b98d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360789994798336176863861896070742638051460526847652175039445993
87599772770538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.36078999479833617686386189607074263805146052684
765217503944599387599772770538
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.76220056386358724486211285565857037960614098654797564025073275187612662943837
Short name T16
Test name
Test status
Simulation time 624328106 ps
CPU time 1322.45 seconds
Started Nov 22 01:23:02 PM PST 23
Finished Nov 22 01:45:16 PM PST 23
Peak memory 401784 kb
Host smart-6e950807-7c30-4690-95ff-1b7205c1cece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=76220056386358724486211285565857037960614098654797564025073275187612662943837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sr
am_ctrl_stress_all_with_rand_reset.76220056386358724486211285565857037960614098654797564025073275187612662943837
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.81577165017458137188073602057195702624063577599108979451281744076387854733340
Short name T336
Test name
Test status
Simulation time 6491370455 ps
CPU time 363.31 seconds
Started Nov 22 01:23:53 PM PST 23
Finished Nov 22 01:30:04 PM PST 23
Peak memory 202632 kb
Host smart-670f378a-6035-42dc-a9fc-7edde5cb4053
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81577165017458137188073602057195702624063577599108979451281744076387854733340
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.815771650174581371880736020571957026240635775991089
79451281744076387854733340
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.85574228340803148204763610565847036662800462989061798906142812772235749237047
Short name T326
Test name
Test status
Simulation time 237420487 ps
CPU time 106.53 seconds
Started Nov 22 01:22:50 PM PST 23
Finished Nov 22 01:24:51 PM PST 23
Peak memory 351324 kb
Host smart-2dcae79c-40e5-49b3-a567-146b66532bfe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855742283408031482047636105658470366628004629890617989
06142812772235749237047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.8557422834080314820476
3610565847036662800462989061798906142812772235749237047
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.81021288788121998726500011542393088852093111862323357720533957145095455363990
Short name T942
Test name
Test status
Simulation time 4471404472 ps
CPU time 840.65 seconds
Started Nov 22 01:22:46 PM PST 23
Finished Nov 22 01:37:00 PM PST 23
Peak memory 375444 kb
Host smart-42947621-cd90-4fa8-874e-7085fba5346f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81021288788121998726500011542393088852093111862323357720533957145095455363990
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during_key_req.810212887881219987265000115423930888520
93111862323357720533957145095455363990
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.28246585678805576326024285339799687656113600592629689590756410165021629317803
Short name T756
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:22:57 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 202140 kb
Host smart-d943af57-842c-4ae1-a971-38da830752f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282465856788055763260242853397996876561136005926296895907564101650
21629317803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.282465856788055763260242853397996876561136005926296895
90756410165021629317803
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.36662172289663043780918610383639738649771753131504757887479608272618266970147
Short name T719
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.8 seconds
Started Nov 22 01:22:59 PM PST 23
Finished Nov 22 01:24:32 PM PST 23
Peak memory 202640 kb
Host smart-682df6a0-be55-4b48-afa2-abacff5f17df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36662172289663043780918610383639738649771753131504757887479608272618266970147 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.36662172289663043780918610383639738649771753131504757887479608272618266970147
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.60161730893757277022566072949754072458428812346973525613918226329077328500372
Short name T117
Test name
Test status
Simulation time 23162112088 ps
CPU time 638.63 seconds
Started Nov 22 01:22:43 PM PST 23
Finished Nov 22 01:33:29 PM PST 23
Peak memory 364632 kb
Host smart-0a19be0c-ea90-45e6-8a5c-9f575942ed2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60161730893757277022566072949754072458428812346973525613918226329077328500372 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.60161730893757277022566072949754072458428812346973525613918226329077328500372
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.27126775782401359810220999556874426886607072462044713609566318066031433778057
Short name T609
Test name
Test status
Simulation time 985753786 ps
CPU time 7.16 seconds
Started Nov 22 01:22:47 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 213224 kb
Host smart-2dce6ebf-fe6d-46eb-ad42-c4913165f947
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27126775782401359810220999556874426886607072462044713609566318066031433778057 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.27126775782401359810220999556874426886607072462044713609566318066031433778057
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.52750064333656169894990142264963134730388268422230421461226357207092797887457
Short name T397
Test name
Test status
Simulation time 209242141 ps
CPU time 133.13 seconds
Started Nov 22 01:22:53 PM PST 23
Finished Nov 22 01:25:20 PM PST 23
Peak memory 351156 kb
Host smart-7f92dba2-9eb3-4ef7-b911-2b4bd4524662
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5275006433365616989499014226496313473038826842223042146
1226357207092797887457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_max_throughput.52750064333656169894990142264963134
730388268422230421461226357207092797887457
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.84958142507378979241500852145269314614198946334721880295178144314699308487622
Short name T933
Test name
Test status
Simulation time 166171057 ps
CPU time 3.1 seconds
Started Nov 22 01:22:50 PM PST 23
Finished Nov 22 01:23:07 PM PST 23
Peak memory 215696 kb
Host smart-c2817d23-6504-4423-b54a-bfff2a9facd3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84958142507378979241500852145269314614198946334721880295178144314699
308487622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.849581425073789792415008521452693146141989463347
21880295178144314699308487622
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.50232675932091982555754627397012566454585885197296435813705026344289957634650
Short name T586
Test name
Test status
Simulation time 590810517 ps
CPU time 5.54 seconds
Started Nov 22 01:22:49 PM PST 23
Finished Nov 22 01:23:09 PM PST 23
Peak memory 202584 kb
Host smart-2d55ff7d-f9ac-426e-b5e6-0cbcf3a41ef1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50232675932091982555754627397012566454585885197296435813705026344289957634650
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.50232675932091982555754627397012566454585885197296435813705026344289957634650
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.65839069170430406076086421863895516198044992949595365279837878364467745564325
Short name T125
Test name
Test status
Simulation time 21947461091 ps
CPU time 676.75 seconds
Started Nov 22 01:22:40 PM PST 23
Finished Nov 22 01:34:04 PM PST 23
Peak memory 371384 kb
Host smart-3d1158b2-11da-4eee-9613-869c9974cb1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65839069170430406076086421863895516198044992949595365279837878364467745564325 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.65839069170430406076086421863895516198044992949595365279837878364467745564325
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.46368212064825787790361824114697899037577857494037569201948508496977174383315
Short name T468
Test name
Test status
Simulation time 445204539 ps
CPU time 11.38 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:23:18 PM PST 23
Peak memory 246508 kb
Host smart-6495eceb-f23c-4edc-9548-504b3a3e0143
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463682120648257877903618241146978990375778574940375692019485084969771
74383315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.463682120648257877903618241146978990375778574940375692
01948508496977174383315
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.96506386336275148225086980411331510781253452789678304741120866225784306370711
Short name T138
Test name
Test status
Simulation time 42305619653 ps
CPU time 542.65 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:32:09 PM PST 23
Peak memory 202724 kb
Host smart-5fcfd8b5-0aab-4f09-ae3b-868fba145bb2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965063863362751482250869804113315107812534527896783047411208662257843
06370711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access_b2b.9650638633627514822508698041133151078125
3452789678304741120866225784306370711
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.62301990980825683801444063699305124082098091002182382865046166447679561457890
Short name T936
Test name
Test status
Simulation time 40672061 ps
CPU time 0.84 seconds
Started Nov 22 01:22:45 PM PST 23
Finished Nov 22 01:22:57 PM PST 23
Peak memory 202484 kb
Host smart-ea0a7b5f-05fd-4b19-b9e8-c217c8a687f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62301990980825683801444063699305124082098091002182382865046166447679561457890 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.62301990980825683801444063699305124082098091002182382865046166447679561457890
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.21670171273209610947008885656889399750127269670272988918747881170292054028167
Short name T363
Test name
Test status
Simulation time 19383553031 ps
CPU time 477.73 seconds
Started Nov 22 01:23:03 PM PST 23
Finished Nov 22 01:31:12 PM PST 23
Peak memory 371820 kb
Host smart-835b6597-e8cc-4cdd-89b6-67a34d51ceea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670171273209610947008885656889399750127269670272988918747881170292054028167 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.21670171273209610947008885656889399750127269670272988918747881170292054028167
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.75655792654850184450479129875477441050262910794601670892181224325547434310329
Short name T702
Test name
Test status
Simulation time 427865392 ps
CPU time 10.99 seconds
Started Nov 22 01:22:54 PM PST 23
Finished Nov 22 01:23:18 PM PST 23
Peak memory 246480 kb
Host smart-6ef7d493-199c-4db5-a618-ad4e19224c82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75655792654850184450479129875477441050262910794601670892181224325547434310329 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.75655792654850184450479129875477441050262910794601670892181224325547434310329
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.81240949379390730060602403635280804912746811068793407578784835039101742419107
Short name T632
Test name
Test status
Simulation time 121463254244 ps
CPU time 3167.58 seconds
Started Nov 22 01:22:58 PM PST 23
Finished Nov 22 02:15:55 PM PST 23
Peak memory 375488 kb
Host smart-5f427fd1-0344-4f72-aa41-be7fd31ff8d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812409493793907300606024036352808049127468110687934075787848350
39101742419107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.81240949379390730060602403635280804912746811068
793407578784835039101742419107
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.19929713051305737355352417141507150167467018617859428176736065610991294813384
Short name T904
Test name
Test status
Simulation time 624328106 ps
CPU time 1216.91 seconds
Started Nov 22 01:22:48 PM PST 23
Finished Nov 22 01:43:19 PM PST 23
Peak memory 401804 kb
Host smart-5071158a-b8f9-41c8-b1e3-f7f4343bbff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=19929713051305737355352417141507150167467018617859428176736065610991294813384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sr
am_ctrl_stress_all_with_rand_reset.19929713051305737355352417141507150167467018617859428176736065610991294813384
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.100714385279725271632459920497588600050225885989672851693442229107417554753768
Short name T1012
Test name
Test status
Simulation time 6491370455 ps
CPU time 350.86 seconds
Started Nov 22 01:23:05 PM PST 23
Finished Nov 22 01:29:07 PM PST 23
Peak memory 202664 kb
Host smart-d8ec08de-90e9-4b3f-bb8d-b728d6aac1ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10071438527972527163245992049758860005022588598967285169344222910741755475376
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.10071438527972527163245992049758860005022588598967
2851693442229107417554753768
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.50302660298010243769468544089980249872489754309218574675061781670927473005442
Short name T438
Test name
Test status
Simulation time 237420487 ps
CPU time 101.65 seconds
Started Nov 22 01:22:44 PM PST 23
Finished Nov 22 01:24:38 PM PST 23
Peak memory 351348 kb
Host smart-b1cc3457-ba23-4c11-875c-eda1127afe08
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503026602980102437694685440899802498724897543092185746
75061781670927473005442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.5030266029801024376946
8544089980249872489754309218574675061781670927473005442
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.4264370688063101832323801437058224293272259376030552242799960127695152220303
Short name T277
Test name
Test status
Simulation time 4471404472 ps
CPU time 740.26 seconds
Started Nov 22 01:23:08 PM PST 23
Finished Nov 22 01:35:39 PM PST 23
Peak memory 375452 kb
Host smart-54252c4e-391b-4ab8-bf46-3ce8aea9deeb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264370688063101832323801437058224293272259376030552242799960127695152220303
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during_key_req.4264370688063101832323801437058224293272
259376030552242799960127695152220303
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.45369581915407095638894691373732244188285161378697124282416062767503205722037
Short name T962
Test name
Test status
Simulation time 16600825 ps
CPU time 0.67 seconds
Started Nov 22 01:22:50 PM PST 23
Finished Nov 22 01:23:04 PM PST 23
Peak memory 202184 kb
Host smart-c4ca5b35-7b2a-48df-9d8b-26c306958aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453695819154070956388946913737322441882851613786971242824160627675
03205722037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.453695819154070956388946913737322441882851613786971242
82416062767503205722037
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.102405566706459531000796772646363105847723043363270672422759630689871388717798
Short name T654
Test name
Test status
Simulation time 9249473390 ps
CPU time 84.57 seconds
Started Nov 22 01:23:08 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 202608 kb
Host smart-961a88dd-d9c1-45cf-8eaf-bce9070f878d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102405566706459531000796772646363105847723043363270672422759630689871388717798 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.102405566706459531000796772646363105847723043363270672422759630689871388717798
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.23573056974758635265702850807907269014011918817980634094544997971286058630763
Short name T146
Test name
Test status
Simulation time 23162112088 ps
CPU time 809.75 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:36:36 PM PST 23
Peak memory 364540 kb
Host smart-fb5c88f5-3ad3-4993-939b-afeb2171d022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23573056974758635265702850807907269014011918817980634094544997971286058630763 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.23573056974758635265702850807907269014011918817980634094544997971286058630763
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.4142548324665885882697066011298168233135514340577872670008386375490744858099
Short name T1011
Test name
Test status
Simulation time 985753786 ps
CPU time 7.23 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:23:14 PM PST 23
Peak memory 213188 kb
Host smart-0117f1a0-370b-4417-98a4-31f5632cf6c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142548324665885882697066011298168233135514340577872670008386375490744858099 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.4142548324665885882697066011298168233135514340577872670008386375490744858099
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.50454740754571347439615712435448981284353617917595676401180731100501637162240
Short name T1037
Test name
Test status
Simulation time 209242141 ps
CPU time 108.2 seconds
Started Nov 22 01:22:56 PM PST 23
Finished Nov 22 01:24:55 PM PST 23
Peak memory 351352 kb
Host smart-1feea372-b22b-4610-9c41-6c216566327f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5045474075457134743961571243544898128435361791759567640
1180731100501637162240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_max_throughput.50454740754571347439615712435448981
284353617917595676401180731100501637162240
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.48335818171783460828441879273109565362781265088516431055905975566887238298859
Short name T552
Test name
Test status
Simulation time 166171057 ps
CPU time 3.16 seconds
Started Nov 22 01:23:06 PM PST 23
Finished Nov 22 01:23:19 PM PST 23
Peak memory 215724 kb
Host smart-326409da-df75-443b-a3a4-09ec171d03f9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48335818171783460828441879273109565362781265088516431055905975566887
238298859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.483358181717834608284418792731095653627812650885
16431055905975566887238298859
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.3006672260875410308113425830547210403519944616268564670185122976566384354711
Short name T492
Test name
Test status
Simulation time 590810517 ps
CPU time 5.87 seconds
Started Nov 22 01:22:58 PM PST 23
Finished Nov 22 01:23:13 PM PST 23
Peak memory 202564 kb
Host smart-ebce3245-c996-421c-992f-bcd2a060afd6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006672260875410308113425830547210403519944616268564670185122976566384354711 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.3006672260875410308113425830547210403519944616268564670185122976566384354711
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.110186172614317348691791567352971214549053800636405696018352760092577543021574
Short name T966
Test name
Test status
Simulation time 21947461091 ps
CPU time 818.62 seconds
Started Nov 22 01:23:06 PM PST 23
Finished Nov 22 01:36:55 PM PST 23
Peak memory 371236 kb
Host smart-6c7523d3-3f23-46b0-9023-4890da58836b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110186172614317348691791567352971214549053800636405696018352760092577543021574 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.110186172614317348691791567352971214549053800636405696018352760092577543021574
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.69282408045891926051312506809352436126524904962193721689384787942986381012106
Short name T284
Test name
Test status
Simulation time 445204539 ps
CPU time 12.77 seconds
Started Nov 22 01:23:03 PM PST 23
Finished Nov 22 01:23:27 PM PST 23
Peak memory 246564 kb
Host smart-9b1b76f7-7b43-402f-a3de-debd24d65a73
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692824080458919260513125068093524361265249049621937216893847879429863
81012106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.692824080458919260513125068093524361265249049621937216
89384787942986381012106
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.73049029695375023563995048556801988987155334009850134113190233849896169245594
Short name T356
Test name
Test status
Simulation time 42305619653 ps
CPU time 537.75 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 01:32:16 PM PST 23
Peak memory 202692 kb
Host smart-d3acee5c-1f74-47b8-ba16-a550ff6775ef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730490296953750235639950485568019889871553340098501341131902338498961
69245594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access_b2b.7304902969537502356399504855680198898715
5334009850134113190233849896169245594
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.913086285923634960151101481117415916892291691642064295715320372530225746290
Short name T440
Test name
Test status
Simulation time 40672061 ps
CPU time 0.86 seconds
Started Nov 22 01:22:52 PM PST 23
Finished Nov 22 01:23:07 PM PST 23
Peak memory 202568 kb
Host smart-236664b7-8257-4fbd-b400-d7e2d8579f82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913086285923634960151101481117415916892291691642064295715320372530225746290 -assert nopostpr
oc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.913086285923634960151101481117415916892291691642064295715320372530225746290
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.94716447176236614191513850390416009169613407968547292427375379591151456481414
Short name T938
Test name
Test status
Simulation time 19383553031 ps
CPU time 536.2 seconds
Started Nov 22 01:23:04 PM PST 23
Finished Nov 22 01:32:12 PM PST 23
Peak memory 371652 kb
Host smart-8f65247b-f585-4126-9f8f-efa5a572f1be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94716447176236614191513850390416009169613407968547292427375379591151456481414 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.94716447176236614191513850390416009169613407968547292427375379591151456481414
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.40316089123269444379182959529725229271576133879042724160023792528882998335003
Short name T112
Test name
Test status
Simulation time 427865392 ps
CPU time 13.28 seconds
Started Nov 22 01:22:50 PM PST 23
Finished Nov 22 01:23:17 PM PST 23
Peak memory 246564 kb
Host smart-1e6e73cc-a0af-4ee1-8ca3-e3b98f802809
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40316089123269444379182959529725229271576133879042724160023792528882998335003 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.40316089123269444379182959529725229271576133879042724160023792528882998335003
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.107385773535770377292320875776881761250274955956800216519921936701003345078482
Short name T932
Test name
Test status
Simulation time 121463254244 ps
CPU time 3548.33 seconds
Started Nov 22 01:22:54 PM PST 23
Finished Nov 22 02:22:15 PM PST 23
Peak memory 375580 kb
Host smart-e1ee4ed5-f0b0-4041-b7b5-5f551bad6c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107385773535770377292320875776881761250274955956800216519921936
701003345078482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.1073857735357703772923208757768817612502749559
56800216519921936701003345078482
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.102295413340208317695389682110370931114663274081649914872094214557915803699471
Short name T928
Test name
Test status
Simulation time 624328106 ps
CPU time 1124.1 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:41:51 PM PST 23
Peak memory 401688 kb
Host smart-354689ba-1948-49d1-b0d8-161866c396d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=102295413340208317695389682110370931114663274081649914872094214557915803699471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.s
ram_ctrl_stress_all_with_rand_reset.102295413340208317695389682110370931114663274081649914872094214557915803699471
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.25439057603629563368995847711463854141552890603715509737864022803275118617949
Short name T267
Test name
Test status
Simulation time 6491370455 ps
CPU time 349.04 seconds
Started Nov 22 01:22:48 PM PST 23
Finished Nov 22 01:28:51 PM PST 23
Peak memory 202648 kb
Host smart-3e43b6de-eaca-444b-8d46-4a2e92cf3a15
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25439057603629563368995847711463854141552890603715509737864022803275118617949
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.254390576036295633689958477114638541415528906037155
09737864022803275118617949
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.51931712574251695239354443975205412772506780642130248261983516765130357251462
Short name T502
Test name
Test status
Simulation time 237420487 ps
CPU time 81.14 seconds
Started Nov 22 01:22:51 PM PST 23
Finished Nov 22 01:24:27 PM PST 23
Peak memory 351380 kb
Host smart-84a0f81a-4582-44c6-98b7-aff979f0ab17
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519317125742516952393544439752054127725067806421302482
61983516765130357251462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.5193171257425169523935
4443975205412772506780642130248261983516765130357251462
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.101165950704738646122004329435129578647005313818326142199825151807833336400878
Short name T19
Test name
Test status
Simulation time 4471404472 ps
CPU time 773.17 seconds
Started Nov 22 01:23:26 PM PST 23
Finished Nov 22 01:36:33 PM PST 23
Peak memory 375508 kb
Host smart-13aefe33-565a-4260-9b8c-6a8f7fab096b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10116595070473864612200432943512957864700531381832614219982515180783333640087
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during_key_req.10116595070473864612200432943512957864
7005313818326142199825151807833336400878
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.23938052518927580169512173708219581107005061284742570606278691172629005306608
Short name T446
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:23:25 PM PST 23
Finished Nov 22 01:23:40 PM PST 23
Peak memory 202072 kb
Host smart-1ddd3dcb-1819-48e1-b15e-e60854c84df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239380525189275801695121737082195811070050612847425706062786911726
29005306608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.239380525189275801695121737082195811070050612847425706
06278691172629005306608
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.1090208392977946909696896308229569128600922510397535934146888034434036767156
Short name T431
Test name
Test status
Simulation time 9249473390 ps
CPU time 81.84 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 01:24:39 PM PST 23
Peak memory 202592 kb
Host smart-ed5c5b24-e9d4-4396-b344-d03b996e5f26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090208392977946909696896308229569128600922510397535934146888034434036767156 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.1090208392977946909696896308229569128600922510397535934146888034434036767156
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.71346850307068123506744831783542241949020384035950567643159384923622454530006
Short name T728
Test name
Test status
Simulation time 23162112088 ps
CPU time 847.04 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 01:37:24 PM PST 23
Peak memory 364660 kb
Host smart-e02e50a3-0f64-4a29-a83d-4134e61fc825
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71346850307068123506744831783542241949020384035950567643159384923622454530006 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.71346850307068123506744831783542241949020384035950567643159384923622454530006
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.38132587049414851503959922899883424044927285749452805824111241164697558639028
Short name T733
Test name
Test status
Simulation time 985753786 ps
CPU time 7.1 seconds
Started Nov 22 01:23:20 PM PST 23
Finished Nov 22 01:23:37 PM PST 23
Peak memory 213208 kb
Host smart-1079d07d-3d50-4ec4-b70f-0add089c84b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38132587049414851503959922899883424044927285749452805824111241164697558639028 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.38132587049414851503959922899883424044927285749452805824111241164697558639028
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.45306274900978819643444007358824795830673339947409499216896699128404271149636
Short name T594
Test name
Test status
Simulation time 209242141 ps
CPU time 75.02 seconds
Started Nov 22 01:23:21 PM PST 23
Finished Nov 22 01:24:46 PM PST 23
Peak memory 351368 kb
Host smart-e493cfb0-3b50-48bb-be86-0dff461239d1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4530627490097881964344400735882479583067333994740949921
6896699128404271149636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_max_throughput.45306274900978819643444007358824795
830673339947409499216896699128404271149636
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.107572347637515943411782246231213108271236011683851837702617680829372039501926
Short name T943
Test name
Test status
Simulation time 166171057 ps
CPU time 3.15 seconds
Started Nov 22 01:23:15 PM PST 23
Finished Nov 22 01:23:26 PM PST 23
Peak memory 215680 kb
Host smart-fa561a06-74df-43a6-bc5e-d00b1ae23ca9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10757234763751594341178224623121310827123601168385183770261768082937
2039501926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.10757234763751594341178224623121310827123601168
3851837702617680829372039501926
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.15466968699400393918382044724536848751447465074209323885392213653893473661211
Short name T803
Test name
Test status
Simulation time 590810517 ps
CPU time 5.4 seconds
Started Nov 22 01:23:14 PM PST 23
Finished Nov 22 01:23:28 PM PST 23
Peak memory 202580 kb
Host smart-5ec1577c-6561-4cac-95b9-a7bb2881f8f2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15466968699400393918382044724536848751447465074209323885392213653893473661211
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.15466968699400393918382044724536848751447465074209323885392213653893473661211
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.109623482235096780387982592226975238973310380427756417861262576330370089599922
Short name T581
Test name
Test status
Simulation time 21947461091 ps
CPU time 691.44 seconds
Started Nov 22 01:22:55 PM PST 23
Finished Nov 22 01:34:39 PM PST 23
Peak memory 371288 kb
Host smart-840a3d8d-0648-4159-9177-a4bb750bb684
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109623482235096780387982592226975238973310380427756417861262576330370089599922 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.109623482235096780387982592226975238973310380427756417861262576330370089599922
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.78753890359400512831375276132111109743273484083882683395561477072460105978185
Short name T392
Test name
Test status
Simulation time 445204539 ps
CPU time 12.93 seconds
Started Nov 22 01:23:08 PM PST 23
Finished Nov 22 01:23:31 PM PST 23
Peak memory 246584 kb
Host smart-e293a1ab-9bc9-436e-a348-40abaabb7464
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787538903594005128313752761321111097432734840838826833955614770724601
05978185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.787538903594005128313752761321111097432734840838826833
95561477072460105978185
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.94147231712384236265359515299575840016581679439922063957464875660514498764290
Short name T367
Test name
Test status
Simulation time 42305619653 ps
CPU time 555.14 seconds
Started Nov 22 01:23:15 PM PST 23
Finished Nov 22 01:32:38 PM PST 23
Peak memory 202668 kb
Host smart-27cffb5e-6457-4d14-a896-e5b4072a325c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941472317123842362653595152995758400165816794399220639574648756605144
98764290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access_b2b.9414723171238423626535951529957584001658
1679439922063957464875660514498764290
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.25256576601464386246313482409916112643519937324244966138137831836677341077933
Short name T349
Test name
Test status
Simulation time 40672061 ps
CPU time 0.85 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 01:23:18 PM PST 23
Peak memory 202608 kb
Host smart-2861694b-80ac-4744-8be9-b4f5a9eabc7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25256576601464386246313482409916112643519937324244966138137831836677341077933 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.25256576601464386246313482409916112643519937324244966138137831836677341077933
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.27167379681294147391166554061382511753193282599040634754652731750616617232826
Short name T971
Test name
Test status
Simulation time 19383553031 ps
CPU time 498.55 seconds
Started Nov 22 01:23:19 PM PST 23
Finished Nov 22 01:31:48 PM PST 23
Peak memory 371836 kb
Host smart-3564f790-31c6-4901-aba4-7c35f4c67ccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167379681294147391166554061382511753193282599040634754652731750616617232826 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.27167379681294147391166554061382511753193282599040634754652731750616617232826
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.59838258602334242620094300027690951432127617583537225842041137878700011373814
Short name T944
Test name
Test status
Simulation time 427865392 ps
CPU time 11.7 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 01:23:29 PM PST 23
Peak memory 246580 kb
Host smart-b600ba04-cc1a-4c79-aedd-83e3a3344756
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59838258602334242620094300027690951432127617583537225842041137878700011373814 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.59838258602334242620094300027690951432127617583537225842041137878700011373814
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.53982174468210043499842449375259347478251207990907048339660018727182702401832
Short name T821
Test name
Test status
Simulation time 121463254244 ps
CPU time 3680.04 seconds
Started Nov 22 01:23:07 PM PST 23
Finished Nov 22 02:24:37 PM PST 23
Peak memory 375500 kb
Host smart-7710942e-fecb-4768-bcab-066f4011b9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539821744682100434998424493752593474782512079909070483396600187
27182702401832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.53982174468210043499842449375259347478251207990
907048339660018727182702401832
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.62529496169039047602412184840970113905405509616430741556472159832323002779057
Short name T837
Test name
Test status
Simulation time 624328106 ps
CPU time 1483.98 seconds
Started Nov 22 01:23:19 PM PST 23
Finished Nov 22 01:48:12 PM PST 23
Peak memory 401816 kb
Host smart-a0bb1755-c96b-46d4-9904-90ca1177be19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=62529496169039047602412184840970113905405509616430741556472159832323002779057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sr
am_ctrl_stress_all_with_rand_reset.62529496169039047602412184840970113905405509616430741556472159832323002779057
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.29152477829772505991294130788208562970977029576546437204398729395220040101348
Short name T566
Test name
Test status
Simulation time 6491370455 ps
CPU time 349.02 seconds
Started Nov 22 01:23:12 PM PST 23
Finished Nov 22 01:29:09 PM PST 23
Peak memory 202548 kb
Host smart-24adb5c7-6820-4f38-ae9c-482269095e0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29152477829772505991294130788208562970977029576546437204398729395220040101348
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.291524778297725059912941307882085629709770295765464
37204398729395220040101348
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.22127350784523170401503459663684744899824533640004891232743172146659845462197
Short name T848
Test name
Test status
Simulation time 237420487 ps
CPU time 96.32 seconds
Started Nov 22 01:23:11 PM PST 23
Finished Nov 22 01:24:56 PM PST 23
Peak memory 351352 kb
Host smart-fadee0b2-e60f-40fe-bbe0-a17737051dd4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221273507845231704015034596636847448998245336400048912
32743172146659845462197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2212735078452317040150
3459663684744899824533640004891232743172146659845462197
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.95326334521783911524410763546279955975830938324947969500127763698318267813538
Short name T572
Test name
Test status
Simulation time 4471404472 ps
CPU time 643.56 seconds
Started Nov 22 01:23:17 PM PST 23
Finished Nov 22 01:34:07 PM PST 23
Peak memory 374892 kb
Host smart-b670773f-4b68-4a71-954e-9360ca7dfdeb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95326334521783911524410763546279955975830938324947969500127763698318267813538
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during_key_req.953263345217839115244107635462799559758
30938324947969500127763698318267813538
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.8217109120961752422090226494787066721400113401703992613746052862258763501709
Short name T142
Test name
Test status
Simulation time 16600825 ps
CPU time 0.63 seconds
Started Nov 22 01:23:13 PM PST 23
Finished Nov 22 01:23:21 PM PST 23
Peak memory 202152 kb
Host smart-0ade1633-ce88-484f-b22d-268e7f79441a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821710912096175242209022649478706672140011340170399261374605286225
8763501709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.8217109120961752422090226494787066721400113401703992613
746052862258763501709
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.2632398480155144828562993746223547930114411329572824190950273239631741257251
Short name T533
Test name
Test status
Simulation time 9249473390 ps
CPU time 85.39 seconds
Started Nov 22 01:23:32 PM PST 23
Finished Nov 22 01:25:11 PM PST 23
Peak memory 202652 kb
Host smart-af880f7b-aba5-4d41-b4a5-d1e6ff013177
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632398480155144828562993746223547930114411329572824190950273239631741257251 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.2632398480155144828562993746223547930114411329572824190950273239631741257251
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.76776406032571805886817522028635662052253706475836054284690518407665176583823
Short name T104
Test name
Test status
Simulation time 23162112088 ps
CPU time 817.99 seconds
Started Nov 22 01:23:23 PM PST 23
Finished Nov 22 01:37:13 PM PST 23
Peak memory 364548 kb
Host smart-5a6134d1-3612-4175-af50-3631d06ccdaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76776406032571805886817522028635662052253706475836054284690518407665176583823 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.76776406032571805886817522028635662052253706475836054284690518407665176583823
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.75521111201849058457481635307955484175459486505805043193869301032634614728820
Short name T578
Test name
Test status
Simulation time 985753786 ps
CPU time 7.16 seconds
Started Nov 22 01:23:25 PM PST 23
Finished Nov 22 01:23:47 PM PST 23
Peak memory 213080 kb
Host smart-5e447f37-fdd0-446d-ba89-6383a1cf48ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75521111201849058457481635307955484175459486505805043193869301032634614728820 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.75521111201849058457481635307955484175459486505805043193869301032634614728820
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.81039114653423355767104946535458790486933750599040150146492876267642836805302
Short name T113
Test name
Test status
Simulation time 209242141 ps
CPU time 85.76 seconds
Started Nov 22 01:23:08 PM PST 23
Finished Nov 22 01:24:44 PM PST 23
Peak memory 351240 kb
Host smart-f967ee65-ca38-4539-97f6-bfce67bf1464
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8103911465342335576710494653545879048693375059904015014
6492876267642836805302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_max_throughput.81039114653423355767104946535458790
486933750599040150146492876267642836805302
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.105012604164137836276244617207961390474646493715865406221106319307229602060670
Short name T394
Test name
Test status
Simulation time 166171057 ps
CPU time 3.1 seconds
Started Nov 22 01:23:16 PM PST 23
Finished Nov 22 01:23:26 PM PST 23
Peak memory 215700 kb
Host smart-20debc34-fabf-484b-8bc6-69e97af1c812
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10501260416413783627624461720796139047464649371586540622110631930722
9602060670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.10501260416413783627624461720796139047464649371
5865406221106319307229602060670
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.78862082606665351667700123732735525477218136396127346822843702713969158077996
Short name T845
Test name
Test status
Simulation time 590810517 ps
CPU time 5.61 seconds
Started Nov 22 01:23:20 PM PST 23
Finished Nov 22 01:23:35 PM PST 23
Peak memory 202620 kb
Host smart-0df3c271-7fa0-4780-a348-d6a985a3bb74
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78862082606665351667700123732735525477218136396127346822843702713969158077996
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.78862082606665351667700123732735525477218136396127346822843702713969158077996
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.52966172161472522433008774741379602351381193424851770815134745558219334682962
Short name T635
Test name
Test status
Simulation time 21947461091 ps
CPU time 702.43 seconds
Started Nov 22 01:23:22 PM PST 23
Finished Nov 22 01:35:14 PM PST 23
Peak memory 371288 kb
Host smart-951b77c7-dc1f-4fcb-bf0a-54bb153178ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52966172161472522433008774741379602351381193424851770815134745558219334682962 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.52966172161472522433008774741379602351381193424851770815134745558219334682962
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.54990659415969552377103188099123465048981875627959568559900450878663783149432
Short name T768
Test name
Test status
Simulation time 445204539 ps
CPU time 13.83 seconds
Started Nov 22 01:23:09 PM PST 23
Finished Nov 22 01:23:33 PM PST 23
Peak memory 246300 kb
Host smart-35f85c48-6935-49df-8ef1-2c79b9d91cec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549906594159695523771031880991234650489818756279595685599004508786637
83149432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.549906594159695523771031880991234650489818756279595685
59900450878663783149432
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.75356635607789925528272639443409321222308599459312245010617703613448474626957
Short name T685
Test name
Test status
Simulation time 42305619653 ps
CPU time 531.95 seconds
Started Nov 22 01:23:19 PM PST 23
Finished Nov 22 01:32:22 PM PST 23
Peak memory 202572 kb
Host smart-6671348a-4e8c-4dc4-be81-53af1a44eff0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753566356077899255282726394434093212223085994593122450106177036134484
74626957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access_b2b.7535663560778992552827263944340932122230
8599459312245010617703613448474626957
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.30586037327003083421169203127303714462087808201587482696809118899238940759632
Short name T447
Test name
Test status
Simulation time 40672061 ps
CPU time 0.83 seconds
Started Nov 22 01:23:13 PM PST 23
Finished Nov 22 01:23:22 PM PST 23
Peak memory 202432 kb
Host smart-fd59980f-3ada-4c89-afd9-b641e66d72e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30586037327003083421169203127303714462087808201587482696809118899238940759632 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.30586037327003083421169203127303714462087808201587482696809118899238940759632
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.18193712575832323426956200144465581294571174614611342797703030918370653996204
Short name T474
Test name
Test status
Simulation time 19383553031 ps
CPU time 510.82 seconds
Started Nov 22 01:23:12 PM PST 23
Finished Nov 22 01:31:51 PM PST 23
Peak memory 371812 kb
Host smart-ed3b37ee-f9da-4e81-b09a-17276bd1f373
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18193712575832323426956200144465581294571174614611342797703030918370653996204 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.18193712575832323426956200144465581294571174614611342797703030918370653996204
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.40945781337219776358067734483493949936861199943262286914765131363193550257285
Short name T818
Test name
Test status
Simulation time 427865392 ps
CPU time 13.14 seconds
Started Nov 22 01:23:20 PM PST 23
Finished Nov 22 01:23:43 PM PST 23
Peak memory 246476 kb
Host smart-fd43111e-139a-4266-aa29-5886715912f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40945781337219776358067734483493949936861199943262286914765131363193550257285 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.40945781337219776358067734483493949936861199943262286914765131363193550257285
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.76778083912144972194590106364474929162787023948829956545723159901914600890374
Short name T111
Test name
Test status
Simulation time 121463254244 ps
CPU time 3263.61 seconds
Started Nov 22 01:23:10 PM PST 23
Finished Nov 22 02:17:43 PM PST 23
Peak memory 375264 kb
Host smart-6a894b8e-28e9-4c6c-a50c-22c6f46412d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767780839121449721945901063644749291627870239488299565457231599
01914600890374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.76778083912144972194590106364474929162787023948
829956545723159901914600890374
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2836494881224575326061939078369757983485089121454306863804000470688022739663
Short name T696
Test name
Test status
Simulation time 624328106 ps
CPU time 1174.38 seconds
Started Nov 22 01:23:09 PM PST 23
Finished Nov 22 01:42:53 PM PST 23
Peak memory 401712 kb
Host smart-4ce1d3b0-152f-46ff-aa2b-0c68cec8c15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2836494881224575326061939078369757983485089121454306863804000470688022739663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sra
m_ctrl_stress_all_with_rand_reset.2836494881224575326061939078369757983485089121454306863804000470688022739663
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.96036441755424018058437999470012837616005994324685580336147077178635003502039
Short name T149
Test name
Test status
Simulation time 6491370455 ps
CPU time 346.07 seconds
Started Nov 22 01:23:17 PM PST 23
Finished Nov 22 01:29:10 PM PST 23
Peak memory 201960 kb
Host smart-ceb2c6b4-f246-45e9-bf3a-0d69cc780f34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96036441755424018058437999470012837616005994324685580336147077178635003502039
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.960364417554240180584379994700128376160059943246855
80336147077178635003502039
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.111428404433508888562996370429156779091721669206766217863666941816475878194216
Short name T116
Test name
Test status
Simulation time 237420487 ps
CPU time 78.38 seconds
Started Nov 22 01:23:09 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 351316 kb
Host smart-93a44a00-201e-493b-97f9-e88a5d63e1a0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111428404433508888562996370429156779091721669206766217
863666941816475878194216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.111428404433508888562
996370429156779091721669206766217863666941816475878194216
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.77716753504190530251955522459643201463957837120179292982024503284859226136048
Short name T462
Test name
Test status
Simulation time 4471404472 ps
CPU time 724.57 seconds
Started Nov 22 01:23:31 PM PST 23
Finished Nov 22 01:35:49 PM PST 23
Peak memory 375412 kb
Host smart-5f20986d-2b02-4143-aab6-91c09ee78b26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77716753504190530251955522459643201463957837120179292982024503284859226136048
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during_key_req.777167535041905302519555224596432014639
57837120179292982024503284859226136048
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.58008089484804372551767363575703857777979844261619289273371231817522351303928
Short name T968
Test name
Test status
Simulation time 16600825 ps
CPU time 0.59 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:23:57 PM PST 23
Peak memory 202140 kb
Host smart-c950d046-76d3-4f3e-984a-f2f0c7f88ff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580080894848043725517673635757038577779798442616192892733712318175
22351303928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.580080894848043725517673635757038577779798442616192892
73371231817522351303928
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.11416982635271120880422573221616108118681705008628778841353200726961663309557
Short name T556
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.67 seconds
Started Nov 22 01:23:12 PM PST 23
Finished Nov 22 01:24:44 PM PST 23
Peak memory 202544 kb
Host smart-1d7ec4d4-8468-417a-9381-86658e2157fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11416982635271120880422573221616108118681705008628778841353200726961663309557 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.11416982635271120880422573221616108118681705008628778841353200726961663309557
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.111334045010501767719041130869676021105475903635299206760690450077978492888496
Short name T482
Test name
Test status
Simulation time 23162112088 ps
CPU time 621.71 seconds
Started Nov 22 01:23:26 PM PST 23
Finished Nov 22 01:34:02 PM PST 23
Peak memory 364600 kb
Host smart-accb0797-b884-40ec-9ded-69fad52fc5f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111334045010501767719041130869676021105475903635299206760690450077978492888496 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.111334045010501767719041130869676021105475903635299206760690450077978492888496
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.87723059032362622690864485815245527864369711916366693167585586152947547251063
Short name T811
Test name
Test status
Simulation time 985753786 ps
CPU time 7.03 seconds
Started Nov 22 01:23:21 PM PST 23
Finished Nov 22 01:23:38 PM PST 23
Peak memory 213100 kb
Host smart-ebd11b88-0fed-4a42-b44d-e1ce7670e89a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87723059032362622690864485815245527864369711916366693167585586152947547251063 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.87723059032362622690864485815245527864369711916366693167585586152947547251063
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.11885217821509622867775364234116838898053191869050459548854479035327287785448
Short name T151
Test name
Test status
Simulation time 209242141 ps
CPU time 77.04 seconds
Started Nov 22 01:23:08 PM PST 23
Finished Nov 22 01:24:36 PM PST 23
Peak memory 351304 kb
Host smart-7081e714-8449-4618-9799-5944a5a38e57
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188521782150962286777536423411683889805319186905045954
8854479035327287785448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_max_throughput.11885217821509622867775364234116838
898053191869050459548854479035327287785448
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.86137224317685889341543759281640945851930666147399327462884092107108096705522
Short name T487
Test name
Test status
Simulation time 166171057 ps
CPU time 2.97 seconds
Started Nov 22 01:24:17 PM PST 23
Finished Nov 22 01:24:25 PM PST 23
Peak memory 215456 kb
Host smart-b3953962-6499-4d8b-bfb4-0a98a4f4da21
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86137224317685889341543759281640945851930666147399327462884092107108
096705522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.861372243176858893415437592816409458519306661473
99327462884092107108096705522
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.68162853298079924156600709418611932360019490038600505245581122202397802548267
Short name T591
Test name
Test status
Simulation time 590810517 ps
CPU time 5.26 seconds
Started Nov 22 01:23:37 PM PST 23
Finished Nov 22 01:23:53 PM PST 23
Peak memory 202448 kb
Host smart-c94fd40f-360a-41d1-8ef3-84aa0df031bc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68162853298079924156600709418611932360019490038600505245581122202397802548267
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.68162853298079924156600709418611932360019490038600505245581122202397802548267
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.54052587566274673149689905166056697990192628763678706047295110940316686494825
Short name T464
Test name
Test status
Simulation time 21947461091 ps
CPU time 1006.18 seconds
Started Nov 22 01:23:09 PM PST 23
Finished Nov 22 01:40:05 PM PST 23
Peak memory 371292 kb
Host smart-f4270907-822c-4a3e-ad56-d404324fb735
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54052587566274673149689905166056697990192628763678706047295110940316686494825 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.54052587566274673149689905166056697990192628763678706047295110940316686494825
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.43490117416743611217671783624286955494116355539083370740059988107542187071085
Short name T742
Test name
Test status
Simulation time 445204539 ps
CPU time 11.45 seconds
Started Nov 22 01:23:10 PM PST 23
Finished Nov 22 01:23:31 PM PST 23
Peak memory 246564 kb
Host smart-33a0e277-c9a9-4fc9-8d23-97ee6b93ce83
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434901174167436112176717836242869554941163555390833707400599881075421
87071085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.434901174167436112176717836242869554941163555390833707
40059988107542187071085
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4790500735461986216542401349145942817350452403592362659996598568229379723425
Short name T1024
Test name
Test status
Simulation time 42305619653 ps
CPU time 552.4 seconds
Started Nov 22 01:23:20 PM PST 23
Finished Nov 22 01:32:42 PM PST 23
Peak memory 202720 kb
Host smart-5c91e8da-777d-44b4-ac29-e25ff274222a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479050073546198621654240134914594281735045240359236265999659856822937
9723425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access_b2b.47905007354619862165424013491459428173504
52403592362659996598568229379723425
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.87374463295413225363714213450303943776497492295928437886865723434780411419507
Short name T661
Test name
Test status
Simulation time 40672061 ps
CPU time 0.91 seconds
Started Nov 22 01:24:12 PM PST 23
Finished Nov 22 01:24:16 PM PST 23
Peak memory 201116 kb
Host smart-4c656c3b-91b0-4f52-9c44-16382ee2af85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87374463295413225363714213450303943776497492295928437886865723434780411419507 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.87374463295413225363714213450303943776497492295928437886865723434780411419507
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.4694090995133778560943152455615370588741997027654421467119105883561003970662
Short name T856
Test name
Test status
Simulation time 19383553031 ps
CPU time 540.57 seconds
Started Nov 22 01:23:33 PM PST 23
Finished Nov 22 01:32:47 PM PST 23
Peak memory 371792 kb
Host smart-a80d522e-11d6-4f15-bbdd-5d5e63a61fb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4694090995133778560943152455615370588741997027654421467119105883561003970662 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.4694090995133778560943152455615370588741997027654421467119105883561003970662
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.34480593930362863207245593588102634665801145922785369165805341221594403254677
Short name T428
Test name
Test status
Simulation time 427865392 ps
CPU time 11.96 seconds
Started Nov 22 01:23:16 PM PST 23
Finished Nov 22 01:23:35 PM PST 23
Peak memory 246544 kb
Host smart-d0ce0d4f-ec29-488a-a0fb-8c3df37c5089
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34480593930362863207245593588102634665801145922785369165805341221594403254677 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.34480593930362863207245593588102634665801145922785369165805341221594403254677
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.41996390314102246718287842624170028316489785098543021381249895710978836055540
Short name T480
Test name
Test status
Simulation time 121463254244 ps
CPU time 2953.84 seconds
Started Nov 22 01:24:13 PM PST 23
Finished Nov 22 02:13:31 PM PST 23
Peak memory 375092 kb
Host smart-03fc3652-0953-4070-a392-a23c194add58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419963903141022467182878426241700283164897850985430213812498957
10978836055540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.41996390314102246718287842624170028316489785098
543021381249895710978836055540
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.61742706462012730919991591309961820843198669064029246904089595143826303729897
Short name T941
Test name
Test status
Simulation time 624328106 ps
CPU time 961.01 seconds
Started Nov 22 01:23:36 PM PST 23
Finished Nov 22 01:39:49 PM PST 23
Peak memory 401640 kb
Host smart-0670e51f-cd5a-4538-bd09-ed290087f97b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=61742706462012730919991591309961820843198669064029246904089595143826303729897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sr
am_ctrl_stress_all_with_rand_reset.61742706462012730919991591309961820843198669064029246904089595143826303729897
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.30201867043403265150899502682253146037958117524374870490165214691148645637309
Short name T128
Test name
Test status
Simulation time 6491370455 ps
CPU time 341.05 seconds
Started Nov 22 01:23:13 PM PST 23
Finished Nov 22 01:29:03 PM PST 23
Peak memory 202656 kb
Host smart-75258de6-2efd-4df0-bd03-6b3ec0cde68b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30201867043403265150899502682253146037958117524374870490165214691148645637309
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.302018670434032651508995026822531460379581175243748
70490165214691148645637309
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.113498988349223741167586978370699879625492948966451511252461385811285698010661
Short name T908
Test name
Test status
Simulation time 237420487 ps
CPU time 102.66 seconds
Started Nov 22 01:23:23 PM PST 23
Finished Nov 22 01:25:19 PM PST 23
Peak memory 351312 kb
Host smart-cf49b9e1-e3d3-4cc0-9997-60c3eedd82e6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113498988349223741167586978370699879625492948966451511
252461385811285698010661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.113498988349223741167
586978370699879625492948966451511252461385811285698010661
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4132949025176941701272314596387321491392695583618590469949765278528663671671
Short name T20
Test name
Test status
Simulation time 4471404472 ps
CPU time 648.57 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:34:47 PM PST 23
Peak memory 375340 kb
Host smart-ba17d893-6227-458f-a3df-2af0b9878e6d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132949025176941701272314596387321491392695583618590469949765278528663671671
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during_key_req.4132949025176941701272314596387321491392
695583618590469949765278528663671671
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.42626429233156256697496002140706359152899340810110625785483152166624316007714
Short name T747
Test name
Test status
Simulation time 16600825 ps
CPU time 0.63 seconds
Started Nov 22 01:23:50 PM PST 23
Finished Nov 22 01:24:00 PM PST 23
Peak memory 202092 kb
Host smart-012f61ec-29d3-4da8-a80c-bb675832a517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426264292331562566974960021407063591528993408101106257854831521666
24316007714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.426264292331562566974960021407063591528993408101106257
85483152166624316007714
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.2369716376398768214210684996491888436423404626704583315000367965051552164072
Short name T1010
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.66 seconds
Started Nov 22 01:23:38 PM PST 23
Finished Nov 22 01:25:13 PM PST 23
Peak memory 202620 kb
Host smart-e3b569ba-d705-4587-9082-73b005a24745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369716376398768214210684996491888436423404626704583315000367965051552164072 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.2369716376398768214210684996491888436423404626704583315000367965051552164072
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.1087166034442462440366884095814138148271088447918626609406917800846491407259
Short name T473
Test name
Test status
Simulation time 23162112088 ps
CPU time 770.92 seconds
Started Nov 22 01:25:00 PM PST 23
Finished Nov 22 01:37:54 PM PST 23
Peak memory 364600 kb
Host smart-02f2ada2-9d3f-4e7c-863e-96b9cf683606
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087166034442462440366884095814138148271088447918626609406917800846491407259 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.1087166034442462440366884095814138148271088447918626609406917800846491407259
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.34312680600155379369641489846087004626044932752879609184890103845046892952673
Short name T759
Test name
Test status
Simulation time 985753786 ps
CPU time 7.27 seconds
Started Nov 22 01:23:43 PM PST 23
Finished Nov 22 01:23:59 PM PST 23
Peak memory 213216 kb
Host smart-03682b46-7d07-4c4f-b938-ee828d1fe72b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34312680600155379369641489846087004626044932752879609184890103845046892952673 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.34312680600155379369641489846087004626044932752879609184890103845046892952673
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.16743591641112034560081614228441242277471367728081633477408996240380023382182
Short name T909
Test name
Test status
Simulation time 209242141 ps
CPU time 90.78 seconds
Started Nov 22 01:24:17 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 351296 kb
Host smart-913df54f-ff4e-4e18-b5a4-fd1816ed6bef
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674359164111203456008161422844124227747136772808163347
7408996240380023382182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_max_throughput.16743591641112034560081614228441242
277471367728081633477408996240380023382182
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.6137601794967240670567620432428017158290624788464938432436789643616453347761
Short name T76
Test name
Test status
Simulation time 166171057 ps
CPU time 3.01 seconds
Started Nov 22 01:24:12 PM PST 23
Finished Nov 22 01:24:18 PM PST 23
Peak memory 215724 kb
Host smart-3d5837e1-745c-4dd8-8e4a-78fc94986e3e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61376017949672406705676204324280171582906247884649384324367896436164
53347761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.6137601794967240670567620432428017158290624788464
938432436789643616453347761
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.45005153626153941424047053737650743269034931988524042840120196740211940359447
Short name T731
Test name
Test status
Simulation time 590810517 ps
CPU time 5.64 seconds
Started Nov 22 01:23:49 PM PST 23
Finished Nov 22 01:24:04 PM PST 23
Peak memory 202616 kb
Host smart-6a39d1f4-274c-4588-9adf-274e6d366e84
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45005153626153941424047053737650743269034931988524042840120196740211940359447
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.45005153626153941424047053737650743269034931988524042840120196740211940359447
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.77626078977660223678496601044457636996117755985122234108263998330200677463489
Short name T542
Test name
Test status
Simulation time 21947461091 ps
CPU time 742.5 seconds
Started Nov 22 01:24:08 PM PST 23
Finished Nov 22 01:36:35 PM PST 23
Peak memory 371352 kb
Host smart-e6262d42-eb12-4b8a-94be-ea734ba89d09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77626078977660223678496601044457636996117755985122234108263998330200677463489 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.77626078977660223678496601044457636996117755985122234108263998330200677463489
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.58497730615046546142739730002011053548229101203509707749451909860884494950743
Short name T866
Test name
Test status
Simulation time 445204539 ps
CPU time 11.36 seconds
Started Nov 22 01:23:39 PM PST 23
Finished Nov 22 01:24:00 PM PST 23
Peak memory 246568 kb
Host smart-0d1081ee-551e-4fd1-8fe0-b87cd8b93f91
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584977306150465461427397300020110535482291012035097077494519098608844
94950743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.584977306150465461427397300020110535482291012035097077
49451909860884494950743
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.79536640142247543520656504135521775239735774699227436349305514962298149389515
Short name T303
Test name
Test status
Simulation time 42305619653 ps
CPU time 537.39 seconds
Started Nov 22 01:23:41 PM PST 23
Finished Nov 22 01:32:49 PM PST 23
Peak memory 202708 kb
Host smart-67ff5220-bbd9-42da-a7bf-1076f4d6c90f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795366401422475435206565041355217752397357746992274363493055149622981
49389515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access_b2b.7953664014224754352065650413552177523973
5774699227436349305514962298149389515
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.31559866005197482465697464711316346969136683212404548459166233189913180923536
Short name T969
Test name
Test status
Simulation time 40672061 ps
CPU time 0.85 seconds
Started Nov 22 01:23:48 PM PST 23
Finished Nov 22 01:23:59 PM PST 23
Peak memory 202672 kb
Host smart-6033b0c8-b0a6-41cc-96cd-f9d7838a5f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31559866005197482465697464711316346969136683212404548459166233189913180923536 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.31559866005197482465697464711316346969136683212404548459166233189913180923536
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.111848954832815694923272918629698020097036665528327820742607755983216377758498
Short name T875
Test name
Test status
Simulation time 19383553031 ps
CPU time 590.47 seconds
Started Nov 22 01:23:40 PM PST 23
Finished Nov 22 01:33:40 PM PST 23
Peak memory 371836 kb
Host smart-225c0f9a-66e4-499c-849a-c8c2cb02b892
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111848954832815694923272918629698020097036665528327820742607755983216377758498 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.111848954832815694923272918629698020097036665528327820742607755983216377758498
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.27184499686666827339871346368404721438814812934136403491898379328701248338520
Short name T707
Test name
Test status
Simulation time 427865392 ps
CPU time 12.03 seconds
Started Nov 22 01:23:25 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 246488 kb
Host smart-eb1505ad-0c33-4e53-b5d3-554dc6c50ea9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27184499686666827339871346368404721438814812934136403491898379328701248338520 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.27184499686666827339871346368404721438814812934136403491898379328701248338520
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.57017357417035488860139742143971435151355473521173580398036437298958018045847
Short name T765
Test name
Test status
Simulation time 121463254244 ps
CPU time 3511.04 seconds
Started Nov 22 01:24:10 PM PST 23
Finished Nov 22 02:22:45 PM PST 23
Peak memory 375416 kb
Host smart-7297cd41-542f-4768-bc18-61701e23ec55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570173574170354888601397421439714351513554735211735803980364372
98958018045847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.57017357417035488860139742143971435151355473521
173580398036437298958018045847
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.36701522467938322209622059432783849932119255948552589303040923993579692464400
Short name T383
Test name
Test status
Simulation time 624328106 ps
CPU time 938.63 seconds
Started Nov 22 01:23:53 PM PST 23
Finished Nov 22 01:39:39 PM PST 23
Peak memory 401648 kb
Host smart-f97964ad-0969-4526-bfd5-9842f11bc6a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=36701522467938322209622059432783849932119255948552589303040923993579692464400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sr
am_ctrl_stress_all_with_rand_reset.36701522467938322209622059432783849932119255948552589303040923993579692464400
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.77265217493931473716201686606955649378544704298666139754715543161926047258245
Short name T838
Test name
Test status
Simulation time 6491370455 ps
CPU time 349.1 seconds
Started Nov 22 01:24:07 PM PST 23
Finished Nov 22 01:30:02 PM PST 23
Peak memory 202656 kb
Host smart-d1bc794e-c035-438a-8170-4cc2c3de9b9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77265217493931473716201686606955649378544704298666139754715543161926047258245
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.772652174939314737162016866069556493785447042986661
39754715543161926047258245
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.12516807500782608066810349517197481431180909905567788143891292095053056013180
Short name T1031
Test name
Test status
Simulation time 237420487 ps
CPU time 91.19 seconds
Started Nov 22 01:24:38 PM PST 23
Finished Nov 22 01:26:10 PM PST 23
Peak memory 351304 kb
Host smart-ff530297-c5e7-47db-a5a9-c5be0b79df42
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125168075007826080668103495171974814311809099055677881
43891292095053056013180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1251680750078260806681
0349517197481431180909905567788143891292095053056013180
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.36133306662461657940219314482876310560285349430458873552146806074580333191114
Short name T784
Test name
Test status
Simulation time 4471404472 ps
CPU time 957.27 seconds
Started Nov 22 01:21:44 PM PST 23
Finished Nov 22 01:37:46 PM PST 23
Peak memory 375480 kb
Host smart-7af22a41-4091-4053-bd7d-d24797759e37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36133306662461657940219314482876310560285349430458873552146806074580333191114
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_key_req.3613330666246165794021931448287631056028
5349430458873552146806074580333191114
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.112165699865862534636207928440458658688379012968476702486608029963611133411967
Short name T22
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:21:24 PM PST 23
Finished Nov 22 01:21:34 PM PST 23
Peak memory 202216 kb
Host smart-afcb8192-2231-4fcf-aac9-2d1d4318fe0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112165699865862534636207928440458658688379012968476702486608029963
611133411967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.112165699865862534636207928440458658688379012968476702
486608029963611133411967
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.98155339026202853486163859420552546153574267972043196309795383887634300850974
Short name T3
Test name
Test status
Simulation time 9249473390 ps
CPU time 82.03 seconds
Started Nov 22 01:21:10 PM PST 23
Finished Nov 22 01:22:34 PM PST 23
Peak memory 202552 kb
Host smart-eade6d53-f600-4985-9b73-1490c9d03ccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98155339026202853486163859420552546153574267972043196309795383887634300850974 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.98155339026202853486163859420552546153574267972043196309795383887634300850974
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.13810264363176128351496225037164812083284797144440116666430512457090456101661
Short name T274
Test name
Test status
Simulation time 23162112088 ps
CPU time 818.6 seconds
Started Nov 22 01:21:17 PM PST 23
Finished Nov 22 01:34:58 PM PST 23
Peak memory 364620 kb
Host smart-1c9fc579-5305-4b7c-a333-65e74d7152ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13810264363176128351496225037164812083284797144440116666430512457090456101661 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.13810264363176128351496225037164812083284797144440116666430512457090456101661
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.109062917510727180553132495483712802197131830952683112208834767338360610276487
Short name T712
Test name
Test status
Simulation time 985753786 ps
CPU time 7.1 seconds
Started Nov 22 01:21:24 PM PST 23
Finished Nov 22 01:21:41 PM PST 23
Peak memory 213132 kb
Host smart-78817e1a-d7d9-4ca8-8326-fd14e0674972
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109062917510727180553132495483712802197131830952683112208834767338360610276487 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.109062917510727180553132495483712802197131830952683112208834767338360610276487
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.60205506806035606508533574875654238849093465702644113068633733083232313699338
Short name T293
Test name
Test status
Simulation time 209242141 ps
CPU time 72.11 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:23:03 PM PST 23
Peak memory 351288 kb
Host smart-ad626704-d24c-4c43-b85d-c15df8f8123c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6020550680603560650853357487565423884909346570264411306
8633733083232313699338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max_throughput.602055068060356065085335748756542388
49093465702644113068633733083232313699338
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.85269171150952880221618033626839756779166265685243311859910753393632304976534
Short name T794
Test name
Test status
Simulation time 166171057 ps
CPU time 3.17 seconds
Started Nov 22 01:21:12 PM PST 23
Finished Nov 22 01:21:16 PM PST 23
Peak memory 215608 kb
Host smart-955c634c-7c8f-4f6b-939f-aa88279c8880
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85269171150952880221618033626839756779166265685243311859910753393632
304976534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.8526917115095288022161803362683975677916626568524
3311859910753393632304976534
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.59016331309324174412886925302423997479824188231015780001429024932352657845023
Short name T718
Test name
Test status
Simulation time 590810517 ps
CPU time 5.52 seconds
Started Nov 22 01:21:14 PM PST 23
Finished Nov 22 01:21:21 PM PST 23
Peak memory 202020 kb
Host smart-43c3b1db-7e16-4ec5-9fcb-497853adc359
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59016331309324174412886925302423997479824188231015780001429024932352657845023
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.59016331309324174412886925302423997479824188231015780001429024932352657845023
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.62350119191542556047600572019964590707464604408420528046780686027762324471474
Short name T640
Test name
Test status
Simulation time 21947461091 ps
CPU time 859.25 seconds
Started Nov 22 01:21:16 PM PST 23
Finished Nov 22 01:35:37 PM PST 23
Peak memory 371288 kb
Host smart-a3f41e29-5b57-4dff-a410-f29dc94fc802
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62350119191542556047600572019964590707464604408420528046780686027762324471474 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.62350119191542556047600572019964590707464604408420528046780686027762324471474
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.61103934098921940129122675426717498096032609772954953237934491309939240484563
Short name T648
Test name
Test status
Simulation time 445204539 ps
CPU time 11.74 seconds
Started Nov 22 01:21:25 PM PST 23
Finished Nov 22 01:21:47 PM PST 23
Peak memory 246564 kb
Host smart-f4fc0dff-6abd-41f0-bf1b-2f5f0835b284
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611039340989219401291226754267174980960326097729549532379344913099392
40484563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.6110393409892194012912267542671749809603260977295495323
7934491309939240484563
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.59913725816168995875251454521228403613878072489834558732025440128854883606618
Short name T760
Test name
Test status
Simulation time 42305619653 ps
CPU time 528.89 seconds
Started Nov 22 01:22:00 PM PST 23
Finished Nov 22 01:30:54 PM PST 23
Peak memory 202500 kb
Host smart-8604cb69-95dd-4bac-96dd-88171037f497
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599137258161689958752514545212284036138780724898345587320254401288548
83606618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access_b2b.59913725816168995875251454521228403613878
072489834558732025440128854883606618
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.104982298674061409626793245010376817831671550755350645209443772788291484626062
Short name T1016
Test name
Test status
Simulation time 40672061 ps
CPU time 0.82 seconds
Started Nov 22 01:21:33 PM PST 23
Finished Nov 22 01:21:40 PM PST 23
Peak memory 202568 kb
Host smart-82f86b88-7183-4565-8b27-f6c91e2b0788
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104982298674061409626793245010376817831671550755350645209443772788291484626062 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.104982298674061409626793245010376817831671550755350645209443772788291484626062
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.76575072153195401233194152486846218751181025080863995781266481062607098412356
Short name T846
Test name
Test status
Simulation time 19383553031 ps
CPU time 461.97 seconds
Started Nov 22 01:21:21 PM PST 23
Finished Nov 22 01:29:07 PM PST 23
Peak memory 371812 kb
Host smart-13b001c8-b519-4100-9fda-8a05be0bca90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76575072153195401233194152486846218751181025080863995781266481062607098412356 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.76575072153195401233194152486846218751181025080863995781266481062607098412356
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.99851521711454908497642519137252438161076990354576297651060661813144875443148
Short name T684
Test name
Test status
Simulation time 427865392 ps
CPU time 11.92 seconds
Started Nov 22 01:21:27 PM PST 23
Finished Nov 22 01:21:48 PM PST 23
Peak memory 246624 kb
Host smart-e2d46626-4679-46e2-a94d-f453a372a7f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99851521711454908497642519137252438161076990354576297651060661813144875443148 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.99851521711454908497642519137252438161076990354576297651060661813144875443148
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.13131518976802970314965441109467322042337836303702394801336242562027473981924
Short name T340
Test name
Test status
Simulation time 121463254244 ps
CPU time 3481.85 seconds
Started Nov 22 01:21:07 PM PST 23
Finished Nov 22 02:19:10 PM PST 23
Peak memory 375480 kb
Host smart-497998a7-1851-4be2-b0a0-0b53292d96af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131315189768029703149654411094673220423378363037023948013362425
62027473981924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.131315189768029703149654411094673220423378363037
02394801336242562027473981924
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.105196375941325852678906279782028807544098947848917007300114080056251594707717
Short name T903
Test name
Test status
Simulation time 624328106 ps
CPU time 1259.74 seconds
Started Nov 22 01:21:22 PM PST 23
Finished Nov 22 01:42:26 PM PST 23
Peak memory 401788 kb
Host smart-f4a2f04f-f96c-401c-bc07-0e80b3941def
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=105196375941325852678906279782028807544098947848917007300114080056251594707717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr
am_ctrl_stress_all_with_rand_reset.105196375941325852678906279782028807544098947848917007300114080056251594707717
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.14967550270344648787872115329067498560188161836994015441741056439677723344553
Short name T95
Test name
Test status
Simulation time 6491370455 ps
CPU time 355.62 seconds
Started Nov 22 01:21:13 PM PST 23
Finished Nov 22 01:27:10 PM PST 23
Peak memory 202560 kb
Host smart-b209ea18-ed05-4c71-bee1-da9e13b9876e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14967550270344648787872115329067498560188161836994015441741056439677723344553
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.1496755027034464878787211532906749856018816183699401
5441741056439677723344553
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.23888212470151803222075057410118165421199974939325542747768724574156146312387
Short name T911
Test name
Test status
Simulation time 237420487 ps
CPU time 110.83 seconds
Started Nov 22 01:21:04 PM PST 23
Finished Nov 22 01:22:58 PM PST 23
Peak memory 351272 kb
Host smart-cae3b166-973f-46b6-9072-8101950c5937
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238882124701518032220750574101181654211999749393255427
47768724574156146312387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.23888212470151803222075
057410118165421199974939325542747768724574156146312387
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.27286282361183275309104239400018827941105799442450543331764884867002760649813
Short name T524
Test name
Test status
Simulation time 4471404472 ps
CPU time 677.66 seconds
Started Nov 22 01:22:46 PM PST 23
Finished Nov 22 01:34:17 PM PST 23
Peak memory 375084 kb
Host smart-616c0bc2-bd39-49b8-b228-fff7be50044e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27286282361183275309104239400018827941105799442450543331764884867002760649813
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_key_req.2728628236118327530910423940001882794110
5799442450543331764884867002760649813
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.16331368040532629229140035269798102078836892359583651510777027652395832003187
Short name T499
Test name
Test status
Simulation time 16600825 ps
CPU time 0.66 seconds
Started Nov 22 01:21:36 PM PST 23
Finished Nov 22 01:21:45 PM PST 23
Peak memory 202108 kb
Host smart-b3c067cf-5ef4-4cbc-86d5-7d710398ad52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163313680405326292291400352697981020788368923595836515107770276523
95832003187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1633136804053262922914003526979810207883689235958365151
0777027652395832003187
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.12955502644157558392889601159808174588790149191073051114837147504586807906557
Short name T71
Test name
Test status
Simulation time 9249473390 ps
CPU time 84.05 seconds
Started Nov 22 01:21:20 PM PST 23
Finished Nov 22 01:22:49 PM PST 23
Peak memory 202624 kb
Host smart-5cdf3a0f-d483-40d0-9846-0cf353fd7880
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12955502644157558392889601159808174588790149191073051114837147504586807906557 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.12955502644157558392889601159808174588790149191073051114837147504586807906557
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.76062380328796112214923030446180008227110811159246449443493727617966790280849
Short name T145
Test name
Test status
Simulation time 23162112088 ps
CPU time 957.59 seconds
Started Nov 22 01:21:05 PM PST 23
Finished Nov 22 01:37:05 PM PST 23
Peak memory 364600 kb
Host smart-da8b15e7-8e34-47f2-b300-a1d1dbb8fe24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76062380328796112214923030446180008227110811159246449443493727617966790280849 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.76062380328796112214923030446180008227110811159246449443493727617966790280849
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.99180398760928107484623878247262781129210864763208644746407766355614007495421
Short name T372
Test name
Test status
Simulation time 985753786 ps
CPU time 7.07 seconds
Started Nov 22 01:21:16 PM PST 23
Finished Nov 22 01:21:25 PM PST 23
Peak memory 213148 kb
Host smart-c51ba8e0-e732-45ee-a232-ff1046b8b34c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99180398760928107484623878247262781129210864763208644746407766355614007495421 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.99180398760928107484623878247262781129210864763208644746407766355614007495421
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.73568623885273730450079797407022815852185794254575124873183461438233075013677
Short name T930
Test name
Test status
Simulation time 209242141 ps
CPU time 87.91 seconds
Started Nov 22 01:21:09 PM PST 23
Finished Nov 22 01:22:38 PM PST 23
Peak memory 351356 kb
Host smart-5ca41421-228e-4319-92b6-41f4af10790c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7356862388527373045007979740702281585218579425457512487
3183461438233075013677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max_throughput.735686238852737304500797974070228158
52185794254575124873183461438233075013677
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.66677470042594116491342412618619656622163038911685073864277221715324330957740
Short name T925
Test name
Test status
Simulation time 166171057 ps
CPU time 2.93 seconds
Started Nov 22 01:21:29 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 215688 kb
Host smart-34083698-bd31-48a8-b6d0-e787bff295d3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66677470042594116491342412618619656622163038911685073864277221715324
330957740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.6667747004259411649134241261861965662216303891168
5073864277221715324330957740
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.5911602860308587051390797758719554071899052118963352774869780093227425479028
Short name T812
Test name
Test status
Simulation time 590810517 ps
CPU time 5.82 seconds
Started Nov 22 01:21:17 PM PST 23
Finished Nov 22 01:21:24 PM PST 23
Peak memory 202616 kb
Host smart-e8345843-cbaa-462e-8329-93579cbd9300
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5911602860308587051390797758719554071899052118963352774869780093227425479028 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.5911602860308587051390797758719554071899052118963352774869780093227425479028
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.115482739590792469674488242208337218723764315047443861333967333048051016566882
Short name T12
Test name
Test status
Simulation time 21947461091 ps
CPU time 978.66 seconds
Started Nov 22 01:21:23 PM PST 23
Finished Nov 22 01:37:51 PM PST 23
Peak memory 371368 kb
Host smart-898d2081-82b9-4d8b-be9d-1578b8429248
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115482739590792469674488242208337218723764315047443861333967333048051016566882 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.115482739590792469674488242208337218723764315047443861333967333048051016566882
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.14344941421282415197790422528215028224121193866675870664768453848515694362217
Short name T483
Test name
Test status
Simulation time 445204539 ps
CPU time 12.91 seconds
Started Nov 22 01:22:06 PM PST 23
Finished Nov 22 01:22:23 PM PST 23
Peak memory 246508 kb
Host smart-996c29d0-146a-4c67-a1e6-40a348716672
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143449414212824151977904225282150282241211938666758706647684538485156
94362217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.1434494142128241519779042252821502822412119386667587066
4768453848515694362217
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.60042177151347530424025626104193139623318635001345088993240563982260837271013
Short name T739
Test name
Test status
Simulation time 42305619653 ps
CPU time 552.54 seconds
Started Nov 22 01:21:08 PM PST 23
Finished Nov 22 01:30:22 PM PST 23
Peak memory 202596 kb
Host smart-525ad2c3-ea7b-4454-8cc7-abfc21ffdafd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600421771513475304240256261041931396233186350013450889932405639822608
37271013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access_b2b.60042177151347530424025626104193139623318
635001345088993240563982260837271013
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.46349811661519030923466520701049093232803646150408893049030623872810625493188
Short name T831
Test name
Test status
Simulation time 40672061 ps
CPU time 0.84 seconds
Started Nov 22 01:21:20 PM PST 23
Finished Nov 22 01:21:24 PM PST 23
Peak memory 202460 kb
Host smart-760a8841-ec85-48b7-a4b9-28ed8b4edc0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46349811661519030923466520701049093232803646150408893049030623872810625493188 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.46349811661519030923466520701049093232803646150408893049030623872810625493188
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.23287645579490758580577757918325195506611203852988081883468930544590490985021
Short name T280
Test name
Test status
Simulation time 19383553031 ps
CPU time 569.9 seconds
Started Nov 22 01:21:20 PM PST 23
Finished Nov 22 01:30:54 PM PST 23
Peak memory 371796 kb
Host smart-955f9edf-fe56-4124-b544-d375b44e7435
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287645579490758580577757918325195506611203852988081883468930544590490985021 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.23287645579490758580577757918325195506611203852988081883468930544590490985021
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.96251202528930839510132270991679513220184281661055215586190553087935650483782
Short name T956
Test name
Test status
Simulation time 427865392 ps
CPU time 10.15 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:22:08 PM PST 23
Peak memory 246296 kb
Host smart-343ed1b0-bb2e-48e2-ad37-558e61d7fcf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96251202528930839510132270991679513220184281661055215586190553087935650483782 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.96251202528930839510132270991679513220184281661055215586190553087935650483782
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.85353275867313696514331649277214793088928481883199193947567604164033899534902
Short name T697
Test name
Test status
Simulation time 121463254244 ps
CPU time 3755.33 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 02:24:14 PM PST 23
Peak memory 375456 kb
Host smart-23dc0a7d-f62f-4d2d-aa45-91b7375bb8a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853532758673136965143316492772147930889284818831991939475676041
64033899534902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.853532758673136965143316492772147930889284818831
99193947567604164033899534902
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.69555725039975662635840466722958196886000686610202195687427698735516701693085
Short name T264
Test name
Test status
Simulation time 624328106 ps
CPU time 1047.3 seconds
Started Nov 22 01:21:11 PM PST 23
Finished Nov 22 01:38:40 PM PST 23
Peak memory 401764 kb
Host smart-18ef7bd7-acc8-43c8-886d-67f42de66057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=69555725039975662635840466722958196886000686610202195687427698735516701693085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sra
m_ctrl_stress_all_with_rand_reset.69555725039975662635840466722958196886000686610202195687427698735516701693085
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.23945994534801221693020966328238164409592974179898272291110653916471235008671
Short name T888
Test name
Test status
Simulation time 6491370455 ps
CPU time 354.33 seconds
Started Nov 22 01:21:14 PM PST 23
Finished Nov 22 01:27:10 PM PST 23
Peak memory 202016 kb
Host smart-21d35395-79a1-4056-a7f8-8c74b239e5b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23945994534801221693020966328238164409592974179898272291110653916471235008671
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.2394599453480122169302096632823816440959297417989827
2291110653916471235008671
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.61984956891140548085685104036553521606657873918289853446968909470106954772250
Short name T364
Test name
Test status
Simulation time 237420487 ps
CPU time 98.01 seconds
Started Nov 22 01:21:10 PM PST 23
Finished Nov 22 01:22:49 PM PST 23
Peak memory 351368 kb
Host smart-1029c578-98d2-4254-879b-0ead9555473e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619849568911405480856851040365535216066578739182898534
46968909470106954772250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.61984956891140548085685
104036553521606657873918289853446968909470106954772250
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3577985479266740933981060288818564848706979753750676925402948328193646718712
Short name T317
Test name
Test status
Simulation time 4471404472 ps
CPU time 820.25 seconds
Started Nov 22 01:21:08 PM PST 23
Finished Nov 22 01:34:49 PM PST 23
Peak memory 375436 kb
Host smart-3d6702e2-9d3d-48c8-80c5-2426f51c9c00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577985479266740933981060288818564848706979753750676925402948328193646718712
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_key_req.35779854792667409339810602888185648487069
79753750676925402948328193646718712
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.60139267486302404347584345701951727311383026523914554390141042192333310784473
Short name T901
Test name
Test status
Simulation time 16600825 ps
CPU time 0.6 seconds
Started Nov 22 01:21:18 PM PST 23
Finished Nov 22 01:21:20 PM PST 23
Peak memory 202184 kb
Host smart-263a3b3a-78d1-47d3-99af-dbdd2ca00b44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601392674863024043475843457019517273113830265239145543901410421923
33310784473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.6013926748630240434758434570195172731138302652391455439
0141042192333310784473
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.51502581011423112901533035013886948661337026809709264202672389402396979459247
Short name T781
Test name
Test status
Simulation time 9249473390 ps
CPU time 86.02 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:23:03 PM PST 23
Peak memory 202624 kb
Host smart-d21721fb-12df-40c7-bf68-bc940e41561b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51502581011423112901533035013886948661337026809709264202672389402396979459247 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.51502581011423112901533035013886948661337026809709264202672389402396979459247
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.20600730255538537312274972644684630989954197950629537199038218661970709202227
Short name T610
Test name
Test status
Simulation time 23162112088 ps
CPU time 711.1 seconds
Started Nov 22 01:22:46 PM PST 23
Finished Nov 22 01:34:51 PM PST 23
Peak memory 364224 kb
Host smart-4cc39b51-73f7-452e-a57f-674b0c994b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20600730255538537312274972644684630989954197950629537199038218661970709202227 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.20600730255538537312274972644684630989954197950629537199038218661970709202227
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.35690086920799195423411771716028634578389106466563056114557304532504448769532
Short name T289
Test name
Test status
Simulation time 985753786 ps
CPU time 7.28 seconds
Started Nov 22 01:22:18 PM PST 23
Finished Nov 22 01:22:28 PM PST 23
Peak memory 213164 kb
Host smart-a6f783ad-ecf3-46e3-b2b1-05c718648551
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35690086920799195423411771716028634578389106466563056114557304532504448769532 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.35690086920799195423411771716028634578389106466563056114557304532504448769532
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.56054440429850230219861969885777422529231957066657698033705350609409608810963
Short name T520
Test name
Test status
Simulation time 209242141 ps
CPU time 86.48 seconds
Started Nov 22 01:22:18 PM PST 23
Finished Nov 22 01:23:46 PM PST 23
Peak memory 351232 kb
Host smart-5e8e42fd-4c2e-4d10-b119-b507b7c3fe47
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5605444042985023021986196988577742252923195706665769803
3705350609409608810963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max_throughput.560544404298502302198619698857774225
29231957066657698033705350609409608810963
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.46785526050071926686252501473361068626393592026297346737313368510419505833929
Short name T948
Test name
Test status
Simulation time 166171057 ps
CPU time 3.03 seconds
Started Nov 22 01:21:29 PM PST 23
Finished Nov 22 01:21:40 PM PST 23
Peak memory 215688 kb
Host smart-6f4eb688-490b-4ccd-b164-50381bece599
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46785526050071926686252501473361068626393592026297346737313368510419
505833929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.4678552605007192668625250147336106862639359202629
7346737313368510419505833929
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.111072705380812467017816096858211547062269652762000376681688380981146192714278
Short name T10
Test name
Test status
Simulation time 590810517 ps
CPU time 5.36 seconds
Started Nov 22 01:21:26 PM PST 23
Finished Nov 22 01:21:41 PM PST 23
Peak memory 202612 kb
Host smart-d2f74e7a-c962-46dd-abc6-385ab079b9bd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111072705380812467017816096858211547062269652762000376681688380981146192714278
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.111072705380812467017816096858211547062269652762000376681688380981146192714278
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.101441567260920966934219090061480866242541885374583565380826672069405484972912
Short name T511
Test name
Test status
Simulation time 21947461091 ps
CPU time 640.34 seconds
Started Nov 22 01:21:13 PM PST 23
Finished Nov 22 01:31:54 PM PST 23
Peak memory 371412 kb
Host smart-52642481-6ac8-4be7-b63f-6d53d767d49e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101441567260920966934219090061480866242541885374583565380826672069405484972912 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.101441567260920966934219090061480866242541885374583565380826672069405484972912
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.87615826307238445229021457318246765914632255424903165061602085439263363503946
Short name T416
Test name
Test status
Simulation time 445204539 ps
CPU time 13.32 seconds
Started Nov 22 01:21:16 PM PST 23
Finished Nov 22 01:21:31 PM PST 23
Peak memory 246492 kb
Host smart-34f00955-1c4a-4104-878d-dd4cd5e82d70
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876158263072384452290214573182467659146322554249031650616020854392633
63503946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.8761582630723844522902145731824676591463225542490316506
1602085439263363503946
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.103298420817463781585869094223277696159579205462358788583953189907559584981655
Short name T693
Test name
Test status
Simulation time 42305619653 ps
CPU time 527.94 seconds
Started Nov 22 01:22:02 PM PST 23
Finished Nov 22 01:30:56 PM PST 23
Peak memory 202508 kb
Host smart-0c2d32fa-b91d-4ca7-abf0-6fec72ecf639
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103298420817463781585869094223277696159579205462358788583953189907559
584981655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access_b2b.1032984208174637815858690942232776961595
79205462358788583953189907559584981655
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.75055511259939642997360943085943001950782419550115774134083590549868738703030
Short name T327
Test name
Test status
Simulation time 40672061 ps
CPU time 0.9 seconds
Started Nov 22 01:21:10 PM PST 23
Finished Nov 22 01:21:12 PM PST 23
Peak memory 202600 kb
Host smart-ed737623-5562-4cf9-aba6-3384cdd9f692
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75055511259939642997360943085943001950782419550115774134083590549868738703030 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.75055511259939642997360943085943001950782419550115774134083590549868738703030
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.60869041169791237175143008689949091822998257362179913883869378981309323245173
Short name T99
Test name
Test status
Simulation time 19383553031 ps
CPU time 601.68 seconds
Started Nov 22 01:21:15 PM PST 23
Finished Nov 22 01:31:18 PM PST 23
Peak memory 371752 kb
Host smart-a54e03f8-bfe3-4eb3-84dd-7f8a911762ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60869041169791237175143008689949091822998257362179913883869378981309323245173 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.60869041169791237175143008689949091822998257362179913883869378981309323245173
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.107268573615754140761536622724032000714056076761052089059788321793244923115909
Short name T732
Test name
Test status
Simulation time 427865392 ps
CPU time 11.83 seconds
Started Nov 22 01:21:34 PM PST 23
Finished Nov 22 01:21:54 PM PST 23
Peak memory 246392 kb
Host smart-a8d1b9e9-9543-41e5-acab-be2b141977df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107268573615754140761536622724032000714056076761052089059788321793244923115909 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.107268573615754140761536622724032000714056076761052089059788321793244923115909
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.28762069131046477770771762995492867668790573870458052888384891740867119256904
Short name T824
Test name
Test status
Simulation time 121463254244 ps
CPU time 3965.98 seconds
Started Nov 22 01:21:18 PM PST 23
Finished Nov 22 02:27:27 PM PST 23
Peak memory 375388 kb
Host smart-98ffcc5e-a878-4cac-9425-f2e2e5a0a5d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287620691310464777707717629954928676687905738704580528883848917
40867119256904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.287620691310464777707717629954928676687905738704
58052888384891740867119256904
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.54885340239896699726216967193861349636818309629989751100721770713945761779266
Short name T977
Test name
Test status
Simulation time 624328106 ps
CPU time 1316.37 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:43:34 PM PST 23
Peak memory 401784 kb
Host smart-8cbd21cd-3a84-446e-b759-19414b1f0fa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=54885340239896699726216967193861349636818309629989751100721770713945761779266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sra
m_ctrl_stress_all_with_rand_reset.54885340239896699726216967193861349636818309629989751100721770713945761779266
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.31871177499736058379082866657305805841102306376816282711362344667802905502638
Short name T449
Test name
Test status
Simulation time 6491370455 ps
CPU time 337.74 seconds
Started Nov 22 01:21:29 PM PST 23
Finished Nov 22 01:27:15 PM PST 23
Peak memory 202628 kb
Host smart-f9abbc04-f777-4c0d-817e-b5c474c12f83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31871177499736058379082866657305805841102306376816282711362344667802905502638
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.3187117749973605837908286665730580584110230637681628
2711362344667802905502638
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.65089179359011457101718108591089154612484316963415503262935712223628793770134
Short name T509
Test name
Test status
Simulation time 237420487 ps
CPU time 100.61 seconds
Started Nov 22 01:21:42 PM PST 23
Finished Nov 22 01:23:28 PM PST 23
Peak memory 351288 kb
Host smart-1679ee80-ebd7-4663-be12-0ebe651714e5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650891793590114571017181085910891546124843169634155032
62935712223628793770134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.65089179359011457101718
108591089154612484316963415503262935712223628793770134
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.29602726678192382767746124875642795097217082769247553132954910302336101728519
Short name T467
Test name
Test status
Simulation time 4471404472 ps
CPU time 811.39 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:35:26 PM PST 23
Peak memory 375496 kb
Host smart-c1b73e9e-95b8-4fe9-aeb9-001c6d6413f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29602726678192382767746124875642795097217082769247553132954910302336101728519
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_key_req.2960272667819238276774612487564279509721
7082769247553132954910302336101728519
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.59827222691222097190372285528329548564319746639128950746402987611787432284471
Short name T714
Test name
Test status
Simulation time 16600825 ps
CPU time 0.61 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:21:38 PM PST 23
Peak memory 202160 kb
Host smart-2404e7d2-a8cc-4a4c-a952-8155dcc93ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598272226912220971903722855283295485643197466391289507464029876117
87432284471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.5982722269122209719037228552832954856431974663912895074
6402987611787432284471
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.98686981392008353745248297210266929255071303108883632248610634244548662914841
Short name T706
Test name
Test status
Simulation time 9249473390 ps
CPU time 83.74 seconds
Started Nov 22 01:21:45 PM PST 23
Finished Nov 22 01:23:15 PM PST 23
Peak memory 202624 kb
Host smart-3d4aecc5-b4a0-41f7-8c6d-8b71c2bf7744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98686981392008353745248297210266929255071303108883632248610634244548662914841 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.98686981392008353745248297210266929255071303108883632248610634244548662914841
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.88866625934449268191083501009800986405917223816995442615443825648832850346578
Short name T259
Test name
Test status
Simulation time 23162112088 ps
CPU time 778.61 seconds
Started Nov 22 01:21:48 PM PST 23
Finished Nov 22 01:34:52 PM PST 23
Peak memory 364632 kb
Host smart-cd7d187c-7eda-4336-8cbc-6d3a0f5e5232
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88866625934449268191083501009800986405917223816995442615443825648832850346578 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.88866625934449268191083501009800986405917223816995442615443825648832850346578
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.76756245338797371144832990566486157184822583058299339704916425785969918969278
Short name T678
Test name
Test status
Simulation time 985753786 ps
CPU time 7.34 seconds
Started Nov 22 01:21:10 PM PST 23
Finished Nov 22 01:21:19 PM PST 23
Peak memory 213204 kb
Host smart-fd287fea-a398-4558-b5d4-9b7263ca4cdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76756245338797371144832990566486157184822583058299339704916425785969918969278 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.76756245338797371144832990566486157184822583058299339704916425785969918969278
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.22848753785648929318714918424684058442489122537431746941612500708547351411536
Short name T526
Test name
Test status
Simulation time 209242141 ps
CPU time 87.59 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:23:04 PM PST 23
Peak memory 351312 kb
Host smart-7745e841-2c65-4c23-bc19-0880e8d29ba6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284875378564892931871491842468405844248912253743174694
1612500708547351411536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max_throughput.228487537856489293187149184246840584
42489122537431746941612500708547351411536
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.48934126875089417922540553653383632612435220211953626077441612815203999136370
Short name T799
Test name
Test status
Simulation time 166171057 ps
CPU time 3.08 seconds
Started Nov 22 01:21:22 PM PST 23
Finished Nov 22 01:21:33 PM PST 23
Peak memory 215716 kb
Host smart-54afb065-fddd-4ee7-b08d-64b5695aab6f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48934126875089417922540553653383632612435220211953626077441612815203
999136370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.4893412687508941792254055365338363261243522021195
3626077441612815203999136370
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.66995042027691610498694193948720571694814978450567914351181149589380036268996
Short name T991
Test name
Test status
Simulation time 590810517 ps
CPU time 5.33 seconds
Started Nov 22 01:21:29 PM PST 23
Finished Nov 22 01:21:42 PM PST 23
Peak memory 202572 kb
Host smart-973fb3c8-36a9-4f26-80b6-5142563ba9d1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66995042027691610498694193948720571694814978450567914351181149589380036268996
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.66995042027691610498694193948720571694814978450567914351181149589380036268996
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.59324070730549328470587203995667987605031876589872948090160619857091363116144
Short name T450
Test name
Test status
Simulation time 21947461091 ps
CPU time 696.27 seconds
Started Nov 22 01:21:31 PM PST 23
Finished Nov 22 01:33:14 PM PST 23
Peak memory 371396 kb
Host smart-e62ec011-e6f6-4e83-92f0-351c4baec225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59324070730549328470587203995667987605031876589872948090160619857091363116144 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.59324070730549328470587203995667987605031876589872948090160619857091363116144
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.101710250639225190176892958128075866593260691958260991560151328266123447925635
Short name T507
Test name
Test status
Simulation time 445204539 ps
CPU time 12.77 seconds
Started Nov 22 01:21:39 PM PST 23
Finished Nov 22 01:21:59 PM PST 23
Peak memory 246404 kb
Host smart-2f0560af-a277-452c-8357-c6d9a2c5f927
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101710250639225190176892958128075866593260691958260991560151328266123
447925635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.101710250639225190176892958128075866593260691958260991
560151328266123447925635
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.97527562628970611548963905447636806920108148521864427632217709385510251577659
Short name T672
Test name
Test status
Simulation time 42305619653 ps
CPU time 526.46 seconds
Started Nov 22 01:21:29 PM PST 23
Finished Nov 22 01:30:23 PM PST 23
Peak memory 202664 kb
Host smart-15be946e-eda4-4d32-9010-fa8b929ae5b2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975275626289706115489639054476368069201081485218644276322177093855102
51577659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access_b2b.97527562628970611548963905447636806920108
148521864427632217709385510251577659
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.12467526404756558329817018159866921215078504423238105137759917260922796437263
Short name T934
Test name
Test status
Simulation time 40672061 ps
CPU time 0.81 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 202572 kb
Host smart-b24f7d33-bcef-427c-b30d-3012bb427902
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467526404756558329817018159866921215078504423238105137759917260922796437263 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.12467526404756558329817018159866921215078504423238105137759917260922796437263
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.1812325402132794412587679296843408336188820318250485269926193785897172315086
Short name T39
Test name
Test status
Simulation time 19383553031 ps
CPU time 537.87 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:30:35 PM PST 23
Peak memory 371788 kb
Host smart-2db1a343-4e70-4c50-9818-b02cbb148d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812325402132794412587679296843408336188820318250485269926193785897172315086 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1812325402132794412587679296843408336188820318250485269926193785897172315086
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.34010296906965006569126588179293475239342198982726440831076936284960942133789
Short name T750
Test name
Test status
Simulation time 427865392 ps
CPU time 12.04 seconds
Started Nov 22 01:21:49 PM PST 23
Finished Nov 22 01:22:07 PM PST 23
Peak memory 246580 kb
Host smart-c74bb75e-d88d-4b41-8fad-fbec86d57032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010296906965006569126588179293475239342198982726440831076936284960942133789 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.34010296906965006569126588179293475239342198982726440831076936284960942133789
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.948537715975402707146338349208542471066046439077034999387761379420097542125
Short name T700
Test name
Test status
Simulation time 121463254244 ps
CPU time 3221.34 seconds
Started Nov 22 01:21:17 PM PST 23
Finished Nov 22 02:15:00 PM PST 23
Peak memory 375348 kb
Host smart-c5f45e3f-d5d9-4f98-b3b4-e5268186e7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948537715975402707146338349208542471066046439077034999387761379
420097542125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.94853771597540270714633834920854247106604643907703
4999387761379420097542125
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.17118937358109241092733380901809092314462258988126116107990354819202212377216
Short name T669
Test name
Test status
Simulation time 624328106 ps
CPU time 986.92 seconds
Started Nov 22 01:21:29 PM PST 23
Finished Nov 22 01:38:04 PM PST 23
Peak memory 401788 kb
Host smart-ff56b02d-c6ce-4607-9778-8daec4654532
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=17118937358109241092733380901809092314462258988126116107990354819202212377216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sra
m_ctrl_stress_all_with_rand_reset.17118937358109241092733380901809092314462258988126116107990354819202212377216
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.95084595706055705461805702240933894320440164539509660218682480951768243703896
Short name T1020
Test name
Test status
Simulation time 6491370455 ps
CPU time 364.08 seconds
Started Nov 22 01:21:15 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 202680 kb
Host smart-4e4482ab-fa43-4b4e-826c-7b47651a0331
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95084595706055705461805702240933894320440164539509660218682480951768243703896
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.9508459570605570546180570224093389432044016453950966
0218682480951768243703896
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2925552119834756505644404915621110316931967523407542756676959058935247997125
Short name T427
Test name
Test status
Simulation time 237420487 ps
CPU time 100.43 seconds
Started Nov 22 01:21:37 PM PST 23
Finished Nov 22 01:23:25 PM PST 23
Peak memory 351288 kb
Host smart-206dce55-1e9f-4d1f-9e49-53a4b0ec84ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292555211983475650564440491562111031693196752340754275
6676959058935247997125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.292555211983475650564440
4915621110316931967523407542756676959058935247997125
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.33210275384407072045686558764764304882321970712295866243981131307577850454229
Short name T18
Test name
Test status
Simulation time 4471404472 ps
CPU time 630.58 seconds
Started Nov 22 01:21:28 PM PST 23
Finished Nov 22 01:32:07 PM PST 23
Peak memory 375524 kb
Host smart-d892bb74-4bda-4222-8c25-34c07ec12743
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210275384407072045686558764764304882321970712295866243981131307577850454229
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_key_req.3321027538440707204568655876476430488232
1970712295866243981131307577850454229
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.7072726667968742500501409844011691926441148598643720420923416940780196465207
Short name T710
Test name
Test status
Simulation time 16600825 ps
CPU time 0.63 seconds
Started Nov 22 01:23:05 PM PST 23
Finished Nov 22 01:23:16 PM PST 23
Peak memory 202236 kb
Host smart-738f2d4d-df74-413a-a095-ffad19744b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707272666796874250050140984401169192644114859864372042092341694078
0196465207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.70727266679687425005014098440116919264411485986437204209
23416940780196465207
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.10186150546143908710557617070074619277501012567211230231712811696727996224750
Short name T600
Test name
Test status
Simulation time 9249473390 ps
CPU time 85.18 seconds
Started Nov 22 01:21:53 PM PST 23
Finished Nov 22 01:23:24 PM PST 23
Peak memory 202596 kb
Host smart-2f2fde48-dd5d-4952-8828-e705515ecccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10186150546143908710557617070074619277501012567211230231712811696727996224750 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.10186150546143908710557617070074619277501012567211230231712811696727996224750
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.38582109453829996607999299518187765971716615820972288744139397524538385864176
Short name T653
Test name
Test status
Simulation time 23162112088 ps
CPU time 876.19 seconds
Started Nov 22 01:21:16 PM PST 23
Finished Nov 22 01:35:53 PM PST 23
Peak memory 364648 kb
Host smart-93aba19e-10d9-48de-855c-f660570ad3fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38582109453829996607999299518187765971716615820972288744139397524538385864176 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.38582109453829996607999299518187765971716615820972288744139397524538385864176
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.91531988655608908144651569934955147702106531841646456792646982025294648913263
Short name T7
Test name
Test status
Simulation time 985753786 ps
CPU time 7.02 seconds
Started Nov 22 01:21:31 PM PST 23
Finished Nov 22 01:21:45 PM PST 23
Peak memory 213032 kb
Host smart-d1acfca0-1685-4853-a28c-ecfef151062a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91531988655608908144651569934955147702106531841646456792646982025294648913263 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.91531988655608908144651569934955147702106531841646456792646982025294648913263
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.75474279717080779415140789650802406580397231318774810176646886775920145698688
Short name T961
Test name
Test status
Simulation time 209242141 ps
CPU time 115.97 seconds
Started Nov 22 01:21:32 PM PST 23
Finished Nov 22 01:23:34 PM PST 23
Peak memory 351304 kb
Host smart-f4741b38-dd39-4d82-a3b2-370348eb97c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7547427971708077941514078965080240658039723131877481017
6646886775920145698688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max_throughput.754742797170807794151407896508024065
80397231318774810176646886775920145698688
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.50518099803098011181764373573957464753765814186252096361452633223662906787723
Short name T81
Test name
Test status
Simulation time 166171057 ps
CPU time 3.14 seconds
Started Nov 22 01:21:23 PM PST 23
Finished Nov 22 01:21:35 PM PST 23
Peak memory 215780 kb
Host smart-e4362f12-f0ea-4d18-a712-31150cf2d682
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50518099803098011181764373573957464753765814186252096361452633223662
906787723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.5051809980309801118176437357395746475376581418625
2096361452633223662906787723
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.11137661250705635192509490470595492533560128665407020809697260007344883440489
Short name T1001
Test name
Test status
Simulation time 590810517 ps
CPU time 5.58 seconds
Started Nov 22 01:22:32 PM PST 23
Finished Nov 22 01:22:42 PM PST 23
Peak memory 202536 kb
Host smart-fe78c3e5-4cf9-4abd-8b8f-91eab7c9be95
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11137661250705635192509490470595492533560128665407020809697260007344883440489
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.11137661250705635192509490470595492533560128665407020809697260007344883440489
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.61215513863061341689039302207107177828356106798290240320758785037811078749705
Short name T853
Test name
Test status
Simulation time 21947461091 ps
CPU time 841.44 seconds
Started Nov 22 01:21:31 PM PST 23
Finished Nov 22 01:35:39 PM PST 23
Peak memory 371232 kb
Host smart-63bd3137-9a59-42de-8d92-bb663a24d199
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61215513863061341689039302207107177828356106798290240320758785037811078749705 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.61215513863061341689039302207107177828356106798290240320758785037811078749705
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.66259496480549433744624919127382445027657773122920471507374287844260032628095
Short name T1002
Test name
Test status
Simulation time 445204539 ps
CPU time 15.02 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:21:52 PM PST 23
Peak memory 246576 kb
Host smart-a5cde222-9930-4640-ab09-d5513c16b362
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662594964805494337446249191273824450276577731229204715073742878442600
32628095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.6625949648054943374462491912738244502765777312292047150
7374287844260032628095
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.108622941655065597048842417336920967265473567494992297383728041028404716543678
Short name T388
Test name
Test status
Simulation time 42305619653 ps
CPU time 568.06 seconds
Started Nov 22 01:21:21 PM PST 23
Finished Nov 22 01:30:53 PM PST 23
Peak memory 202660 kb
Host smart-92590017-e965-455b-beac-4b481b380618
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108622941655065597048842417336920967265473567494992297383728041028404
716543678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access_b2b.1086229416550655970488424173369209672654
73567494992297383728041028404716543678
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.29237753485018919991620075799628330353839069736796984320284839201822190954964
Short name T415
Test name
Test status
Simulation time 40672061 ps
CPU time 0.83 seconds
Started Nov 22 01:21:27 PM PST 23
Finished Nov 22 01:21:37 PM PST 23
Peak memory 202512 kb
Host smart-86667608-c206-4ef1-8538-c01277066101
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29237753485018919991620075799628330353839069736796984320284839201822190954964 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.29237753485018919991620075799628330353839069736796984320284839201822190954964
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.18638246328515846987062078399420194193206106253239173243212335044274312699231
Short name T302
Test name
Test status
Simulation time 19383553031 ps
CPU time 559.9 seconds
Started Nov 22 01:21:31 PM PST 23
Finished Nov 22 01:30:57 PM PST 23
Peak memory 371644 kb
Host smart-acb41d5d-5e11-4392-a7cf-df383e22d2af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18638246328515846987062078399420194193206106253239173243212335044274312699231 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.18638246328515846987062078399420194193206106253239173243212335044274312699231
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.52405322244210542872684244780245642756506570679308041845496560130761966386328
Short name T456
Test name
Test status
Simulation time 427865392 ps
CPU time 12.65 seconds
Started Nov 22 01:21:22 PM PST 23
Finished Nov 22 01:21:42 PM PST 23
Peak memory 246616 kb
Host smart-670ea0c6-479f-484f-94ad-2dc2ad7ce45c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52405322244210542872684244780245642756506570679308041845496560130761966386328 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.52405322244210542872684244780245642756506570679308041845496560130761966386328
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.32561909432011009478850295973152701765742351180266636509046410101674391673069
Short name T120
Test name
Test status
Simulation time 121463254244 ps
CPU time 3533.89 seconds
Started Nov 22 01:21:19 PM PST 23
Finished Nov 22 02:20:16 PM PST 23
Peak memory 375336 kb
Host smart-c2934d8f-623d-43cf-b5d1-d2117f7472ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325619094320110094788502959731527017657423511802666365090464101
01674391673069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.325619094320110094788502959731527017657423511802
66636509046410101674391673069
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.53769950094295375819207509616024577470094719417416263722193460289390467052425
Short name T834
Test name
Test status
Simulation time 624328106 ps
CPU time 1252.93 seconds
Started Nov 22 01:21:30 PM PST 23
Finished Nov 22 01:42:30 PM PST 23
Peak memory 401520 kb
Host smart-210c45db-2b84-415f-967d-24922a68d0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=53769950094295375819207509616024577470094719417416263722193460289390467052425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sra
m_ctrl_stress_all_with_rand_reset.53769950094295375819207509616024577470094719417416263722193460289390467052425
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.86559766893484739796543933534953085904998031979751824795342750853454956011434
Short name T514
Test name
Test status
Simulation time 6491370455 ps
CPU time 356.74 seconds
Started Nov 22 01:21:12 PM PST 23
Finished Nov 22 01:27:10 PM PST 23
Peak memory 202684 kb
Host smart-22d28409-b09e-4c92-839c-ebd472a6d486
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86559766893484739796543933534953085904998031979751824795342750853454956011434
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.8655976689348473979654393353495308590499803197975182
4795342750853454956011434
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2596501180263477885895381754843758332367859132101905112730354490980657841261
Short name T298
Test name
Test status
Simulation time 237420487 ps
CPU time 83.86 seconds
Started Nov 22 01:21:19 PM PST 23
Finished Nov 22 01:22:45 PM PST 23
Peak memory 351160 kb
Host smart-ec10a334-6400-484b-a171-fdbaabe0fe90
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259650118026347788589538175484375833236785913210190511
2730354490980657841261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.259650118026347788589538
1754843758332367859132101905112730354490980657841261
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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