Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.95 100.00 97.69 99.14 100.00 99.71 99.70 96.44


Total test records in report: 1040
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T754 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.13510526361221151424701902077379227678341356426960540368495302768486168949076 Nov 22 01:21:46 PM PST 23 Nov 22 01:21:55 PM PST 23 166171057 ps
T755 /workspace/coverage/default/38.sram_ctrl_alert_test.31725415314929095152264168921006991938451039897222575424488999665962413577202 Nov 22 01:23:18 PM PST 23 Nov 22 01:23:24 PM PST 23 16600825 ps
T756 /workspace/coverage/default/44.sram_ctrl_alert_test.28246585678805576326024285339799687656113600592629689590756410165021629317803 Nov 22 01:22:57 PM PST 23 Nov 22 01:23:08 PM PST 23 16600825 ps
T757 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.71476032282298857630388016945555846955470153435068769060796972101694587750392 Nov 22 01:21:38 PM PST 23 Nov 22 01:23:27 PM PST 23 237420487 ps
T758 /workspace/coverage/default/3.sram_ctrl_mem_walk.44342730148360012273335441633753263664095782860852531043831109968648259609638 Nov 22 01:21:45 PM PST 23 Nov 22 01:21:56 PM PST 23 590810517 ps
T759 /workspace/coverage/default/49.sram_ctrl_lc_escalation.34312680600155379369641489846087004626044932752879609184890103845046892952673 Nov 22 01:23:43 PM PST 23 Nov 22 01:23:59 PM PST 23 985753786 ps
T760 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.59913725816168995875251454521228403613878072489834558732025440128854883606618 Nov 22 01:22:00 PM PST 23 Nov 22 01:30:54 PM PST 23 42305619653 ps
T761 /workspace/coverage/default/1.sram_ctrl_partial_access.30880946945318422708268369211646607514241870973750913185084869898883784542035 Nov 22 01:21:49 PM PST 23 Nov 22 01:22:06 PM PST 23 445204539 ps
T762 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.30294014216060535721808470786423769991093856719385043723296547117145036142654 Nov 22 01:22:04 PM PST 23 Nov 22 01:31:32 PM PST 23 42305619653 ps
T763 /workspace/coverage/default/34.sram_ctrl_executable.37756277380668475842236878787661931887598927597764397957932836330432028863309 Nov 22 01:22:47 PM PST 23 Nov 22 01:36:56 PM PST 23 23162112088 ps
T764 /workspace/coverage/default/36.sram_ctrl_partial_access.25881588730249523638903975690572996381837623995706560381423052756620023357681 Nov 22 01:22:41 PM PST 23 Nov 22 01:23:00 PM PST 23 445204539 ps
T765 /workspace/coverage/default/49.sram_ctrl_stress_all.57017357417035488860139742143971435151355473521173580398036437298958018045847 Nov 22 01:24:10 PM PST 23 Nov 22 02:22:45 PM PST 23 121463254244 ps
T766 /workspace/coverage/default/32.sram_ctrl_multiple_keys.108173441743873041969335034732688561403679586825091594601181319952905914570170 Nov 22 01:22:25 PM PST 23 Nov 22 01:32:56 PM PST 23 21947461091 ps
T767 /workspace/coverage/default/24.sram_ctrl_mem_walk.100098812624745739691197539041902428531566843658549589735108504149441004661109 Nov 22 01:21:57 PM PST 23 Nov 22 01:22:09 PM PST 23 590810517 ps
T768 /workspace/coverage/default/47.sram_ctrl_partial_access.54990659415969552377103188099123465048981875627959568559900450878663783149432 Nov 22 01:23:09 PM PST 23 Nov 22 01:23:33 PM PST 23 445204539 ps
T769 /workspace/coverage/default/26.sram_ctrl_regwen.117025491091673981731458421396490865908422833477080518835638727103636213389 Nov 22 01:22:59 PM PST 23 Nov 22 01:32:02 PM PST 23 19383553031 ps
T770 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.64745208372071245416321145015234894228990619928985585185445664469552711719645 Nov 22 01:22:29 PM PST 23 Nov 22 01:24:13 PM PST 23 237420487 ps
T771 /workspace/coverage/default/11.sram_ctrl_partial_access.79086528893541392635544345878460963118420001727611065526997656137335209135306 Nov 22 01:21:47 PM PST 23 Nov 22 01:22:06 PM PST 23 445204539 ps
T772 /workspace/coverage/default/14.sram_ctrl_partial_access.30680950572749343353462793400127722538690430362001751539433840850252270386136 Nov 22 01:21:38 PM PST 23 Nov 22 01:21:57 PM PST 23 445204539 ps
T773 /workspace/coverage/default/43.sram_ctrl_ram_cfg.16664095586185458855442638764449985701175647123457064168800239187485746239400 Nov 22 01:23:00 PM PST 23 Nov 22 01:23:12 PM PST 23 40672061 ps
T774 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.85902081824195693165396637849167053299845167359398109892642961617430376287986 Nov 22 01:22:57 PM PST 23 Nov 22 01:24:54 PM PST 23 237420487 ps
T775 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.51118509641109110146341703358360493391260860205816778076262894544299209365235 Nov 22 01:21:49 PM PST 23 Nov 22 01:30:58 PM PST 23 42305619653 ps
T776 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.100536932845631692405587559369055264153803457635814978867039995448939158875404 Nov 22 01:22:50 PM PST 23 Nov 22 01:23:07 PM PST 23 166171057 ps
T777 /workspace/coverage/default/3.sram_ctrl_alert_test.105672312474726149877280895662723156162305709291310755540292631705697613754786 Nov 22 01:21:09 PM PST 23 Nov 22 01:21:11 PM PST 23 16600825 ps
T778 /workspace/coverage/default/0.sram_ctrl_lc_escalation.25392333695349327588501154078251371154535908483965248084387793395332942629203 Nov 22 01:20:57 PM PST 23 Nov 22 01:21:10 PM PST 23 985753786 ps
T779 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.109448178781807594974700921784520452032221007628891670062208206883960142715225 Nov 22 01:21:50 PM PST 23 Nov 22 01:38:51 PM PST 23 624328106 ps
T780 /workspace/coverage/default/10.sram_ctrl_ram_cfg.7465951270134390842507776696398044633391991412074414669900758010711846835548 Nov 22 01:21:22 PM PST 23 Nov 22 01:21:31 PM PST 23 40672061 ps
T781 /workspace/coverage/default/7.sram_ctrl_bijection.51502581011423112901533035013886948661337026809709264202672389402396979459247 Nov 22 01:21:30 PM PST 23 Nov 22 01:23:03 PM PST 23 9249473390 ps
T782 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.12702468083925503948287745533259265554650469696602796276324311523211128597821 Nov 22 01:22:29 PM PST 23 Nov 22 01:41:15 PM PST 23 624328106 ps
T783 /workspace/coverage/default/26.sram_ctrl_smoke.1329892229905264131109143371794254047600053402651739960335463564583410000052 Nov 22 01:21:59 PM PST 23 Nov 22 01:22:17 PM PST 23 427865392 ps
T784 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.36133306662461657940219314482876310560285349430458873552146806074580333191114 Nov 22 01:21:44 PM PST 23 Nov 22 01:37:46 PM PST 23 4471404472 ps
T785 /workspace/coverage/default/29.sram_ctrl_lc_escalation.18712676115304527042195782572484960401299519260653489382339872615574857090427 Nov 22 01:22:13 PM PST 23 Nov 22 01:22:23 PM PST 23 985753786 ps
T786 /workspace/coverage/default/37.sram_ctrl_stress_all.74487219404037192388917601871586843488221188095276735781819364078929393611907 Nov 22 01:22:28 PM PST 23 Nov 22 02:20:15 PM PST 23 121463254244 ps
T26 /workspace/coverage/default/1.sram_ctrl_sec_cm.86192131635851343923358514393058795744492742351365429744480422948177636077370 Nov 22 01:21:09 PM PST 23 Nov 22 01:21:13 PM PST 23 216402798 ps
T787 /workspace/coverage/default/23.sram_ctrl_max_throughput.109978642132389260745485708013245882858947859091439834707256984523990408396747 Nov 22 01:22:23 PM PST 23 Nov 22 01:23:53 PM PST 23 209242141 ps
T788 /workspace/coverage/default/14.sram_ctrl_executable.84332259452224024536321920816991316341951354597656512039768948974676599026250 Nov 22 01:21:34 PM PST 23 Nov 22 01:33:45 PM PST 23 23162112088 ps
T789 /workspace/coverage/default/41.sram_ctrl_lc_escalation.44564150866772628454767858057299430799568866453022715199587432543390952072748 Nov 22 01:23:05 PM PST 23 Nov 22 01:23:23 PM PST 23 985753786 ps
T790 /workspace/coverage/default/33.sram_ctrl_ram_cfg.7904021141244889601683473664583552123524622161927346748431920194274815672551 Nov 22 01:22:42 PM PST 23 Nov 22 01:22:50 PM PST 23 40672061 ps
T791 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.82997659036543847213273394015830681374989114152764316710165079075390422914508 Nov 22 01:22:23 PM PST 23 Nov 22 01:23:48 PM PST 23 237420487 ps
T792 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.9885648436008766744452234270905687452403883627440813298295647884670597982834 Nov 22 01:22:57 PM PST 23 Nov 22 01:29:08 PM PST 23 6491370455 ps
T793 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.11527869491607646918706355460646434643020072852430064871396886960131162447588 Nov 22 01:21:21 PM PST 23 Nov 22 01:21:28 PM PST 23 166171057 ps
T794 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.85269171150952880221618033626839756779166265685243311859910753393632304976534 Nov 22 01:21:12 PM PST 23 Nov 22 01:21:16 PM PST 23 166171057 ps
T795 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.14417049002531871296452114736915321686071668256165754659997505832574574392545 Nov 22 01:22:54 PM PST 23 Nov 22 01:31:54 PM PST 23 42305619653 ps
T796 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.1980347256926081547487536655518175738053831500739308263741012364283422148607 Nov 22 01:22:01 PM PST 23 Nov 22 01:22:10 PM PST 23 166171057 ps
T797 /workspace/coverage/default/2.sram_ctrl_executable.94793268114377114657518359847755171276732431238019939971879531755434666279014 Nov 22 01:21:50 PM PST 23 Nov 22 01:34:10 PM PST 23 23162112088 ps
T798 /workspace/coverage/default/33.sram_ctrl_multiple_keys.66199559407240464116415393617885577744067287214908858149374749782809656154071 Nov 22 01:22:19 PM PST 23 Nov 22 01:33:59 PM PST 23 21947461091 ps
T799 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.48934126875089417922540553653383632612435220211953626077441612815203999136370 Nov 22 01:21:22 PM PST 23 Nov 22 01:21:33 PM PST 23 166171057 ps
T800 /workspace/coverage/default/33.sram_ctrl_stress_all.50693594166069433349667626457425129305586475398550601882138746181231857170639 Nov 22 01:22:42 PM PST 23 Nov 22 02:14:15 PM PST 23 121463254244 ps
T801 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.88561664911560483681431121203465115449917075427347680459944487919040209671938 Nov 22 01:21:58 PM PST 23 Nov 22 01:27:59 PM PST 23 6491370455 ps
T802 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.100376085826933028172977718233196215759210850713939604963374341388960354658690 Nov 22 01:22:40 PM PST 23 Nov 22 01:31:41 PM PST 23 42305619653 ps
T803 /workspace/coverage/default/46.sram_ctrl_mem_walk.15466968699400393918382044724536848751447465074209323885392213653893473661211 Nov 22 01:23:14 PM PST 23 Nov 22 01:23:28 PM PST 23 590810517 ps
T804 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.750726238201773112868081618269998046415777230905376076281628372564614905101 Nov 22 01:22:49 PM PST 23 Nov 22 01:32:57 PM PST 23 4471404472 ps
T805 /workspace/coverage/default/3.sram_ctrl_max_throughput.6755474641088016919451192744583140257212865248369548404264843654387710132036 Nov 22 01:22:31 PM PST 23 Nov 22 01:24:21 PM PST 23 209242141 ps
T806 /workspace/coverage/default/40.sram_ctrl_multiple_keys.12258485658873560493724587827199194145407398860285885607979881725011056509346 Nov 22 01:22:44 PM PST 23 Nov 22 01:32:54 PM PST 23 21947461091 ps
T807 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.47108113471646906402218163036120442095927677697565694481955708109346474255182 Nov 22 01:22:19 PM PST 23 Nov 22 01:28:30 PM PST 23 6491370455 ps
T808 /workspace/coverage/default/26.sram_ctrl_lc_escalation.81739448994769522940815919931829558910139278932362931001729786774332723823538 Nov 22 01:22:40 PM PST 23 Nov 22 01:22:53 PM PST 23 985753786 ps
T809 /workspace/coverage/default/13.sram_ctrl_partial_access.10177835613722140044783150520485194852243306574783121143104597475602301238033 Nov 22 01:21:35 PM PST 23 Nov 22 01:21:57 PM PST 23 445204539 ps
T810 /workspace/coverage/default/41.sram_ctrl_executable.34491213285703825030823342922386793951252829076850383975944971966824565451928 Nov 22 01:22:51 PM PST 23 Nov 22 01:35:12 PM PST 23 23162112088 ps
T811 /workspace/coverage/default/48.sram_ctrl_lc_escalation.87723059032362622690864485815245527864369711916366693167585586152947547251063 Nov 22 01:23:21 PM PST 23 Nov 22 01:23:38 PM PST 23 985753786 ps
T812 /workspace/coverage/default/6.sram_ctrl_mem_walk.5911602860308587051390797758719554071899052118963352774869780093227425479028 Nov 22 01:21:17 PM PST 23 Nov 22 01:21:24 PM PST 23 590810517 ps
T813 /workspace/coverage/default/38.sram_ctrl_partial_access.7304163662256428449555306918776343215948866847643183339541429068439486406498 Nov 22 01:22:34 PM PST 23 Nov 22 01:22:52 PM PST 23 445204539 ps
T814 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.109442701990148307154655538657264858216826371011370132383979323872250634534158 Nov 22 01:22:32 PM PST 23 Nov 22 01:22:40 PM PST 23 166171057 ps
T815 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.16274004261799692852930414100667737568717663646997113870736004339023327740720 Nov 22 01:22:42 PM PST 23 Nov 22 01:22:52 PM PST 23 166171057 ps
T816 /workspace/coverage/default/21.sram_ctrl_executable.109346962945522177357223374122393354029911836165803090737333205945195750005606 Nov 22 01:21:54 PM PST 23 Nov 22 01:35:09 PM PST 23 23162112088 ps
T817 /workspace/coverage/default/15.sram_ctrl_bijection.91603864804516889946022657933481296393328664531852114304839583310459484025769 Nov 22 01:21:57 PM PST 23 Nov 22 01:23:23 PM PST 23 9249473390 ps
T818 /workspace/coverage/default/47.sram_ctrl_smoke.40945781337219776358067734483493949936861199943262286914765131363193550257285 Nov 22 01:23:20 PM PST 23 Nov 22 01:23:43 PM PST 23 427865392 ps
T819 /workspace/coverage/default/3.sram_ctrl_partial_access.67159750566313413841843390613611481498127892983067505115039822991657277224216 Nov 22 01:20:52 PM PST 23 Nov 22 01:21:10 PM PST 23 445204539 ps
T820 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.22251018936695658722309689048376031784427711703137884692166855274226151905306 Nov 22 01:21:59 PM PST 23 Nov 22 01:22:07 PM PST 23 166171057 ps
T821 /workspace/coverage/default/46.sram_ctrl_stress_all.53982174468210043499842449375259347478251207990907048339660018727182702401832 Nov 22 01:23:07 PM PST 23 Nov 22 02:24:37 PM PST 23 121463254244 ps
T822 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.38287368371536759719237716905514664913565274815754844348185897835387143015718 Nov 22 01:21:50 PM PST 23 Nov 22 01:35:07 PM PST 23 4471404472 ps
T823 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.81832978110922828766861885344702076803132209652862901812568038265497178350428 Nov 22 01:21:25 PM PST 23 Nov 22 01:27:34 PM PST 23 6491370455 ps
T824 /workspace/coverage/default/7.sram_ctrl_stress_all.28762069131046477770771762995492867668790573870458052888384891740867119256904 Nov 22 01:21:18 PM PST 23 Nov 22 02:27:27 PM PST 23 121463254244 ps
T825 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.102331998893834818700692746509910011232435630458320835278281173528178574029785 Nov 22 01:22:35 PM PST 23 Nov 22 01:43:48 PM PST 23 624328106 ps
T826 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.21604106477201952070399193998285670358864892911229437644761230546283052210554 Nov 22 01:24:13 PM PST 23 Nov 22 01:29:55 PM PST 23 6491370455 ps
T35 /workspace/coverage/default/3.sram_ctrl_sec_cm.90018739862516877329874270694872479676441507245956452353135153887618078208937 Nov 22 01:21:54 PM PST 23 Nov 22 01:22:02 PM PST 23 216402798 ps
T827 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.45349818723076232925598691574082139909973811951422266286092803972068869566066 Nov 22 01:21:33 PM PST 23 Nov 22 01:42:23 PM PST 23 624328106 ps
T828 /workspace/coverage/default/20.sram_ctrl_alert_test.71880384621748407562544915762371843102681347484233602601090319965484397853223 Nov 22 01:21:48 PM PST 23 Nov 22 01:21:54 PM PST 23 16600825 ps
T829 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.39424714365573770662526053318245988502451318607543204262603981100342406548192 Nov 22 01:22:48 PM PST 23 Nov 22 01:23:05 PM PST 23 166171057 ps
T830 /workspace/coverage/default/26.sram_ctrl_partial_access.29025617488157645871125297708213814008505587821126439041252255254707109604549 Nov 22 01:23:32 PM PST 23 Nov 22 01:23:56 PM PST 23 445204539 ps
T831 /workspace/coverage/default/6.sram_ctrl_ram_cfg.46349811661519030923466520701049093232803646150408893049030623872810625493188 Nov 22 01:21:20 PM PST 23 Nov 22 01:21:24 PM PST 23 40672061 ps
T832 /workspace/coverage/default/18.sram_ctrl_ram_cfg.51059367189292262110108058086184725852909759341371879776505211686023955429239 Nov 22 01:21:45 PM PST 23 Nov 22 01:21:52 PM PST 23 40672061 ps
T833 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.62220971276999120234531364785433479875394905998326791909685912450283431600989 Nov 22 01:22:05 PM PST 23 Nov 22 01:22:13 PM PST 23 166171057 ps
T834 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.53769950094295375819207509616024577470094719417416263722193460289390467052425 Nov 22 01:21:30 PM PST 23 Nov 22 01:42:30 PM PST 23 624328106 ps
T835 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.72351756966655140523783188537745026609092249271091996777488592491633421297252 Nov 22 01:22:23 PM PST 23 Nov 22 01:36:36 PM PST 23 4471404472 ps
T836 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.22534253794458489173011319354460174052661384204421188777275505669112454983981 Nov 22 01:22:30 PM PST 23 Nov 22 01:22:38 PM PST 23 166171057 ps
T837 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.62529496169039047602412184840970113905405509616430741556472159832323002779057 Nov 22 01:23:19 PM PST 23 Nov 22 01:48:12 PM PST 23 624328106 ps
T838 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.77265217493931473716201686606955649378544704298666139754715543161926047258245 Nov 22 01:24:07 PM PST 23 Nov 22 01:30:02 PM PST 23 6491370455 ps
T839 /workspace/coverage/default/18.sram_ctrl_bijection.9728140080238061126875884068275791666014629565111995224045911103306107003528 Nov 22 01:21:46 PM PST 23 Nov 22 01:23:12 PM PST 23 9249473390 ps
T840 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.14582673230296905898051161416450768878203093757622752429164165915461624906986 Nov 22 01:22:54 PM PST 23 Nov 22 01:36:04 PM PST 23 4471404472 ps
T841 /workspace/coverage/default/0.sram_ctrl_stress_all.42570385845434014528322010843689705894502004247752466480837443023324630326267 Nov 22 01:21:30 PM PST 23 Nov 22 02:14:12 PM PST 23 121463254244 ps
T842 /workspace/coverage/default/15.sram_ctrl_stress_all.9360838981923430215292335240639610711851900166076719291296038606036213789415 Nov 22 01:21:39 PM PST 23 Nov 22 02:15:39 PM PST 23 121463254244 ps
T843 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.114475108214266024144170532478041371290125723232701870271739532005347351838319 Nov 22 01:22:46 PM PST 23 Nov 22 01:38:13 PM PST 23 624328106 ps
T844 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.59708936186981864824136457134133140573034361233443271437023536298986028730744 Nov 22 01:22:52 PM PST 23 Nov 22 01:31:58 PM PST 23 42305619653 ps
T845 /workspace/coverage/default/47.sram_ctrl_mem_walk.78862082606665351667700123732735525477218136396127346822843702713969158077996 Nov 22 01:23:20 PM PST 23 Nov 22 01:23:35 PM PST 23 590810517 ps
T846 /workspace/coverage/default/5.sram_ctrl_regwen.76575072153195401233194152486846218751181025080863995781266481062607098412356 Nov 22 01:21:21 PM PST 23 Nov 22 01:29:07 PM PST 23 19383553031 ps
T847 /workspace/coverage/default/22.sram_ctrl_stress_all.106020343157674789080050407748154920336572218845993801591545697351487844609558 Nov 22 01:22:53 PM PST 23 Nov 22 02:14:08 PM PST 23 121463254244 ps
T848 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.22127350784523170401503459663684744899824533640004891232743172146659845462197 Nov 22 01:23:11 PM PST 23 Nov 22 01:24:56 PM PST 23 237420487 ps
T849 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.110497778170917441657276488549948018703895273929777106595607362586271361461311 Nov 22 01:22:03 PM PST 23 Nov 22 01:28:07 PM PST 23 6491370455 ps
T850 /workspace/coverage/default/2.sram_ctrl_lc_escalation.82952622582655739324410474817945075906226515194210661551792286223297883088862 Nov 22 01:22:21 PM PST 23 Nov 22 01:22:30 PM PST 23 985753786 ps
T851 /workspace/coverage/default/35.sram_ctrl_multiple_keys.102072246504059541037868422005406045608962049124403184226794568159836268653101 Nov 22 01:22:31 PM PST 23 Nov 22 01:36:18 PM PST 23 21947461091 ps
T852 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4820659454883046737869942918410880640381327967671834364591452796694246109309 Nov 22 01:23:13 PM PST 23 Nov 22 01:25:01 PM PST 23 237420487 ps
T853 /workspace/coverage/default/9.sram_ctrl_multiple_keys.61215513863061341689039302207107177828356106798290240320758785037811078749705 Nov 22 01:21:31 PM PST 23 Nov 22 01:35:39 PM PST 23 21947461091 ps
T854 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.13764800011716197698539528365256024385031003850726376700372287973810442928940 Nov 22 01:21:33 PM PST 23 Nov 22 01:21:43 PM PST 23 166171057 ps
T855 /workspace/coverage/default/23.sram_ctrl_stress_all.52070791235600633497154068306967930027790899749912937765655760285582302253145 Nov 22 01:22:01 PM PST 23 Nov 22 02:19:04 PM PST 23 121463254244 ps
T856 /workspace/coverage/default/48.sram_ctrl_regwen.4694090995133778560943152455615370588741997027654421467119105883561003970662 Nov 22 01:23:33 PM PST 23 Nov 22 01:32:47 PM PST 23 19383553031 ps
T857 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.7909056555143456118223271645164128975816695203205498652619767357139711017363 Nov 22 01:22:04 PM PST 23 Nov 22 01:40:17 PM PST 23 624328106 ps
T858 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1906671492047171774867015152152532660194828478658898651143510021526297041782 Nov 22 01:22:12 PM PST 23 Nov 22 01:40:49 PM PST 23 624328106 ps
T859 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.12479697714721868190479839705827581993675011301953390807745092886270682781867 Nov 22 01:21:46 PM PST 23 Nov 22 01:35:18 PM PST 23 4471404472 ps
T860 /workspace/coverage/default/29.sram_ctrl_multiple_keys.93445375608957181691842287320470800223408091037366255365038261728687606386934 Nov 22 01:22:19 PM PST 23 Nov 22 01:35:11 PM PST 23 21947461091 ps
T861 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.92211947135522550392152630487936040063724653830320843157100705426841197496069 Nov 22 01:22:11 PM PST 23 Nov 22 01:28:02 PM PST 23 6491370455 ps
T862 /workspace/coverage/default/28.sram_ctrl_multiple_keys.101455597974810602425995611681992568350488905525716371398228553372793860601568 Nov 22 01:23:00 PM PST 23 Nov 22 01:34:01 PM PST 23 21947461091 ps
T863 /workspace/coverage/default/14.sram_ctrl_stress_all.60208606097386086684209088521857528112778447296708624575272214355109914250890 Nov 22 01:21:38 PM PST 23 Nov 22 02:13:19 PM PST 23 121463254244 ps
T864 /workspace/coverage/default/19.sram_ctrl_alert_test.51788294147936980998851524000119956578374809612948511374039148538705787426953 Nov 22 01:21:48 PM PST 23 Nov 22 01:21:54 PM PST 23 16600825 ps
T865 /workspace/coverage/default/38.sram_ctrl_mem_walk.22360764403301644660255531024136442363991581198998418259876073860111171863778 Nov 22 01:22:35 PM PST 23 Nov 22 01:22:45 PM PST 23 590810517 ps
T866 /workspace/coverage/default/49.sram_ctrl_partial_access.58497730615046546142739730002011053548229101203509707749451909860884494950743 Nov 22 01:23:39 PM PST 23 Nov 22 01:24:00 PM PST 23 445204539 ps
T867 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.51067229256599184505604681155853168134314733595496670260600485632475424859302 Nov 22 01:21:10 PM PST 23 Nov 22 01:27:07 PM PST 23 6491370455 ps
T868 /workspace/coverage/default/16.sram_ctrl_lc_escalation.41076834867122674005209344390924928037198562516821546784242880326617208111146 Nov 22 01:22:16 PM PST 23 Nov 22 01:22:25 PM PST 23 985753786 ps
T869 /workspace/coverage/default/40.sram_ctrl_stress_all.92910286816818715007728132103908394824428528942078501459506430091164094859162 Nov 22 01:22:40 PM PST 23 Nov 22 02:15:01 PM PST 23 121463254244 ps
T870 /workspace/coverage/default/30.sram_ctrl_alert_test.42716853479593261098580305445395997404190190288626340074637123742798868512778 Nov 22 01:22:42 PM PST 23 Nov 22 01:22:50 PM PST 23 16600825 ps
T871 /workspace/coverage/default/42.sram_ctrl_smoke.105107523433331636740378296896184080295016604340040918766181362691111894917124 Nov 22 01:23:44 PM PST 23 Nov 22 01:24:03 PM PST 23 427865392 ps
T872 /workspace/coverage/default/28.sram_ctrl_smoke.59123655645937336625412507304573813468148404748144096724305021291029007637101 Nov 22 01:22:00 PM PST 23 Nov 22 01:22:17 PM PST 23 427865392 ps
T873 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.42588906523244881160578604965495533415738011137157864469063351701556311291152 Nov 22 01:21:56 PM PST 23 Nov 22 01:39:18 PM PST 23 624328106 ps
T874 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.46997020474322374877447972280918510062712098529169811757035658126175299952273 Nov 22 01:21:36 PM PST 23 Nov 22 01:30:35 PM PST 23 42305619653 ps
T875 /workspace/coverage/default/49.sram_ctrl_regwen.111848954832815694923272918629698020097036665528327820742607755983216377758498 Nov 22 01:23:40 PM PST 23 Nov 22 01:33:40 PM PST 23 19383553031 ps
T876 /workspace/coverage/default/13.sram_ctrl_lc_escalation.11770980817098740344192368344571038357180599469533347190363401592032257910372 Nov 22 01:21:55 PM PST 23 Nov 22 01:22:08 PM PST 23 985753786 ps
T877 /workspace/coverage/default/31.sram_ctrl_regwen.38964484276615915237315991827491519459532187448286639800404315383332851959651 Nov 22 01:22:23 PM PST 23 Nov 22 01:32:35 PM PST 23 19383553031 ps
T878 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.35055463217127148148857119907080821397615838283628509306826008521422817451140 Nov 22 01:22:16 PM PST 23 Nov 22 01:31:13 PM PST 23 42305619653 ps
T879 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.70434836700295125973024175335339584540482820044753010895244845461977082391578 Nov 22 01:21:51 PM PST 23 Nov 22 01:31:01 PM PST 23 42305619653 ps
T880 /workspace/coverage/default/4.sram_ctrl_bijection.21943164358629660176046959346908482520726709677306800041606257617383097845478 Nov 22 01:21:53 PM PST 23 Nov 22 01:23:21 PM PST 23 9249473390 ps
T881 /workspace/coverage/default/36.sram_ctrl_max_throughput.21812162824857780218590841989776090797249153351815840570171456301834743651505 Nov 22 01:22:35 PM PST 23 Nov 22 01:24:02 PM PST 23 209242141 ps
T882 /workspace/coverage/default/22.sram_ctrl_executable.53107608293228398825969024305637552740974284708315816142636901183959172710973 Nov 22 01:22:53 PM PST 23 Nov 22 01:35:15 PM PST 23 23162112088 ps
T883 /workspace/coverage/default/17.sram_ctrl_lc_escalation.62071036621695895190201306694704766830790414009149291717504924799124282130050 Nov 22 01:22:52 PM PST 23 Nov 22 01:23:15 PM PST 23 985753786 ps
T884 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.111906826186446590067947010435964210965517161332928240532762976412391006159143 Nov 22 01:22:54 PM PST 23 Nov 22 01:23:10 PM PST 23 166171057 ps
T885 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.67153761160578804632134823821817324137960030686327270864636546973494354808008 Nov 22 01:22:40 PM PST 23 Nov 22 01:34:57 PM PST 23 4471404472 ps
T886 /workspace/coverage/default/42.sram_ctrl_multiple_keys.114392471580682171790527669478343165183651305134291616685340191300948155087916 Nov 22 01:22:59 PM PST 23 Nov 22 01:35:11 PM PST 23 21947461091 ps
T887 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.52198656579954140436613595283778747906094485706062031237091449206326738432012 Nov 22 01:22:37 PM PST 23 Nov 22 01:44:47 PM PST 23 624328106 ps
T888 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.23945994534801221693020966328238164409592974179898272291110653916471235008671 Nov 22 01:21:14 PM PST 23 Nov 22 01:27:10 PM PST 23 6491370455 ps
T889 /workspace/coverage/default/15.sram_ctrl_lc_escalation.55712891620812098623027123419619677409140789540665561824147314554666594682356 Nov 22 01:21:35 PM PST 23 Nov 22 01:21:53 PM PST 23 985753786 ps
T890 /workspace/coverage/default/41.sram_ctrl_regwen.27851247728351297242413279217662358462029428678966569121009783301467388707501 Nov 22 01:23:04 PM PST 23 Nov 22 01:32:25 PM PST 23 19383553031 ps
T891 /workspace/coverage/default/30.sram_ctrl_regwen.19563222813730350586617621394072789511432722273562758979585873136252675141589 Nov 22 01:22:36 PM PST 23 Nov 22 01:30:55 PM PST 23 19383553031 ps
T892 /workspace/coverage/default/0.sram_ctrl_ram_cfg.1477827698200789526909523852237566627122907642215976744960545875469382650862 Nov 22 01:20:53 PM PST 23 Nov 22 01:21:00 PM PST 23 40672061 ps
T893 /workspace/coverage/default/10.sram_ctrl_smoke.66363172091608892694837861189932473834187081098052177767034039791412045346232 Nov 22 01:21:22 PM PST 23 Nov 22 01:21:37 PM PST 23 427865392 ps
T894 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.48219836865544681991865627965046317702651748044311684427237537950507776953998 Nov 22 01:21:52 PM PST 23 Nov 22 01:23:30 PM PST 23 237420487 ps
T895 /workspace/coverage/default/28.sram_ctrl_alert_test.58602967464169964596623410230023422027158434291091059774900796464195749252207 Nov 22 01:22:05 PM PST 23 Nov 22 01:22:11 PM PST 23 16600825 ps
T896 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.65149939642701177838102629993834243476956089440431585632943955981393692358083 Nov 22 01:23:22 PM PST 23 Nov 22 01:32:44 PM PST 23 42305619653 ps
T897 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.56662053032729541331180685530730310515963357424191292307072348521776650295960 Nov 22 01:21:57 PM PST 23 Nov 22 01:23:34 PM PST 23 237420487 ps
T898 /workspace/coverage/default/25.sram_ctrl_partial_access.57762249797376042914293698209315901698510146616011037583407753993974630195843 Nov 22 01:22:39 PM PST 23 Nov 22 01:22:59 PM PST 23 445204539 ps
T899 /workspace/coverage/default/2.sram_ctrl_alert_test.62653208073682573185892534357099773147630468185354882140386442747943171200266 Nov 22 01:20:54 PM PST 23 Nov 22 01:20:59 PM PST 23 16600825 ps
T900 /workspace/coverage/default/22.sram_ctrl_ram_cfg.34901146269398373628592926690924257587663475134627277866987319316019863205487 Nov 22 01:22:23 PM PST 23 Nov 22 01:22:26 PM PST 23 40672061 ps
T901 /workspace/coverage/default/7.sram_ctrl_alert_test.60139267486302404347584345701951727311383026523914554390141042192333310784473 Nov 22 01:21:18 PM PST 23 Nov 22 01:21:20 PM PST 23 16600825 ps
T902 /workspace/coverage/default/38.sram_ctrl_multiple_keys.36782808639232374132315391901565691275527869732894476263578684379888566013066 Nov 22 01:22:35 PM PST 23 Nov 22 01:32:47 PM PST 23 21947461091 ps
T903 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.105196375941325852678906279782028807544098947848917007300114080056251594707717 Nov 22 01:21:22 PM PST 23 Nov 22 01:42:26 PM PST 23 624328106 ps
T904 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.19929713051305737355352417141507150167467018617859428176736065610991294813384 Nov 22 01:22:48 PM PST 23 Nov 22 01:43:19 PM PST 23 624328106 ps
T905 /workspace/coverage/default/17.sram_ctrl_executable.91575050799390135557249665496349166810490958723916188809187726150568905293838 Nov 22 01:21:55 PM PST 23 Nov 22 01:33:27 PM PST 23 23162112088 ps
T906 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.44693390756000589728867917356156251924930870169070542367202107694008094107543 Nov 22 01:22:17 PM PST 23 Nov 22 01:22:22 PM PST 23 166171057 ps
T907 /workspace/coverage/default/24.sram_ctrl_lc_escalation.15519132094590431357526690611229138699763862301084716311519304601082618703875 Nov 22 01:22:18 PM PST 23 Nov 22 01:22:27 PM PST 23 985753786 ps
T908 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.113498988349223741167586978370699879625492948966451511252461385811285698010661 Nov 22 01:23:23 PM PST 23 Nov 22 01:25:19 PM PST 23 237420487 ps
T909 /workspace/coverage/default/49.sram_ctrl_max_throughput.16743591641112034560081614228441242277471367728081633477408996240380023382182 Nov 22 01:24:17 PM PST 23 Nov 22 01:25:53 PM PST 23 209242141 ps
T910 /workspace/coverage/default/23.sram_ctrl_bijection.85454447141973971052888751494180590453873148496160262706764675172282771246829 Nov 22 01:22:11 PM PST 23 Nov 22 01:23:36 PM PST 23 9249473390 ps
T911 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.23888212470151803222075057410118165421199974939325542747768724574156146312387 Nov 22 01:21:04 PM PST 23 Nov 22 01:22:58 PM PST 23 237420487 ps
T912 /workspace/coverage/default/16.sram_ctrl_ram_cfg.101964114374607823675480393261376739251172461384729754663772049843064148775899 Nov 22 01:21:40 PM PST 23 Nov 22 01:21:47 PM PST 23 40672061 ps
T913 /workspace/coverage/default/19.sram_ctrl_bijection.96353594786783526303627679987569574547116864642572552865166765731803603594050 Nov 22 01:21:39 PM PST 23 Nov 22 01:23:10 PM PST 23 9249473390 ps
T914 /workspace/coverage/default/38.sram_ctrl_max_throughput.18342712148109825675989513267830945708715324240187419561037160173439670824650 Nov 22 01:23:13 PM PST 23 Nov 22 01:25:03 PM PST 23 209242141 ps
T915 /workspace/coverage/default/16.sram_ctrl_smoke.114517560193747830872824350199539694834347346766866417795547220869858962520261 Nov 22 01:21:57 PM PST 23 Nov 22 01:22:13 PM PST 23 427865392 ps
T916 /workspace/coverage/default/31.sram_ctrl_smoke.24886929557943644580275989602934648888053886256782835391982286231730729214419 Nov 22 01:22:25 PM PST 23 Nov 22 01:22:41 PM PST 23 427865392 ps
T917 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.48141037378607230231127326729417631484600290717465877257236560469631153408555 Nov 22 01:22:18 PM PST 23 Nov 22 01:31:02 PM PST 23 42305619653 ps
T918 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.83887632815976751157831823402889388460388218462482823374113481564565805529564 Nov 22 01:23:11 PM PST 23 Nov 22 01:23:22 PM PST 23 166171057 ps
T919 /workspace/coverage/default/15.sram_ctrl_executable.53109468032943466214160597510344816076365816539536273104422329153052756823036 Nov 22 01:22:00 PM PST 23 Nov 22 01:35:47 PM PST 23 23162112088 ps
T920 /workspace/coverage/default/43.sram_ctrl_smoke.39018246115942262952029611944492264685830676277662363808232053016008839576384 Nov 22 01:23:05 PM PST 23 Nov 22 01:23:28 PM PST 23 427865392 ps
T921 /workspace/coverage/default/29.sram_ctrl_regwen.37679145472523666571799787572414993857439498120255072803614233663751156802808 Nov 22 01:22:19 PM PST 23 Nov 22 01:30:57 PM PST 23 19383553031 ps
T922 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.10846161846055321170062633115153549547081931061567017687853609807646967961407 Nov 22 01:21:49 PM PST 23 Nov 22 01:41:57 PM PST 23 624328106 ps
T923 /workspace/coverage/default/39.sram_ctrl_stress_all.12344276389793354467350630405401572417776774706497372888118456775654843237961 Nov 22 01:22:33 PM PST 23 Nov 22 02:18:44 PM PST 23 121463254244 ps
T924 /workspace/coverage/default/16.sram_ctrl_bijection.1847812102232623498666662265582957592214618725025800866507778629621498026189 Nov 22 01:22:48 PM PST 23 Nov 22 01:24:22 PM PST 23 9249473390 ps
T925 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.66677470042594116491342412618619656622163038911685073864277221715324330957740 Nov 22 01:21:29 PM PST 23 Nov 22 01:21:39 PM PST 23 166171057 ps
T926 /workspace/coverage/default/20.sram_ctrl_stress_all.97141024816147043238977155064032059663240454008700431492471871691132950664492 Nov 22 01:22:01 PM PST 23 Nov 22 02:23:36 PM PST 23 121463254244 ps
T927 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.55031850908518188580003611162846253625983512526461652057230589159530174017027 Nov 22 01:21:25 PM PST 23 Nov 22 01:41:49 PM PST 23 624328106 ps
T928 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.102295413340208317695389682110370931114663274081649914872094214557915803699471 Nov 22 01:22:55 PM PST 23 Nov 22 01:41:51 PM PST 23 624328106 ps
T929 /workspace/coverage/default/21.sram_ctrl_multiple_keys.114428426342734089422113678215040696782797408169662995091057143238381278500526 Nov 22 01:21:49 PM PST 23 Nov 22 01:36:00 PM PST 23 21947461091 ps
T930 /workspace/coverage/default/6.sram_ctrl_max_throughput.73568623885273730450079797407022815852185794254575124873183461438233075013677 Nov 22 01:21:09 PM PST 23 Nov 22 01:22:38 PM PST 23 209242141 ps
T931 /workspace/coverage/default/40.sram_ctrl_alert_test.3006556912771304803541505270527442674910501780107097128311277880993041714692 Nov 22 01:24:14 PM PST 23 Nov 22 01:24:19 PM PST 23 16600825 ps
T932 /workspace/coverage/default/45.sram_ctrl_stress_all.107385773535770377292320875776881761250274955956800216519921936701003345078482 Nov 22 01:22:54 PM PST 23 Nov 22 02:22:15 PM PST 23 121463254244 ps
T933 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.84958142507378979241500852145269314614198946334721880295178144314699308487622 Nov 22 01:22:50 PM PST 23 Nov 22 01:23:07 PM PST 23 166171057 ps
T934 /workspace/coverage/default/8.sram_ctrl_ram_cfg.12467526404756558329817018159866921215078504423238105137759917260922796437263 Nov 22 01:21:32 PM PST 23 Nov 22 01:21:39 PM PST 23 40672061 ps
T935 /workspace/coverage/default/20.sram_ctrl_lc_escalation.53904776118985137970736001636137440608364920014769311809502660083098389837554 Nov 22 01:21:43 PM PST 23 Nov 22 01:21:55 PM PST 23 985753786 ps
T936 /workspace/coverage/default/44.sram_ctrl_ram_cfg.62301990980825683801444063699305124082098091002182382865046166447679561457890 Nov 22 01:22:45 PM PST 23 Nov 22 01:22:57 PM PST 23 40672061 ps
T937 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.67335005843994664961113096364353396711013030666178967429650266259298663071024 Nov 22 01:21:45 PM PST 23 Nov 22 01:27:45 PM PST 23 6491370455 ps
T938 /workspace/coverage/default/45.sram_ctrl_regwen.94716447176236614191513850390416009169613407968547292427375379591151456481414 Nov 22 01:23:04 PM PST 23 Nov 22 01:32:12 PM PST 23 19383553031 ps
T939 /workspace/coverage/default/33.sram_ctrl_max_throughput.58546374884310576947340248932801967099554961846341558211024693409617010151173 Nov 22 01:22:47 PM PST 23 Nov 22 01:24:29 PM PST 23 209242141 ps
T940 /workspace/coverage/default/4.sram_ctrl_stress_all.69023538523044490748150602372808865639186165274740335903605399321661171464937 Nov 22 01:21:11 PM PST 23 Nov 22 02:12:05 PM PST 23 121463254244 ps
T941 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.61742706462012730919991591309961820843198669064029246904089595143826303729897 Nov 22 01:23:36 PM PST 23 Nov 22 01:39:49 PM PST 23 624328106 ps
T942 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.81021288788121998726500011542393088852093111862323357720533957145095455363990 Nov 22 01:22:46 PM PST 23 Nov 22 01:37:00 PM PST 23 4471404472 ps
T943 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.107572347637515943411782246231213108271236011683851837702617680829372039501926 Nov 22 01:23:15 PM PST 23 Nov 22 01:23:26 PM PST 23 166171057 ps
T944 /workspace/coverage/default/46.sram_ctrl_smoke.59838258602334242620094300027690951432127617583537225842041137878700011373814 Nov 22 01:23:07 PM PST 23 Nov 22 01:23:29 PM PST 23 427865392 ps
T945 /workspace/coverage/default/30.sram_ctrl_partial_access.26083631682655643198577306331909751048223474205500945505079701343028547901895 Nov 22 01:22:14 PM PST 23 Nov 22 01:22:31 PM PST 23 445204539 ps
T946 /workspace/coverage/default/37.sram_ctrl_mem_walk.46569213069461285162817537747235384020981531577352498961319495448346180156606 Nov 22 01:22:34 PM PST 23 Nov 22 01:22:45 PM PST 23 590810517 ps
T947 /workspace/coverage/default/12.sram_ctrl_mem_walk.62633630876266494338717751995137336238682631121011276589843416502124836962858 Nov 22 01:21:34 PM PST 23 Nov 22 01:21:49 PM PST 23 590810517 ps
T948 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.46785526050071926686252501473361068626393592026297346737313368510419505833929 Nov 22 01:21:29 PM PST 23 Nov 22 01:21:40 PM PST 23 166171057 ps
T949 /workspace/coverage/default/3.sram_ctrl_lc_escalation.66994285236785778622539584124901701101804409258609260929839803973519614106871 Nov 22 01:20:55 PM PST 23 Nov 22 01:21:07 PM PST 23 985753786 ps
T950 /workspace/coverage/default/31.sram_ctrl_stress_all.113516623056935847429676479844138386318176478545174517255353131331659848684764 Nov 22 01:22:24 PM PST 23 Nov 22 02:23:55 PM PST 23 121463254244 ps
T951 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.73103885418266391479221257643274312602695324380218314567267029749870552235663 Nov 22 01:22:47 PM PST 23 Nov 22 01:28:51 PM PST 23 6491370455 ps
T952 /workspace/coverage/default/21.sram_ctrl_smoke.88527670457682773418134953649272979339750641752728773930270147478151335265639 Nov 22 01:22:53 PM PST 23 Nov 22 01:23:18 PM PST 23 427865392 ps
T953 /workspace/coverage/default/43.sram_ctrl_executable.77573189432209705948476261367896162206063221392625883248034404843355420375184 Nov 22 01:22:52 PM PST 23 Nov 22 01:34:33 PM PST 23 23162112088 ps
T954 /workspace/coverage/default/28.sram_ctrl_ram_cfg.113816947058349316865769640655134204436988779489211379679602640095042525272192 Nov 22 01:23:23 PM PST 23 Nov 22 01:23:36 PM PST 23 40672061 ps
T955 /workspace/coverage/default/26.sram_ctrl_executable.25418432842965597840366745533953709618896521748716921966949465057789620268238 Nov 22 01:22:06 PM PST 23 Nov 22 01:35:13 PM PST 23 23162112088 ps
T956 /workspace/coverage/default/6.sram_ctrl_smoke.96251202528930839510132270991679513220184281661055215586190553087935650483782 Nov 22 01:21:53 PM PST 23 Nov 22 01:22:08 PM PST 23 427865392 ps
T957 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.19401918232351504331144778796044188168718921776615402763767290680932502680823 Nov 22 01:22:42 PM PST 23 Nov 22 01:22:51 PM PST 23 166171057 ps
T958 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.100262168089083653715369359869739734791012886361977802512417658366160562479327 Nov 22 01:22:08 PM PST 23 Nov 22 01:22:15 PM PST 23 166171057 ps
T959 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.76582240957513955320920515812871682730806969517157615611762132969880372990905 Nov 22 01:21:50 PM PST 23 Nov 22 01:24:22 PM PST 23 237420487 ps
T960 /workspace/coverage/default/40.sram_ctrl_lc_escalation.72206890255603464320825077773407530145930620324146991706685261076975818878670 Nov 22 01:22:39 PM PST 23 Nov 22 01:22:51 PM PST 23 985753786 ps
T961 /workspace/coverage/default/9.sram_ctrl_max_throughput.75474279717080779415140789650802406580397231318774810176646886775920145698688 Nov 22 01:21:32 PM PST 23 Nov 22 01:23:34 PM PST 23 209242141 ps
T962 /workspace/coverage/default/45.sram_ctrl_alert_test.45369581915407095638894691373732244188285161378697124282416062767503205722037 Nov 22 01:22:50 PM PST 23 Nov 22 01:23:04 PM PST 23 16600825 ps
T963 /workspace/coverage/default/30.sram_ctrl_ram_cfg.26558155975833782653535466823795475469807422658685915519128665965079107759550 Nov 22 01:22:28 PM PST 23 Nov 22 01:22:33 PM PST 23 40672061 ps
T964 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.74362740860346635986859140854800864953222183859748627561177665411982263228586 Nov 22 01:23:07 PM PST 23 Nov 22 01:39:14 PM PST 23 624328106 ps
T965 /workspace/coverage/default/3.sram_ctrl_bijection.75679624866838646689707607381781304499324220017302134359485518523600543711976 Nov 22 01:20:52 PM PST 23 Nov 22 01:22:16 PM PST 23 9249473390 ps
T966 /workspace/coverage/default/45.sram_ctrl_multiple_keys.110186172614317348691791567352971214549053800636405696018352760092577543021574 Nov 22 01:23:06 PM PST 23 Nov 22 01:36:55 PM PST 23 21947461091 ps
T967 /workspace/coverage/default/36.sram_ctrl_executable.14273650176880768722295117366771820869278180572942804965829715838438887036508 Nov 22 01:22:28 PM PST 23 Nov 22 01:33:10 PM PST 23 23162112088 ps
T968 /workspace/coverage/default/48.sram_ctrl_alert_test.58008089484804372551767363575703857777979844261619289273371231817522351303928 Nov 22 01:23:48 PM PST 23 Nov 22 01:23:57 PM PST 23 16600825 ps
T969 /workspace/coverage/default/49.sram_ctrl_ram_cfg.31559866005197482465697464711316346969136683212404548459166233189913180923536 Nov 22 01:23:48 PM PST 23 Nov 22 01:23:59 PM PST 23 40672061 ps
T970 /workspace/coverage/default/41.sram_ctrl_max_throughput.47914591265117104521569815796036825589083969327620788926700544030378637896795 Nov 22 01:23:58 PM PST 23 Nov 22 01:25:36 PM PST 23 209242141 ps
T971 /workspace/coverage/default/46.sram_ctrl_regwen.27167379681294147391166554061382511753193282599040634754652731750616617232826 Nov 22 01:23:19 PM PST 23 Nov 22 01:31:48 PM PST 23 19383553031 ps
T972 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.69819206460832710346729696302604204843889773269420574387068926832847262571980 Nov 22 01:22:27 PM PST 23 Nov 22 01:28:33 PM PST 23 6491370455 ps
T973 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.25398933373505817592617051625917210109925141312306791509192776257599248754516 Nov 22 01:21:09 PM PST 23 Nov 22 01:22:43 PM PST 23 237420487 ps
T974 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.49746362967807542156736647118714417937470891359009462363666859675958381374930 Nov 22 01:22:01 PM PST 23 Nov 22 01:38:59 PM PST 23 624328106 ps
T975 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.33561590909934377835522065292997824064731776961381281864509325435192773725234 Nov 22 01:22:34 PM PST 23 Nov 22 01:47:59 PM PST 23 624328106 ps
T976 /workspace/coverage/default/17.sram_ctrl_smoke.47872642094625117982458851826668886198942304430708508486649350521257839327880 Nov 22 01:22:43 PM PST 23 Nov 22 01:22:59 PM PST 23 427865392 ps
T977 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.54885340239896699726216967193861349636818309629989751100721770713945761779266 Nov 22 01:21:32 PM PST 23 Nov 22 01:43:34 PM PST 23 624328106 ps
T978 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.53666240741821479582149312139653054195205656500532930680340669002154338502262 Nov 22 01:22:04 PM PST 23 Nov 22 01:28:04 PM PST 23 6491370455 ps
T979 /workspace/coverage/default/12.sram_ctrl_partial_access.38935772364887323100128738322600650147034397919993328571963136403218255084918 Nov 22 01:22:47 PM PST 23 Nov 22 01:23:12 PM PST 23 445204539 ps
T980 /workspace/coverage/default/22.sram_ctrl_bijection.26762825465311560634885004407943158239189373892385629643784361854146155462791 Nov 22 01:21:57 PM PST 23 Nov 22 01:23:31 PM PST 23 9249473390 ps
T981 /workspace/coverage/default/31.sram_ctrl_bijection.13094114611336336255354568972446814458085717930528965784365576867104801457409 Nov 22 01:22:23 PM PST 23 Nov 22 01:23:49 PM PST 23 9249473390 ps
T982 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.34370102316908948492659853074304976369513694265038260593300549092267732115846 Nov 22 01:23:32 PM PST 23 Nov 22 01:44:24 PM PST 23 624328106 ps
T983 /workspace/coverage/default/43.sram_ctrl_bijection.107085100906894759430902772723655348279585872806151728968827212313167949844562 Nov 22 01:23:10 PM PST 23 Nov 22 01:24:42 PM PST 23 9249473390 ps
T984 /workspace/coverage/default/22.sram_ctrl_multiple_keys.94200518776035004485292260284537089585803803014889723154521631618802520437753 Nov 22 01:21:45 PM PST 23 Nov 22 01:34:40 PM PST 23 21947461091 ps
T985 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.91254959293074726312168495686570764731063359233046959074657873368846802406164 Nov 22 01:22:03 PM PST 23 Nov 22 01:23:31 PM PST 23 237420487 ps
T986 /workspace/coverage/default/0.sram_ctrl_max_throughput.33957541668400020569517363942578767592289877519388977039243942950027388773836 Nov 22 01:20:43 PM PST 23 Nov 22 01:21:58 PM PST 23 209242141 ps
T987 /workspace/coverage/default/20.sram_ctrl_multiple_keys.55965346759576978187713794508801670879012617291871930787451284328591529490578 Nov 22 01:22:03 PM PST 23 Nov 22 01:34:30 PM PST 23 21947461091 ps
T988 /workspace/coverage/default/39.sram_ctrl_multiple_keys.65005965898765840292398954796169988517080453589619280032004812507746012791325 Nov 22 01:22:34 PM PST 23 Nov 22 01:37:15 PM PST 23 21947461091 ps
T989 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.38327052525534646699345669085724032596427246435350178369673009574686052272377 Nov 22 01:22:45 PM PST 23 Nov 22 01:24:22 PM PST 23 237420487 ps
T990 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.98581217975778937554411116166464487229699562461513095682055171839521623911211 Nov 22 01:22:41 PM PST 23 Nov 22 01:32:17 PM PST 23 42305619653 ps
T991 /workspace/coverage/default/8.sram_ctrl_mem_walk.66995042027691610498694193948720571694814978450567914351181149589380036268996 Nov 22 01:21:29 PM PST 23 Nov 22 01:21:42 PM PST 23 590810517 ps
T992 /workspace/coverage/default/18.sram_ctrl_alert_test.115748097112794557432921841725862711577207794312791853585244987648468402611961 Nov 22 01:22:26 PM PST 23 Nov 22 01:22:32 PM PST 23 16600825 ps
T993 /workspace/coverage/default/12.sram_ctrl_smoke.98923680135182801760187372702703066548585812385306492058214701269664099637535 Nov 22 01:22:43 PM PST 23 Nov 22 01:23:01 PM PST 23 427865392 ps
T994 /workspace/coverage/default/14.sram_ctrl_alert_test.110956867298953943336076351425990844343770550031169108862225852772842251751363 Nov 22 01:21:52 PM PST 23 Nov 22 01:21:58 PM PST 23 16600825 ps
T995 /workspace/coverage/default/25.sram_ctrl_ram_cfg.45264526321721683960778969934740367020962446007579983458459911130612657942820 Nov 22 01:22:00 PM PST 23 Nov 22 01:22:07 PM PST 23 40672061 ps
T996 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.54036826517843256562121107866281309010498540414334919188373013897992372110336 Nov 22 01:22:31 PM PST 23 Nov 22 01:28:15 PM PST 23 6491370455 ps
T997 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.27654331729933046758561559545183098659917819580224003610188938306819700801942 Nov 22 01:21:55 PM PST 23 Nov 22 01:28:02 PM PST 23 6491370455 ps
T998 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.32763204743636201630839606011321713426683539616208660915130700152995996750488 Nov 22 01:21:29 PM PST 23 Nov 22 01:30:31 PM PST 23 42305619653 ps
T999 /workspace/coverage/default/39.sram_ctrl_lc_escalation.112853349799907891572780118769745020106534185141417406847447133964719569377329 Nov 22 01:22:55 PM PST 23 Nov 22 01:23:14 PM PST 23 985753786 ps
T1000 /workspace/coverage/default/22.sram_ctrl_partial_access.85526506594079661754157316178290349030028586666438602273408199647281839244470 Nov 22 01:22:43 PM PST 23 Nov 22 01:23:01 PM PST 23 445204539 ps
T1001 /workspace/coverage/default/9.sram_ctrl_mem_walk.11137661250705635192509490470595492533560128665407020809697260007344883440489 Nov 22 01:22:32 PM PST 23 Nov 22 01:22:42 PM PST 23 590810517 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%