SRAM_CTRL/RET Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.759m	644.260us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.640s	82.836us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.660s	28.487us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.980s	770.645us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.690s	16.449us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.490s	36.540us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.660s	28.487us	20	20	100.00
		sram_ctrl_csr_aliasing	0.690s	16.449us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.080s	2.741ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.070s	2.383ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.624m	17.145ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.731m	16.106ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.410m	10.394ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.888m	3.932ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.180s	2.153ms	44	50	88.00
V2	executable	sram_ctrl_executable	34.601m	74.241ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.309m	222.553us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.933m	130.627ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.426m	525.503us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.202m	306.171us	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.208m	93.001ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.800s	180.392us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.278h	410.070ms	41	50	82.00
V2	alert_test	sram_ctrl_alert_test	0.700s	13.116us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.320s	268.695us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.320s	268.695us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.640s	82.836us	5	5	100.00
		sram_ctrl_csr_rw	0.660s	28.487us	20	20	100.00
		sram_ctrl_csr_aliasing	0.690s	16.449us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.720s	51.129us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.640s	82.836us	5	5	100.00
		sram_ctrl_csr_rw	0.660s	28.487us	20	20	100.00
		sram_ctrl_csr_aliasing	0.690s	16.449us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.720s	51.129us	20	20	100.00
V2		TOTAL			724	740	97.84
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	12.670s	492.098us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.950s	1.002ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.160s	1.296ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.950s	1.002ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.160s	1.296ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.208m	93.001ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.660s	28.487us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.601m	74.241ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.601m	74.241ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.601m	74.241ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.180s	2.153ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	12.670s	492.098us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.759m	644.260us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.759m	644.260us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.601m	74.241ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.950s	1.002ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.180s	2.153ms	44	50	88.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.950s	1.002ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.950s	1.002ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.759m	644.260us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.950s	1.002ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.536h	886.866us	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	100.00	98.13	100.00	100.00	99.71	99.70	100.00

Failure Buckets

UVM_ERROR (sram_ctrl_scoreboard.sv:369) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*])

has 13 failures:

Test sram_ctrl_stress_all has 7 failures.

2.sram_ctrl_stress_all.40488676726529327721185719933338914295087618162551158454675729522619689646215
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 588978496 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 588978496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.sram_ctrl_stress_all.110440643732251135686442715964249628833284406955951776063428295646606547317873
Line 300, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 3490904716 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 3490904716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test sram_ctrl_lc_escalation has 6 failures.

3.sram_ctrl_lc_escalation.9231165871391099375042105277854453594617385847990128976349901185078445753521
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 806334106 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 806334106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.sram_ctrl_lc_escalation.9914194031013058298351045971793247108155371632929517483287035429639920224571
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 183227428 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 183227428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_executable has 1 failures.
  - 19.sram_ctrl_executable.100340911999319010117089319105692135390154481551457856134389246086468769539448
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 15196003135 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xb61a2a02
  UVM_INFO @ 15196003135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 2 failures.
  - 31.sram_ctrl_stress_all.37821883600923110716442742819588106993776608956355905166686719381847905863801
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 41655485775 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x1d92dc38
  UVM_INFO @ 41655485775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.sram_ctrl_stress_all.25082210439295608514651797576695998176116276351996258845788194480890510630418
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 87756405370 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x66f0736b
  UVM_INFO @ 87756405370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```