Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23057

1

T1

466

T2

22

T4

106

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8532	1			T1	104		T2	4		T4	29
values[0x0]	7632	1			T1	201		T2	15		T4	38
values[0x1]	7910	1			T1	161		T2	3		T4	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	520	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23554

1

T1

466

T2

22

T4

106

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	96	1			T1	1		T2	1		T8	1
valid_sources[0x01]	64	1			T1	1		T9	4		T8	1
valid_sources[0x02]	305	1			T17	3		T50	2		T64	190
valid_sources[0x03]	93	1			T1	2		T9	3		T7	1
valid_sources[0x04]	49	1			T9	4		T7	1		T14	1
valid_sources[0x05]	83	1			T1	3		T4	1		T9	2
valid_sources[0x06]	91	1			T1	1		T12	2		T18	2
valid_sources[0x07]	100	1			T1	1		T9	1		T17	2
valid_sources[0x08]	68	1			T1	4		T2	2		T14	1
valid_sources[0x09]	63	1			T1	1		T14	2		T17	1
valid_sources[0x0a]	71	1			T1	4		T4	7		T9	1
valid_sources[0x0b]	51	1			T1	2		T4	1		T9	2
valid_sources[0x0c]	79	1			T1	2		T9	1		T18	2
valid_sources[0x0d]	50	1			T1	1		T9	2		T12	1
valid_sources[0x0e]	77	1			T1	2		T18	1		T53	2
valid_sources[0x0f]	57	1			T4	1		T9	1		T14	2
valid_sources[0x10]	76	1			T1	1		T4	2		T9	2
valid_sources[0x11]	131	1			T1	2		T4	1		T14	2
valid_sources[0x12]	103	1			T1	2		T17	5		T18	5
valid_sources[0x13]	85	1			T1	2		T4	3		T9	1
valid_sources[0x14]	83	1			T1	1		T9	1		T17	3
valid_sources[0x15]	65	1			T1	4		T9	3		T14	4
valid_sources[0x16]	116	1			T1	4		T6	1		T17	3
valid_sources[0x17]	158	1			T1	1		T9	1		T6	1
valid_sources[0x18]	73	1			T1	3		T2	1		T4	1
valid_sources[0x19]	58	1			T1	1		T12	2		T18	6
valid_sources[0x1a]	244	1			T1	1		T9	1		T18	2
valid_sources[0x1b]	71	1			T1	4		T9	1		T7	2
valid_sources[0x1c]	61	1			T17	4		T18	3		T31	3
valid_sources[0x1d]	80	1			T1	1		T6	2		T12	2
valid_sources[0x1e]	80	1			T1	1		T17	7		T31	2
valid_sources[0x1f]	75	1			T1	3		T2	1		T9	1
valid_sources[0x20]	101	1			T1	1		T9	3		T7	1
valid_sources[0x21]	56	1			T1	3		T14	1		T18	1
valid_sources[0x22]	118	1			T1	4		T9	1		T14	5
valid_sources[0x23]	106	1			T1	3		T9	4		T6	1
valid_sources[0x24]	87	1			T1	1		T9	1		T14	1
valid_sources[0x25]	117	1			T1	3		T4	5		T9	1
valid_sources[0x26]	66	1			T7	1		T17	1		T50	1
valid_sources[0x27]	85	1			T9	3		T17	2		T18	1
valid_sources[0x28]	64	1			T1	1		T4	3		T9	1
valid_sources[0x29]	81	1			T1	3		T18	1		T31	10
valid_sources[0x2a]	88	1			T9	1		T17	2		T18	5
valid_sources[0x2b]	89	1			T1	2		T9	1		T17	2
valid_sources[0x2c]	59	1			T1	1		T9	1		T14	1
valid_sources[0x2d]	97	1			T1	2		T2	1		T9	1
valid_sources[0x2e]	58	1			T1	1		T17	1		T18	2
valid_sources[0x2f]	83	1			T1	4		T2	2		T9	1
valid_sources[0x30]	95	1			T1	1		T9	3		T6	1
valid_sources[0x31]	95	1			T1	1		T9	2		T18	2
valid_sources[0x32]	82	1			T6	1		T12	1		T17	4
valid_sources[0x33]	71	1			T1	4		T4	1		T14	1
valid_sources[0x34]	85	1			T1	3		T9	1		T17	4
valid_sources[0x35]	132	1			T1	4		T9	1		T12	1
valid_sources[0x36]	118	1			T1	3		T2	1		T17	2
valid_sources[0x37]	62	1			T1	2		T4	1		T9	3
valid_sources[0x38]	80	1			T1	3		T12	1		T14	2
valid_sources[0x39]	81	1			T1	2		T9	2		T7	1
valid_sources[0x3a]	71	1			T1	3		T9	2		T17	2
valid_sources[0x3b]	91	1			T1	2		T17	4		T31	6
valid_sources[0x3c]	80	1			T1	5		T9	4		T14	1
valid_sources[0x3d]	76	1			T1	2		T17	3		T31	3
valid_sources[0x3e]	70	1			T1	1		T4	3		T9	3
valid_sources[0x3f]	72	1			T1	1		T4	1		T9	2
valid_sources[0x40]	99	1			T1	2		T14	1		T17	1
valid_sources[0x41]	107	1			T9	2		T14	1		T17	1
valid_sources[0x42]	51	1			T9	1		T18	2		T50	1
valid_sources[0x43]	142	1			T1	1		T9	1		T7	1
valid_sources[0x44]	115	1			T1	2		T9	1		T17	4
valid_sources[0x45]	52	1			T1	1		T9	2		T17	2
valid_sources[0x46]	76	1			T1	1		T9	5		T18	5
valid_sources[0x47]	414	1			T14	1		T16	340		T18	1
valid_sources[0x48]	66	1			T9	1		T18	6		T31	4
valid_sources[0x49]	235	1			T1	3		T9	2		T18	2
valid_sources[0x4a]	59	1			T1	2		T9	1		T50	1
valid_sources[0x4b]	453	1			T1	1		T17	1		T18	9
valid_sources[0x4c]	61	1			T6	1		T17	3		T18	1
valid_sources[0x4d]	98	1			T9	2		T7	1		T14	1
valid_sources[0x4e]	90	1			T1	2		T17	4		T18	2
valid_sources[0x4f]	58	1			T1	1		T9	2		T7	1
valid_sources[0x50]	78	1			T1	3		T17	5		T18	4
valid_sources[0x51]	185	1			T1	2		T4	6		T9	2
valid_sources[0x52]	54	1			T1	2		T14	2		T17	2
valid_sources[0x53]	67	1			T1	5		T4	1		T9	2
valid_sources[0x54]	77	1			T1	4		T17	2		T18	1
valid_sources[0x55]	263	1			T1	2		T9	1		T17	2
valid_sources[0x56]	90	1			T1	3		T4	1		T9	3
valid_sources[0x57]	129	1			T1	1		T12	2		T14	2
valid_sources[0x58]	85	1			T1	1		T9	1		T17	2
valid_sources[0x59]	74	1			T1	2		T9	2		T12	1
valid_sources[0x5a]	134	1			T4	3		T9	4		T18	5
valid_sources[0x5b]	100	1			T1	5		T17	4		T18	1
valid_sources[0x5c]	80	1			T2	1		T9	1		T12	1
valid_sources[0x5d]	47	1			T1	3		T9	1		T18	7
valid_sources[0x5e]	383	1			T1	1		T9	3		T16	297
valid_sources[0x5f]	112	1			T1	3		T9	1		T12	1
valid_sources[0x60]	92	1			T1	2		T9	2		T17	2
valid_sources[0x61]	64	1			T1	1		T4	1		T9	3
valid_sources[0x62]	77	1			T9	2		T18	7		T31	2
valid_sources[0x63]	125	1			T1	3		T9	1		T14	2
valid_sources[0x64]	87	1			T1	2		T9	2		T14	1
valid_sources[0x65]	72	1			T1	2		T17	4		T31	2
valid_sources[0x66]	104	1			T1	1		T17	5		T18	2
valid_sources[0x67]	74	1			T2	1		T9	1		T17	1
valid_sources[0x68]	67	1			T9	1		T17	3		T18	2
valid_sources[0x69]	95	1			T1	3		T18	4		T51	2
valid_sources[0x6a]	131	1			T2	1		T9	4		T14	2
valid_sources[0x6b]	59	1			T1	1		T9	1		T7	1
valid_sources[0x6c]	89	1			T1	2		T4	1		T9	3
valid_sources[0x6d]	94	1			T1	3		T14	3		T17	1
valid_sources[0x6e]	81	1			T1	3		T4	1		T12	1
valid_sources[0x6f]	154	1			T1	2		T9	1		T7	1
valid_sources[0x70]	91	1			T1	3		T17	4		T18	4
valid_sources[0x71]	83	1			T1	3		T4	1		T6	1
valid_sources[0x72]	64	1			T1	3		T4	2		T9	1
valid_sources[0x73]	68	1			T1	5		T9	1		T17	2
valid_sources[0x74]	110	1			T1	4		T9	1		T14	1
valid_sources[0x75]	111	1			T1	1		T9	3		T12	4
valid_sources[0x76]	58	1			T1	1		T9	1		T18	5
valid_sources[0x77]	58	1			T1	2		T4	1		T17	2
valid_sources[0x78]	106	1			T1	1		T9	2		T7	1
valid_sources[0x79]	58	1			T1	4		T9	2		T14	1
valid_sources[0x7a]	50	1			T14	1		T17	4		T18	2
valid_sources[0x7b]	55	1			T1	2		T4	1		T9	2
valid_sources[0x7c]	58	1			T1	3		T9	4		T12	1
valid_sources[0x7d]	63	1			T1	1		T18	2		T31	1
valid_sources[0x7e]	115	1			T1	4		T9	1		T14	3
valid_sources[0x7f]	88	1			T1	4		T18	1		T31	1
valid_sources[0x80]	85	1			T1	1		T4	2		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8024

1

T1

104

T2

4

T4

29

values[0x0]

all_enables

biggest_size

7478

1

T1

201

T2

15

T4

38

values[0x1]

all_enables

biggest_size

7555

1

T1

161

T2

3

T4

39

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14535	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16617

1

T1

370

T2

68

T3

165

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14696	1			T1	111		T2	25		T3	83
values[0x0]	8031	1			T1	127		T2	29		T3	41
values[0x1]	8425	1			T1	136		T2	19		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19908

1

T1

371

T2

69

T3

165

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	87	1			T2	2		T21	1		T19	6
valid_sources[0x01]	358	1			T1	1		T9	2		T6	1
valid_sources[0x02]	130	1			T1	4		T2	3		T9	1
valid_sources[0x03]	122	1			T1	1		T4	1		T6	4
valid_sources[0x04]	91	1			T9	1		T7	2		T8	1
valid_sources[0x05]	162	1			T1	4		T4	2		T9	1
valid_sources[0x06]	87	1			T4	1		T9	1		T21	2
valid_sources[0x07]	66	1			T1	2		T4	1		T10	1
valid_sources[0x08]	98	1			T1	3		T4	3		T10	1
valid_sources[0x09]	93	1			T1	3		T9	1		T21	1
valid_sources[0x0a]	91	1			T1	1		T3	4		T4	1
valid_sources[0x0b]	112	1			T1	2		T4	1		T11	2
valid_sources[0x0c]	79	1			T1	2		T10	1		T11	1
valid_sources[0x0d]	233	1			T1	1		T2	3		T4	2
valid_sources[0x0e]	108	1			T1	3		T9	4		T8	1
valid_sources[0x0f]	132	1			T21	1		T65	12		T66	5
valid_sources[0x10]	79	1			T21	3		T29	2		T18	1
valid_sources[0x11]	66	1			T1	3		T4	1		T11	4
valid_sources[0x12]	237	1			T1	1		T7	2		T14	93
valid_sources[0x13]	109	1			T1	4		T7	1		T15	1
valid_sources[0x14]	122	1			T10	1		T7	3		T16	3
valid_sources[0x15]	114	1			T1	1		T13	3		T9	1
valid_sources[0x16]	80	1			T1	2		T10	2		T11	1
valid_sources[0x17]	129	1			T1	1		T9	1		T7	2
valid_sources[0x18]	98	1			T4	2		T10	2		T7	5
valid_sources[0x19]	116	1			T7	5		T8	3		T15	4
valid_sources[0x1a]	78	1			T1	1		T8	1		T15	2
valid_sources[0x1b]	76	1			T1	1		T4	2		T10	3
valid_sources[0x1c]	106	1			T1	4		T2	1		T4	1
valid_sources[0x1d]	108	1			T1	4		T4	2		T10	1
valid_sources[0x1e]	167	1			T1	2		T5	1		T4	1
valid_sources[0x1f]	75	1			T13	4		T9	1		T6	1
valid_sources[0x20]	67	1			T2	1		T3	3		T10	1
valid_sources[0x21]	82	1			T1	4		T2	1		T4	1
valid_sources[0x22]	101	1			T6	1		T7	8		T8	1
valid_sources[0x23]	87	1			T1	4		T4	1		T9	2
valid_sources[0x24]	130	1			T1	3		T11	4		T9	1
valid_sources[0x25]	134	1			T1	4		T5	1		T4	1
valid_sources[0x26]	121	1			T1	2		T3	1		T4	1
valid_sources[0x27]	138	1			T1	2		T2	1		T4	1
valid_sources[0x28]	160	1			T1	2		T3	9		T5	2
valid_sources[0x29]	242	1			T4	1		T7	2		T8	2
valid_sources[0x2a]	99	1			T2	1		T5	1		T4	1
valid_sources[0x2b]	99	1			T1	2		T4	1		T8	1
valid_sources[0x2c]	126	1			T1	3		T2	4		T4	1
valid_sources[0x2d]	103	1			T1	3		T4	2		T6	1
valid_sources[0x2e]	272	1			T1	1		T7	9		T17	7
valid_sources[0x2f]	128	1			T1	2		T4	1		T10	1
valid_sources[0x30]	90	1			T1	1		T3	5		T9	1
valid_sources[0x31]	77	1			T1	3		T9	1		T6	1
valid_sources[0x32]	112	1			T1	1		T21	1		T8	1
valid_sources[0x33]	120	1			T4	1		T11	4		T9	1
valid_sources[0x34]	137	1			T1	1		T2	1		T5	2
valid_sources[0x35]	119	1			T1	2		T9	1		T8	1
valid_sources[0x36]	226	1			T1	2		T2	1		T6	2
valid_sources[0x37]	128	1			T6	2		T16	1		T17	32
valid_sources[0x38]	115	1			T1	1		T2	1		T4	1
valid_sources[0x39]	128	1			T3	5		T9	1		T8	1
valid_sources[0x3a]	118	1			T1	1		T32	2		T18	3
valid_sources[0x3b]	88	1			T1	1		T4	1		T7	1
valid_sources[0x3c]	90	1			T1	1		T21	1		T8	2
valid_sources[0x3d]	81	1			T3	1		T4	1		T9	1
valid_sources[0x3e]	127	1			T1	2		T4	1		T6	1
valid_sources[0x3f]	384	1			T9	3		T6	2		T8	6
valid_sources[0x40]	157	1			T1	3		T10	1		T9	1
valid_sources[0x41]	85	1			T4	1		T7	2		T8	4
valid_sources[0x42]	133	1			T1	1		T9	1		T6	2
valid_sources[0x43]	99	1			T2	1		T6	2		T21	1
valid_sources[0x44]	81	1			T1	3		T3	1		T4	2
valid_sources[0x45]	96	1			T1	2		T10	1		T8	3
valid_sources[0x46]	96	1			T1	1		T21	1		T8	1
valid_sources[0x47]	155	1			T9	1		T6	2		T21	1
valid_sources[0x48]	115	1			T1	2		T6	2		T21	1
valid_sources[0x49]	185	1			T1	2		T9	2		T6	2
valid_sources[0x4a]	215	1			T1	2		T2	3		T3	2
valid_sources[0x4b]	91	1			T1	2		T13	5		T9	1
valid_sources[0x4c]	72	1			T9	2		T21	2		T15	1
valid_sources[0x4d]	113	1			T4	2		T9	2		T7	1
valid_sources[0x4e]	108	1			T1	2		T2	4		T9	1
valid_sources[0x4f]	214	1			T1	1		T5	1		T4	1
valid_sources[0x50]	100	1			T1	1		T4	1		T11	1
valid_sources[0x51]	105	1			T2	1		T3	11		T4	1
valid_sources[0x52]	68	1			T1	2		T4	1		T7	2
valid_sources[0x53]	153	1			T1	1		T21	2		T8	1
valid_sources[0x54]	96	1			T4	2		T13	2		T6	1
valid_sources[0x55]	110	1			T1	1		T4	1		T21	1
valid_sources[0x56]	101	1			T1	2		T9	1		T21	1
valid_sources[0x57]	190	1			T1	2		T2	1		T3	9
valid_sources[0x58]	89	1			T1	1		T16	2		T65	11
valid_sources[0x59]	211	1			T1	1		T4	1		T9	1
valid_sources[0x5a]	97	1			T1	1		T2	2		T4	1
valid_sources[0x5b]	151	1			T1	1		T5	1		T9	4
valid_sources[0x5c]	249	1			T1	1		T9	1		T6	1
valid_sources[0x5d]	118	1			T1	1		T7	1		T8	2
valid_sources[0x5e]	160	1			T1	1		T2	3		T10	1
valid_sources[0x5f]	81	1			T1	2		T9	2		T6	1
valid_sources[0x60]	146	1			T1	1		T3	2		T6	1
valid_sources[0x61]	119	1			T4	1		T13	6		T16	4
valid_sources[0x62]	133	1			T1	3		T2	1		T21	1
valid_sources[0x63]	117	1			T1	1		T4	1		T8	5
valid_sources[0x64]	225	1			T1	3		T3	8		T9	1
valid_sources[0x65]	262	1			T1	1		T2	1		T21	3
valid_sources[0x66]	140	1			T1	4		T4	1		T6	1
valid_sources[0x67]	91	1			T10	1		T9	1		T12	1
valid_sources[0x68]	129	1			T1	3		T4	2		T8	4
valid_sources[0x69]	84	1			T1	3		T3	2		T6	1
valid_sources[0x6a]	157	1			T1	1		T9	1		T21	1
valid_sources[0x6b]	92	1			T1	1		T2	2		T4	2
valid_sources[0x6c]	142	1			T1	1		T4	1		T10	2
valid_sources[0x6d]	139	1			T1	3		T8	1		T16	1
valid_sources[0x6e]	116	1			T1	1		T5	1		T9	2
valid_sources[0x6f]	91	1			T1	2		T3	5		T4	1
valid_sources[0x70]	140	1			T1	3		T11	1		T9	1
valid_sources[0x71]	238	1			T1	1		T3	11		T4	1
valid_sources[0x72]	92	1			T1	1		T10	1		T9	1
valid_sources[0x73]	101	1			T9	2		T7	3		T12	1
valid_sources[0x74]	140	1			T1	3		T8	1		T65	3
valid_sources[0x75]	139	1			T5	2		T15	2		T65	3
valid_sources[0x76]	169	1			T9	1		T6	3		T21	1
valid_sources[0x77]	130	1			T4	1		T10	1		T21	1
valid_sources[0x78]	124	1			T4	2		T10	1		T9	1
valid_sources[0x79]	77	1			T1	1		T5	1		T21	1
valid_sources[0x7a]	92	1			T1	1		T2	1		T3	5
valid_sources[0x7b]	191	1			T1	3		T9	1		T6	2
valid_sources[0x7c]	102	1			T1	3		T18	3		T65	5
valid_sources[0x7d]	238	1			T1	3		T4	2		T6	1
valid_sources[0x7e]	124	1			T8	1		T15	1		T65	10
valid_sources[0x7f]	102	1			T1	1		T4	1		T11	2
valid_sources[0x80]	145	1			T21	4		T8	3		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6491

1

T1

109

T2

23

T3

83

values[0x0]

all_enables

biggest_size

5346

1

T1

127

T2

29

T3

41

values[0x1]

all_enables

biggest_size

4780

1

T1

134

T2

16

T3

41