Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15599

1

T1

577

T2

43

T4

86

full_word

24779

1

T1

533

T2

27

T4

116

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	40048	1			T1	1110		T2	70		T4	202
auto[TlIntgErrCmd]	125	1			T9	4		T17	8		T47	12
auto[TlIntgErrData]	101	1			T9	2		T17	7		T47	3
auto[TlIntgErrBoth]	104	1			T9	4		T17	5		T47	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11867

1

T1

222

T2

9

T4

52

auto[1]

28511

1

T1

888

T2

61

T4

150

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3335	1			T1	108		T2	5		T4	18
auto[TlIntgErrNone]	partial	auto[1]	11964	1			T1	469		T2	38		T4	68
auto[TlIntgErrNone]	full_word	auto[0]	8394	1			T1	114		T2	4		T4	34
auto[TlIntgErrNone]	full_word	auto[1]	16355	1			T1	419		T2	23		T4	82
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T9	1		T17	3		T47	3
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T9	3		T17	5		T47	8
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T47	1		T59	1		T57	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T59	1		T54	1		T57	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T9	2		T17	2		T47	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T17	4		T60	2		T59	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T17	1		T47	1		T54	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T47	1		T56	1		T61	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T9	2		T17	1		T47	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T9	2		T17	3		T47	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T62	1		T58	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T17	1		T63	1		T62	1