| T555 |
/workspace/coverage/default/0.sram_ctrl_executable.3355496736 |
|
|
Mar 17 12:46:30 PM PDT 24 |
Mar 17 12:55:03 PM PDT 24 |
1900503316 ps |
| T556 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.783001330 |
|
|
Mar 17 12:46:38 PM PDT 24 |
Mar 17 12:53:43 PM PDT 24 |
5573758833 ps |
| T557 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1647628255 |
|
|
Mar 17 12:49:05 PM PDT 24 |
Mar 17 12:49:09 PM PDT 24 |
1250149578 ps |
| T558 |
/workspace/coverage/default/34.sram_ctrl_alert_test.3442192744 |
|
|
Mar 17 12:48:16 PM PDT 24 |
Mar 17 12:48:18 PM PDT 24 |
21915767 ps |
| T559 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2096692714 |
|
|
Mar 17 12:48:11 PM PDT 24 |
Mar 17 12:56:44 PM PDT 24 |
79784931632 ps |
| T560 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.865360869 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 01:04:16 PM PDT 24 |
7821420267 ps |
| T561 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3411727019 |
|
|
Mar 17 12:48:54 PM PDT 24 |
Mar 17 01:56:14 PM PDT 24 |
11056293904 ps |
| T562 |
/workspace/coverage/default/11.sram_ctrl_bijection.206689142 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:47 PM PDT 24 |
5302970346 ps |
| T563 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1782377294 |
|
|
Mar 17 12:47:54 PM PDT 24 |
Mar 17 12:52:56 PM PDT 24 |
4143669261 ps |
| T564 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.1622264770 |
|
|
Mar 17 12:49:15 PM PDT 24 |
Mar 17 12:49:21 PM PDT 24 |
3613249210 ps |
| T565 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2636480670 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:58:41 PM PDT 24 |
12449341255 ps |
| T566 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.2844807474 |
|
|
Mar 17 12:48:16 PM PDT 24 |
Mar 17 12:48:21 PM PDT 24 |
1170532123 ps |
| T567 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.4066327096 |
|
|
Mar 17 12:47:14 PM PDT 24 |
Mar 17 12:47:53 PM PDT 24 |
216625123 ps |
| T568 |
/workspace/coverage/default/37.sram_ctrl_regwen.3525673811 |
|
|
Mar 17 12:48:38 PM PDT 24 |
Mar 17 01:08:09 PM PDT 24 |
59076568002 ps |
| T569 |
/workspace/coverage/default/25.sram_ctrl_regwen.1414558627 |
|
|
Mar 17 12:47:48 PM PDT 24 |
Mar 17 12:56:53 PM PDT 24 |
2361496029 ps |
| T570 |
/workspace/coverage/default/1.sram_ctrl_executable.1487683570 |
|
|
Mar 17 12:46:37 PM PDT 24 |
Mar 17 01:02:26 PM PDT 24 |
103146352860 ps |
| T571 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1230917146 |
|
|
Mar 17 12:48:50 PM PDT 24 |
Mar 17 12:48:51 PM PDT 24 |
70954684 ps |
| T572 |
/workspace/coverage/default/22.sram_ctrl_bijection.1007116225 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:48:11 PM PDT 24 |
4365381704 ps |
| T573 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3290541459 |
|
|
Mar 17 12:49:03 PM PDT 24 |
Mar 17 12:51:39 PM PDT 24 |
2341063848 ps |
| T574 |
/workspace/coverage/default/36.sram_ctrl_partial_access.3958404552 |
|
|
Mar 17 12:48:23 PM PDT 24 |
Mar 17 12:48:30 PM PDT 24 |
820001380 ps |
| T575 |
/workspace/coverage/default/23.sram_ctrl_bijection.668560923 |
|
|
Mar 17 12:47:32 PM PDT 24 |
Mar 17 12:47:58 PM PDT 24 |
441784936 ps |
| T576 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.3330231323 |
|
|
Mar 17 12:48:52 PM PDT 24 |
Mar 17 12:48:53 PM PDT 24 |
345936099 ps |
| T577 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1138871682 |
|
|
Mar 17 12:49:09 PM PDT 24 |
Mar 17 12:51:07 PM PDT 24 |
163466525 ps |
| T578 |
/workspace/coverage/default/6.sram_ctrl_regwen.3085309449 |
|
|
Mar 17 12:47:01 PM PDT 24 |
Mar 17 12:58:03 PM PDT 24 |
76018996582 ps |
| T579 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.764651614 |
|
|
Mar 17 12:47:47 PM PDT 24 |
Mar 17 12:47:48 PM PDT 24 |
76598933 ps |
| T580 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.2849264714 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 01:00:55 PM PDT 24 |
16674851525 ps |
| T581 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1030275671 |
|
|
Mar 17 12:48:16 PM PDT 24 |
Mar 17 12:51:05 PM PDT 24 |
6957298875 ps |
| T582 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.99885642 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:48:41 PM PDT 24 |
233262399 ps |
| T32 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3020894784 |
|
|
Mar 17 12:47:02 PM PDT 24 |
Mar 17 12:47:04 PM PDT 24 |
238384581 ps |
| T583 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.687608202 |
|
|
Mar 17 12:48:18 PM PDT 24 |
Mar 17 01:05:39 PM PDT 24 |
19998121461 ps |
| T584 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.166970758 |
|
|
Mar 17 12:47:33 PM PDT 24 |
Mar 17 12:52:51 PM PDT 24 |
9340144598 ps |
| T585 |
/workspace/coverage/default/1.sram_ctrl_smoke.578119343 |
|
|
Mar 17 12:46:26 PM PDT 24 |
Mar 17 12:46:36 PM PDT 24 |
217301865 ps |
| T586 |
/workspace/coverage/default/7.sram_ctrl_alert_test.880823195 |
|
|
Mar 17 12:47:14 PM PDT 24 |
Mar 17 12:47:15 PM PDT 24 |
22449463 ps |
| T587 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1017446101 |
|
|
Mar 17 12:46:39 PM PDT 24 |
Mar 17 12:53:16 PM PDT 24 |
71604064450 ps |
| T588 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1516891165 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:28 PM PDT 24 |
253252283 ps |
| T80 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1219494635 |
|
|
Mar 17 12:48:12 PM PDT 24 |
Mar 17 12:48:15 PM PDT 24 |
217897676 ps |
| T589 |
/workspace/coverage/default/23.sram_ctrl_partial_access.130206826 |
|
|
Mar 17 12:47:28 PM PDT 24 |
Mar 17 12:47:36 PM PDT 24 |
773793785 ps |
| T590 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2491675970 |
|
|
Mar 17 12:48:16 PM PDT 24 |
Mar 17 12:48:22 PM PDT 24 |
382439125 ps |
| T591 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1948076575 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:48:08 PM PDT 24 |
66053111 ps |
| T592 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1164350002 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:24 PM PDT 24 |
13025905 ps |
| T593 |
/workspace/coverage/default/12.sram_ctrl_bijection.89715720 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:48:23 PM PDT 24 |
5321394826 ps |
| T594 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3331805291 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 01:54:43 PM PDT 24 |
10992215530 ps |
| T595 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.4146359770 |
|
|
Mar 17 12:49:27 PM PDT 24 |
Mar 17 12:53:56 PM PDT 24 |
5816658106 ps |
| T596 |
/workspace/coverage/default/40.sram_ctrl_alert_test.2957176721 |
|
|
Mar 17 12:48:53 PM PDT 24 |
Mar 17 12:48:54 PM PDT 24 |
10911668 ps |
| T597 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2918719857 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:48:13 PM PDT 24 |
589576276 ps |
| T598 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.2162766087 |
|
|
Mar 17 12:47:29 PM PDT 24 |
Mar 17 12:53:01 PM PDT 24 |
3515439360 ps |
| T599 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2808038560 |
|
|
Mar 17 12:48:51 PM PDT 24 |
Mar 17 12:54:30 PM PDT 24 |
3611656180 ps |
| T600 |
/workspace/coverage/default/3.sram_ctrl_smoke.3061073814 |
|
|
Mar 17 12:46:30 PM PDT 24 |
Mar 17 12:47:41 PM PDT 24 |
442100681 ps |
| T601 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2537714441 |
|
|
Mar 17 12:48:05 PM PDT 24 |
Mar 17 01:03:54 PM PDT 24 |
5594763617 ps |
| T602 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1676582341 |
|
|
Mar 17 12:47:25 PM PDT 24 |
Mar 17 12:47:28 PM PDT 24 |
194834295 ps |
| T603 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1726872689 |
|
|
Mar 17 12:48:08 PM PDT 24 |
Mar 17 12:48:09 PM PDT 24 |
50622730 ps |
| T604 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.50452316 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:47:26 PM PDT 24 |
345455347 ps |
| T605 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.2698617018 |
|
|
Mar 17 12:48:30 PM PDT 24 |
Mar 17 12:50:07 PM PDT 24 |
980448664 ps |
| T606 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2522781928 |
|
|
Mar 17 12:47:16 PM PDT 24 |
Mar 17 12:47:23 PM PDT 24 |
380579441 ps |
| T607 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3035087357 |
|
|
Mar 17 12:48:54 PM PDT 24 |
Mar 17 12:55:07 PM PDT 24 |
55682613137 ps |
| T608 |
/workspace/coverage/default/18.sram_ctrl_stress_all.4140384185 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 01:49:05 PM PDT 24 |
230014926178 ps |
| T609 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3136151301 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:47:24 PM PDT 24 |
31283169 ps |
| T610 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.256161971 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 12:47:30 PM PDT 24 |
79437433 ps |
| T611 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3568861317 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:48:13 PM PDT 24 |
456450304 ps |
| T612 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2507216710 |
|
|
Mar 17 12:48:11 PM PDT 24 |
Mar 17 12:51:46 PM PDT 24 |
4290685419 ps |
| T613 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1378165920 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:47:23 PM PDT 24 |
282812471 ps |
| T614 |
/workspace/coverage/default/30.sram_ctrl_smoke.1016870935 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:49:37 PM PDT 24 |
4426372507 ps |
| T615 |
/workspace/coverage/default/32.sram_ctrl_stress_all.276944265 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 01:08:30 PM PDT 24 |
45877791135 ps |
| T616 |
/workspace/coverage/default/26.sram_ctrl_executable.3864281569 |
|
|
Mar 17 12:47:44 PM PDT 24 |
Mar 17 12:58:34 PM PDT 24 |
21737047223 ps |
| T617 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.4171742665 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 01:01:28 PM PDT 24 |
12769292750 ps |
| T618 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3622664734 |
|
|
Mar 17 12:46:53 PM PDT 24 |
Mar 17 12:52:23 PM PDT 24 |
18747740762 ps |
| T619 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3353976755 |
|
|
Mar 17 12:48:32 PM PDT 24 |
Mar 17 12:52:34 PM PDT 24 |
2663354030 ps |
| T620 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1041559846 |
|
|
Mar 17 12:47:58 PM PDT 24 |
Mar 17 01:05:42 PM PDT 24 |
4119704052 ps |
| T621 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.794521929 |
|
|
Mar 17 12:46:58 PM PDT 24 |
Mar 17 12:47:44 PM PDT 24 |
658246263 ps |
| T622 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.3631975370 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:59:14 PM PDT 24 |
2127139783 ps |
| T623 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1421116510 |
|
|
Mar 17 12:49:05 PM PDT 24 |
Mar 17 01:08:56 PM PDT 24 |
49057568633 ps |
| T624 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.2113295951 |
|
|
Mar 17 12:46:30 PM PDT 24 |
Mar 17 12:46:35 PM PDT 24 |
976741740 ps |
| T625 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.1542403922 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 12:47:35 PM PDT 24 |
1215636633 ps |
| T626 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2307448445 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:48:10 PM PDT 24 |
11362247 ps |
| T627 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.2743289944 |
|
|
Mar 17 12:48:44 PM PDT 24 |
Mar 17 12:48:45 PM PDT 24 |
83298201 ps |
| T628 |
/workspace/coverage/default/13.sram_ctrl_alert_test.480638968 |
|
|
Mar 17 12:47:26 PM PDT 24 |
Mar 17 12:47:27 PM PDT 24 |
14194180 ps |
| T109 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.293430109 |
|
|
Mar 17 12:47:35 PM PDT 24 |
Mar 17 12:49:25 PM PDT 24 |
1154077832 ps |
| T629 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1486551801 |
|
|
Mar 17 12:47:08 PM PDT 24 |
Mar 17 12:49:23 PM PDT 24 |
3097543398 ps |
| T630 |
/workspace/coverage/default/19.sram_ctrl_partial_access.3855763961 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:48:52 PM PDT 24 |
727203245 ps |
| T631 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.944658351 |
|
|
Mar 17 12:49:36 PM PDT 24 |
Mar 17 12:49:38 PM PDT 24 |
48527691 ps |
| T632 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3538753664 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:56:09 PM PDT 24 |
1848293449 ps |
| T633 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.183383254 |
|
|
Mar 17 12:48:17 PM PDT 24 |
Mar 17 12:48:24 PM PDT 24 |
1040786137 ps |
| T634 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3327768503 |
|
|
Mar 17 12:47:58 PM PDT 24 |
Mar 17 12:52:33 PM PDT 24 |
424977311 ps |
| T635 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2579949769 |
|
|
Mar 17 12:48:04 PM PDT 24 |
Mar 17 12:52:45 PM PDT 24 |
14514464806 ps |
| T636 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3426456 |
|
|
Mar 17 12:47:40 PM PDT 24 |
Mar 17 12:47:41 PM PDT 24 |
45291524 ps |
| T637 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1099720712 |
|
|
Mar 17 12:49:03 PM PDT 24 |
Mar 17 12:49:04 PM PDT 24 |
86303346 ps |
| T638 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.98729460 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:47:30 PM PDT 24 |
2679519020 ps |
| T639 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.4048196522 |
|
|
Mar 17 12:46:31 PM PDT 24 |
Mar 17 12:50:03 PM PDT 24 |
6364023461 ps |
| T640 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3857610023 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:48:29 PM PDT 24 |
135706865 ps |
| T641 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2183145495 |
|
|
Mar 17 12:46:29 PM PDT 24 |
Mar 17 12:47:31 PM PDT 24 |
502699143 ps |
| T642 |
/workspace/coverage/default/4.sram_ctrl_smoke.2770989806 |
|
|
Mar 17 12:47:01 PM PDT 24 |
Mar 17 12:47:09 PM PDT 24 |
135957324 ps |
| T643 |
/workspace/coverage/default/32.sram_ctrl_partial_access.2022830654 |
|
|
Mar 17 12:48:08 PM PDT 24 |
Mar 17 12:48:33 PM PDT 24 |
347716868 ps |
| T644 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1399461991 |
|
|
Mar 17 12:48:58 PM PDT 24 |
Mar 17 12:49:03 PM PDT 24 |
81039009 ps |
| T645 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1029723131 |
|
|
Mar 17 12:49:28 PM PDT 24 |
Mar 17 01:05:17 PM PDT 24 |
46412214008 ps |
| T646 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2602477517 |
|
|
Mar 17 12:48:18 PM PDT 24 |
Mar 17 12:48:20 PM PDT 24 |
99465898 ps |
| T647 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2106617892 |
|
|
Mar 17 12:46:30 PM PDT 24 |
Mar 17 12:50:26 PM PDT 24 |
9676933459 ps |
| T648 |
/workspace/coverage/default/2.sram_ctrl_partial_access.2335295931 |
|
|
Mar 17 12:46:32 PM PDT 24 |
Mar 17 12:46:48 PM PDT 24 |
886792651 ps |
| T649 |
/workspace/coverage/default/18.sram_ctrl_alert_test.835045938 |
|
|
Mar 17 12:48:56 PM PDT 24 |
Mar 17 12:48:57 PM PDT 24 |
16030301 ps |
| T650 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.4117713985 |
|
|
Mar 17 12:47:33 PM PDT 24 |
Mar 17 12:47:44 PM PDT 24 |
117799126 ps |
| T651 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3138143899 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:28 PM PDT 24 |
595287914 ps |
| T652 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.55240902 |
|
|
Mar 17 12:48:51 PM PDT 24 |
Mar 17 12:48:56 PM PDT 24 |
652904206 ps |
| T653 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3114575635 |
|
|
Mar 17 12:47:16 PM PDT 24 |
Mar 17 12:50:59 PM PDT 24 |
1258372755 ps |
| T654 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1512355739 |
|
|
Mar 17 12:48:51 PM PDT 24 |
Mar 17 01:07:09 PM PDT 24 |
3778231680 ps |
| T655 |
/workspace/coverage/default/4.sram_ctrl_partial_access.3952170422 |
|
|
Mar 17 12:46:58 PM PDT 24 |
Mar 17 12:47:00 PM PDT 24 |
927996709 ps |
| T656 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2751137774 |
|
|
Mar 17 12:48:43 PM PDT 24 |
Mar 17 12:48:46 PM PDT 24 |
147022333 ps |
| T657 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1708738275 |
|
|
Mar 17 12:47:14 PM PDT 24 |
Mar 17 12:47:15 PM PDT 24 |
11045397 ps |
| T658 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1232990936 |
|
|
Mar 17 12:48:23 PM PDT 24 |
Mar 17 01:04:54 PM PDT 24 |
9014229559 ps |
| T659 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.775752192 |
|
|
Mar 17 12:47:34 PM PDT 24 |
Mar 17 12:53:49 PM PDT 24 |
5268340203 ps |
| T660 |
/workspace/coverage/default/10.sram_ctrl_bijection.89347332 |
|
|
Mar 17 12:47:29 PM PDT 24 |
Mar 17 12:47:43 PM PDT 24 |
282099180 ps |
| T661 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1463766583 |
|
|
Mar 17 12:47:31 PM PDT 24 |
Mar 17 12:47:34 PM PDT 24 |
171148242 ps |
| T662 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2929329240 |
|
|
Mar 17 12:48:56 PM PDT 24 |
Mar 17 12:48:59 PM PDT 24 |
125295546 ps |
| T663 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1613866512 |
|
|
Mar 17 12:49:15 PM PDT 24 |
Mar 17 12:49:17 PM PDT 24 |
101500256 ps |
| T664 |
/workspace/coverage/default/11.sram_ctrl_regwen.1584535663 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:59:47 PM PDT 24 |
17082641860 ps |
| T665 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.797878499 |
|
|
Mar 17 12:48:27 PM PDT 24 |
Mar 17 12:48:32 PM PDT 24 |
894931504 ps |
| T666 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2313799344 |
|
|
Mar 17 12:49:34 PM PDT 24 |
Mar 17 12:49:57 PM PDT 24 |
371090071 ps |
| T667 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.962799620 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:47:29 PM PDT 24 |
143929747 ps |
| T668 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.608562521 |
|
|
Mar 17 12:48:18 PM PDT 24 |
Mar 17 12:48:23 PM PDT 24 |
251535839 ps |
| T669 |
/workspace/coverage/default/21.sram_ctrl_partial_access.2905303544 |
|
|
Mar 17 12:47:37 PM PDT 24 |
Mar 17 12:47:53 PM PDT 24 |
265297514 ps |
| T670 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1944044321 |
|
|
Mar 17 12:48:57 PM PDT 24 |
Mar 17 12:54:32 PM PDT 24 |
12494847897 ps |
| T671 |
/workspace/coverage/default/28.sram_ctrl_partial_access.279099773 |
|
|
Mar 17 12:47:58 PM PDT 24 |
Mar 17 12:48:07 PM PDT 24 |
340088332 ps |
| T672 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4068637884 |
|
|
Mar 17 12:48:42 PM PDT 24 |
Mar 17 12:52:20 PM PDT 24 |
42337280894 ps |
| T673 |
/workspace/coverage/default/31.sram_ctrl_executable.1589838053 |
|
|
Mar 17 12:48:06 PM PDT 24 |
Mar 17 01:00:02 PM PDT 24 |
41255582955 ps |
| T674 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.4045766722 |
|
|
Mar 17 12:47:29 PM PDT 24 |
Mar 17 12:47:38 PM PDT 24 |
572771660 ps |
| T675 |
/workspace/coverage/default/22.sram_ctrl_alert_test.3582985948 |
|
|
Mar 17 12:47:33 PM PDT 24 |
Mar 17 12:47:34 PM PDT 24 |
13256237 ps |
| T676 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.223300565 |
|
|
Mar 17 12:46:56 PM PDT 24 |
Mar 17 12:59:56 PM PDT 24 |
2820470275 ps |
| T677 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3412984038 |
|
|
Mar 17 12:48:51 PM PDT 24 |
Mar 17 12:48:53 PM PDT 24 |
27928768 ps |
| T678 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3986697198 |
|
|
Mar 17 12:48:52 PM PDT 24 |
Mar 17 12:48:54 PM PDT 24 |
21131059 ps |
| T679 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1977046900 |
|
|
Mar 17 12:49:10 PM PDT 24 |
Mar 17 12:49:15 PM PDT 24 |
395161288 ps |
| T680 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.519537645 |
|
|
Mar 17 12:48:56 PM PDT 24 |
Mar 17 12:49:01 PM PDT 24 |
57606835 ps |
| T681 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3103851406 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:55:39 PM PDT 24 |
68567672575 ps |
| T682 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1372753519 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 12:47:37 PM PDT 24 |
2012252338 ps |
| T683 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3327468590 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:47:25 PM PDT 24 |
52214660 ps |
| T684 |
/workspace/coverage/default/31.sram_ctrl_regwen.3912396504 |
|
|
Mar 17 12:48:06 PM PDT 24 |
Mar 17 01:03:32 PM PDT 24 |
44544780531 ps |
| T685 |
/workspace/coverage/default/9.sram_ctrl_smoke.2077477644 |
|
|
Mar 17 12:47:13 PM PDT 24 |
Mar 17 12:47:25 PM PDT 24 |
1052588306 ps |
| T686 |
/workspace/coverage/default/18.sram_ctrl_regwen.2852887796 |
|
|
Mar 17 12:47:29 PM PDT 24 |
Mar 17 01:09:49 PM PDT 24 |
14227815347 ps |
| T687 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3724541258 |
|
|
Mar 17 12:47:53 PM PDT 24 |
Mar 17 12:47:59 PM PDT 24 |
216566171 ps |
| T688 |
/workspace/coverage/default/22.sram_ctrl_smoke.541417201 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 12:48:44 PM PDT 24 |
109986602 ps |
| T689 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2656655566 |
|
|
Mar 17 12:46:30 PM PDT 24 |
Mar 17 12:46:36 PM PDT 24 |
1323801770 ps |
| T690 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2567200172 |
|
|
Mar 17 12:47:16 PM PDT 24 |
Mar 17 12:47:18 PM PDT 24 |
89559109 ps |
| T691 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.3397554272 |
|
|
Mar 17 12:48:52 PM PDT 24 |
Mar 17 12:49:02 PM PDT 24 |
268317133 ps |
| T692 |
/workspace/coverage/default/42.sram_ctrl_smoke.3973487455 |
|
|
Mar 17 12:48:59 PM PDT 24 |
Mar 17 12:49:01 PM PDT 24 |
265665327 ps |
| T693 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.2795589667 |
|
|
Mar 17 12:46:59 PM PDT 24 |
Mar 17 12:47:07 PM PDT 24 |
1624545836 ps |
| T694 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1440258510 |
|
|
Mar 17 12:49:36 PM PDT 24 |
Mar 17 12:49:59 PM PDT 24 |
782554602 ps |
| T695 |
/workspace/coverage/default/30.sram_ctrl_executable.212338171 |
|
|
Mar 17 12:48:01 PM PDT 24 |
Mar 17 12:58:38 PM PDT 24 |
11482625000 ps |
| T696 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2100294556 |
|
|
Mar 17 12:46:31 PM PDT 24 |
Mar 17 12:50:34 PM PDT 24 |
2621342440 ps |
| T697 |
/workspace/coverage/default/23.sram_ctrl_regwen.4125783352 |
|
|
Mar 17 12:47:25 PM PDT 24 |
Mar 17 12:55:01 PM PDT 24 |
12601377517 ps |
| T698 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3496740488 |
|
|
Mar 17 12:47:15 PM PDT 24 |
Mar 17 12:48:11 PM PDT 24 |
511077218 ps |
| T699 |
/workspace/coverage/default/26.sram_ctrl_stress_all.1932571848 |
|
|
Mar 17 12:47:44 PM PDT 24 |
Mar 17 01:54:49 PM PDT 24 |
42195229159 ps |
| T700 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2026800060 |
|
|
Mar 17 12:48:57 PM PDT 24 |
Mar 17 12:51:41 PM PDT 24 |
265963090 ps |
| T701 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.3840229970 |
|
|
Mar 17 12:47:33 PM PDT 24 |
Mar 17 12:47:43 PM PDT 24 |
3282041024 ps |
| T702 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2093695308 |
|
|
Mar 17 12:49:17 PM PDT 24 |
Mar 17 12:49:18 PM PDT 24 |
86752652 ps |
| T703 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3944330539 |
|
|
Mar 17 12:47:26 PM PDT 24 |
Mar 17 12:49:42 PM PDT 24 |
18863579634 ps |
| T704 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2144833868 |
|
|
Mar 17 12:47:12 PM PDT 24 |
Mar 17 12:47:17 PM PDT 24 |
1217213538 ps |
| T705 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.488840777 |
|
|
Mar 17 12:46:58 PM PDT 24 |
Mar 17 12:47:01 PM PDT 24 |
278393364 ps |
| T706 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2378698722 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:48:59 PM PDT 24 |
1085976161 ps |
| T707 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.1771232404 |
|
|
Mar 17 12:47:05 PM PDT 24 |
Mar 17 12:47:06 PM PDT 24 |
92020663 ps |
| T708 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.1237153819 |
|
|
Mar 17 12:48:24 PM PDT 24 |
Mar 17 12:48:28 PM PDT 24 |
501051115 ps |
| T709 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1051186145 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:48:11 PM PDT 24 |
317621168 ps |
| T710 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1706508017 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 01:21:46 PM PDT 24 |
36964124552 ps |
| T711 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2054998547 |
|
|
Mar 17 12:46:59 PM PDT 24 |
Mar 17 12:48:51 PM PDT 24 |
491596566 ps |
| T712 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1063619876 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:51:05 PM PDT 24 |
1235161369 ps |
| T713 |
/workspace/coverage/default/20.sram_ctrl_stress_all.154274143 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 01:22:05 PM PDT 24 |
37108462932 ps |
| T714 |
/workspace/coverage/default/14.sram_ctrl_bijection.1177417498 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:48:14 PM PDT 24 |
21711880828 ps |
| T715 |
/workspace/coverage/default/33.sram_ctrl_bijection.2905508663 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:48:34 PM PDT 24 |
1824072107 ps |
| T716 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1658165977 |
|
|
Mar 17 12:48:31 PM PDT 24 |
Mar 17 12:52:19 PM PDT 24 |
3582983806 ps |
| T717 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.458658666 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:47:27 PM PDT 24 |
100588029 ps |
| T718 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2961176331 |
|
|
Mar 17 12:48:58 PM PDT 24 |
Mar 17 12:49:35 PM PDT 24 |
205588228 ps |
| T719 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.2255021460 |
|
|
Mar 17 12:48:29 PM PDT 24 |
Mar 17 12:48:31 PM PDT 24 |
40188829 ps |
| T720 |
/workspace/coverage/default/21.sram_ctrl_stress_all.4252745000 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 01:37:53 PM PDT 24 |
9430061160 ps |
| T721 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3154059313 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:47:34 PM PDT 24 |
1743108013 ps |
| T722 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2269774485 |
|
|
Mar 17 12:48:44 PM PDT 24 |
Mar 17 12:52:54 PM PDT 24 |
5598936260 ps |
| T723 |
/workspace/coverage/default/32.sram_ctrl_bijection.1350773417 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:48:56 PM PDT 24 |
1470344539 ps |
| T110 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2589591770 |
|
|
Mar 17 12:49:16 PM PDT 24 |
Mar 17 12:50:05 PM PDT 24 |
4320693304 ps |
| T724 |
/workspace/coverage/default/47.sram_ctrl_executable.2837968622 |
|
|
Mar 17 12:49:21 PM PDT 24 |
Mar 17 01:27:22 PM PDT 24 |
19984415791 ps |
| T81 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1971343772 |
|
|
Mar 17 12:48:31 PM PDT 24 |
Mar 17 12:48:35 PM PDT 24 |
63015388 ps |
| T725 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.2142752546 |
|
|
Mar 17 12:48:54 PM PDT 24 |
Mar 17 12:49:04 PM PDT 24 |
450520074 ps |
| T726 |
/workspace/coverage/default/28.sram_ctrl_stress_all.2626436297 |
|
|
Mar 17 12:47:58 PM PDT 24 |
Mar 17 01:11:14 PM PDT 24 |
92414793444 ps |
| T727 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2641198932 |
|
|
Mar 17 12:48:50 PM PDT 24 |
Mar 17 01:16:39 PM PDT 24 |
19633690666 ps |
| T728 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2708865668 |
|
|
Mar 17 12:48:14 PM PDT 24 |
Mar 17 01:18:41 PM PDT 24 |
25055267266 ps |
| T729 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2512572306 |
|
|
Mar 17 12:49:33 PM PDT 24 |
Mar 17 12:49:36 PM PDT 24 |
47809659 ps |
| T730 |
/workspace/coverage/default/17.sram_ctrl_smoke.3712683792 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 12:47:37 PM PDT 24 |
179508204 ps |
| T731 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3262991134 |
|
|
Mar 17 12:49:11 PM PDT 24 |
Mar 17 12:49:16 PM PDT 24 |
594031580 ps |
| T732 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.974943331 |
|
|
Mar 17 12:49:17 PM PDT 24 |
Mar 17 12:58:37 PM PDT 24 |
1179690172 ps |
| T733 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.901492581 |
|
|
Mar 17 12:48:05 PM PDT 24 |
Mar 17 12:48:10 PM PDT 24 |
327900877 ps |
| T734 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3124322376 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 01:00:33 PM PDT 24 |
21244197039 ps |
| T735 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2464179458 |
|
|
Mar 17 12:48:40 PM PDT 24 |
Mar 17 12:48:45 PM PDT 24 |
317585390 ps |
| T736 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2468981212 |
|
|
Mar 17 12:49:34 PM PDT 24 |
Mar 17 01:05:59 PM PDT 24 |
4643422863 ps |
| T737 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.3535260598 |
|
|
Mar 17 12:47:45 PM PDT 24 |
Mar 17 12:48:09 PM PDT 24 |
76852873 ps |
| T738 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.759554237 |
|
|
Mar 17 12:49:20 PM PDT 24 |
Mar 17 12:50:51 PM PDT 24 |
905992062 ps |
| T739 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.75791837 |
|
|
Mar 17 12:49:36 PM PDT 24 |
Mar 17 12:49:40 PM PDT 24 |
374793833 ps |
| T740 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2274435615 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:48:47 PM PDT 24 |
89182575 ps |
| T741 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.1831107456 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:47:32 PM PDT 24 |
140686869 ps |
| T742 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1383037265 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 01:10:00 PM PDT 24 |
61075700210 ps |
| T743 |
/workspace/coverage/default/38.sram_ctrl_alert_test.341819188 |
|
|
Mar 17 12:48:43 PM PDT 24 |
Mar 17 12:48:43 PM PDT 24 |
10710489 ps |
| T744 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2948939667 |
|
|
Mar 17 12:47:26 PM PDT 24 |
Mar 17 12:48:55 PM PDT 24 |
633131777 ps |
| T745 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.571799850 |
|
|
Mar 17 12:47:55 PM PDT 24 |
Mar 17 01:02:50 PM PDT 24 |
1989549090 ps |
| T746 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3681626163 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 01:02:22 PM PDT 24 |
5201412420 ps |
| T747 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.908981748 |
|
|
Mar 17 12:49:09 PM PDT 24 |
Mar 17 12:53:18 PM PDT 24 |
20632008263 ps |
| T748 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3531074127 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:47:28 PM PDT 24 |
602328965 ps |
| T749 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2305530958 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:47:23 PM PDT 24 |
77050911 ps |
| T750 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3722470400 |
|
|
Mar 17 12:47:15 PM PDT 24 |
Mar 17 12:47:26 PM PDT 24 |
1315270666 ps |
| T751 |
/workspace/coverage/default/46.sram_ctrl_partial_access.1893561155 |
|
|
Mar 17 12:49:12 PM PDT 24 |
Mar 17 12:49:20 PM PDT 24 |
178298378 ps |
| T752 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.870847399 |
|
|
Mar 17 12:47:38 PM PDT 24 |
Mar 17 12:57:11 PM PDT 24 |
4471744874 ps |
| T753 |
/workspace/coverage/default/33.sram_ctrl_partial_access.3287504231 |
|
|
Mar 17 12:48:11 PM PDT 24 |
Mar 17 12:48:29 PM PDT 24 |
911676107 ps |
| T754 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3620220521 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:49:15 PM PDT 24 |
617684746 ps |
| T755 |
/workspace/coverage/default/34.sram_ctrl_smoke.919809533 |
|
|
Mar 17 12:48:14 PM PDT 24 |
Mar 17 12:48:40 PM PDT 24 |
1556624173 ps |
| T756 |
/workspace/coverage/default/9.sram_ctrl_executable.1793707668 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 01:03:58 PM PDT 24 |
22680578045 ps |
| T757 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2573884554 |
|
|
Mar 17 12:47:37 PM PDT 24 |
Mar 17 01:10:39 PM PDT 24 |
7721003719 ps |
| T758 |
/workspace/coverage/default/20.sram_ctrl_regwen.2643315247 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:54:26 PM PDT 24 |
1895493363 ps |
| T759 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.309766463 |
|
|
Mar 17 12:48:56 PM PDT 24 |
Mar 17 12:49:07 PM PDT 24 |
4838479057 ps |
| T760 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2006259971 |
|
|
Mar 17 12:47:56 PM PDT 24 |
Mar 17 12:47:57 PM PDT 24 |
47029145 ps |
| T761 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2168244220 |
|
|
Mar 17 12:47:39 PM PDT 24 |
Mar 17 12:52:17 PM PDT 24 |
24879460872 ps |
| T762 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1371074424 |
|
|
Mar 17 12:49:32 PM PDT 24 |
Mar 17 12:49:48 PM PDT 24 |
237952331 ps |
| T763 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3146549206 |
|
|
Mar 17 12:47:00 PM PDT 24 |
Mar 17 01:03:33 PM PDT 24 |
15850382535 ps |
| T764 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3473569120 |
|
|
Mar 17 12:48:16 PM PDT 24 |
Mar 17 01:07:23 PM PDT 24 |
4647755868 ps |
| T765 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.956991481 |
|
|
Mar 17 12:48:44 PM PDT 24 |
Mar 17 12:50:52 PM PDT 24 |
162945474 ps |
| T766 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.51517846 |
|
|
Mar 17 12:47:31 PM PDT 24 |
Mar 17 12:51:19 PM PDT 24 |
2517185163 ps |
| T767 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2353281020 |
|
|
Mar 17 12:46:27 PM PDT 24 |
Mar 17 12:46:29 PM PDT 24 |
59947741 ps |
| T768 |
/workspace/coverage/default/1.sram_ctrl_bijection.2333397262 |
|
|
Mar 17 12:46:31 PM PDT 24 |
Mar 17 12:47:22 PM PDT 24 |
12664830151 ps |
| T769 |
/workspace/coverage/default/3.sram_ctrl_regwen.1978298392 |
|
|
Mar 17 12:46:37 PM PDT 24 |
Mar 17 01:03:59 PM PDT 24 |
33993423737 ps |
| T770 |
/workspace/coverage/default/5.sram_ctrl_executable.3419298624 |
|
|
Mar 17 12:47:03 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
11698077071 ps |
| T771 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1970568613 |
|
|
Mar 17 12:46:31 PM PDT 24 |
Mar 17 12:46:31 PM PDT 24 |
43433653 ps |
| T772 |
/workspace/coverage/default/29.sram_ctrl_stress_all.1992941258 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 01:34:53 PM PDT 24 |
10005322462 ps |
| T773 |
/workspace/coverage/default/25.sram_ctrl_alert_test.1497811570 |
|
|
Mar 17 12:48:00 PM PDT 24 |
Mar 17 12:48:01 PM PDT 24 |
22328972 ps |
| T774 |
/workspace/coverage/default/44.sram_ctrl_regwen.2000827787 |
|
|
Mar 17 12:49:06 PM PDT 24 |
Mar 17 12:59:53 PM PDT 24 |
5606445695 ps |
| T775 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.642466705 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:48:11 PM PDT 24 |
30859734 ps |
| T776 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3435379681 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:47:29 PM PDT 24 |
712885861 ps |
| T777 |
/workspace/coverage/default/33.sram_ctrl_stress_all.2199459407 |
|
|
Mar 17 12:48:11 PM PDT 24 |
Mar 17 01:54:33 PM PDT 24 |
49984361701 ps |
| T778 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1485622750 |
|
|
Mar 17 12:46:57 PM PDT 24 |
Mar 17 12:46:58 PM PDT 24 |
25828716 ps |
| T779 |
/workspace/coverage/default/0.sram_ctrl_bijection.1178405351 |
|
|
Mar 17 12:47:01 PM PDT 24 |
Mar 17 12:47:44 PM PDT 24 |
10646872940 ps |
| T780 |
/workspace/coverage/default/13.sram_ctrl_partial_access.722804754 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:47:33 PM PDT 24 |
849209502 ps |
| T781 |
/workspace/coverage/default/7.sram_ctrl_partial_access.3553423180 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:48:05 PM PDT 24 |
2333854234 ps |
| T782 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.677710413 |
|
|
Mar 17 12:47:05 PM PDT 24 |
Mar 17 12:47:32 PM PDT 24 |
378896660 ps |
| T783 |
/workspace/coverage/default/49.sram_ctrl_partial_access.463587486 |
|
|
Mar 17 12:49:33 PM PDT 24 |
Mar 17 12:49:38 PM PDT 24 |
103982674 ps |
| T784 |
/workspace/coverage/default/7.sram_ctrl_smoke.4060569073 |
|
|
Mar 17 12:47:01 PM PDT 24 |
Mar 17 12:47:09 PM PDT 24 |
676891453 ps |
| T785 |
/workspace/coverage/default/24.sram_ctrl_executable.3535965699 |
|
|
Mar 17 12:47:31 PM PDT 24 |
Mar 17 12:51:36 PM PDT 24 |
9060388810 ps |
| T786 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.783704338 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:49:37 PM PDT 24 |
155139803 ps |
| T787 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.351809053 |
|
|
Mar 17 12:47:13 PM PDT 24 |
Mar 17 12:47:23 PM PDT 24 |
813455807 ps |
| T788 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3350819113 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 12:47:32 PM PDT 24 |
213675055 ps |
| T789 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3020866459 |
|
|
Mar 17 12:46:56 PM PDT 24 |
Mar 17 12:47:13 PM PDT 24 |
77679652 ps |
| T790 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.19588814 |
|
|
Mar 17 12:47:00 PM PDT 24 |
Mar 17 12:52:54 PM PDT 24 |
90626692374 ps |
| T791 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.657595454 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:53:28 PM PDT 24 |
18756453114 ps |
| T792 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.374731248 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 12:47:27 PM PDT 24 |
99487066 ps |
| T793 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.746976867 |
|
|
Mar 17 12:48:30 PM PDT 24 |
Mar 17 12:48:39 PM PDT 24 |
553006638 ps |
| T794 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1938575385 |
|
|
Mar 17 12:48:27 PM PDT 24 |
Mar 17 12:54:36 PM PDT 24 |
4111001041 ps |
| T795 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1141335217 |
|
|
Mar 17 12:47:32 PM PDT 24 |
Mar 17 12:47:45 PM PDT 24 |
594774158 ps |
| T796 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2228476061 |
|
|
Mar 17 12:47:25 PM PDT 24 |
Mar 17 01:21:55 PM PDT 24 |
83243937282 ps |
| T797 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.1689620770 |
|
|
Mar 17 12:46:29 PM PDT 24 |
Mar 17 12:48:01 PM PDT 24 |
1645835925 ps |
| T798 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3548593209 |
|
|
Mar 17 12:49:25 PM PDT 24 |
Mar 17 12:51:51 PM PDT 24 |
4345967293 ps |
| T799 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1118685329 |
|
|
Mar 17 12:48:54 PM PDT 24 |
Mar 17 12:49:25 PM PDT 24 |
416060758 ps |