| T82 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2759981687 |
|
|
Mar 17 12:47:56 PM PDT 24 |
Mar 17 12:47:59 PM PDT 24 |
434821349 ps |
| T800 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.895659359 |
|
|
Mar 17 12:48:51 PM PDT 24 |
Mar 17 12:57:41 PM PDT 24 |
6705217222 ps |
| T801 |
/workspace/coverage/default/13.sram_ctrl_smoke.948311162 |
|
|
Mar 17 12:48:54 PM PDT 24 |
Mar 17 12:49:11 PM PDT 24 |
536382722 ps |
| T802 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.296487755 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:49:23 PM PDT 24 |
543226676 ps |
| T803 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1694293053 |
|
|
Mar 17 12:49:03 PM PDT 24 |
Mar 17 12:49:04 PM PDT 24 |
26867505 ps |
| T804 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2339976444 |
|
|
Mar 17 12:48:58 PM PDT 24 |
Mar 17 01:09:39 PM PDT 24 |
4125381067 ps |
| T805 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1701547908 |
|
|
Mar 17 12:48:25 PM PDT 24 |
Mar 17 12:48:26 PM PDT 24 |
12875698 ps |
| T111 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2058873063 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:48:25 PM PDT 24 |
2958766425 ps |
| T112 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2952382553 |
|
|
Mar 17 12:46:39 PM PDT 24 |
Mar 17 12:46:49 PM PDT 24 |
318439041 ps |
| T806 |
/workspace/coverage/default/16.sram_ctrl_regwen.1934217650 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:33 PM PDT 24 |
721515261 ps |
| T807 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2362830932 |
|
|
Mar 17 12:49:11 PM PDT 24 |
Mar 17 01:51:04 PM PDT 24 |
49631357868 ps |
| T808 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1839214484 |
|
|
Mar 17 12:48:58 PM PDT 24 |
Mar 17 12:50:53 PM PDT 24 |
602266052 ps |
| T809 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.492877615 |
|
|
Mar 17 12:47:28 PM PDT 24 |
Mar 17 12:51:00 PM PDT 24 |
12199074061 ps |
| T810 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.92831151 |
|
|
Mar 17 12:49:27 PM PDT 24 |
Mar 17 12:53:33 PM PDT 24 |
10739383120 ps |
| T811 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1386484447 |
|
|
Mar 17 12:48:24 PM PDT 24 |
Mar 17 12:54:22 PM PDT 24 |
12073711667 ps |
| T812 |
/workspace/coverage/default/6.sram_ctrl_stress_all.2993870603 |
|
|
Mar 17 12:47:10 PM PDT 24 |
Mar 17 01:38:07 PM PDT 24 |
48111026688 ps |
| T813 |
/workspace/coverage/default/29.sram_ctrl_bijection.1878249899 |
|
|
Mar 17 12:48:04 PM PDT 24 |
Mar 17 12:48:23 PM PDT 24 |
691434486 ps |
| T814 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2992607981 |
|
|
Mar 17 12:47:56 PM PDT 24 |
Mar 17 12:48:25 PM PDT 24 |
119774441 ps |
| T815 |
/workspace/coverage/default/17.sram_ctrl_partial_access.2749932586 |
|
|
Mar 17 12:47:26 PM PDT 24 |
Mar 17 12:47:36 PM PDT 24 |
393053386 ps |
| T816 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.3354628842 |
|
|
Mar 17 12:47:34 PM PDT 24 |
Mar 17 12:47:49 PM PDT 24 |
321715885 ps |
| T817 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.528231530 |
|
|
Mar 17 12:48:56 PM PDT 24 |
Mar 17 12:51:23 PM PDT 24 |
4106248598 ps |
| T818 |
/workspace/coverage/default/1.sram_ctrl_regwen.3143368467 |
|
|
Mar 17 12:47:01 PM PDT 24 |
Mar 17 01:08:06 PM PDT 24 |
6187267063 ps |
| T819 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3972357210 |
|
|
Mar 17 12:48:12 PM PDT 24 |
Mar 17 12:48:20 PM PDT 24 |
2236115469 ps |
| T820 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3931219811 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:53:39 PM PDT 24 |
4931969329 ps |
| T821 |
/workspace/coverage/default/12.sram_ctrl_executable.2467023951 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 01:11:32 PM PDT 24 |
4248575927 ps |
| T822 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.19561310 |
|
|
Mar 17 12:47:38 PM PDT 24 |
Mar 17 12:57:10 PM PDT 24 |
8120778146 ps |
| T823 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1371117955 |
|
|
Mar 17 12:47:02 PM PDT 24 |
Mar 17 01:08:41 PM PDT 24 |
9456956982 ps |
| T824 |
/workspace/coverage/default/14.sram_ctrl_smoke.3636908740 |
|
|
Mar 17 12:47:34 PM PDT 24 |
Mar 17 12:49:24 PM PDT 24 |
603574573 ps |
| T825 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2932690445 |
|
|
Mar 17 12:47:31 PM PDT 24 |
Mar 17 12:47:58 PM PDT 24 |
198915498 ps |
| T826 |
/workspace/coverage/default/18.sram_ctrl_executable.3361685343 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 01:01:05 PM PDT 24 |
4091110902 ps |
| T827 |
/workspace/coverage/default/7.sram_ctrl_regwen.243778892 |
|
|
Mar 17 12:47:14 PM PDT 24 |
Mar 17 01:00:34 PM PDT 24 |
99236572149 ps |
| T828 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2226629456 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:52:45 PM PDT 24 |
50083851649 ps |
| T829 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4014916527 |
|
|
Mar 17 12:46:56 PM PDT 24 |
Mar 17 12:50:29 PM PDT 24 |
8447987452 ps |
| T830 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3066132786 |
|
|
Mar 17 12:48:57 PM PDT 24 |
Mar 17 12:52:18 PM PDT 24 |
3012325527 ps |
| T831 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2735082590 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:50:07 PM PDT 24 |
1817741230 ps |
| T832 |
/workspace/coverage/default/41.sram_ctrl_stress_all.2221609951 |
|
|
Mar 17 12:48:51 PM PDT 24 |
Mar 17 01:42:56 PM PDT 24 |
11879428530 ps |
| T833 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1182585451 |
|
|
Mar 17 12:48:11 PM PDT 24 |
Mar 17 12:49:24 PM PDT 24 |
546668329 ps |
| T834 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3784915983 |
|
|
Mar 17 12:47:17 PM PDT 24 |
Mar 17 12:51:20 PM PDT 24 |
2584677233 ps |
| T835 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3245162170 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:52:50 PM PDT 24 |
43159194427 ps |
| T836 |
/workspace/coverage/default/44.sram_ctrl_bijection.2063920518 |
|
|
Mar 17 12:49:04 PM PDT 24 |
Mar 17 12:49:25 PM PDT 24 |
1409379495 ps |
| T837 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.1072156095 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:48:08 PM PDT 24 |
165055424 ps |
| T838 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.925149343 |
|
|
Mar 17 12:49:11 PM PDT 24 |
Mar 17 01:08:53 PM PDT 24 |
95198186159 ps |
| T839 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2732889190 |
|
|
Mar 17 12:46:55 PM PDT 24 |
Mar 17 12:47:03 PM PDT 24 |
573217420 ps |
| T840 |
/workspace/coverage/default/34.sram_ctrl_executable.2927395689 |
|
|
Mar 17 12:48:21 PM PDT 24 |
Mar 17 01:07:38 PM PDT 24 |
32444605538 ps |
| T33 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.133203247 |
|
|
Mar 17 12:46:57 PM PDT 24 |
Mar 17 12:47:00 PM PDT 24 |
911946544 ps |
| T841 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4074371620 |
|
|
Mar 17 12:47:16 PM PDT 24 |
Mar 17 12:47:20 PM PDT 24 |
2766934917 ps |
| T842 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3795614299 |
|
|
Mar 17 12:47:03 PM PDT 24 |
Mar 17 12:47:10 PM PDT 24 |
1305149006 ps |
| T843 |
/workspace/coverage/default/11.sram_ctrl_executable.1243450326 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:52:24 PM PDT 24 |
3933233729 ps |
| T844 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.646648793 |
|
|
Mar 17 12:46:54 PM PDT 24 |
Mar 17 12:47:03 PM PDT 24 |
2701742000 ps |
| T845 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2127267171 |
|
|
Mar 17 12:49:01 PM PDT 24 |
Mar 17 12:54:32 PM PDT 24 |
13230185559 ps |
| T846 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.674924403 |
|
|
Mar 17 12:47:17 PM PDT 24 |
Mar 17 12:48:06 PM PDT 24 |
540925349 ps |
| T847 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.496148959 |
|
|
Mar 17 12:47:48 PM PDT 24 |
Mar 17 12:47:55 PM PDT 24 |
3495813641 ps |
| T848 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2716845059 |
|
|
Mar 17 12:48:43 PM PDT 24 |
Mar 17 12:48:54 PM PDT 24 |
1362632186 ps |
| T849 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.981199987 |
|
|
Mar 17 12:47:06 PM PDT 24 |
Mar 17 12:47:41 PM PDT 24 |
441422174 ps |
| T850 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3858953568 |
|
|
Mar 17 12:49:27 PM PDT 24 |
Mar 17 12:49:51 PM PDT 24 |
923750417 ps |
| T851 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4019930284 |
|
|
Mar 17 12:46:58 PM PDT 24 |
Mar 17 12:56:11 PM PDT 24 |
10858108793 ps |
| T852 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2553654716 |
|
|
Mar 17 12:47:48 PM PDT 24 |
Mar 17 12:47:49 PM PDT 24 |
102061882 ps |
| T853 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.4147002394 |
|
|
Mar 17 12:47:29 PM PDT 24 |
Mar 17 12:55:15 PM PDT 24 |
22847814044 ps |
| T854 |
/workspace/coverage/default/45.sram_ctrl_smoke.3220029865 |
|
|
Mar 17 12:49:18 PM PDT 24 |
Mar 17 12:49:26 PM PDT 24 |
727667992 ps |
| T855 |
/workspace/coverage/default/47.sram_ctrl_bijection.936644780 |
|
|
Mar 17 12:49:19 PM PDT 24 |
Mar 17 12:49:55 PM PDT 24 |
618512893 ps |
| T856 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3578542464 |
|
|
Mar 17 12:46:35 PM PDT 24 |
Mar 17 01:05:02 PM PDT 24 |
40212029587 ps |
| T857 |
/workspace/coverage/default/19.sram_ctrl_bijection.2530263059 |
|
|
Mar 17 12:48:39 PM PDT 24 |
Mar 17 12:48:55 PM PDT 24 |
805788115 ps |
| T858 |
/workspace/coverage/default/43.sram_ctrl_alert_test.577639066 |
|
|
Mar 17 12:49:03 PM PDT 24 |
Mar 17 12:49:04 PM PDT 24 |
86156201 ps |
| T859 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.1523432952 |
|
|
Mar 17 12:48:29 PM PDT 24 |
Mar 17 12:48:33 PM PDT 24 |
78269177 ps |
| T860 |
/workspace/coverage/default/38.sram_ctrl_stress_all.1056976688 |
|
|
Mar 17 12:48:43 PM PDT 24 |
Mar 17 01:02:52 PM PDT 24 |
13864051209 ps |
| T861 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2216853797 |
|
|
Mar 17 12:48:58 PM PDT 24 |
Mar 17 12:49:05 PM PDT 24 |
2448447416 ps |
| T862 |
/workspace/coverage/default/36.sram_ctrl_bijection.2896001149 |
|
|
Mar 17 12:48:26 PM PDT 24 |
Mar 17 12:49:50 PM PDT 24 |
11245299609 ps |
| T863 |
/workspace/coverage/default/9.sram_ctrl_regwen.1632078309 |
|
|
Mar 17 12:48:54 PM PDT 24 |
Mar 17 01:00:12 PM PDT 24 |
65317030851 ps |
| T864 |
/workspace/coverage/default/11.sram_ctrl_alert_test.574543547 |
|
|
Mar 17 12:47:16 PM PDT 24 |
Mar 17 12:47:17 PM PDT 24 |
17497866 ps |
| T865 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.72749732 |
|
|
Mar 17 12:48:04 PM PDT 24 |
Mar 17 12:51:52 PM PDT 24 |
1939194030 ps |
| T866 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.1398847945 |
|
|
Mar 17 12:47:25 PM PDT 24 |
Mar 17 12:47:28 PM PDT 24 |
1394732421 ps |
| T867 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1148883312 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 12:47:35 PM PDT 24 |
234952108 ps |
| T868 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2673034003 |
|
|
Mar 17 12:47:28 PM PDT 24 |
Mar 17 12:49:18 PM PDT 24 |
301954508 ps |
| T869 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1505949080 |
|
|
Mar 17 12:49:09 PM PDT 24 |
Mar 17 12:54:10 PM PDT 24 |
1267373051 ps |
| T870 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3535091564 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:59:42 PM PDT 24 |
42052726726 ps |
| T871 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.4230370137 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:47:40 PM PDT 24 |
172555524 ps |
| T872 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2450491108 |
|
|
Mar 17 12:47:09 PM PDT 24 |
Mar 17 12:48:38 PM PDT 24 |
272808565 ps |
| T873 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.995705357 |
|
|
Mar 17 12:46:29 PM PDT 24 |
Mar 17 12:46:46 PM PDT 24 |
1244710026 ps |
| T874 |
/workspace/coverage/default/8.sram_ctrl_regwen.896398332 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 01:12:09 PM PDT 24 |
19616452195 ps |
| T875 |
/workspace/coverage/default/25.sram_ctrl_smoke.2316353432 |
|
|
Mar 17 12:47:38 PM PDT 24 |
Mar 17 12:47:49 PM PDT 24 |
227007391 ps |
| T876 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1204244278 |
|
|
Mar 17 12:47:17 PM PDT 24 |
Mar 17 12:47:20 PM PDT 24 |
49498411 ps |
| T877 |
/workspace/coverage/default/49.sram_ctrl_regwen.198515588 |
|
|
Mar 17 12:49:33 PM PDT 24 |
Mar 17 01:04:57 PM PDT 24 |
25855627818 ps |
| T878 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.1501229324 |
|
|
Mar 17 12:46:51 PM PDT 24 |
Mar 17 12:47:23 PM PDT 24 |
93324043 ps |
| T879 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.2965925669 |
|
|
Mar 17 12:47:13 PM PDT 24 |
Mar 17 12:47:18 PM PDT 24 |
89827701 ps |
| T880 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.1950894952 |
|
|
Mar 17 12:47:36 PM PDT 24 |
Mar 17 12:47:41 PM PDT 24 |
1330294694 ps |
| T881 |
/workspace/coverage/default/11.sram_ctrl_stress_all.846101626 |
|
|
Mar 17 12:47:25 PM PDT 24 |
Mar 17 01:27:26 PM PDT 24 |
61023231442 ps |
| T882 |
/workspace/coverage/default/5.sram_ctrl_regwen.3221040808 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:58:17 PM PDT 24 |
63624760249 ps |
| T883 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.4066781788 |
|
|
Mar 17 12:48:51 PM PDT 24 |
Mar 17 12:49:01 PM PDT 24 |
916686127 ps |
| T884 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.945619070 |
|
|
Mar 17 12:48:19 PM PDT 24 |
Mar 17 12:48:25 PM PDT 24 |
61492623 ps |
| T885 |
/workspace/coverage/default/16.sram_ctrl_smoke.2460068577 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 12:47:37 PM PDT 24 |
59324791 ps |
| T886 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.4083010017 |
|
|
Mar 17 12:47:00 PM PDT 24 |
Mar 17 12:47:03 PM PDT 24 |
366243230 ps |
| T887 |
/workspace/coverage/default/43.sram_ctrl_stress_all.3739241274 |
|
|
Mar 17 12:49:05 PM PDT 24 |
Mar 17 01:38:04 PM PDT 24 |
42671839739 ps |
| T888 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1273405280 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 01:01:44 PM PDT 24 |
10929640192 ps |
| T889 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2298478905 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:24 PM PDT 24 |
30071498 ps |
| T890 |
/workspace/coverage/default/12.sram_ctrl_smoke.3316175617 |
|
|
Mar 17 12:47:15 PM PDT 24 |
Mar 17 12:47:31 PM PDT 24 |
4845229641 ps |
| T891 |
/workspace/coverage/default/19.sram_ctrl_executable.1260378753 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 01:00:22 PM PDT 24 |
6995002410 ps |
| T892 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2085628916 |
|
|
Mar 17 12:48:53 PM PDT 24 |
Mar 17 12:50:25 PM PDT 24 |
133977150 ps |
| T893 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1764461764 |
|
|
Mar 17 12:48:30 PM PDT 24 |
Mar 17 12:48:34 PM PDT 24 |
215009434 ps |
| T894 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.2456851768 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:47:33 PM PDT 24 |
1360992277 ps |
| T895 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.2981079487 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:48:11 PM PDT 24 |
362620605 ps |
| T896 |
/workspace/coverage/default/29.sram_ctrl_regwen.1431658497 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:57:33 PM PDT 24 |
2635670111 ps |
| T897 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2941308656 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:49:34 PM PDT 24 |
645156075 ps |
| T898 |
/workspace/coverage/default/25.sram_ctrl_partial_access.2344043964 |
|
|
Mar 17 12:47:42 PM PDT 24 |
Mar 17 12:49:12 PM PDT 24 |
2296766382 ps |
| T899 |
/workspace/coverage/default/30.sram_ctrl_bijection.4166200203 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:48:39 PM PDT 24 |
2516301435 ps |
| T900 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.747266886 |
|
|
Mar 17 12:47:07 PM PDT 24 |
Mar 17 12:50:04 PM PDT 24 |
3829199710 ps |
| T901 |
/workspace/coverage/default/41.sram_ctrl_smoke.932568691 |
|
|
Mar 17 12:48:54 PM PDT 24 |
Mar 17 12:49:09 PM PDT 24 |
250746426 ps |
| T902 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2068308973 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:47:23 PM PDT 24 |
80469158 ps |
| T903 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2357175910 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:47:27 PM PDT 24 |
194682187 ps |
| T904 |
/workspace/coverage/default/0.sram_ctrl_smoke.1542003438 |
|
|
Mar 17 12:47:02 PM PDT 24 |
Mar 17 12:47:08 PM PDT 24 |
455590219 ps |
| T905 |
/workspace/coverage/default/4.sram_ctrl_regwen.74012505 |
|
|
Mar 17 12:47:04 PM PDT 24 |
Mar 17 12:57:42 PM PDT 24 |
10735774932 ps |
| T906 |
/workspace/coverage/default/35.sram_ctrl_alert_test.3451284155 |
|
|
Mar 17 12:48:22 PM PDT 24 |
Mar 17 12:48:23 PM PDT 24 |
38121986 ps |
| T907 |
/workspace/coverage/default/21.sram_ctrl_regwen.3585597557 |
|
|
Mar 17 12:47:31 PM PDT 24 |
Mar 17 12:51:09 PM PDT 24 |
8162091262 ps |
| T908 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2025821451 |
|
|
Mar 17 12:47:00 PM PDT 24 |
Mar 17 01:10:01 PM PDT 24 |
66043300357 ps |
| T909 |
/workspace/coverage/default/41.sram_ctrl_executable.903818081 |
|
|
Mar 17 12:48:53 PM PDT 24 |
Mar 17 12:56:49 PM PDT 24 |
10222781007 ps |
| T910 |
/workspace/coverage/default/23.sram_ctrl_alert_test.839256860 |
|
|
Mar 17 12:47:32 PM PDT 24 |
Mar 17 12:47:32 PM PDT 24 |
16239661 ps |
| T911 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.366992881 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 01:00:40 PM PDT 24 |
5424548370 ps |
| T912 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3012512795 |
|
|
Mar 17 12:47:08 PM PDT 24 |
Mar 17 12:47:08 PM PDT 24 |
31641863 ps |
| T913 |
/workspace/coverage/default/48.sram_ctrl_alert_test.327996325 |
|
|
Mar 17 12:49:34 PM PDT 24 |
Mar 17 12:49:35 PM PDT 24 |
14722456 ps |
| T83 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2185038782 |
|
|
Mar 17 12:46:35 PM PDT 24 |
Mar 17 12:46:37 PM PDT 24 |
46766157 ps |
| T914 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1745628139 |
|
|
Mar 17 12:46:56 PM PDT 24 |
Mar 17 12:52:21 PM PDT 24 |
3388708850 ps |
| T915 |
/workspace/coverage/default/49.sram_ctrl_executable.413111987 |
|
|
Mar 17 12:49:33 PM PDT 24 |
Mar 17 01:01:53 PM PDT 24 |
1630985621 ps |
| T916 |
/workspace/coverage/default/18.sram_ctrl_bijection.1137262355 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:47:48 PM PDT 24 |
409972321 ps |
| T917 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1398640497 |
|
|
Mar 17 12:49:36 PM PDT 24 |
Mar 17 12:55:31 PM PDT 24 |
30799135376 ps |
| T918 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1736128246 |
|
|
Mar 17 12:47:54 PM PDT 24 |
Mar 17 12:48:18 PM PDT 24 |
321694817 ps |
| T919 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.545460254 |
|
|
Mar 17 12:47:07 PM PDT 24 |
Mar 17 12:51:06 PM PDT 24 |
770354368 ps |
| T920 |
/workspace/coverage/default/0.sram_ctrl_regwen.1870648514 |
|
|
Mar 17 12:46:39 PM PDT 24 |
Mar 17 12:57:04 PM PDT 24 |
6216019123 ps |
| T921 |
/workspace/coverage/default/9.sram_ctrl_bijection.465746217 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:47:51 PM PDT 24 |
5941326231 ps |
| T922 |
/workspace/coverage/default/22.sram_ctrl_regwen.2372753178 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 01:06:53 PM PDT 24 |
48961743827 ps |
| T923 |
/workspace/coverage/default/20.sram_ctrl_executable.149081061 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 01:08:41 PM PDT 24 |
12939400379 ps |
| T924 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.671428349 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:58:17 PM PDT 24 |
8333504060 ps |
| T925 |
/workspace/coverage/default/34.sram_ctrl_partial_access.3052407999 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:48:40 PM PDT 24 |
364598417 ps |
| T926 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1273297166 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 01:07:01 PM PDT 24 |
58074341503 ps |
| T927 |
/workspace/coverage/default/48.sram_ctrl_executable.937741921 |
|
|
Mar 17 12:49:27 PM PDT 24 |
Mar 17 01:13:43 PM PDT 24 |
214867362145 ps |
| T928 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3828775550 |
|
|
Mar 17 12:46:37 PM PDT 24 |
Mar 17 12:46:48 PM PDT 24 |
827412141 ps |
| T929 |
/workspace/coverage/default/15.sram_ctrl_bijection.2232794680 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:48:01 PM PDT 24 |
9540334728 ps |
| T930 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.4127301376 |
|
|
Mar 17 12:48:12 PM PDT 24 |
Mar 17 12:48:15 PM PDT 24 |
87866223 ps |
| T931 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1443018135 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:47:30 PM PDT 24 |
556269832 ps |
| T932 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4278078084 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:59:54 PM PDT 24 |
2969786029 ps |
| T933 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.256096966 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:50:46 PM PDT 24 |
2158277430 ps |
| T934 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1078920911 |
|
|
Mar 17 12:46:28 PM PDT 24 |
Mar 17 12:46:29 PM PDT 24 |
27014724 ps |
| T935 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.450252768 |
|
|
Mar 17 12:46:56 PM PDT 24 |
Mar 17 12:54:03 PM PDT 24 |
16989256632 ps |
| T936 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1173955843 |
|
|
Mar 17 12:48:05 PM PDT 24 |
Mar 17 02:39:29 PM PDT 24 |
53540558616 ps |
| T937 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.4229321100 |
|
|
Mar 17 12:47:28 PM PDT 24 |
Mar 17 12:47:34 PM PDT 24 |
927528024 ps |
| T938 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1495716744 |
|
|
Mar 17 12:47:00 PM PDT 24 |
Mar 17 12:51:48 PM PDT 24 |
13006287610 ps |
| T939 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.1241424481 |
|
|
Mar 17 12:47:46 PM PDT 24 |
Mar 17 12:47:54 PM PDT 24 |
2458813970 ps |
| T940 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.325733311 |
|
|
Mar 17 12:47:59 PM PDT 24 |
Mar 17 12:58:32 PM PDT 24 |
50076953618 ps |
| T941 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.4163066489 |
|
|
Mar 17 12:49:08 PM PDT 24 |
Mar 17 12:49:11 PM PDT 24 |
171677350 ps |
| T93 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2300469158 |
|
|
Mar 17 01:04:10 PM PDT 24 |
Mar 17 01:04:15 PM PDT 24 |
6260687611 ps |
| T942 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4122271492 |
|
|
Mar 17 01:03:52 PM PDT 24 |
Mar 17 01:03:53 PM PDT 24 |
58796813 ps |
| T94 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2490077699 |
|
|
Mar 17 01:03:56 PM PDT 24 |
Mar 17 01:03:58 PM PDT 24 |
98908004 ps |
| T102 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3597945727 |
|
|
Mar 17 01:03:52 PM PDT 24 |
Mar 17 01:03:54 PM PDT 24 |
367655435 ps |
| T56 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.824013166 |
|
|
Mar 17 01:03:42 PM PDT 24 |
Mar 17 01:03:43 PM PDT 24 |
19524261 ps |
| T57 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3876450534 |
|
|
Mar 17 01:03:42 PM PDT 24 |
Mar 17 01:03:45 PM PDT 24 |
809404617 ps |
| T943 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.730534431 |
|
|
Mar 17 01:03:41 PM PDT 24 |
Mar 17 01:03:45 PM PDT 24 |
910875475 ps |
| T58 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.791751446 |
|
|
Mar 17 01:04:00 PM PDT 24 |
Mar 17 01:04:01 PM PDT 24 |
14872545 ps |
| T59 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1153421935 |
|
|
Mar 17 01:04:11 PM PDT 24 |
Mar 17 01:04:12 PM PDT 24 |
28756546 ps |
| T60 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1044879706 |
|
|
Mar 17 01:03:40 PM PDT 24 |
Mar 17 01:03:41 PM PDT 24 |
79816113 ps |
| T61 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4104061446 |
|
|
Mar 17 01:03:44 PM PDT 24 |
Mar 17 01:03:45 PM PDT 24 |
14001483 ps |
| T103 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3919449436 |
|
|
Mar 17 01:03:56 PM PDT 24 |
Mar 17 01:04:00 PM PDT 24 |
251494721 ps |
| T104 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3476730874 |
|
|
Mar 17 01:04:18 PM PDT 24 |
Mar 17 01:04:21 PM PDT 24 |
377633270 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1325739416 |
|
|
Mar 17 01:03:53 PM PDT 24 |
Mar 17 01:03:56 PM PDT 24 |
127131948 ps |
| T62 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3693959151 |
|
|
Mar 17 01:03:42 PM PDT 24 |
Mar 17 01:03:45 PM PDT 24 |
513003532 ps |
| T101 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2860206376 |
|
|
Mar 17 01:03:56 PM PDT 24 |
Mar 17 01:03:57 PM PDT 24 |
29584377 ps |
| T945 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.46719840 |
|
|
Mar 17 01:04:04 PM PDT 24 |
Mar 17 01:04:08 PM PDT 24 |
232094817 ps |
| T123 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2974071973 |
|
|
Mar 17 01:04:00 PM PDT 24 |
Mar 17 01:04:02 PM PDT 24 |
198835084 ps |
| T946 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2483524225 |
|
|
Mar 17 01:03:54 PM PDT 24 |
Mar 17 01:03:58 PM PDT 24 |
830957367 ps |
| T122 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3712487983 |
|
|
Mar 17 01:04:02 PM PDT 24 |
Mar 17 01:04:04 PM PDT 24 |
201809404 ps |
| T63 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3146367099 |
|
|
Mar 17 01:03:41 PM PDT 24 |
Mar 17 01:03:44 PM PDT 24 |
1783060237 ps |
| T95 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.728623175 |
|
|
Mar 17 01:03:49 PM PDT 24 |
Mar 17 01:03:49 PM PDT 24 |
39026546 ps |
| T64 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2100868321 |
|
|
Mar 17 01:04:08 PM PDT 24 |
Mar 17 01:04:09 PM PDT 24 |
38397366 ps |
| T65 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2436233644 |
|
|
Mar 17 01:04:19 PM PDT 24 |
Mar 17 01:04:20 PM PDT 24 |
37561232 ps |
| T947 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.208547288 |
|
|
Mar 17 01:03:47 PM PDT 24 |
Mar 17 01:03:50 PM PDT 24 |
2036829113 ps |
| T948 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2051076096 |
|
|
Mar 17 01:03:55 PM PDT 24 |
Mar 17 01:03:57 PM PDT 24 |
88103739 ps |
| T949 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1849080003 |
|
|
Mar 17 01:03:51 PM PDT 24 |
Mar 17 01:03:54 PM PDT 24 |
89690297 ps |
| T124 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3263986418 |
|
|
Mar 17 01:03:48 PM PDT 24 |
Mar 17 01:03:51 PM PDT 24 |
566873489 ps |
| T950 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2283208859 |
|
|
Mar 17 01:04:14 PM PDT 24 |
Mar 17 01:04:15 PM PDT 24 |
18719711 ps |
| T129 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2799954844 |
|
|
Mar 17 01:04:09 PM PDT 24 |
Mar 17 01:04:12 PM PDT 24 |
386904520 ps |
| T128 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2569523319 |
|
|
Mar 17 01:04:08 PM PDT 24 |
Mar 17 01:04:11 PM PDT 24 |
1993726138 ps |
| T951 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1944324770 |
|
|
Mar 17 01:04:06 PM PDT 24 |
Mar 17 01:04:08 PM PDT 24 |
37075490 ps |
| T131 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3592066875 |
|
|
Mar 17 01:03:46 PM PDT 24 |
Mar 17 01:03:47 PM PDT 24 |
93814736 ps |
| T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.16787342 |
|
|
Mar 17 01:03:42 PM PDT 24 |
Mar 17 01:03:44 PM PDT 24 |
86625282 ps |
| T953 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1919509146 |
|
|
Mar 17 01:03:42 PM PDT 24 |
Mar 17 01:03:43 PM PDT 24 |
118472799 ps |
| T125 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3873128546 |
|
|
Mar 17 01:04:13 PM PDT 24 |
Mar 17 01:04:15 PM PDT 24 |
779507018 ps |
| T954 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1720848234 |
|
|
Mar 17 01:04:13 PM PDT 24 |
Mar 17 01:04:14 PM PDT 24 |
43675008 ps |
| T955 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.530128500 |
|
|
Mar 17 01:04:13 PM PDT 24 |
Mar 17 01:04:16 PM PDT 24 |
68519221 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.890817909 |
|
|
Mar 17 01:03:41 PM PDT 24 |
Mar 17 01:03:42 PM PDT 24 |
18167295 ps |
| T126 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2070960 |
|
|
Mar 17 01:03:40 PM PDT 24 |
Mar 17 01:03:41 PM PDT 24 |
1131940920 ps |
| T957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3011721627 |
|
|
Mar 17 01:04:00 PM PDT 24 |
Mar 17 01:04:01 PM PDT 24 |
14564702 ps |
| T958 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4280607380 |
|
|
Mar 17 01:03:51 PM PDT 24 |
Mar 17 01:03:53 PM PDT 24 |
206280482 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2599268007 |
|
|
Mar 17 01:03:47 PM PDT 24 |
Mar 17 01:03:48 PM PDT 24 |
29112433 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.867590976 |
|
|
Mar 17 01:03:42 PM PDT 24 |
Mar 17 01:03:44 PM PDT 24 |
110956652 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4245486008 |
|
|
Mar 17 01:03:47 PM PDT 24 |
Mar 17 01:03:50 PM PDT 24 |
68099418 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2699180101 |
|
|
Mar 17 01:03:38 PM PDT 24 |
Mar 17 01:03:40 PM PDT 24 |
360202159 ps |
| T962 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3119138389 |
|
|
Mar 17 01:03:44 PM PDT 24 |
Mar 17 01:03:47 PM PDT 24 |
260874369 ps |
| T963 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3399388401 |
|
|
Mar 17 01:03:49 PM PDT 24 |
Mar 17 01:03:52 PM PDT 24 |
32789603 ps |
| T69 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1782882411 |
|
|
Mar 17 01:04:12 PM PDT 24 |
Mar 17 01:04:16 PM PDT 24 |
1546233386 ps |
| T70 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.659336161 |
|
|
Mar 17 01:03:54 PM PDT 24 |
Mar 17 01:03:57 PM PDT 24 |
1778824357 ps |
| T71 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.676849127 |
|
|
Mar 17 01:03:45 PM PDT 24 |
Mar 17 01:03:47 PM PDT 24 |
328684914 ps |
| T72 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3144032701 |
|
|
Mar 17 01:03:51 PM PDT 24 |
Mar 17 01:03:52 PM PDT 24 |
46280518 ps |
| T964 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2424942982 |
|
|
Mar 17 01:04:02 PM PDT 24 |
Mar 17 01:04:04 PM PDT 24 |
169501372 ps |
| T965 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3818418913 |
|
|
Mar 17 01:04:12 PM PDT 24 |
Mar 17 01:04:13 PM PDT 24 |
35637899 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4042605087 |
|
|
Mar 17 01:03:51 PM PDT 24 |
Mar 17 01:03:52 PM PDT 24 |
106136586 ps |
| T84 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.245645126 |
|
|
Mar 17 01:03:42 PM PDT 24 |
Mar 17 01:03:43 PM PDT 24 |
30372394 ps |
| T132 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1631428356 |
|
|
Mar 17 01:03:46 PM PDT 24 |
Mar 17 01:03:49 PM PDT 24 |
592660367 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3951228775 |
|
|
Mar 17 01:03:39 PM PDT 24 |
Mar 17 01:03:41 PM PDT 24 |
67582121 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2467466328 |
|
|
Mar 17 01:03:50 PM PDT 24 |
Mar 17 01:03:52 PM PDT 24 |
32119109 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4243857296 |
|
|
Mar 17 01:03:47 PM PDT 24 |
Mar 17 01:03:49 PM PDT 24 |
77140951 ps |
| T970 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4194610277 |
|
|
Mar 17 01:03:50 PM PDT 24 |
Mar 17 01:03:52 PM PDT 24 |
20285140 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3926842789 |
|
|
Mar 17 01:03:55 PM PDT 24 |
Mar 17 01:03:58 PM PDT 24 |
33989921 ps |
| T133 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4229463315 |
|
|
Mar 17 01:03:43 PM PDT 24 |
Mar 17 01:03:44 PM PDT 24 |
117157117 ps |
| T972 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2183185200 |
|
|
Mar 17 01:04:12 PM PDT 24 |
Mar 17 01:04:13 PM PDT 24 |
32473151 ps |
| T973 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.664806700 |
|
|
Mar 17 01:03:54 PM PDT 24 |
Mar 17 01:03:57 PM PDT 24 |
37787794 ps |
| T127 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1721741375 |
|
|
Mar 17 01:04:13 PM PDT 24 |
Mar 17 01:04:14 PM PDT 24 |
461313735 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1896283692 |
|
|
Mar 17 01:03:54 PM PDT 24 |
Mar 17 01:03:56 PM PDT 24 |
30693287 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3867191395 |
|
|
Mar 17 01:03:56 PM PDT 24 |
Mar 17 01:03:57 PM PDT 24 |
17765221 ps |
| T134 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3455383455 |
|
|
Mar 17 01:03:51 PM PDT 24 |
Mar 17 01:03:54 PM PDT 24 |
2606955437 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2339488503 |
|
|
Mar 17 01:03:40 PM PDT 24 |
Mar 17 01:03:41 PM PDT 24 |
67085979 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2409575791 |
|
|
Mar 17 01:03:41 PM PDT 24 |
Mar 17 01:03:42 PM PDT 24 |
36509616 ps |
| T978 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3712099167 |
|
|
Mar 17 01:03:41 PM PDT 24 |
Mar 17 01:03:42 PM PDT 24 |
28092505 ps |
| T85 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1067833684 |
|
|
Mar 17 01:03:53 PM PDT 24 |
Mar 17 01:03:54 PM PDT 24 |
35556353 ps |
| T979 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4084719732 |
|
|
Mar 17 01:03:51 PM PDT 24 |
Mar 17 01:03:52 PM PDT 24 |
59400172 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3036496748 |
|
|
Mar 17 01:03:56 PM PDT 24 |
Mar 17 01:03:58 PM PDT 24 |
187427333 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1316945209 |
|
|
Mar 17 01:03:39 PM PDT 24 |
Mar 17 01:03:41 PM PDT 24 |
43439147 ps |
| T982 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.860708234 |
|
|
Mar 17 01:04:00 PM PDT 24 |
Mar 17 01:04:02 PM PDT 24 |
109182086 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2963163990 |
|
|
Mar 17 01:03:48 PM PDT 24 |
Mar 17 01:03:49 PM PDT 24 |
48482804 ps |
| T984 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1090456390 |
|
|
Mar 17 01:04:11 PM PDT 24 |
Mar 17 01:04:12 PM PDT 24 |
30964445 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2666511399 |
|
|
Mar 17 01:03:42 PM PDT 24 |
Mar 17 01:03:44 PM PDT 24 |
461858945 ps |
| T986 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3491584201 |
|
|
Mar 17 01:03:45 PM PDT 24 |
Mar 17 01:03:46 PM PDT 24 |
47877497 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1046766882 |
|
|
Mar 17 01:04:05 PM PDT 24 |
Mar 17 01:04:08 PM PDT 24 |
502341906 ps |
| T86 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4181736743 |
|
|
Mar 17 01:03:56 PM PDT 24 |
Mar 17 01:03:58 PM PDT 24 |
237198932 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2312864208 |
|
|
Mar 17 01:03:41 PM PDT 24 |
Mar 17 01:03:43 PM PDT 24 |
59419855 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1176980641 |
|
|
Mar 17 01:03:56 PM PDT 24 |
Mar 17 01:03:57 PM PDT 24 |
14359336 ps |
| T990 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3939456797 |
|
|
Mar 17 01:04:11 PM PDT 24 |
Mar 17 01:04:11 PM PDT 24 |
22043781 ps |
| T991 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1825845995 |
|
|
Mar 17 01:04:02 PM PDT 24 |
Mar 17 01:04:03 PM PDT 24 |
43907168 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2106146780 |
|
|
Mar 17 01:03:42 PM PDT 24 |
Mar 17 01:03:43 PM PDT 24 |
20847051 ps |
| T993 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.864380554 |
|
|
Mar 17 01:03:56 PM PDT 24 |
Mar 17 01:03:59 PM PDT 24 |
118548397 ps |
| T994 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2001712465 |
|
|
Mar 17 01:03:49 PM PDT 24 |
Mar 17 01:03:54 PM PDT 24 |
135409314 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1592104771 |
|
|
Mar 17 01:03:41 PM PDT 24 |
Mar 17 01:03:42 PM PDT 24 |
150275255 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2966138375 |
|
|
Mar 17 01:03:59 PM PDT 24 |
Mar 17 01:04:00 PM PDT 24 |
46140183 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3260244046 |
|
|
Mar 17 01:03:41 PM PDT 24 |
Mar 17 01:03:41 PM PDT 24 |
36265227 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3189944682 |
|
|
Mar 17 01:03:43 PM PDT 24 |
Mar 17 01:03:44 PM PDT 24 |
168468396 ps |
| T130 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2167589329 |
|
|
Mar 17 01:03:50 PM PDT 24 |
Mar 17 01:03:52 PM PDT 24 |
444972561 ps |
| T997 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.691165268 |
|
|
Mar 17 01:04:17 PM PDT 24 |
Mar 17 01:04:19 PM PDT 24 |
32563934 ps |
| T998 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.216143799 |
|
|
Mar 17 01:03:57 PM PDT 24 |
Mar 17 01:03:58 PM PDT 24 |
14527845 ps |
| T999 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1913536892 |
|
|
Mar 17 01:04:11 PM PDT 24 |
Mar 17 01:04:12 PM PDT 24 |
46820979 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2107373637 |
|
|
Mar 17 01:03:55 PM PDT 24 |
Mar 17 01:03:57 PM PDT 24 |
139096556 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2392618792 |
|
|
Mar 17 01:03:44 PM PDT 24 |
Mar 17 01:03:48 PM PDT 24 |
190410958 ps |
| T1002 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3210492509 |
|
|
Mar 17 01:04:02 PM PDT 24 |
Mar 17 01:04:03 PM PDT 24 |
16374443 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2105850915 |
|
|
Mar 17 01:03:45 PM PDT 24 |
Mar 17 01:03:46 PM PDT 24 |
27309086 ps |
| T1004 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1169699801 |
|
|
Mar 17 01:03:49 PM PDT 24 |
Mar 17 01:03:51 PM PDT 24 |
96017712 ps |