Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.36 100.00 97.77 100.00 100.00 99.71 99.70 98.33


Total test records in report: 1031
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T87 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1456114005 Mar 17 01:04:14 PM PDT 24 Mar 17 01:04:17 PM PDT 24 433921778 ps
T1005 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1565060791 Mar 17 01:04:00 PM PDT 24 Mar 17 01:04:01 PM PDT 24 65147380 ps
T1006 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3520248005 Mar 17 01:03:42 PM PDT 24 Mar 17 01:03:44 PM PDT 24 31598207 ps
T1007 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3553831579 Mar 17 01:03:52 PM PDT 24 Mar 17 01:03:53 PM PDT 24 63187017 ps
T1008 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1375483624 Mar 17 01:03:58 PM PDT 24 Mar 17 01:04:02 PM PDT 24 526123980 ps
T88 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.656986394 Mar 17 01:03:39 PM PDT 24 Mar 17 01:03:41 PM PDT 24 407622269 ps
T1009 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1309665616 Mar 17 01:03:50 PM PDT 24 Mar 17 01:03:51 PM PDT 24 52126357 ps
T1010 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4252973525 Mar 17 01:03:48 PM PDT 24 Mar 17 01:03:49 PM PDT 24 24720064 ps
T1011 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.727167063 Mar 17 01:04:07 PM PDT 24 Mar 17 01:04:08 PM PDT 24 33636527 ps
T1012 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1561701099 Mar 17 01:04:16 PM PDT 24 Mar 17 01:04:20 PM PDT 24 410487095 ps
T1013 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1533849856 Mar 17 01:03:41 PM PDT 24 Mar 17 01:03:43 PM PDT 24 157145859 ps
T1014 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3338923590 Mar 17 01:03:55 PM PDT 24 Mar 17 01:03:56 PM PDT 24 20748242 ps
T89 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1924712845 Mar 17 01:04:03 PM PDT 24 Mar 17 01:04:05 PM PDT 24 195791316 ps
T1015 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1801765722 Mar 17 01:04:07 PM PDT 24 Mar 17 01:04:08 PM PDT 24 31249233 ps
T92 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3444832964 Mar 17 01:04:13 PM PDT 24 Mar 17 01:04:16 PM PDT 24 831941352 ps
T1016 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3450212225 Mar 17 01:03:51 PM PDT 24 Mar 17 01:03:55 PM PDT 24 545309210 ps
T1017 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1562262109 Mar 17 01:04:05 PM PDT 24 Mar 17 01:04:06 PM PDT 24 55659287 ps
T1018 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2087886031 Mar 17 01:03:49 PM PDT 24 Mar 17 01:03:51 PM PDT 24 504111313 ps
T1019 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3964731539 Mar 17 01:03:42 PM PDT 24 Mar 17 01:03:43 PM PDT 24 52894085 ps
T1020 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3597565917 Mar 17 01:04:14 PM PDT 24 Mar 17 01:04:16 PM PDT 24 31847908 ps
T1021 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2994168740 Mar 17 01:03:39 PM PDT 24 Mar 17 01:03:40 PM PDT 24 39551733 ps
T1022 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1094350714 Mar 17 01:03:51 PM PDT 24 Mar 17 01:03:55 PM PDT 24 84310150 ps
T1023 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.740058598 Mar 17 01:04:07 PM PDT 24 Mar 17 01:04:08 PM PDT 24 55821230 ps
T1024 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1865583564 Mar 17 01:04:16 PM PDT 24 Mar 17 01:04:18 PM PDT 24 219186817 ps
T1025 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1452368457 Mar 17 01:03:44 PM PDT 24 Mar 17 01:03:46 PM PDT 24 1171529561 ps
T1026 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2978493529 Mar 17 01:03:56 PM PDT 24 Mar 17 01:03:57 PM PDT 24 95766637 ps
T1027 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.258959909 Mar 17 01:03:49 PM PDT 24 Mar 17 01:03:51 PM PDT 24 476828924 ps
T1028 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2133461150 Mar 17 01:03:40 PM PDT 24 Mar 17 01:03:42 PM PDT 24 77774984 ps
T1029 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1790508156 Mar 17 01:04:13 PM PDT 24 Mar 17 01:04:14 PM PDT 24 38787511 ps
T1030 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1948605562 Mar 17 01:03:40 PM PDT 24 Mar 17 01:03:40 PM PDT 24 147866544 ps
T1031 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.110129039 Mar 17 01:03:44 PM PDT 24 Mar 17 01:03:45 PM PDT 24 421745136 ps

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.4058842548
Short name T4
Test name
Test status
Simulation time 19884464754 ps
CPU time 1980.1 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 01:20:21 PM PDT 24
Peak memory 383252 kb
Host smart-0a4688d4-eafd-4ae9-a202-8556f5bb8fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058842548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.4058842548
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1083769935
Short name T18
Test name
Test status
Simulation time 4245882116 ps
CPU time 48.05 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:48:12 PM PDT 24
Peak memory 294528 kb
Host smart-1cc3793e-7482-4cf9-8c1e-158eb9e5b327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1083769935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1083769935
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.3447111390
Short name T9
Test name
Test status
Simulation time 6113098800 ps
CPU time 3.94 seconds
Started Mar 17 12:47:00 PM PDT 24
Finished Mar 17 12:47:04 PM PDT 24
Peak memory 222424 kb
Host smart-72d249be-7d4a-4aab-bff8-e654bb25e016
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447111390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.3447111390
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.3250235596
Short name T7
Test name
Test status
Simulation time 51261467968 ps
CPU time 1448.48 seconds
Started Mar 17 12:49:06 PM PDT 24
Finished Mar 17 01:13:14 PM PDT 24
Peak memory 382356 kb
Host smart-3afff57a-40cb-476f-bf6c-b18c0c82599c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250235596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.3250235596
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3476730874
Short name T104
Test name
Test status
Simulation time 377633270 ps
CPU time 2.27 seconds
Started Mar 17 01:04:18 PM PDT 24
Finished Mar 17 01:04:21 PM PDT 24
Peak memory 201832 kb
Host smart-225167b4-8ebc-4a0e-b4f5-da8b678f7551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476730874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.3476730874
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2494629255
Short name T34
Test name
Test status
Simulation time 16757380379 ps
CPU time 413.17 seconds
Started Mar 17 12:48:25 PM PDT 24
Finished Mar 17 12:55:18 PM PDT 24
Peak memory 203304 kb
Host smart-7fbc4077-2644-4d9c-9f85-ab1cc4e6d73a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494629255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.2494629255
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3876450534
Short name T57
Test name
Test status
Simulation time 809404617 ps
CPU time 3.13 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 201864 kb
Host smart-8aaf7a9f-4d26-47c5-9d90-71edc6be7c40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876450534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3876450534
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.3755921525
Short name T139
Test name
Test status
Simulation time 224146382264 ps
CPU time 6441.93 seconds
Started Mar 17 12:49:34 PM PDT 24
Finished Mar 17 02:36:57 PM PDT 24
Peak memory 377172 kb
Host smart-b1818226-271b-4290-a948-f564e0232870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755921525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.3755921525
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.267345704
Short name T22
Test name
Test status
Simulation time 6330775316 ps
CPU time 371.3 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:55:03 PM PDT 24
Peak memory 368992 kb
Host smart-43f8417c-dbc1-47b2-b566-edf179c0015f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267345704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.sram_ctrl_access_during_key_req.267345704
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.4253132334
Short name T13
Test name
Test status
Simulation time 31298799 ps
CPU time 0.74 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:47:22 PM PDT 24
Peak memory 203200 kb
Host smart-d97ea13c-06ad-4c23-ba90-bcedb0210f6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253132334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.4253132334
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2569523319
Short name T128
Test name
Test status
Simulation time 1993726138 ps
CPU time 2.53 seconds
Started Mar 17 01:04:08 PM PDT 24
Finished Mar 17 01:04:11 PM PDT 24
Peak memory 201824 kb
Host smart-bf234c09-f747-4700-92de-12450905602c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569523319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.2569523319
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2395911714
Short name T42
Test name
Test status
Simulation time 3450607292 ps
CPU time 124.7 seconds
Started Mar 17 12:47:54 PM PDT 24
Finished Mar 17 12:49:59 PM PDT 24
Peak memory 289284 kb
Host smart-882e9a03-e71e-47d8-8150-55c74a470259
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2395911714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2395911714
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.2000798863
Short name T12
Test name
Test status
Simulation time 40775545 ps
CPU time 0.63 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 202104 kb
Host smart-c80b8675-56e7-4534-b8e3-083de56811bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000798863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.2000798863
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.134741070
Short name T143
Test name
Test status
Simulation time 90919563032 ps
CPU time 3153.52 seconds
Started Mar 17 12:47:32 PM PDT 24
Finished Mar 17 01:40:06 PM PDT 24
Peak memory 373512 kb
Host smart-967a72ee-ec71-47e6-a8e1-9dc83b7d768c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134741070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_stress_all.134741070
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3873128546
Short name T125
Test name
Test status
Simulation time 779507018 ps
CPU time 2.15 seconds
Started Mar 17 01:04:13 PM PDT 24
Finished Mar 17 01:04:15 PM PDT 24
Peak memory 201828 kb
Host smart-262e2a38-d35e-4334-88a0-b378b56ba6a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873128546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.3873128546
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1721741375
Short name T127
Test name
Test status
Simulation time 461313735 ps
CPU time 1.53 seconds
Started Mar 17 01:04:13 PM PDT 24
Finished Mar 17 01:04:14 PM PDT 24
Peak memory 201796 kb
Host smart-6c76d65a-c58a-41ee-9f4d-3289e3501a56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721741375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.1721741375
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.488285452
Short name T119
Test name
Test status
Simulation time 35615466235 ps
CPU time 2650.82 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 01:31:39 PM PDT 24
Peak memory 383256 kb
Host smart-408b241b-5358-4e9c-ac35-bc06775e611d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488285452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_stress_all.488285452
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.245645126
Short name T84
Test name
Test status
Simulation time 30372394 ps
CPU time 0.69 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 200516 kb
Host smart-9d1d490c-3902-44e4-ab5d-c7bdfe76c0ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245645126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_aliasing.245645126
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2599268007
Short name T959
Test name
Test status
Simulation time 29112433 ps
CPU time 1.19 seconds
Started Mar 17 01:03:47 PM PDT 24
Finished Mar 17 01:03:48 PM PDT 24
Peak memory 201596 kb
Host smart-1feea823-376d-44b7-84fc-2d0434acec13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599268007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.2599268007
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2994168740
Short name T1021
Test name
Test status
Simulation time 39551733 ps
CPU time 0.78 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 200664 kb
Host smart-e4d54db0-a360-4349-8ef7-eefa213f9c44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994168740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.2994168740
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1948605562
Short name T1030
Test name
Test status
Simulation time 147866544 ps
CPU time 0.69 seconds
Started Mar 17 01:03:40 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 201528 kb
Host smart-2db521dd-ea42-4754-a292-d3d4e2af9fa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948605562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.1948605562
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3693959151
Short name T62
Test name
Test status
Simulation time 513003532 ps
CPU time 3.16 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 201900 kb
Host smart-6b88e4e8-0b20-4a61-aa77-7658d1aea7f4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693959151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3693959151
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4252973525
Short name T1010
Test name
Test status
Simulation time 24720064 ps
CPU time 0.66 seconds
Started Mar 17 01:03:48 PM PDT 24
Finished Mar 17 01:03:49 PM PDT 24
Peak memory 201560 kb
Host smart-4592822e-87f9-4166-a30f-2b500084b652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252973525 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.4252973525
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.730534431
Short name T943
Test name
Test status
Simulation time 910875475 ps
CPU time 3.73 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 201788 kb
Host smart-1886a703-9721-42b9-8d03-157c07b157a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730534431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_tl_errors.730534431
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1631428356
Short name T132
Test name
Test status
Simulation time 592660367 ps
CPU time 3.14 seconds
Started Mar 17 01:03:46 PM PDT 24
Finished Mar 17 01:03:49 PM PDT 24
Peak memory 201736 kb
Host smart-8cdb0abd-6974-4c3c-980d-d58581e9ff12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631428356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.1631428356
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2966138375
Short name T90
Test name
Test status
Simulation time 46140183 ps
CPU time 0.69 seconds
Started Mar 17 01:03:59 PM PDT 24
Finished Mar 17 01:04:00 PM PDT 24
Peak memory 201580 kb
Host smart-a28515f2-4fbf-494d-9e7d-95de416f348a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966138375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.2966138375
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2312864208
Short name T988
Test name
Test status
Simulation time 59419855 ps
CPU time 1.81 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 201692 kb
Host smart-a4a28b9e-6fff-404e-8fc6-a6f85c2f6e87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312864208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.2312864208
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4104061446
Short name T61
Test name
Test status
Simulation time 14001483 ps
CPU time 0.7 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 201528 kb
Host smart-e6698862-a71a-427f-b790-360a41654530
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104061446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.4104061446
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2339488503
Short name T976
Test name
Test status
Simulation time 67085979 ps
CPU time 1.48 seconds
Started Mar 17 01:03:40 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 210072 kb
Host smart-1f8e6d55-1d78-4a08-afb6-128ebf3df9bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339488503 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2339488503
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3260244046
Short name T91
Test name
Test status
Simulation time 36265227 ps
CPU time 0.61 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 200860 kb
Host smart-4c309a6f-9954-4ddc-8d56-7b4c86117e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260244046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.3260244046
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3964731539
Short name T1019
Test name
Test status
Simulation time 52894085 ps
CPU time 0.68 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 201164 kb
Host smart-63143d81-7066-4907-99ab-d18ba39682d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964731539 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3964731539
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1896283692
Short name T974
Test name
Test status
Simulation time 30693287 ps
CPU time 1.96 seconds
Started Mar 17 01:03:54 PM PDT 24
Finished Mar 17 01:03:56 PM PDT 24
Peak memory 201760 kb
Host smart-e1200398-7740-4524-b9fb-499f920e97c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896283692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.1896283692
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3592066875
Short name T131
Test name
Test status
Simulation time 93814736 ps
CPU time 1.42 seconds
Started Mar 17 01:03:46 PM PDT 24
Finished Mar 17 01:03:47 PM PDT 24
Peak memory 201796 kb
Host smart-a701db44-fe43-418f-b781-ef4290afba71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592066875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.3592066875
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2467466328
Short name T968
Test name
Test status
Simulation time 32119109 ps
CPU time 1.68 seconds
Started Mar 17 01:03:50 PM PDT 24
Finished Mar 17 01:03:52 PM PDT 24
Peak memory 211100 kb
Host smart-0e57ea9b-f744-4c2d-9550-821990d8b0e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467466328 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2467466328
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4042605087
Short name T966
Test name
Test status
Simulation time 106136586 ps
CPU time 0.64 seconds
Started Mar 17 01:03:51 PM PDT 24
Finished Mar 17 01:03:52 PM PDT 24
Peak memory 200500 kb
Host smart-c4df2866-eb77-4a6e-80ee-21f017f96413
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042605087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.4042605087
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1456114005
Short name T87
Test name
Test status
Simulation time 433921778 ps
CPU time 3.15 seconds
Started Mar 17 01:04:14 PM PDT 24
Finished Mar 17 01:04:17 PM PDT 24
Peak memory 201828 kb
Host smart-830883a0-4308-4915-90d8-c227ab9ebe27
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456114005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.1456114005
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3553831579
Short name T1007
Test name
Test status
Simulation time 63187017 ps
CPU time 0.71 seconds
Started Mar 17 01:03:52 PM PDT 24
Finished Mar 17 01:03:53 PM PDT 24
Peak memory 201616 kb
Host smart-e412cbf9-a8e6-4b1e-bfdd-02964729422d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553831579 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3553831579
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1561701099
Short name T1012
Test name
Test status
Simulation time 410487095 ps
CPU time 3.83 seconds
Started Mar 17 01:04:16 PM PDT 24
Finished Mar 17 01:04:20 PM PDT 24
Peak memory 201756 kb
Host smart-eb054ec4-36f5-4c65-9ece-cf50da5372f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561701099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.1561701099
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3597945727
Short name T102
Test name
Test status
Simulation time 367655435 ps
CPU time 1.51 seconds
Started Mar 17 01:03:52 PM PDT 24
Finished Mar 17 01:03:54 PM PDT 24
Peak memory 201860 kb
Host smart-c8999aa1-da79-41b8-a97d-9c9a4d1272f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597945727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.3597945727
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3926842789
Short name T971
Test name
Test status
Simulation time 33989921 ps
CPU time 2.07 seconds
Started Mar 17 01:03:55 PM PDT 24
Finished Mar 17 01:03:58 PM PDT 24
Peak memory 210312 kb
Host smart-76d0a3ce-7e87-40a1-b097-d80da3c2272c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926842789 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3926842789
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2978493529
Short name T1026
Test name
Test status
Simulation time 95766637 ps
CPU time 0.67 seconds
Started Mar 17 01:03:56 PM PDT 24
Finished Mar 17 01:03:57 PM PDT 24
Peak memory 201568 kb
Host smart-96e10ae6-f6ea-4f96-87a8-307befb5714f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978493529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.2978493529
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.258959909
Short name T1027
Test name
Test status
Simulation time 476828924 ps
CPU time 2 seconds
Started Mar 17 01:03:49 PM PDT 24
Finished Mar 17 01:03:51 PM PDT 24
Peak memory 201732 kb
Host smart-4c9d4e1d-4e99-473b-ad87-e0cf90c13958
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258959909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.258959909
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1825845995
Short name T991
Test name
Test status
Simulation time 43907168 ps
CPU time 0.72 seconds
Started Mar 17 01:04:02 PM PDT 24
Finished Mar 17 01:04:03 PM PDT 24
Peak memory 201620 kb
Host smart-b61800e1-0576-4f67-ae8d-529063f4eb20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825845995 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1825845995
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2001712465
Short name T994
Test name
Test status
Simulation time 135409314 ps
CPU time 4.17 seconds
Started Mar 17 01:03:49 PM PDT 24
Finished Mar 17 01:03:54 PM PDT 24
Peak memory 201860 kb
Host smart-37514fdb-415f-4e5a-8f51-940153a65337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001712465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.2001712465
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2974071973
Short name T123
Test name
Test status
Simulation time 198835084 ps
CPU time 1.49 seconds
Started Mar 17 01:04:00 PM PDT 24
Finished Mar 17 01:04:02 PM PDT 24
Peak memory 201776 kb
Host smart-50ad3e1c-5b0b-4aa1-b0f1-57fc056ffac7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974071973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.2974071973
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4084719732
Short name T979
Test name
Test status
Simulation time 59400172 ps
CPU time 1.06 seconds
Started Mar 17 01:03:51 PM PDT 24
Finished Mar 17 01:03:52 PM PDT 24
Peak memory 209732 kb
Host smart-c62aeaf6-1f57-4c52-b806-36a7137ff3e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084719732 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.4084719732
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3939456797
Short name T990
Test name
Test status
Simulation time 22043781 ps
CPU time 0.65 seconds
Started Mar 17 01:04:11 PM PDT 24
Finished Mar 17 01:04:11 PM PDT 24
Peak memory 201476 kb
Host smart-f6c027e5-52d7-4c1e-92d0-029c17909f02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939456797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.3939456797
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2300469158
Short name T93
Test name
Test status
Simulation time 6260687611 ps
CPU time 4.66 seconds
Started Mar 17 01:04:10 PM PDT 24
Finished Mar 17 01:04:15 PM PDT 24
Peak memory 201864 kb
Host smart-d63306e4-d99d-4abe-a755-e0dc6e902f46
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300469158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2300469158
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1801765722
Short name T1015
Test name
Test status
Simulation time 31249233 ps
CPU time 0.79 seconds
Started Mar 17 01:04:07 PM PDT 24
Finished Mar 17 01:04:08 PM PDT 24
Peak memory 201532 kb
Host smart-27578863-9c4c-4f43-9fe5-da7da8a4cbf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801765722 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1801765722
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1375483624
Short name T1008
Test name
Test status
Simulation time 526123980 ps
CPU time 4.41 seconds
Started Mar 17 01:03:58 PM PDT 24
Finished Mar 17 01:04:02 PM PDT 24
Peak memory 209976 kb
Host smart-e6a951e0-ac05-4d12-b0a0-b38dbc539e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375483624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.1375483624
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.740058598
Short name T1023
Test name
Test status
Simulation time 55821230 ps
CPU time 1.09 seconds
Started Mar 17 01:04:07 PM PDT 24
Finished Mar 17 01:04:08 PM PDT 24
Peak memory 209760 kb
Host smart-4561fb2e-5dfc-4ddd-b546-6f82396eaee2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740058598 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.740058598
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3210492509
Short name T1002
Test name
Test status
Simulation time 16374443 ps
CPU time 0.65 seconds
Started Mar 17 01:04:02 PM PDT 24
Finished Mar 17 01:04:03 PM PDT 24
Peak memory 201404 kb
Host smart-c16643b1-4d50-49af-8910-95420c841e53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210492509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.3210492509
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4181736743
Short name T86
Test name
Test status
Simulation time 237198932 ps
CPU time 1.92 seconds
Started Mar 17 01:03:56 PM PDT 24
Finished Mar 17 01:03:58 PM PDT 24
Peak memory 201680 kb
Host smart-cd3093fa-a1bc-4a1e-bf5f-3552d125f0be
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181736743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.4181736743
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1562262109
Short name T1017
Test name
Test status
Simulation time 55659287 ps
CPU time 0.69 seconds
Started Mar 17 01:04:05 PM PDT 24
Finished Mar 17 01:04:06 PM PDT 24
Peak memory 200936 kb
Host smart-d42efc08-5744-4c8f-8e77-f795310902c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562262109 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.1562262109
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.530128500
Short name T955
Test name
Test status
Simulation time 68519221 ps
CPU time 2.42 seconds
Started Mar 17 01:04:13 PM PDT 24
Finished Mar 17 01:04:16 PM PDT 24
Peak memory 201780 kb
Host smart-931daf05-946a-4b99-beb7-9097b382c510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530128500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_tl_errors.530128500
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3455383455
Short name T134
Test name
Test status
Simulation time 2606955437 ps
CPU time 2.22 seconds
Started Mar 17 01:03:51 PM PDT 24
Finished Mar 17 01:03:54 PM PDT 24
Peak memory 201852 kb
Host smart-44a90e50-06ba-47d6-9505-7a02b5aec622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455383455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.3455383455
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.860708234
Short name T982
Test name
Test status
Simulation time 109182086 ps
CPU time 1.4 seconds
Started Mar 17 01:04:00 PM PDT 24
Finished Mar 17 01:04:02 PM PDT 24
Peak memory 211016 kb
Host smart-64355ef6-70c7-4675-a99d-9fb4e281ea99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860708234 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.860708234
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.791751446
Short name T58
Test name
Test status
Simulation time 14872545 ps
CPU time 0.63 seconds
Started Mar 17 01:04:00 PM PDT 24
Finished Mar 17 01:04:01 PM PDT 24
Peak memory 201540 kb
Host smart-695c93a7-a1ac-4ad1-b8c5-68f111120bb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791751446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 14.sram_ctrl_csr_rw.791751446
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1865583564
Short name T1024
Test name
Test status
Simulation time 219186817 ps
CPU time 1.91 seconds
Started Mar 17 01:04:16 PM PDT 24
Finished Mar 17 01:04:18 PM PDT 24
Peak memory 201636 kb
Host smart-50df1120-66ec-4e1b-874f-b039aa66e008
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865583564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1865583564
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2436233644
Short name T65
Test name
Test status
Simulation time 37561232 ps
CPU time 0.7 seconds
Started Mar 17 01:04:19 PM PDT 24
Finished Mar 17 01:04:20 PM PDT 24
Peak memory 201536 kb
Host smart-e2fa11aa-e216-47cd-b4f8-1864b4644fcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436233644 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.2436233644
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1849080003
Short name T949
Test name
Test status
Simulation time 89690297 ps
CPU time 2.84 seconds
Started Mar 17 01:03:51 PM PDT 24
Finished Mar 17 01:03:54 PM PDT 24
Peak memory 201856 kb
Host smart-9de07b8f-d1d5-44f1-8105-6ad98e532bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849080003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.1849080003
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2424942982
Short name T964
Test name
Test status
Simulation time 169501372 ps
CPU time 1.53 seconds
Started Mar 17 01:04:02 PM PDT 24
Finished Mar 17 01:04:04 PM PDT 24
Peak memory 211104 kb
Host smart-eb593755-4f8e-4a8d-a9ad-1c96d94bfbb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424942982 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2424942982
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2283208859
Short name T950
Test name
Test status
Simulation time 18719711 ps
CPU time 0.65 seconds
Started Mar 17 01:04:14 PM PDT 24
Finished Mar 17 01:04:15 PM PDT 24
Peak memory 201556 kb
Host smart-665b54a0-799b-4035-bf07-24e029a68cc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283208859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.2283208859
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3450212225
Short name T1016
Test name
Test status
Simulation time 545309210 ps
CPU time 3.65 seconds
Started Mar 17 01:03:51 PM PDT 24
Finished Mar 17 01:03:55 PM PDT 24
Peak memory 201800 kb
Host smart-11badc12-02da-4921-b51d-8be5747e9f57
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450212225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3450212225
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.216143799
Short name T998
Test name
Test status
Simulation time 14527845 ps
CPU time 0.75 seconds
Started Mar 17 01:03:57 PM PDT 24
Finished Mar 17 01:03:58 PM PDT 24
Peak memory 201532 kb
Host smart-bcae73f7-ee70-4587-90bf-e4290c1c777d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216143799 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.216143799
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3399388401
Short name T963
Test name
Test status
Simulation time 32789603 ps
CPU time 2.83 seconds
Started Mar 17 01:03:49 PM PDT 24
Finished Mar 17 01:03:52 PM PDT 24
Peak memory 201880 kb
Host smart-01c13010-90ce-4871-9b71-5fd367ddf654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399388401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.3399388401
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3712487983
Short name T122
Test name
Test status
Simulation time 201809404 ps
CPU time 2.35 seconds
Started Mar 17 01:04:02 PM PDT 24
Finished Mar 17 01:04:04 PM PDT 24
Peak memory 201792 kb
Host smart-e3af8f87-79a6-4c34-9dcf-839d54696cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712487983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.3712487983
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3597565917
Short name T1020
Test name
Test status
Simulation time 31847908 ps
CPU time 1.67 seconds
Started Mar 17 01:04:14 PM PDT 24
Finished Mar 17 01:04:16 PM PDT 24
Peak memory 210008 kb
Host smart-fdf16b48-e652-4a93-b543-ca3f5b860659
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597565917 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3597565917
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2860206376
Short name T101
Test name
Test status
Simulation time 29584377 ps
CPU time 0.67 seconds
Started Mar 17 01:03:56 PM PDT 24
Finished Mar 17 01:03:57 PM PDT 24
Peak memory 201612 kb
Host smart-fdd556f2-6c00-4a6a-af64-2ac726f139a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860206376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.2860206376
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3444832964
Short name T92
Test name
Test status
Simulation time 831941352 ps
CPU time 2.94 seconds
Started Mar 17 01:04:13 PM PDT 24
Finished Mar 17 01:04:16 PM PDT 24
Peak memory 201796 kb
Host smart-8062ff62-ecd3-45e2-adbb-b53cc5470f0e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444832964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.3444832964
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2490077699
Short name T94
Test name
Test status
Simulation time 98908004 ps
CPU time 0.85 seconds
Started Mar 17 01:03:56 PM PDT 24
Finished Mar 17 01:03:58 PM PDT 24
Peak memory 201656 kb
Host smart-23bd91d0-24f7-432b-b134-e2202fee92a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490077699 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2490077699
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.664806700
Short name T973
Test name
Test status
Simulation time 37787794 ps
CPU time 1.97 seconds
Started Mar 17 01:03:54 PM PDT 24
Finished Mar 17 01:03:57 PM PDT 24
Peak memory 201872 kb
Host smart-17f878c7-3192-498c-97b1-082d04a59851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664806700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.664806700
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1309665616
Short name T1009
Test name
Test status
Simulation time 52126357 ps
CPU time 0.9 seconds
Started Mar 17 01:03:50 PM PDT 24
Finished Mar 17 01:03:51 PM PDT 24
Peak memory 201624 kb
Host smart-19178449-cc7e-409f-bc08-7c7c1e02772a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309665616 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1309665616
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3818418913
Short name T965
Test name
Test status
Simulation time 35637899 ps
CPU time 0.68 seconds
Started Mar 17 01:04:12 PM PDT 24
Finished Mar 17 01:04:13 PM PDT 24
Peak memory 201504 kb
Host smart-e91394cc-70e3-477d-8e1c-3efea58e1eb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818418913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.3818418913
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2087886031
Short name T1018
Test name
Test status
Simulation time 504111313 ps
CPU time 1.93 seconds
Started Mar 17 01:03:49 PM PDT 24
Finished Mar 17 01:03:51 PM PDT 24
Peak memory 201716 kb
Host smart-7461a24b-08be-40a3-91a1-f4f58fa025d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087886031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2087886031
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.728623175
Short name T95
Test name
Test status
Simulation time 39026546 ps
CPU time 0.63 seconds
Started Mar 17 01:03:49 PM PDT 24
Finished Mar 17 01:03:49 PM PDT 24
Peak memory 200940 kb
Host smart-0ec2efce-c7d6-4e66-ab1b-572bd3f0a8a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728623175 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.728623175
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1094350714
Short name T1022
Test name
Test status
Simulation time 84310150 ps
CPU time 4.36 seconds
Started Mar 17 01:03:51 PM PDT 24
Finished Mar 17 01:03:55 PM PDT 24
Peak memory 201860 kb
Host smart-ce8d09b9-c153-4196-ade0-949f38bef95f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094350714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1094350714
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1046766882
Short name T987
Test name
Test status
Simulation time 502341906 ps
CPU time 2.46 seconds
Started Mar 17 01:04:05 PM PDT 24
Finished Mar 17 01:04:08 PM PDT 24
Peak memory 201860 kb
Host smart-99f4071b-117a-4649-80f6-f15f8af8867e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046766882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.1046766882
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4122271492
Short name T942
Test name
Test status
Simulation time 58796813 ps
CPU time 1.31 seconds
Started Mar 17 01:03:52 PM PDT 24
Finished Mar 17 01:03:53 PM PDT 24
Peak memory 209944 kb
Host smart-4f48579b-9297-4343-8f64-74aea7644857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122271492 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.4122271492
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.727167063
Short name T1011
Test name
Test status
Simulation time 33636527 ps
CPU time 0.68 seconds
Started Mar 17 01:04:07 PM PDT 24
Finished Mar 17 01:04:08 PM PDT 24
Peak memory 201596 kb
Host smart-ff4d7447-cc3e-4651-b311-2483167ca575
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727167063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.sram_ctrl_csr_rw.727167063
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1782882411
Short name T69
Test name
Test status
Simulation time 1546233386 ps
CPU time 3.34 seconds
Started Mar 17 01:04:12 PM PDT 24
Finished Mar 17 01:04:16 PM PDT 24
Peak memory 201852 kb
Host smart-911514aa-f6f9-4729-ac2a-1d96e6bdb422
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782882411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1782882411
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1153421935
Short name T59
Test name
Test status
Simulation time 28756546 ps
CPU time 0.68 seconds
Started Mar 17 01:04:11 PM PDT 24
Finished Mar 17 01:04:12 PM PDT 24
Peak memory 201620 kb
Host smart-36597367-89c3-4dfe-9046-6edd25daa5d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153421935 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1153421935
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2051076096
Short name T948
Test name
Test status
Simulation time 88103739 ps
CPU time 1.93 seconds
Started Mar 17 01:03:55 PM PDT 24
Finished Mar 17 01:03:57 PM PDT 24
Peak memory 201852 kb
Host smart-72396e54-7d85-41ac-9f6b-e0b0791f8ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051076096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.2051076096
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.691165268
Short name T997
Test name
Test status
Simulation time 32563934 ps
CPU time 1.77 seconds
Started Mar 17 01:04:17 PM PDT 24
Finished Mar 17 01:04:19 PM PDT 24
Peak memory 210988 kb
Host smart-ae67da58-5324-4c6f-8c3f-e5b19f38570a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691165268 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.691165268
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3011721627
Short name T957
Test name
Test status
Simulation time 14564702 ps
CPU time 0.64 seconds
Started Mar 17 01:04:00 PM PDT 24
Finished Mar 17 01:04:01 PM PDT 24
Peak memory 201544 kb
Host smart-bd37c4a0-c2c6-45c3-a78d-f19376abe1ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011721627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.3011721627
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1924712845
Short name T89
Test name
Test status
Simulation time 195791316 ps
CPU time 1.84 seconds
Started Mar 17 01:04:03 PM PDT 24
Finished Mar 17 01:04:05 PM PDT 24
Peak memory 201724 kb
Host smart-f7739251-b085-4955-9361-7743f62be88f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924712845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1924712845
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2100868321
Short name T64
Test name
Test status
Simulation time 38397366 ps
CPU time 0.77 seconds
Started Mar 17 01:04:08 PM PDT 24
Finished Mar 17 01:04:09 PM PDT 24
Peak memory 201644 kb
Host smart-f745cbbf-3077-4d34-8015-4957ac0253a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100868321 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2100868321
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.864380554
Short name T993
Test name
Test status
Simulation time 118548397 ps
CPU time 2.8 seconds
Started Mar 17 01:03:56 PM PDT 24
Finished Mar 17 01:03:59 PM PDT 24
Peak memory 201808 kb
Host smart-5e9c20c3-2de0-44a8-b006-f603f5b596be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864380554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_tl_errors.864380554
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3919449436
Short name T103
Test name
Test status
Simulation time 251494721 ps
CPU time 2.38 seconds
Started Mar 17 01:03:56 PM PDT 24
Finished Mar 17 01:04:00 PM PDT 24
Peak memory 201764 kb
Host smart-a54455a0-031e-4978-96ec-68003e857732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919449436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.3919449436
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.890817909
Short name T956
Test name
Test status
Simulation time 18167295 ps
CPU time 0.69 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 201452 kb
Host smart-67ce7e6c-fd06-40af-a5c0-0ddeb5de9a4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890817909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_aliasing.890817909
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1316945209
Short name T981
Test name
Test status
Simulation time 43439147 ps
CPU time 1.76 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 201756 kb
Host smart-70427f31-0f82-41bf-8dca-6e5d8217627a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316945209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.1316945209
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1592104771
Short name T995
Test name
Test status
Simulation time 150275255 ps
CPU time 0.64 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 201488 kb
Host smart-482486d8-540f-4020-902d-427cf0e627fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592104771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.1592104771
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1533849856
Short name T1013
Test name
Test status
Simulation time 157145859 ps
CPU time 1.5 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 209976 kb
Host smart-74cc5382-452f-49ff-9bce-47f9de066378
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533849856 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1533849856
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2106146780
Short name T992
Test name
Test status
Simulation time 20847051 ps
CPU time 0.71 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 201744 kb
Host smart-2d2cc0ca-968c-486c-9bde-16c43d413778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106146780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.2106146780
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.656986394
Short name T88
Test name
Test status
Simulation time 407622269 ps
CPU time 1.88 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 201660 kb
Host smart-3aa5c3ae-32be-4913-a5c1-9d67e4dd2ed0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656986394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.656986394
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1044879706
Short name T60
Test name
Test status
Simulation time 79816113 ps
CPU time 0.72 seconds
Started Mar 17 01:03:40 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 201648 kb
Host smart-04b5553e-d7df-4e4e-90c1-32a2f1822a9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044879706 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1044879706
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4243857296
Short name T969
Test name
Test status
Simulation time 77140951 ps
CPU time 1.67 seconds
Started Mar 17 01:03:47 PM PDT 24
Finished Mar 17 01:03:49 PM PDT 24
Peak memory 201796 kb
Host smart-3067fcef-f086-4044-a9cd-78b6bb2ebcfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243857296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.4243857296
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2070960
Short name T126
Test name
Test status
Simulation time 1131940920 ps
CPU time 1.48 seconds
Started Mar 17 01:03:40 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 201800 kb
Host smart-fba5a36d-d69c-4a2c-82b7-09a038ccd4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_tl_intg_err.2070960
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3338923590
Short name T1014
Test name
Test status
Simulation time 20748242 ps
CPU time 0.67 seconds
Started Mar 17 01:03:55 PM PDT 24
Finished Mar 17 01:03:56 PM PDT 24
Peak memory 201744 kb
Host smart-7a4a1bfa-8003-42f7-a148-26b8e03ec7ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338923590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.3338923590
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.16787342
Short name T952
Test name
Test status
Simulation time 86625282 ps
CPU time 1.85 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 201868 kb
Host smart-a0d663ac-c4bf-4d82-9ae3-4cec5c58c653
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16787342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_bit_bash.16787342
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2105850915
Short name T1003
Test name
Test status
Simulation time 27309086 ps
CPU time 0.6 seconds
Started Mar 17 01:03:45 PM PDT 24
Finished Mar 17 01:03:46 PM PDT 24
Peak memory 201544 kb
Host smart-35f702a7-46ab-48b8-8c0b-6183f2fc1a35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105850915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.2105850915
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2666511399
Short name T985
Test name
Test status
Simulation time 461858945 ps
CPU time 1.69 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 210524 kb
Host smart-da8e521f-1bbd-4f3c-b8ce-75de9c9a5673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666511399 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2666511399
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3867191395
Short name T975
Test name
Test status
Simulation time 17765221 ps
CPU time 0.64 seconds
Started Mar 17 01:03:56 PM PDT 24
Finished Mar 17 01:03:57 PM PDT 24
Peak memory 201496 kb
Host smart-36b76500-b7b5-49e9-9abb-9c673520a038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867191395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.3867191395
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.676849127
Short name T71
Test name
Test status
Simulation time 328684914 ps
CPU time 1.93 seconds
Started Mar 17 01:03:45 PM PDT 24
Finished Mar 17 01:03:47 PM PDT 24
Peak memory 201732 kb
Host smart-cd528db8-8e44-4939-9b69-b7483b78d07e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676849127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.676849127
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3491584201
Short name T986
Test name
Test status
Simulation time 47877497 ps
CPU time 0.71 seconds
Started Mar 17 01:03:45 PM PDT 24
Finished Mar 17 01:03:46 PM PDT 24
Peak memory 201664 kb
Host smart-1d5d77b3-3ec3-499c-9da5-3c37311b7811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491584201 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3491584201
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2392618792
Short name T1001
Test name
Test status
Simulation time 190410958 ps
CPU time 4.01 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:48 PM PDT 24
Peak memory 201800 kb
Host smart-636ca0cc-a884-4ebb-9267-18cf8eee9386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392618792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.2392618792
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.110129039
Short name T1031
Test name
Test status
Simulation time 421745136 ps
CPU time 1.53 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 201776 kb
Host smart-d0337935-ca09-4b64-9e04-c8f09d64c9fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110129039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.sram_ctrl_tl_intg_err.110129039
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2409575791
Short name T977
Test name
Test status
Simulation time 36509616 ps
CPU time 0.7 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 201500 kb
Host smart-d993cbfd-17a3-4c08-b777-b5d628c8f96b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409575791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.2409575791
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3036496748
Short name T980
Test name
Test status
Simulation time 187427333 ps
CPU time 1.46 seconds
Started Mar 17 01:03:56 PM PDT 24
Finished Mar 17 01:03:58 PM PDT 24
Peak memory 201704 kb
Host smart-be7bbc9e-7843-4a28-af59-0fb2867614cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036496748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3036496748
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3189944682
Short name T996
Test name
Test status
Simulation time 168468396 ps
CPU time 0.68 seconds
Started Mar 17 01:03:43 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 201480 kb
Host smart-e12784a9-a4ca-4dc5-a064-c134100f79c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189944682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.3189944682
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4245486008
Short name T961
Test name
Test status
Simulation time 68099418 ps
CPU time 2.81 seconds
Started Mar 17 01:03:47 PM PDT 24
Finished Mar 17 01:03:50 PM PDT 24
Peak memory 211132 kb
Host smart-61dcfff3-e255-4341-b4bb-04f78baa2cd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245486008 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.4245486008
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1176980641
Short name T989
Test name
Test status
Simulation time 14359336 ps
CPU time 0.66 seconds
Started Mar 17 01:03:56 PM PDT 24
Finished Mar 17 01:03:57 PM PDT 24
Peak memory 201568 kb
Host smart-ad541153-1e70-4e64-a60c-9d4fe5a069b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176980641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.1176980641
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2699180101
Short name T68
Test name
Test status
Simulation time 360202159 ps
CPU time 2.09 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 201708 kb
Host smart-69ee9006-7042-46c5-a766-bcf4e1aa0d2d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699180101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2699180101
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1919509146
Short name T953
Test name
Test status
Simulation time 118472799 ps
CPU time 0.76 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 201620 kb
Host smart-caeafe9d-61fe-4b9a-8363-3a2c28f1a218
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919509146 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1919509146
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3951228775
Short name T967
Test name
Test status
Simulation time 67582121 ps
CPU time 2.54 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 201776 kb
Host smart-4d79d22c-ba6b-41c1-b4c0-81e2a81e132b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951228775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.3951228775
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.867590976
Short name T960
Test name
Test status
Simulation time 110956652 ps
CPU time 1.5 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 201880 kb
Host smart-77cba865-8bb4-418c-a8ad-0e0da3a8764c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867590976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.sram_ctrl_tl_intg_err.867590976
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3520248005
Short name T1006
Test name
Test status
Simulation time 31598207 ps
CPU time 1.99 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 209900 kb
Host smart-e86dcc76-f591-47f0-a787-8d30ae6c40f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520248005 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3520248005
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.824013166
Short name T56
Test name
Test status
Simulation time 19524261 ps
CPU time 0.64 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 200476 kb
Host smart-d56bca84-1b21-472e-8dfe-4cc63c727960
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824013166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 5.sram_ctrl_csr_rw.824013166
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3146367099
Short name T63
Test name
Test status
Simulation time 1783060237 ps
CPU time 2.98 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 201884 kb
Host smart-aad01b7a-8ec7-4e9e-8e40-9313e6e39144
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146367099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3146367099
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3712099167
Short name T978
Test name
Test status
Simulation time 28092505 ps
CPU time 0.69 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 201576 kb
Host smart-6cebad9b-2faf-4faa-bc4f-887a6f60e8b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712099167 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3712099167
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3119138389
Short name T962
Test name
Test status
Simulation time 260874369 ps
CPU time 2.36 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:47 PM PDT 24
Peak memory 201784 kb
Host smart-adeecd82-20d6-4850-9506-48d0c3c6fc7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119138389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.3119138389
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4229463315
Short name T133
Test name
Test status
Simulation time 117157117 ps
CPU time 1.52 seconds
Started Mar 17 01:03:43 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 201764 kb
Host smart-4151bb47-f095-4f22-b9a1-ac273d473f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229463315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.4229463315
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2107373637
Short name T1000
Test name
Test status
Simulation time 139096556 ps
CPU time 1.33 seconds
Started Mar 17 01:03:55 PM PDT 24
Finished Mar 17 01:03:57 PM PDT 24
Peak memory 210060 kb
Host smart-e2c2e46d-0623-45ff-823c-db33acc30c0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107373637 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2107373637
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1090456390
Short name T984
Test name
Test status
Simulation time 30964445 ps
CPU time 0.63 seconds
Started Mar 17 01:04:11 PM PDT 24
Finished Mar 17 01:04:12 PM PDT 24
Peak memory 200904 kb
Host smart-b31d4483-c0bf-4708-a508-3e7179337ce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090456390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.1090456390
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1452368457
Short name T1025
Test name
Test status
Simulation time 1171529561 ps
CPU time 2.21 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:46 PM PDT 24
Peak memory 201860 kb
Host smart-a700d74c-6316-49a9-b70f-ddc82d663024
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452368457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.1452368457
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4194610277
Short name T970
Test name
Test status
Simulation time 20285140 ps
CPU time 0.77 seconds
Started Mar 17 01:03:50 PM PDT 24
Finished Mar 17 01:03:52 PM PDT 24
Peak memory 201576 kb
Host smart-756c82ba-2c04-42a8-a233-55ca9ebc456c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194610277 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.4194610277
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2133461150
Short name T1028
Test name
Test status
Simulation time 77774984 ps
CPU time 1.93 seconds
Started Mar 17 01:03:40 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 201816 kb
Host smart-be875297-feb2-4995-8a5a-3d43910015fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133461150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.2133461150
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1169699801
Short name T1004
Test name
Test status
Simulation time 96017712 ps
CPU time 1.37 seconds
Started Mar 17 01:03:49 PM PDT 24
Finished Mar 17 01:03:51 PM PDT 24
Peak memory 201852 kb
Host smart-da79bf6c-77b2-4605-afe2-2ddb7ad6021d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169699801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.1169699801
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1565060791
Short name T1005
Test name
Test status
Simulation time 65147380 ps
CPU time 1 seconds
Started Mar 17 01:04:00 PM PDT 24
Finished Mar 17 01:04:01 PM PDT 24
Peak memory 201724 kb
Host smart-7dad5721-cee0-478e-b702-c48ac180d679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565060791 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1565060791
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1913536892
Short name T999
Test name
Test status
Simulation time 46820979 ps
CPU time 0.63 seconds
Started Mar 17 01:04:11 PM PDT 24
Finished Mar 17 01:04:12 PM PDT 24
Peak memory 201560 kb
Host smart-a19989ac-9afc-4829-a55a-87996aae5ffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913536892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.1913536892
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4280607380
Short name T958
Test name
Test status
Simulation time 206280482 ps
CPU time 1.9 seconds
Started Mar 17 01:03:51 PM PDT 24
Finished Mar 17 01:03:53 PM PDT 24
Peak memory 201596 kb
Host smart-1c2701c4-d9a6-4da8-a08e-d1991e62e3f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280607380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.4280607380
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2963163990
Short name T983
Test name
Test status
Simulation time 48482804 ps
CPU time 0.76 seconds
Started Mar 17 01:03:48 PM PDT 24
Finished Mar 17 01:03:49 PM PDT 24
Peak memory 201560 kb
Host smart-fc72039b-343a-4663-97d6-2e6d0f5998bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963163990 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.2963163990
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1325739416
Short name T944
Test name
Test status
Simulation time 127131948 ps
CPU time 2.01 seconds
Started Mar 17 01:03:53 PM PDT 24
Finished Mar 17 01:03:56 PM PDT 24
Peak memory 201884 kb
Host smart-97a7b449-b112-40ef-9807-67442d5b85b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325739416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.1325739416
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2167589329
Short name T130
Test name
Test status
Simulation time 444972561 ps
CPU time 1.97 seconds
Started Mar 17 01:03:50 PM PDT 24
Finished Mar 17 01:03:52 PM PDT 24
Peak memory 201808 kb
Host smart-b22f8884-c82f-4efd-a70b-148a38e3db56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167589329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.2167589329
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2183185200
Short name T972
Test name
Test status
Simulation time 32473151 ps
CPU time 0.94 seconds
Started Mar 17 01:04:12 PM PDT 24
Finished Mar 17 01:04:13 PM PDT 24
Peak memory 210876 kb
Host smart-384c5a93-6c6d-4479-9f49-b720bace8eda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183185200 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2183185200
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1067833684
Short name T85
Test name
Test status
Simulation time 35556353 ps
CPU time 0.64 seconds
Started Mar 17 01:03:53 PM PDT 24
Finished Mar 17 01:03:54 PM PDT 24
Peak memory 200612 kb
Host smart-3c79d813-3d6b-4d9c-8e4e-658657088360
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067833684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.1067833684
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.208547288
Short name T947
Test name
Test status
Simulation time 2036829113 ps
CPU time 2.54 seconds
Started Mar 17 01:03:47 PM PDT 24
Finished Mar 17 01:03:50 PM PDT 24
Peak memory 201708 kb
Host smart-474015c2-10cb-4941-851c-58108aba5908
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208547288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.208547288
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1720848234
Short name T954
Test name
Test status
Simulation time 43675008 ps
CPU time 0.77 seconds
Started Mar 17 01:04:13 PM PDT 24
Finished Mar 17 01:04:14 PM PDT 24
Peak memory 201596 kb
Host smart-905b00ac-b726-432e-bb90-8925241c218d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720848234 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1720848234
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.46719840
Short name T945
Test name
Test status
Simulation time 232094817 ps
CPU time 3.57 seconds
Started Mar 17 01:04:04 PM PDT 24
Finished Mar 17 01:04:08 PM PDT 24
Peak memory 201792 kb
Host smart-495f66ae-e895-4732-9fad-c425f5e219fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46719840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST
_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_tl_errors.46719840
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2799954844
Short name T129
Test name
Test status
Simulation time 386904520 ps
CPU time 2.19 seconds
Started Mar 17 01:04:09 PM PDT 24
Finished Mar 17 01:04:12 PM PDT 24
Peak memory 201792 kb
Host smart-25247fb8-8035-4141-9f6a-085601c281fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799954844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.2799954844
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1944324770
Short name T951
Test name
Test status
Simulation time 37075490 ps
CPU time 2.34 seconds
Started Mar 17 01:04:06 PM PDT 24
Finished Mar 17 01:04:08 PM PDT 24
Peak memory 211144 kb
Host smart-d59e16bd-bcf8-4b7f-ba3e-7e82c89c9627
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944324770 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1944324770
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3144032701
Short name T72
Test name
Test status
Simulation time 46280518 ps
CPU time 0.64 seconds
Started Mar 17 01:03:51 PM PDT 24
Finished Mar 17 01:03:52 PM PDT 24
Peak memory 201396 kb
Host smart-212b5fdb-444a-4055-a8c8-64962e4e347f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144032701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.3144032701
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.659336161
Short name T70
Test name
Test status
Simulation time 1778824357 ps
CPU time 2.27 seconds
Started Mar 17 01:03:54 PM PDT 24
Finished Mar 17 01:03:57 PM PDT 24
Peak memory 201724 kb
Host smart-86edb6f0-8719-421a-9bc3-e563f7f79a30
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659336161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.659336161
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1790508156
Short name T1029
Test name
Test status
Simulation time 38787511 ps
CPU time 0.7 seconds
Started Mar 17 01:04:13 PM PDT 24
Finished Mar 17 01:04:14 PM PDT 24
Peak memory 201624 kb
Host smart-cefdb1b1-71bf-487f-993e-1002c0e16d60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790508156 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1790508156
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2483524225
Short name T946
Test name
Test status
Simulation time 830957367 ps
CPU time 4.75 seconds
Started Mar 17 01:03:54 PM PDT 24
Finished Mar 17 01:03:58 PM PDT 24
Peak memory 201728 kb
Host smart-c36a528e-e946-4cc6-b8b3-81cd2977a74e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483524225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.2483524225
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3263986418
Short name T124
Test name
Test status
Simulation time 566873489 ps
CPU time 2.13 seconds
Started Mar 17 01:03:48 PM PDT 24
Finished Mar 17 01:03:51 PM PDT 24
Peak memory 201880 kb
Host smart-6670466e-ade0-4e27-abd2-c2623d972a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263986418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.3263986418
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1377790856
Short name T552
Test name
Test status
Simulation time 1372661839 ps
CPU time 316.93 seconds
Started Mar 17 12:47:13 PM PDT 24
Finished Mar 17 12:52:30 PM PDT 24
Peak memory 351784 kb
Host smart-bbf822c8-13ea-4a25-ae4a-04de56f3d930
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377790856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1377790856
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.1970568613
Short name T771
Test name
Test status
Simulation time 43433653 ps
CPU time 0.62 seconds
Started Mar 17 12:46:31 PM PDT 24
Finished Mar 17 12:46:31 PM PDT 24
Peak memory 202932 kb
Host smart-ef964a0a-7ce2-41b5-86fa-06c854c2257c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970568613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.1970568613
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1178405351
Short name T779
Test name
Test status
Simulation time 10646872940 ps
CPU time 42.6 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 12:47:44 PM PDT 24
Peak memory 203196 kb
Host smart-3cb8c6b8-6c51-41a5-af80-6e93a9ff9b4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178405351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1178405351
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.3355496736
Short name T555
Test name
Test status
Simulation time 1900503316 ps
CPU time 513.35 seconds
Started Mar 17 12:46:30 PM PDT 24
Finished Mar 17 12:55:03 PM PDT 24
Peak memory 365548 kb
Host smart-a984cf02-fd33-4767-8d89-fabb2335f91d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355496736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.3355496736
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.646648793
Short name T844
Test name
Test status
Simulation time 2701742000 ps
CPU time 7.92 seconds
Started Mar 17 12:46:54 PM PDT 24
Finished Mar 17 12:47:03 PM PDT 24
Peak memory 203252 kb
Host smart-e0f9366a-484d-4fdb-a666-e8d14fdb4fe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646648793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca
lation.646648793
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.1501229324
Short name T878
Test name
Test status
Simulation time 93324043 ps
CPU time 27.21 seconds
Started Mar 17 12:46:51 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 292024 kb
Host smart-f90a188d-a5b7-4da1-9571-d52c852be047
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501229324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.1501229324
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2923435171
Short name T318
Test name
Test status
Simulation time 980040904 ps
CPU time 2.87 seconds
Started Mar 17 12:47:05 PM PDT 24
Finished Mar 17 12:47:08 PM PDT 24
Peak memory 211412 kb
Host smart-7c019a73-3b74-46a7-9a5e-c72ca4cb1902
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923435171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.2923435171
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.2874763095
Short name T311
Test name
Test status
Simulation time 138571169 ps
CPU time 8.29 seconds
Started Mar 17 12:46:58 PM PDT 24
Finished Mar 17 12:47:07 PM PDT 24
Peak memory 203172 kb
Host smart-1b2730a2-06d7-4bcf-8390-7b1af5630e90
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874763095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.2874763095
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.3560090948
Short name T269
Test name
Test status
Simulation time 48887136480 ps
CPU time 1052.95 seconds
Started Mar 17 12:46:53 PM PDT 24
Finished Mar 17 01:04:27 PM PDT 24
Peak memory 373864 kb
Host smart-5c31ce48-2798-4bbf-b83a-acea355e6408
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560090948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.3560090948
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.2343612233
Short name T179
Test name
Test status
Simulation time 146070349 ps
CPU time 1.4 seconds
Started Mar 17 12:46:58 PM PDT 24
Finished Mar 17 12:47:00 PM PDT 24
Peak memory 203208 kb
Host smart-8d560f23-154c-47fc-b832-ceda5f549209
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343612233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.2343612233
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1017446101
Short name T587
Test name
Test status
Simulation time 71604064450 ps
CPU time 397.38 seconds
Started Mar 17 12:46:39 PM PDT 24
Finished Mar 17 12:53:16 PM PDT 24
Peak memory 203296 kb
Host smart-42d7ede8-0f7c-4897-bb1b-45e0b374f32a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017446101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1017446101
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.1078920911
Short name T934
Test name
Test status
Simulation time 27014724 ps
CPU time 0.79 seconds
Started Mar 17 12:46:28 PM PDT 24
Finished Mar 17 12:46:29 PM PDT 24
Peak memory 203220 kb
Host smart-5eb02841-d952-48db-9d22-b753e700c7c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078920911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1078920911
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.1870648514
Short name T920
Test name
Test status
Simulation time 6216019123 ps
CPU time 625.49 seconds
Started Mar 17 12:46:39 PM PDT 24
Finished Mar 17 12:57:04 PM PDT 24
Peak memory 372928 kb
Host smart-103b97ad-3e00-4832-ae1c-05fe9c14262a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870648514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1870648514
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.1542003438
Short name T904
Test name
Test status
Simulation time 455590219 ps
CPU time 5.71 seconds
Started Mar 17 12:47:02 PM PDT 24
Finished Mar 17 12:47:08 PM PDT 24
Peak memory 203096 kb
Host smart-baebc10b-2cdf-4071-a3fd-55094e732d32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542003438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.1542003438
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.2977838395
Short name T436
Test name
Test status
Simulation time 11092381605 ps
CPU time 620.64 seconds
Started Mar 17 12:46:29 PM PDT 24
Finished Mar 17 12:56:50 PM PDT 24
Peak memory 382512 kb
Host smart-ab3bf6b7-bc97-430f-8bf3-fe6bcd61afa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977838395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.2977838395
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.836037902
Short name T105
Test name
Test status
Simulation time 3143479889 ps
CPU time 46.17 seconds
Started Mar 17 12:46:57 PM PDT 24
Finished Mar 17 12:47:43 PM PDT 24
Peak memory 300200 kb
Host smart-e14d9243-95ad-41c9-89c4-d90cd2511856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=836037902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.836037902
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2106617892
Short name T647
Test name
Test status
Simulation time 9676933459 ps
CPU time 235.52 seconds
Started Mar 17 12:46:30 PM PDT 24
Finished Mar 17 12:50:26 PM PDT 24
Peak memory 203296 kb
Host smart-a3afc7ee-7737-4990-8829-2939f7fb27a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106617892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.2106617892
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2353281020
Short name T767
Test name
Test status
Simulation time 59947741 ps
CPU time 0.94 seconds
Started Mar 17 12:46:27 PM PDT 24
Finished Mar 17 12:46:29 PM PDT 24
Peak memory 202868 kb
Host smart-22136dd9-c130-4715-b49b-45d19e6c85cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353281020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.2353281020
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.4019930284
Short name T851
Test name
Test status
Simulation time 10858108793 ps
CPU time 552.93 seconds
Started Mar 17 12:46:58 PM PDT 24
Finished Mar 17 12:56:11 PM PDT 24
Peak memory 365144 kb
Host smart-20f6e2b6-1418-4da4-b911-38953f3490b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019930284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.4019930284
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.3949808870
Short name T266
Test name
Test status
Simulation time 52812256 ps
CPU time 0.62 seconds
Started Mar 17 12:46:26 PM PDT 24
Finished Mar 17 12:46:26 PM PDT 24
Peak memory 202208 kb
Host smart-e6c6f30e-8bec-4687-b070-dabd2335c6bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949808870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.3949808870
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.2333397262
Short name T768
Test name
Test status
Simulation time 12664830151 ps
CPU time 50.51 seconds
Started Mar 17 12:46:31 PM PDT 24
Finished Mar 17 12:47:22 PM PDT 24
Peak memory 203104 kb
Host smart-0ffdf640-69c5-4eca-97d9-c10ee2767aa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333397262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
2333397262
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.1487683570
Short name T570
Test name
Test status
Simulation time 103146352860 ps
CPU time 944.29 seconds
Started Mar 17 12:46:37 PM PDT 24
Finished Mar 17 01:02:26 PM PDT 24
Peak memory 374132 kb
Host smart-4443be2e-44b8-468d-8f01-90426c2f9da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487683570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.1487683570
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.2522781928
Short name T606
Test name
Test status
Simulation time 380579441 ps
CPU time 5.24 seconds
Started Mar 17 12:47:16 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 203204 kb
Host smart-3b58378f-65d9-44e4-a75a-53e960165783
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522781928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.2522781928
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.1637918308
Short name T418
Test name
Test status
Simulation time 92881484 ps
CPU time 32.34 seconds
Started Mar 17 12:47:02 PM PDT 24
Finished Mar 17 12:47:34 PM PDT 24
Peak memory 294080 kb
Host smart-531ee218-839a-41d2-bf4a-217a36b81a99
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637918308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.1637918308
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1936548484
Short name T73
Test name
Test status
Simulation time 334699232 ps
CPU time 4.9 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 12:47:06 PM PDT 24
Peak memory 211424 kb
Host smart-6f3853fa-c2d0-42c0-9f3d-b079312720c9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936548484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.1936548484
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.2656655566
Short name T689
Test name
Test status
Simulation time 1323801770 ps
CPU time 5.37 seconds
Started Mar 17 12:46:30 PM PDT 24
Finished Mar 17 12:46:36 PM PDT 24
Peak memory 203132 kb
Host smart-f581c363-b6e5-4e2c-ad25-212267abe9b2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656655566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.2656655566
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.3578542464
Short name T856
Test name
Test status
Simulation time 40212029587 ps
CPU time 1106.82 seconds
Started Mar 17 12:46:35 PM PDT 24
Finished Mar 17 01:05:02 PM PDT 24
Peak memory 371840 kb
Host smart-2e8dbd29-9e38-4567-991a-abdfe3fad975
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578542464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.3578542464
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.3438377281
Short name T388
Test name
Test status
Simulation time 388076089 ps
CPU time 7.09 seconds
Started Mar 17 12:46:29 PM PDT 24
Finished Mar 17 12:46:36 PM PDT 24
Peak memory 203164 kb
Host smart-95e0a51e-c5ad-4485-a1f3-a7409a7d45bf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438377281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.3438377281
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3622664734
Short name T618
Test name
Test status
Simulation time 18747740762 ps
CPU time 328.86 seconds
Started Mar 17 12:46:53 PM PDT 24
Finished Mar 17 12:52:23 PM PDT 24
Peak memory 203264 kb
Host smart-469bdefd-ce49-4825-a695-7ec601b266ec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622664734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.3622664734
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.1027835932
Short name T161
Test name
Test status
Simulation time 122006754 ps
CPU time 0.76 seconds
Started Mar 17 12:47:07 PM PDT 24
Finished Mar 17 12:47:08 PM PDT 24
Peak memory 203136 kb
Host smart-4c27fa2a-6d58-406d-911f-779b37e69f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027835932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1027835932
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3143368467
Short name T818
Test name
Test status
Simulation time 6187267063 ps
CPU time 1264.34 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 01:08:06 PM PDT 24
Peak memory 374852 kb
Host smart-8a1514ab-fbd7-404b-877b-10964cc09789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143368467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3143368467
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.133203247
Short name T33
Test name
Test status
Simulation time 911946544 ps
CPU time 3.19 seconds
Started Mar 17 12:46:57 PM PDT 24
Finished Mar 17 12:47:00 PM PDT 24
Peak memory 222080 kb
Host smart-7a3fdd01-0b99-406e-a35c-9c22b072a3ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133203247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_sec_cm.133203247
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.578119343
Short name T585
Test name
Test status
Simulation time 217301865 ps
CPU time 9.11 seconds
Started Mar 17 12:46:26 PM PDT 24
Finished Mar 17 12:46:36 PM PDT 24
Peak memory 237852 kb
Host smart-2c760bde-6867-4e00-8ae4-bb6c52cd222a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578119343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.578119343
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4014916527
Short name T829
Test name
Test status
Simulation time 8447987452 ps
CPU time 213.08 seconds
Started Mar 17 12:46:56 PM PDT 24
Finished Mar 17 12:50:29 PM PDT 24
Peak memory 355284 kb
Host smart-b033251e-db12-439e-b685-d4de9aceba0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4014916527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.4014916527
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2100294556
Short name T696
Test name
Test status
Simulation time 2621342440 ps
CPU time 243.02 seconds
Started Mar 17 12:46:31 PM PDT 24
Finished Mar 17 12:50:34 PM PDT 24
Peak memory 203176 kb
Host smart-a3fa78d8-da37-4e8a-b426-1605b6a6f3ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100294556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.2100294556
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2183145495
Short name T641
Test name
Test status
Simulation time 502699143 ps
CPU time 61.67 seconds
Started Mar 17 12:46:29 PM PDT 24
Finished Mar 17 12:47:31 PM PDT 24
Peak memory 331068 kb
Host smart-884573ef-d49a-4cfb-bb80-72437fcc28a3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183145495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.2183145495
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2412757372
Short name T270
Test name
Test status
Simulation time 10325806226 ps
CPU time 564.82 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:56:48 PM PDT 24
Peak memory 364868 kb
Host smart-cdfa5f4a-3309-40ca-b8d4-74f9fe77b179
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412757372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.2412757372
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.1856920873
Short name T246
Test name
Test status
Simulation time 13444740 ps
CPU time 0.71 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 202988 kb
Host smart-2b1d0145-fa0b-430c-a133-d85aaa4b10da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856920873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.1856920873
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.89347332
Short name T660
Test name
Test status
Simulation time 282099180 ps
CPU time 14.19 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:47:43 PM PDT 24
Peak memory 203200 kb
Host smart-1553a9a3-c16f-4265-b3ff-50e51c9b16b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89347332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.89347332
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.2998241412
Short name T235
Test name
Test status
Simulation time 36702588896 ps
CPU time 539 seconds
Started Mar 17 12:47:15 PM PDT 24
Finished Mar 17 12:56:15 PM PDT 24
Peak memory 369868 kb
Host smart-c2f9a900-2ab6-46b4-bdc4-6b06089b79ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998241412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.2998241412
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.1668251333
Short name T337
Test name
Test status
Simulation time 2405420234 ps
CPU time 8.54 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:32 PM PDT 24
Peak memory 203196 kb
Host smart-5ddfdc96-fa68-4928-b1ce-85cdad7f5448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668251333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.1668251333
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.256161971
Short name T610
Test name
Test status
Simulation time 79437433 ps
CPU time 2.26 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 12:47:30 PM PDT 24
Peak memory 219268 kb
Host smart-b6bb23b3-9148-4577-bd5e-fb66c4123567
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256161971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.sram_ctrl_max_throughput.256161971
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.937100072
Short name T373
Test name
Test status
Simulation time 182412013 ps
CPU time 2.81 seconds
Started Mar 17 12:48:56 PM PDT 24
Finished Mar 17 12:48:59 PM PDT 24
Peak memory 211332 kb
Host smart-53890949-aa91-4996-bca3-81ecb37b8378
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937100072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.sram_ctrl_mem_partial_access.937100072
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.2142752546
Short name T725
Test name
Test status
Simulation time 450520074 ps
CPU time 8.87 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 12:49:04 PM PDT 24
Peak memory 203148 kb
Host smart-2d12d1ed-6b42-446f-ba4f-0023a0382fa1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142752546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.2142752546
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.3610744280
Short name T147
Test name
Test status
Simulation time 11248773277 ps
CPU time 1028.42 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 01:04:31 PM PDT 24
Peak memory 374912 kb
Host smart-63eb59d8-0743-4465-b5e8-6547db3976f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610744280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.3610744280
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.95878485
Short name T257
Test name
Test status
Simulation time 1205160505 ps
CPU time 17.23 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:40 PM PDT 24
Peak memory 203132 kb
Host smart-81e78101-ab73-4c05-a449-9372ba6dcbbb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95878485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sr
am_ctrl_partial_access.95878485
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3788653692
Short name T450
Test name
Test status
Simulation time 24204036144 ps
CPU time 339.04 seconds
Started Mar 17 12:48:40 PM PDT 24
Finished Mar 17 12:54:19 PM PDT 24
Peak memory 202704 kb
Host smart-233442a1-3d1f-4bb1-82f4-d651fa0d3615
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788653692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.3788653692
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.2305530958
Short name T749
Test name
Test status
Simulation time 77050911 ps
CPU time 0.74 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 203256 kb
Host smart-7ee139be-bf8a-4a20-bd3e-0b0826255b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305530958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2305530958
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1586072623
Short name T468
Test name
Test status
Simulation time 11472936351 ps
CPU time 82.64 seconds
Started Mar 17 12:48:39 PM PDT 24
Finished Mar 17 12:50:03 PM PDT 24
Peak memory 269304 kb
Host smart-30d04305-5108-4c2b-8fdd-40ce0b9039d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586072623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1586072623
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.301742342
Short name T157
Test name
Test status
Simulation time 1552498910 ps
CPU time 34.8 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:48:00 PM PDT 24
Peak memory 290000 kb
Host smart-5a7fcf5a-4f9e-4618-b600-62fd6a827a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301742342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.301742342
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.1823736707
Short name T307
Test name
Test status
Simulation time 13294333233 ps
CPU time 767.79 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 01:00:11 PM PDT 24
Peak memory 349272 kb
Host smart-74cc4091-a68d-43fe-9e85-402711504bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823736707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.1823736707
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4115246352
Short name T375
Test name
Test status
Simulation time 502992366 ps
CPU time 8.04 seconds
Started Mar 17 12:47:12 PM PDT 24
Finished Mar 17 12:47:20 PM PDT 24
Peak memory 211416 kb
Host smart-48bc1570-8f5a-4e14-9d5d-7d42db4a2bc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4115246352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.4115246352
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1486551801
Short name T629
Test name
Test status
Simulation time 3097543398 ps
CPU time 134.94 seconds
Started Mar 17 12:47:08 PM PDT 24
Finished Mar 17 12:49:23 PM PDT 24
Peak memory 203224 kb
Host smart-77c55500-60a0-4b53-bd64-0a7b8b436c01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486551801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.1486551801
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2450114444
Short name T346
Test name
Test status
Simulation time 294276048 ps
CPU time 25.14 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:47 PM PDT 24
Peak memory 289336 kb
Host smart-4ca9c13d-2b2d-4129-b2fc-cfe4921f6069
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450114444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2450114444
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.865360869
Short name T560
Test name
Test status
Simulation time 7821420267 ps
CPU time 1013.17 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 01:04:16 PM PDT 24
Peak memory 374972 kb
Host smart-20ec8b01-f919-4bd9-ab1b-f0d39aa411a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865360869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.sram_ctrl_access_during_key_req.865360869
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.574543547
Short name T864
Test name
Test status
Simulation time 17497866 ps
CPU time 0.62 seconds
Started Mar 17 12:47:16 PM PDT 24
Finished Mar 17 12:47:17 PM PDT 24
Peak memory 202028 kb
Host smart-7fa6d8f9-7e71-4137-b6f1-bf4d5915a299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574543547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.574543547
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.206689142
Short name T562
Test name
Test status
Simulation time 5302970346 ps
CPU time 24.07 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:47 PM PDT 24
Peak memory 203192 kb
Host smart-702a5246-241b-412f-9d4c-7d5bd34c9c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206689142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.
206689142
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.1243450326
Short name T843
Test name
Test status
Simulation time 3933233729 ps
CPU time 300.94 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:52:24 PM PDT 24
Peak memory 362696 kb
Host smart-69052c72-a156-4e29-8bd7-03fe1cf48cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243450326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.1243450326
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.4201308326
Short name T524
Test name
Test status
Simulation time 463921488 ps
CPU time 2.2 seconds
Started Mar 17 12:48:39 PM PDT 24
Finished Mar 17 12:48:42 PM PDT 24
Peak memory 201232 kb
Host smart-5a29363a-4521-4d0b-ad3c-298caab5070a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201308326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.4201308326
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.1118685329
Short name T799
Test name
Test status
Simulation time 416060758 ps
CPU time 29.45 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 12:49:25 PM PDT 24
Peak memory 293280 kb
Host smart-ff280b12-32b0-40d9-a9d6-b9a65546632b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118685329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.1118685329
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1204244278
Short name T876
Test name
Test status
Simulation time 49498411 ps
CPU time 2.48 seconds
Started Mar 17 12:47:17 PM PDT 24
Finished Mar 17 12:47:20 PM PDT 24
Peak memory 211432 kb
Host smart-c1cdc4bb-9c5d-4201-b7e6-604047a196fc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204244278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.1204244278
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.1831107456
Short name T741
Test name
Test status
Simulation time 140686869 ps
CPU time 8.02 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:47:32 PM PDT 24
Peak memory 203236 kb
Host smart-9d5ba064-8088-4916-9a49-5f99b3d2fdd4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831107456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.1831107456
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.3114575635
Short name T653
Test name
Test status
Simulation time 1258372755 ps
CPU time 221.48 seconds
Started Mar 17 12:47:16 PM PDT 24
Finished Mar 17 12:50:59 PM PDT 24
Peak memory 355008 kb
Host smart-03d0bdc1-60f0-48e3-8c85-d76bcb91cf14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114575635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.3114575635
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.3572495563
Short name T20
Test name
Test status
Simulation time 447911991 ps
CPU time 9.76 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:47:35 PM PDT 24
Peak memory 235884 kb
Host smart-45c7b86e-7f4f-41aa-8023-286388136913
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572495563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.3572495563
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.90478692
Short name T261
Test name
Test status
Simulation time 5852403713 ps
CPU time 192.82 seconds
Started Mar 17 12:48:39 PM PDT 24
Finished Mar 17 12:51:53 PM PDT 24
Peak memory 201460 kb
Host smart-55aa5886-0483-4190-b7ba-9e87079c58cb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90478692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_partial_access_b2b.90478692
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.1378165920
Short name T613
Test name
Test status
Simulation time 282812471 ps
CPU time 0.76 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 203252 kb
Host smart-e2fe0159-10a9-40f4-908d-7880bde4ac82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378165920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1378165920
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.1584535663
Short name T664
Test name
Test status
Simulation time 17082641860 ps
CPU time 742.3 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:59:47 PM PDT 24
Peak memory 375044 kb
Host smart-9a26fbf3-b6af-464e-940b-cb250fa421d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584535663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1584535663
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.1754116711
Short name T156
Test name
Test status
Simulation time 1834572845 ps
CPU time 14.98 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 12:49:10 PM PDT 24
Peak memory 203092 kb
Host smart-5811aeaa-018c-47de-8834-765a25d8c6b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754116711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.1754116711
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.846101626
Short name T881
Test name
Test status
Simulation time 61023231442 ps
CPU time 2400.52 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 01:27:26 PM PDT 24
Peak memory 376036 kb
Host smart-f7821010-afef-40a6-abf9-50d382a55b8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846101626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_stress_all.846101626
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3944330539
Short name T703
Test name
Test status
Simulation time 18863579634 ps
CPU time 134.94 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:49:42 PM PDT 24
Peak memory 321848 kb
Host smart-e5f59e18-59c6-44cf-bf6f-d20a365b4e9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3944330539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3944330539
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2735082590
Short name T831
Test name
Test status
Simulation time 1817741230 ps
CPU time 166.05 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:50:07 PM PDT 24
Peak memory 203228 kb
Host smart-2bba013c-1248-44c3-818a-a15401fb89e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735082590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.2735082590
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2357175910
Short name T903
Test name
Test status
Simulation time 194682187 ps
CPU time 3.59 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 220580 kb
Host smart-ea1ca265-84d5-4507-9d6e-3a22f0ed5d41
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357175910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.2357175910
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.37838607
Short name T276
Test name
Test status
Simulation time 481340900 ps
CPU time 49.23 seconds
Started Mar 17 12:47:12 PM PDT 24
Finished Mar 17 12:48:01 PM PDT 24
Peak memory 288564 kb
Host smart-94ead566-3a37-46d6-8c62-f4ab8cc5594d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37838607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.sram_ctrl_access_during_key_req.37838607
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.329115283
Short name T438
Test name
Test status
Simulation time 24071958 ps
CPU time 0.83 seconds
Started Mar 17 12:48:39 PM PDT 24
Finished Mar 17 12:48:41 PM PDT 24
Peak memory 199964 kb
Host smart-f76c1f0a-3518-4747-984a-1ce9c0f8e6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329115283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.329115283
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.89715720
Short name T593
Test name
Test status
Simulation time 5321394826 ps
CPU time 62.25 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:48:23 PM PDT 24
Peak memory 203152 kb
Host smart-bcd1fd04-6c21-4b2a-9da7-dc78c21378af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89715720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.89715720
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.2467023951
Short name T821
Test name
Test status
Simulation time 4248575927 ps
CPU time 1448.44 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 01:11:32 PM PDT 24
Peak memory 373936 kb
Host smart-8b7d77a0-b77b-43a9-96de-5cbd196f81ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467023951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.2467023951
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.215279158
Short name T356
Test name
Test status
Simulation time 206804651 ps
CPU time 1.04 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 202980 kb
Host smart-29d2de06-31c0-4772-a768-c93234434e25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215279158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_esc
alation.215279158
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.4230370137
Short name T871
Test name
Test status
Simulation time 172555524 ps
CPU time 17.28 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:40 PM PDT 24
Peak memory 273716 kb
Host smart-6e7ba671-4287-42f9-85fb-fc0b210d2334
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230370137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.4230370137
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3138143899
Short name T651
Test name
Test status
Simulation time 595287914 ps
CPU time 4.93 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:28 PM PDT 24
Peak memory 211436 kb
Host smart-0c78f9dd-ac52-425a-b115-68fb71f51017
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138143899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.3138143899
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.1179066314
Short name T226
Test name
Test status
Simulation time 307627865 ps
CPU time 5.09 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 203184 kb
Host smart-af7beb0c-a990-4d12-a67f-d589775b9bc1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179066314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.1179066314
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.1287197319
Short name T543
Test name
Test status
Simulation time 13158146691 ps
CPU time 1131.45 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 01:07:47 PM PDT 24
Peak memory 371720 kb
Host smart-76bf891d-9c87-4d0b-9a9d-5c96c41a5811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287197319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.1287197319
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.3596716056
Short name T113
Test name
Test status
Simulation time 216061620 ps
CPU time 2.86 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 203196 kb
Host smart-4b266d36-d974-4f49-bf44-d969bbfba5a9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596716056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.3596716056
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3035087357
Short name T607
Test name
Test status
Simulation time 55682613137 ps
CPU time 371.6 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 12:55:07 PM PDT 24
Peak memory 203240 kb
Host smart-b4046136-5c3e-455e-afc7-4b184ad6827b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035087357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.3035087357
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.3986430367
Short name T302
Test name
Test status
Simulation time 77401568 ps
CPU time 0.83 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 203216 kb
Host smart-df0463d6-caa4-4f8a-b7c6-75d3a9ff725f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986430367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3986430367
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.1108800077
Short name T171
Test name
Test status
Simulation time 7161488422 ps
CPU time 313.68 seconds
Started Mar 17 12:48:40 PM PDT 24
Finished Mar 17 12:53:54 PM PDT 24
Peak memory 371516 kb
Host smart-c9ab1c3e-8554-45be-9084-9a03028358ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108800077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1108800077
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.3316175617
Short name T890
Test name
Test status
Simulation time 4845229641 ps
CPU time 14.64 seconds
Started Mar 17 12:47:15 PM PDT 24
Finished Mar 17 12:47:31 PM PDT 24
Peak memory 203180 kb
Host smart-b573c769-add8-48df-83c1-74323c223371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316175617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3316175617
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.1706508017
Short name T710
Test name
Test status
Simulation time 36964124552 ps
CPU time 2062.84 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 01:21:46 PM PDT 24
Peak memory 375132 kb
Host smart-509f6b8c-a975-4567-a003-b5f4f4c401b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706508017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.1706508017
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1554868936
Short name T427
Test name
Test status
Simulation time 3415367088 ps
CPU time 28.29 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 12:49:23 PM PDT 24
Peak memory 251828 kb
Host smart-e9f61ca5-f3a3-4404-a76c-b953519c369c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1554868936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1554868936
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2949273759
Short name T100
Test name
Test status
Simulation time 10791372162 ps
CPU time 267.42 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:51:48 PM PDT 24
Peak memory 203212 kb
Host smart-6471a918-1935-4685-9ba9-d255182a4bb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949273759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.2949273759
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1782688622
Short name T410
Test name
Test status
Simulation time 126573531 ps
CPU time 50.92 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:48:11 PM PDT 24
Peak memory 317568 kb
Host smart-d9dec764-9710-43cc-9f4e-64d7837cdc3f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782688622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1782688622
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3681626163
Short name T746
Test name
Test status
Simulation time 5201412420 ps
CPU time 900.54 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 01:02:22 PM PDT 24
Peak memory 372932 kb
Host smart-6f8b5400-cf8a-47cc-bb80-2e7873af83ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681626163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.3681626163
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.480638968
Short name T628
Test name
Test status
Simulation time 14194180 ps
CPU time 0.68 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 202056 kb
Host smart-fec2fd35-65b8-415f-bb45-ea661ca9c7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480638968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.480638968
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.3445620103
Short name T443
Test name
Test status
Simulation time 2368402871 ps
CPU time 49.48 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:48:14 PM PDT 24
Peak memory 203172 kb
Host smart-9fde2ec6-2a0d-4d95-b556-d1800920bc66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445620103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.3445620103
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.2579370490
Short name T295
Test name
Test status
Simulation time 18710469212 ps
CPU time 379.19 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:53:42 PM PDT 24
Peak memory 359632 kb
Host smart-2d14c6cb-5ba2-4e31-abe3-625d65692036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579370490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.2579370490
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.3159244790
Short name T314
Test name
Test status
Simulation time 971605380 ps
CPU time 10.01 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:32 PM PDT 24
Peak memory 203156 kb
Host smart-8b5f420d-46c6-4534-abda-63be73ef7c28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159244790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.3159244790
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.1151169749
Short name T3
Test name
Test status
Simulation time 541540670 ps
CPU time 105.77 seconds
Started Mar 17 12:47:32 PM PDT 24
Finished Mar 17 12:49:18 PM PDT 24
Peak memory 369700 kb
Host smart-97d77926-bcee-469a-80e6-d46fda745b23
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151169749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.1151169749
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.458658666
Short name T717
Test name
Test status
Simulation time 100588029 ps
CPU time 2.93 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 211448 kb
Host smart-f4e587b9-f1ed-484e-a312-8663dabb7ae6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458658666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.sram_ctrl_mem_partial_access.458658666
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.1950894952
Short name T880
Test name
Test status
Simulation time 1330294694 ps
CPU time 5.55 seconds
Started Mar 17 12:47:36 PM PDT 24
Finished Mar 17 12:47:41 PM PDT 24
Peak memory 203184 kb
Host smart-e0f877ca-026e-45dd-900f-30fb6e1043bb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950894952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.1950894952
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.1273297166
Short name T926
Test name
Test status
Simulation time 58074341503 ps
CPU time 1176.75 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 01:07:01 PM PDT 24
Peak memory 373804 kb
Host smart-0786264a-8833-4c8c-94bb-b7c3d17bf9e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273297166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.1273297166
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.722804754
Short name T780
Test name
Test status
Simulation time 849209502 ps
CPU time 14.09 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:47:33 PM PDT 24
Peak memory 203076 kb
Host smart-18dcfd82-0905-4012-9d43-cda7ee1c4d51
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722804754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.s
ram_ctrl_partial_access.722804754
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.247917781
Short name T530
Test name
Test status
Simulation time 8181040845 ps
CPU time 209.46 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:50:52 PM PDT 24
Peak memory 203236 kb
Host smart-59011894-069d-4e40-90fa-a5c7faa84752
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247917781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.sram_ctrl_partial_access_b2b.247917781
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.374731248
Short name T792
Test name
Test status
Simulation time 99487066 ps
CPU time 0.71 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 203088 kb
Host smart-366a525e-6f6f-4a67-ac58-13d14edbcd7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374731248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.374731248
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.1530406237
Short name T230
Test name
Test status
Simulation time 2759622985 ps
CPU time 1036.48 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 01:04:39 PM PDT 24
Peak memory 369896 kb
Host smart-6545e1ae-4620-48d6-aefc-4d85537e9b6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530406237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.1530406237
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.948311162
Short name T801
Test name
Test status
Simulation time 536382722 ps
CPU time 15.51 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 12:49:11 PM PDT 24
Peak memory 260100 kb
Host smart-2022b1fb-c184-452f-8a09-8db519cda437
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948311162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.948311162
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.2228476061
Short name T796
Test name
Test status
Simulation time 83243937282 ps
CPU time 2069.75 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 01:21:55 PM PDT 24
Peak memory 375980 kb
Host smart-9a3bce95-141d-4470-b7c9-cae2e83726c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228476061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.2228476061
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1443018135
Short name T931
Test name
Test status
Simulation time 556269832 ps
CPU time 9.24 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:47:30 PM PDT 24
Peak memory 211476 kb
Host smart-7217bfb4-47c3-4d9e-bd00-495f5a5e2ce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1443018135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1443018135
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3931533287
Short name T449
Test name
Test status
Simulation time 22897832342 ps
CPU time 290.87 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:52:14 PM PDT 24
Peak memory 203148 kb
Host smart-633e6f9f-c354-4494-aad7-df35037d87aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931533287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.3931533287
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.4117713985
Short name T650
Test name
Test status
Simulation time 117799126 ps
CPU time 11 seconds
Started Mar 17 12:47:33 PM PDT 24
Finished Mar 17 12:47:44 PM PDT 24
Peak memory 251920 kb
Host smart-9980fa8f-5401-497c-ac37-f4e300ab17c0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117713985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.4117713985
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2849264714
Short name T580
Test name
Test status
Simulation time 16674851525 ps
CPU time 804.39 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 01:00:55 PM PDT 24
Peak memory 358152 kb
Host smart-9ed53c0b-0d15-456e-aa38-4089c5680b63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849264714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.2849264714
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.880739472
Short name T279
Test name
Test status
Simulation time 19749640 ps
CPU time 0.63 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:47:28 PM PDT 24
Peak memory 202080 kb
Host smart-c1066fde-2538-4705-bea9-eaacfb055547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880739472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.880739472
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.1177417498
Short name T714
Test name
Test status
Simulation time 21711880828 ps
CPU time 51.39 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:48:14 PM PDT 24
Peak memory 203100 kb
Host smart-2ea61d93-fe5c-4f29-95f4-e90a0819dca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177417498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.1177417498
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.4230187550
Short name T424
Test name
Test status
Simulation time 52599049210 ps
CPU time 1536.89 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 01:13:01 PM PDT 24
Peak memory 373636 kb
Host smart-ae5ea891-32ca-40c8-814e-07d95a6de53a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230187550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.4230187550
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.1296046566
Short name T206
Test name
Test status
Simulation time 3182122405 ps
CPU time 7.7 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:31 PM PDT 24
Peak memory 203232 kb
Host smart-0b9ae430-7b6a-41bf-9bb4-57491855cc9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296046566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.1296046566
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.3598943050
Short name T202
Test name
Test status
Simulation time 104166850 ps
CPU time 46.87 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:48:16 PM PDT 24
Peak memory 307544 kb
Host smart-a5402603-525f-40fe-9fdd-299ae251a883
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598943050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.3598943050
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.690620328
Short name T289
Test name
Test status
Simulation time 102323119 ps
CPU time 2.81 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 211352 kb
Host smart-811d0571-ce35-498b-8e09-e6cc9ceedac5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690620328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_mem_partial_access.690620328
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.647992069
Short name T513
Test name
Test status
Simulation time 407378541 ps
CPU time 5.08 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:47:35 PM PDT 24
Peak memory 202948 kb
Host smart-ddf33086-d52b-46dd-a20e-a42aa33bac31
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647992069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl
_mem_walk.647992069
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.97785200
Short name T398
Test name
Test status
Simulation time 19477079371 ps
CPU time 640.62 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:58:06 PM PDT 24
Peak memory 370796 kb
Host smart-537edde4-b58f-40b1-ab45-1e73f33c4709
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97785200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multipl
e_keys.97785200
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.78260211
Short name T482
Test name
Test status
Simulation time 224133539 ps
CPU time 158.01 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:50:01 PM PDT 24
Peak memory 365688 kb
Host smart-5ebb958a-42d8-4784-bd8a-d6f98d4ad6bc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78260211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sr
am_ctrl_partial_access.78260211
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.775752192
Short name T659
Test name
Test status
Simulation time 5268340203 ps
CPU time 374.21 seconds
Started Mar 17 12:47:34 PM PDT 24
Finished Mar 17 12:53:49 PM PDT 24
Peak memory 203272 kb
Host smart-e719cd43-d3f8-4340-a447-23e5f520d64a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775752192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.sram_ctrl_partial_access_b2b.775752192
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.2068308973
Short name T902
Test name
Test status
Simulation time 80469158 ps
CPU time 0.72 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 203176 kb
Host smart-449f51da-4da9-4c2e-a3fe-a6604666c6ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068308973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2068308973
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.2342956924
Short name T173
Test name
Test status
Simulation time 18504644003 ps
CPU time 785.36 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 01:00:29 PM PDT 24
Peak memory 369860 kb
Host smart-600e4185-1681-4ecf-84dc-67cb4bb040c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342956924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2342956924
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.3636908740
Short name T824
Test name
Test status
Simulation time 603574573 ps
CPU time 109.91 seconds
Started Mar 17 12:47:34 PM PDT 24
Finished Mar 17 12:49:24 PM PDT 24
Peak memory 347756 kb
Host smart-9e76173b-8732-40a6-8f66-9e791c6bd4b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636908740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3636908740
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.3331805291
Short name T594
Test name
Test status
Simulation time 10992215530 ps
CPU time 4038.64 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 01:54:43 PM PDT 24
Peak memory 375732 kb
Host smart-fffdc453-0d68-4be0-9536-b763764c8bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331805291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.3331805291
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3931219811
Short name T820
Test name
Test status
Simulation time 4931969329 ps
CPU time 376.13 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:53:39 PM PDT 24
Peak memory 371576 kb
Host smart-753a8060-3675-488e-b88a-feac93cff136
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3931219811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3931219811
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2162766087
Short name T598
Test name
Test status
Simulation time 3515439360 ps
CPU time 332.01 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:53:01 PM PDT 24
Peak memory 203248 kb
Host smart-d43860a4-ff29-44d3-94b5-12cc43ca3ea7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162766087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.2162766087
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.95664947
Short name T467
Test name
Test status
Simulation time 95214173 ps
CPU time 15.88 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:38 PM PDT 24
Peak memory 268344 kb
Host smart-175fe403-31f7-489c-aab4-367143b30f66
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95664947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.sram_ctrl_throughput_w_partial_write.95664947
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.147575117
Short name T361
Test name
Test status
Simulation time 54774158066 ps
CPU time 1401.01 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 01:10:46 PM PDT 24
Peak memory 375080 kb
Host smart-5f7af5f1-53db-4d9a-9184-1ada636f549b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147575117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 15.sram_ctrl_access_during_key_req.147575117
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.2232794680
Short name T929
Test name
Test status
Simulation time 9540334728 ps
CPU time 42.21 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:48:01 PM PDT 24
Peak memory 203232 kb
Host smart-d76ce748-062a-4aa3-966e-661471bd0c92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232794680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.2232794680
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.3999730056
Short name T475
Test name
Test status
Simulation time 104756060091 ps
CPU time 721.12 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:59:27 PM PDT 24
Peak memory 372340 kb
Host smart-4e30105a-b7b7-449d-8535-d1390f77eb34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999730056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.3999730056
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.3531074127
Short name T748
Test name
Test status
Simulation time 602328965 ps
CPU time 7.03 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:47:28 PM PDT 24
Peak memory 203148 kb
Host smart-12995858-98ee-478f-b371-b1fc00e86b28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531074127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.3531074127
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.2965925669
Short name T879
Test name
Test status
Simulation time 89827701 ps
CPU time 5.09 seconds
Started Mar 17 12:47:13 PM PDT 24
Finished Mar 17 12:47:18 PM PDT 24
Peak memory 226204 kb
Host smart-d0f433c8-db9f-4f53-a453-1ef73d577ef8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965925669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.2965925669
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1398847945
Short name T866
Test name
Test status
Simulation time 1394732421 ps
CPU time 3.01 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:47:28 PM PDT 24
Peak memory 211308 kb
Host smart-05cef55b-85e6-40d3-b584-d38e3ffdf803
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398847945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.1398847945
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.4045766722
Short name T674
Test name
Test status
Simulation time 572771660 ps
CPU time 9.34 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:47:38 PM PDT 24
Peak memory 203156 kb
Host smart-65be4152-861e-4467-8075-a1d2a3017daa
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045766722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.4045766722
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.3245099525
Short name T298
Test name
Test status
Simulation time 9010041348 ps
CPU time 580.57 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:57:03 PM PDT 24
Peak memory 375072 kb
Host smart-cad7d471-da60-41ba-841b-a2ad10b9fe4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245099525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.3245099525
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.359460408
Short name T472
Test name
Test status
Simulation time 2174356589 ps
CPU time 14.13 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:47:38 PM PDT 24
Peak memory 203188 kb
Host smart-3d8d10df-a2e2-4c95-8c09-9d11da5e2ba7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359460408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s
ram_ctrl_partial_access.359460408
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.180509933
Short name T212
Test name
Test status
Simulation time 32008274939 ps
CPU time 186.44 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:50:27 PM PDT 24
Peak memory 203256 kb
Host smart-93b2c03f-489d-4b1f-9ed3-68b2c91c64ca
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180509933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.sram_ctrl_partial_access_b2b.180509933
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.2798355129
Short name T474
Test name
Test status
Simulation time 292951649 ps
CPU time 0.73 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 203184 kb
Host smart-9ac1998b-d561-4be8-83e4-a80aeb510b0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798355129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2798355129
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.1849977970
Short name T312
Test name
Test status
Simulation time 15659006178 ps
CPU time 373.45 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:53:42 PM PDT 24
Peak memory 375608 kb
Host smart-2f169577-45ab-46ea-b62c-786ce6aa5866
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849977970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1849977970
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.2922568698
Short name T154
Test name
Test status
Simulation time 668480510 ps
CPU time 88.42 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:48:57 PM PDT 24
Peak memory 353368 kb
Host smart-202f8557-0f2f-4924-984d-59b01eb351ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922568698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2922568698
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2941308656
Short name T897
Test name
Test status
Simulation time 645156075 ps
CPU time 129.92 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:49:34 PM PDT 24
Peak memory 372908 kb
Host smart-269b6415-c54b-4b6f-88c7-f10840bde6e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2941308656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2941308656
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3725656766
Short name T168
Test name
Test status
Simulation time 2470576303 ps
CPU time 238.05 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:51:23 PM PDT 24
Peak memory 203296 kb
Host smart-49f3e233-61fb-420e-af46-af00280eaebf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725656766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.3725656766
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3620220521
Short name T754
Test name
Test status
Simulation time 617684746 ps
CPU time 112.17 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:49:15 PM PDT 24
Peak memory 370700 kb
Host smart-e8da7f2c-6a9f-45cd-a9ba-3d53f738a581
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620220521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.3620220521
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1273405280
Short name T888
Test name
Test status
Simulation time 10929640192 ps
CPU time 858.77 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 01:01:44 PM PDT 24
Peak memory 366936 kb
Host smart-d238c3c0-1645-4e50-870e-0ab165554789
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273405280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.1273405280
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.3136151301
Short name T609
Test name
Test status
Simulation time 31283169 ps
CPU time 0.63 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 202304 kb
Host smart-2eee6ccb-5c1d-4404-9066-db7fa21441bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136151301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.3136151301
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1102430513
Short name T502
Test name
Test status
Simulation time 993553791 ps
CPU time 61.22 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:48:26 PM PDT 24
Peak memory 203188 kb
Host smart-59f0ebbc-122f-489a-a1c1-1013ee56e7ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102430513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1102430513
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.2798508850
Short name T399
Test name
Test status
Simulation time 103054731854 ps
CPU time 874.47 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 01:01:59 PM PDT 24
Peak memory 375128 kb
Host smart-6888627f-3c4d-4b0d-8604-a9328a57feb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798508850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.2798508850
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.469471406
Short name T207
Test name
Test status
Simulation time 47449169 ps
CPU time 1.36 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:25 PM PDT 24
Peak memory 211352 kb
Host smart-cfe5c13c-3d84-4bde-9ba2-517d25c6a540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469471406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_esc
alation.469471406
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.3896210224
Short name T163
Test name
Test status
Simulation time 383018694 ps
CPU time 4.73 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:35 PM PDT 24
Peak memory 227520 kb
Host smart-f8e560ec-7b8a-4932-9e76-951807583185
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896210224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.3896210224
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.45296378
Short name T403
Test name
Test status
Simulation time 160081948 ps
CPU time 2.57 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:47:28 PM PDT 24
Peak memory 211456 kb
Host smart-4422ea42-8773-484d-a21e-4f22c4919e8e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45296378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_mem_partial_access.45296378
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.1148883312
Short name T867
Test name
Test status
Simulation time 234952108 ps
CPU time 5.13 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:35 PM PDT 24
Peak memory 203108 kb
Host smart-c9676a92-f0f1-443d-80ee-c8d53c519b49
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148883312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.1148883312
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.113881002
Short name T282
Test name
Test status
Simulation time 36285083363 ps
CPU time 938.22 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 01:02:59 PM PDT 24
Peak memory 374748 kb
Host smart-42d1fc2f-ac38-4357-9a44-e4d0725b6b94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113881002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multip
le_keys.113881002
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.1350589627
Short name T35
Test name
Test status
Simulation time 679759066 ps
CPU time 12.38 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 12:47:39 PM PDT 24
Peak memory 203212 kb
Host smart-eda18c16-7943-477b-9887-04c88ced9731
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350589627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.1350589627
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1222456688
Short name T169
Test name
Test status
Simulation time 71437410139 ps
CPU time 546.48 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:56:30 PM PDT 24
Peak memory 203284 kb
Host smart-1b14c1c5-4b6a-4bdb-affd-e3571695dae2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222456688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.1222456688
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.439842957
Short name T354
Test name
Test status
Simulation time 48589187 ps
CPU time 0.72 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:47:29 PM PDT 24
Peak memory 203220 kb
Host smart-a6e95d4a-4822-4195-b739-eef55f48f498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439842957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.439842957
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.1934217650
Short name T806
Test name
Test status
Simulation time 721515261 ps
CPU time 10.02 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:33 PM PDT 24
Peak memory 203172 kb
Host smart-f9d04212-e51a-4541-9993-54208b577d4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934217650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1934217650
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.2460068577
Short name T885
Test name
Test status
Simulation time 59324791 ps
CPU time 9.83 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 12:47:37 PM PDT 24
Peak memory 244828 kb
Host smart-af5d4095-f117-40eb-9ca7-aaa64647ebf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460068577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2460068577
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1109825566
Short name T280
Test name
Test status
Simulation time 3038075815 ps
CPU time 285.41 seconds
Started Mar 17 12:47:33 PM PDT 24
Finished Mar 17 12:52:18 PM PDT 24
Peak memory 203280 kb
Host smart-ecc5148a-3c41-43ba-ba21-9da91d83c269
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109825566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.1109825566
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.871902612
Short name T255
Test name
Test status
Simulation time 605021346 ps
CPU time 20.2 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:44 PM PDT 24
Peak memory 278692 kb
Host smart-d4ecec14-8208-49e4-9b6c-168ed10ab4ad
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871902612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.871902612
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2819350301
Short name T75
Test name
Test status
Simulation time 2259394560 ps
CPU time 658.73 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:58:22 PM PDT 24
Peak memory 356600 kb
Host smart-f4a27fe6-3b54-47ef-bb99-5580906ce5a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819350301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.2819350301
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.1164350002
Short name T592
Test name
Test status
Simulation time 13025905 ps
CPU time 0.64 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 202108 kb
Host smart-c3fb2d61-bab0-40eb-b6a0-89c1566591d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164350002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.1164350002
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.400583059
Short name T542
Test name
Test status
Simulation time 703327318 ps
CPU time 22.05 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:47:47 PM PDT 24
Peak memory 203088 kb
Host smart-49f06a21-5152-4e64-ab83-4e8778e4dead
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400583059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.
400583059
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.3325309372
Short name T331
Test name
Test status
Simulation time 6172631935 ps
CPU time 408.15 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:54:12 PM PDT 24
Peak memory 369560 kb
Host smart-5d5c670a-e599-4013-b6f0-bd2c0d4f507f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325309372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.3325309372
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.3435379681
Short name T776
Test name
Test status
Simulation time 712885861 ps
CPU time 7.24 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:29 PM PDT 24
Peak memory 203144 kb
Host smart-756606ee-b300-4d1c-a743-9067922f6893
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435379681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.3435379681
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.3417464369
Short name T526
Test name
Test status
Simulation time 247734357 ps
CPU time 93.87 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:48:57 PM PDT 24
Peak memory 355464 kb
Host smart-61506a90-193f-4d56-bbe7-a5a504087312
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417464369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.3417464369
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1084672799
Short name T334
Test name
Test status
Simulation time 243731868 ps
CPU time 4 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 211444 kb
Host smart-ce285a43-abd3-4dbd-a54d-d757fec5d3c1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084672799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.1084672799
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.2882901503
Short name T221
Test name
Test status
Simulation time 296556531 ps
CPU time 5.04 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 203392 kb
Host smart-56d8c409-9b8f-4805-bb93-9c6d2b6217d2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882901503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.2882901503
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.2503722871
Short name T51
Test name
Test status
Simulation time 20445597689 ps
CPU time 655.91 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:58:24 PM PDT 24
Peak memory 373884 kb
Host smart-5490579e-c518-4a50-aeea-a934bbe14eda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503722871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.2503722871
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.2749932586
Short name T815
Test name
Test status
Simulation time 393053386 ps
CPU time 9.91 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:47:36 PM PDT 24
Peak memory 203184 kb
Host smart-9b3d5a51-bf54-427b-a055-2c6325687ede
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749932586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.2749932586
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2226629456
Short name T828
Test name
Test status
Simulation time 50083851649 ps
CPU time 320.65 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:52:45 PM PDT 24
Peak memory 203204 kb
Host smart-90940c7d-c599-431b-a9ec-aba478e06c2c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226629456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.2226629456
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.3893907067
Short name T451
Test name
Test status
Simulation time 55781060 ps
CPU time 0.84 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 203180 kb
Host smart-e0a21189-3c95-4412-8225-a2a7c6ac6bdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893907067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3893907067
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.3185643350
Short name T55
Test name
Test status
Simulation time 46430254522 ps
CPU time 1023.84 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 01:04:34 PM PDT 24
Peak memory 370972 kb
Host smart-f4241527-b9ea-46e6-ab18-58333a92c8e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185643350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3185643350
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.3712683792
Short name T730
Test name
Test status
Simulation time 179508204 ps
CPU time 6.93 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:37 PM PDT 24
Peak memory 231964 kb
Host smart-143491ce-21ba-4255-a86d-d75c15c7e7b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712683792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3712683792
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4278078084
Short name T932
Test name
Test status
Simulation time 2969786029 ps
CPU time 751.77 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:59:54 PM PDT 24
Peak memory 383248 kb
Host smart-059e084a-b697-4b86-9811-3dea5f75af03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4278078084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.4278078084
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.1402444302
Short name T98
Test name
Test status
Simulation time 22432894227 ps
CPU time 259.67 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:51:44 PM PDT 24
Peak memory 203236 kb
Host smart-55b4620c-117b-4ccf-84c3-af58ac74c378
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402444302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.1402444302
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3857610023
Short name T640
Test name
Test status
Simulation time 135706865 ps
CPU time 68.74 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:48:29 PM PDT 24
Peak memory 336176 kb
Host smart-fb3c3517-bfd9-4c4a-ae6a-0117dc8222e1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857610023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.3857610023
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.528231530
Short name T817
Test name
Test status
Simulation time 4106248598 ps
CPU time 147.02 seconds
Started Mar 17 12:48:56 PM PDT 24
Finished Mar 17 12:51:23 PM PDT 24
Peak memory 371652 kb
Host smart-4ad0e461-1967-41e7-a51f-301015246b9d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528231530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.sram_ctrl_access_during_key_req.528231530
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.835045938
Short name T649
Test name
Test status
Simulation time 16030301 ps
CPU time 0.62 seconds
Started Mar 17 12:48:56 PM PDT 24
Finished Mar 17 12:48:57 PM PDT 24
Peak memory 201960 kb
Host smart-2eb05bb9-60f9-469b-984b-8bbb6fe22898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835045938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.835045938
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.1137262355
Short name T916
Test name
Test status
Simulation time 409972321 ps
CPU time 24.44 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:48 PM PDT 24
Peak memory 203016 kb
Host smart-13edc7df-dc1b-4f1b-87e9-5dc072053173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137262355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.1137262355
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.3361685343
Short name T826
Test name
Test status
Simulation time 4091110902 ps
CPU time 815.08 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 01:01:05 PM PDT 24
Peak memory 374004 kb
Host smart-69959c07-d114-4c3d-8c5e-75b472fb1046
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361685343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.3361685343
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.1372753519
Short name T682
Test name
Test status
Simulation time 2012252338 ps
CPU time 6.97 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:37 PM PDT 24
Peak memory 203184 kb
Host smart-874ff19e-f40f-4665-a48b-bed7c7e7c072
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372753519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.1372753519
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.2932690445
Short name T825
Test name
Test status
Simulation time 198915498 ps
CPU time 27.46 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:47:58 PM PDT 24
Peak memory 293296 kb
Host smart-60445711-71c9-492d-a41e-9ae127b214e4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932690445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.2932690445
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2464179458
Short name T735
Test name
Test status
Simulation time 317585390 ps
CPU time 4.81 seconds
Started Mar 17 12:48:40 PM PDT 24
Finished Mar 17 12:48:45 PM PDT 24
Peak memory 211092 kb
Host smart-f8928f1e-3789-4b31-afd1-e645cbe7def5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464179458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.2464179458
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.2456851768
Short name T894
Test name
Test status
Simulation time 1360992277 ps
CPU time 10.34 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:33 PM PDT 24
Peak memory 203192 kb
Host smart-36053ccb-ab5d-488c-944b-151fe353f19d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456851768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.2456851768
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.1312286314
Short name T175
Test name
Test status
Simulation time 298410276 ps
CPU time 43.31 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:48:15 PM PDT 24
Peak memory 294076 kb
Host smart-06ded57f-02b4-4afb-93b0-dad44fcb92e3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312286314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.1312286314
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3063758014
Short name T191
Test name
Test status
Simulation time 13331323010 ps
CPU time 230.83 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:51:22 PM PDT 24
Peak memory 203272 kb
Host smart-7f84b9f9-f8a2-449c-9eeb-d2cf55835545
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063758014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.3063758014
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.3327468590
Short name T683
Test name
Test status
Simulation time 52214660 ps
CPU time 0.85 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:47:25 PM PDT 24
Peak memory 203216 kb
Host smart-380c7a29-0bea-4db8-84b5-28929cd8ff60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327468590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.3327468590
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.2852887796
Short name T686
Test name
Test status
Simulation time 14227815347 ps
CPU time 1339.94 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 375048 kb
Host smart-1f4a9f33-3f06-43f5-a19f-7498f37e7e6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852887796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2852887796
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.4177228037
Short name T333
Test name
Test status
Simulation time 1661505075 ps
CPU time 8.25 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:39 PM PDT 24
Peak memory 203120 kb
Host smart-bc241c05-2bba-4ff7-b785-fc9fa3b4a5b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177228037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.4177228037
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.4140384185
Short name T608
Test name
Test status
Simulation time 230014926178 ps
CPU time 3703.01 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 01:49:05 PM PDT 24
Peak memory 375024 kb
Host smart-3cc24a73-ec22-4840-a560-5bd552d894a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140384185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.4140384185
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3228521561
Short name T44
Test name
Test status
Simulation time 362203217 ps
CPU time 6.52 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:47:32 PM PDT 24
Peak memory 211444 kb
Host smart-5d9f5bf7-7d10-4ba2-af73-45514669a9df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3228521561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.3228521561
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.4006448094
Short name T383
Test name
Test status
Simulation time 9608087543 ps
CPU time 436.7 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 12:56:12 PM PDT 24
Peak memory 203204 kb
Host smart-aef2fb12-da67-459c-96e5-9b272768027a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006448094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.4006448094
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2927314625
Short name T426
Test name
Test status
Simulation time 106979986 ps
CPU time 17.77 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:48 PM PDT 24
Peak memory 270636 kb
Host smart-7ce81b82-3035-4023-9dc8-c95dc42d9ce8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927314625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.2927314625
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.671428349
Short name T924
Test name
Test status
Simulation time 8333504060 ps
CPU time 653.86 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:58:17 PM PDT 24
Peak memory 374000 kb
Host smart-34633dbc-4e27-4894-9cae-5ea3fc32bf81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671428349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.sram_ctrl_access_during_key_req.671428349
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2808414455
Short name T471
Test name
Test status
Simulation time 12873256 ps
CPU time 0.61 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:47:30 PM PDT 24
Peak memory 202012 kb
Host smart-44cf2d16-146b-42ae-bc87-dd19a987bcc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808414455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2808414455
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.2530263059
Short name T857
Test name
Test status
Simulation time 805788115 ps
CPU time 15.58 seconds
Started Mar 17 12:48:39 PM PDT 24
Finished Mar 17 12:48:55 PM PDT 24
Peak memory 202300 kb
Host smart-c208e2ae-8f25-4395-a184-6902c7af7d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530263059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.2530263059
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.1260378753
Short name T891
Test name
Test status
Simulation time 6995002410 ps
CPU time 779.23 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 01:00:22 PM PDT 24
Peak memory 373972 kb
Host smart-a952ecda-01ac-4bdf-91c2-c4f20c70804a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260378753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.1260378753
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.3840229970
Short name T701
Test name
Test status
Simulation time 3282041024 ps
CPU time 10.1 seconds
Started Mar 17 12:47:33 PM PDT 24
Finished Mar 17 12:47:43 PM PDT 24
Peak memory 203112 kb
Host smart-c0f26004-3cf8-4724-839f-c20b91605c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840229970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.3840229970
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.2113826473
Short name T231
Test name
Test status
Simulation time 135182950 ps
CPU time 11.08 seconds
Started Mar 17 12:47:16 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 252152 kb
Host smart-3e353134-30b1-43f3-aaef-f31550b521ef
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113826473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.2113826473
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.850818455
Short name T251
Test name
Test status
Simulation time 103152538 ps
CPU time 2.86 seconds
Started Mar 17 12:47:32 PM PDT 24
Finished Mar 17 12:47:35 PM PDT 24
Peak memory 211412 kb
Host smart-177f57a8-3617-490f-b682-8f240016df92
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850818455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_mem_partial_access.850818455
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.1564325724
Short name T186
Test name
Test status
Simulation time 275979840 ps
CPU time 8.42 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:32 PM PDT 24
Peak memory 203164 kb
Host smart-cf88cccb-cc8e-41a6-8003-e80a04dbbed3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564325724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.1564325724
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.2194756952
Short name T496
Test name
Test status
Simulation time 9133082103 ps
CPU time 707.42 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 370856 kb
Host smart-069377aa-1ee1-4672-a7a4-6006542ffd6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194756952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.2194756952
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.3855763961
Short name T630
Test name
Test status
Simulation time 727203245 ps
CPU time 87.81 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:48:52 PM PDT 24
Peak memory 360296 kb
Host smart-9ce6c4dd-a8c9-481b-94dc-56f5b1c09e20
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855763961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.3855763961
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1937978304
Short name T37
Test name
Test status
Simulation time 5315430753 ps
CPU time 325.28 seconds
Started Mar 17 12:48:56 PM PDT 24
Finished Mar 17 12:54:21 PM PDT 24
Peak memory 203184 kb
Host smart-6077d2bf-fa29-4ebd-b3e1-554bc02b96a0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937978304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.1937978304
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.3983459921
Short name T303
Test name
Test status
Simulation time 123282407 ps
CPU time 0.76 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 203132 kb
Host smart-fba0c925-8f84-4567-bd22-d433571caea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983459921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3983459921
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.2356816748
Short name T313
Test name
Test status
Simulation time 377490771 ps
CPU time 21.16 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:47:45 PM PDT 24
Peak memory 204648 kb
Host smart-9947aff2-6432-47c9-98f8-75284753d97d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356816748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2356816748
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.1698833705
Short name T240
Test name
Test status
Simulation time 1439140910 ps
CPU time 15.32 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:47:39 PM PDT 24
Peak memory 203132 kb
Host smart-00cbf8a3-3762-470b-9779-3b2005390d66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698833705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.1698833705
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.766550960
Short name T390
Test name
Test status
Simulation time 12089503579 ps
CPU time 601.89 seconds
Started Mar 17 12:47:34 PM PDT 24
Finished Mar 17 12:57:36 PM PDT 24
Peak memory 376008 kb
Host smart-440ef1d0-88a3-4828-bb7a-4fb4346e3c47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766550960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_stress_all.766550960
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1842278735
Short name T523
Test name
Test status
Simulation time 2781008029 ps
CPU time 53.74 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:48:17 PM PDT 24
Peak memory 299536 kb
Host smart-4bdda5f8-f2e1-4b70-8f25-53daa1abb76c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1842278735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.1842278735
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.775834627
Short name T489
Test name
Test status
Simulation time 4115652223 ps
CPU time 357.43 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:53:23 PM PDT 24
Peak memory 203224 kb
Host smart-eb736eef-788c-49e8-a882-f005b04eb8da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775834627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_stress_pipeline.775834627
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.519537645
Short name T680
Test name
Test status
Simulation time 57606835 ps
CPU time 4.99 seconds
Started Mar 17 12:48:56 PM PDT 24
Finished Mar 17 12:49:01 PM PDT 24
Peak memory 235816 kb
Host smart-8bbc4e27-26fe-49d4-9d98-84c172fba307
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519537645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.519537645
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2223175081
Short name T286
Test name
Test status
Simulation time 1830115784 ps
CPU time 289.74 seconds
Started Mar 17 12:46:29 PM PDT 24
Finished Mar 17 12:51:19 PM PDT 24
Peak memory 373236 kb
Host smart-4b2f3d2c-9aed-4acd-83f8-9e5340f85cc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223175081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.2223175081
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.2457428773
Short name T527
Test name
Test status
Simulation time 14899569 ps
CPU time 0.63 seconds
Started Mar 17 12:46:28 PM PDT 24
Finished Mar 17 12:46:29 PM PDT 24
Peak memory 202124 kb
Host smart-05ce5824-685e-44f8-bfcd-27e63780f90b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457428773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.2457428773
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.486743048
Short name T494
Test name
Test status
Simulation time 8478576495 ps
CPU time 43.03 seconds
Started Mar 17 12:46:29 PM PDT 24
Finished Mar 17 12:47:12 PM PDT 24
Peak memory 203176 kb
Host smart-10107434-3a29-4f52-a648-7b7a527934ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486743048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.486743048
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.533856000
Short name T192
Test name
Test status
Simulation time 5548533201 ps
CPU time 759.24 seconds
Started Mar 17 12:46:31 PM PDT 24
Finished Mar 17 12:59:10 PM PDT 24
Peak memory 374956 kb
Host smart-84d87858-68b9-49bc-8cb9-19552c1cc023
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533856000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable
.533856000
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.213053658
Short name T236
Test name
Test status
Simulation time 636911313 ps
CPU time 6.82 seconds
Started Mar 17 12:46:32 PM PDT 24
Finished Mar 17 12:46:38 PM PDT 24
Peak memory 203208 kb
Host smart-511a4afd-27a7-4f45-a3a3-ef36863cf9ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213053658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esca
lation.213053658
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.3020866459
Short name T789
Test name
Test status
Simulation time 77679652 ps
CPU time 17.21 seconds
Started Mar 17 12:46:56 PM PDT 24
Finished Mar 17 12:47:13 PM PDT 24
Peak memory 268668 kb
Host smart-9a9a3da2-b32e-4a58-b6bc-ad1d9b4c4751
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020866459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.3020866459
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2395216461
Short name T247
Test name
Test status
Simulation time 158275204 ps
CPU time 4.91 seconds
Started Mar 17 12:46:30 PM PDT 24
Finished Mar 17 12:46:35 PM PDT 24
Peak memory 211328 kb
Host smart-3aa725e0-5749-42ff-a728-effe51f77f94
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395216461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.2395216461
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.2113295951
Short name T624
Test name
Test status
Simulation time 976741740 ps
CPU time 5.11 seconds
Started Mar 17 12:46:30 PM PDT 24
Finished Mar 17 12:46:35 PM PDT 24
Peak memory 203092 kb
Host smart-859bef74-9ecf-4137-ad9c-9ac0845809c3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113295951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.2113295951
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.1689620770
Short name T797
Test name
Test status
Simulation time 1645835925 ps
CPU time 92.19 seconds
Started Mar 17 12:46:29 PM PDT 24
Finished Mar 17 12:48:01 PM PDT 24
Peak memory 338540 kb
Host smart-b5d1c6d3-e4eb-4cd9-a075-62a139c7eebb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689620770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.1689620770
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.2335295931
Short name T648
Test name
Test status
Simulation time 886792651 ps
CPU time 16.17 seconds
Started Mar 17 12:46:32 PM PDT 24
Finished Mar 17 12:46:48 PM PDT 24
Peak memory 203232 kb
Host smart-4d88a3d4-2b3f-4ace-8b10-0e798c376f76
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335295931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.2335295931
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.4048196522
Short name T639
Test name
Test status
Simulation time 6364023461 ps
CPU time 211.86 seconds
Started Mar 17 12:46:31 PM PDT 24
Finished Mar 17 12:50:03 PM PDT 24
Peak memory 203236 kb
Host smart-3b0110e7-16f1-49c1-bbe8-1b8865202f93
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048196522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.4048196522
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.1688466246
Short name T30
Test name
Test status
Simulation time 48412623 ps
CPU time 0.72 seconds
Started Mar 17 12:46:34 PM PDT 24
Finished Mar 17 12:46:35 PM PDT 24
Peak memory 203240 kb
Host smart-ec190285-0d03-4b2b-a997-3a20d5cfb697
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688466246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1688466246
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.1713716583
Short name T339
Test name
Test status
Simulation time 1694587410 ps
CPU time 214.59 seconds
Started Mar 17 12:46:30 PM PDT 24
Finished Mar 17 12:50:05 PM PDT 24
Peak memory 321684 kb
Host smart-ee9eb015-538e-41de-b1db-69a9e46823ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713716583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1713716583
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.3306835546
Short name T26
Test name
Test status
Simulation time 144617985 ps
CPU time 1.97 seconds
Started Mar 17 12:46:30 PM PDT 24
Finished Mar 17 12:46:32 PM PDT 24
Peak memory 222072 kb
Host smart-d0ec1a81-a753-4905-8fbf-c765545221f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306835546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.3306835546
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.2707019341
Short name T400
Test name
Test status
Simulation time 461305278 ps
CPU time 13.18 seconds
Started Mar 17 12:46:27 PM PDT 24
Finished Mar 17 12:46:43 PM PDT 24
Peak memory 203116 kb
Host smart-b31eb678-9e36-422b-9737-ec7d66dc296b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707019341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2707019341
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.652937690
Short name T553
Test name
Test status
Simulation time 7313492993 ps
CPU time 831.77 seconds
Started Mar 17 12:46:28 PM PDT 24
Finished Mar 17 01:00:20 PM PDT 24
Peak memory 374796 kb
Host smart-6dee23b3-cf9f-426c-a0c8-9a04235c4e18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652937690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_stress_all.652937690
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.995705357
Short name T873
Test name
Test status
Simulation time 1244710026 ps
CPU time 16.82 seconds
Started Mar 17 12:46:29 PM PDT 24
Finished Mar 17 12:46:46 PM PDT 24
Peak memory 211352 kb
Host smart-38a12c70-2988-4d5e-8acf-b1edac1ecffc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=995705357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.995705357
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3452343079
Short name T332
Test name
Test status
Simulation time 4447365632 ps
CPU time 201.63 seconds
Started Mar 17 12:46:32 PM PDT 24
Finished Mar 17 12:49:54 PM PDT 24
Peak memory 203268 kb
Host smart-2b9720e2-c211-4e68-971d-42a110f9c551
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452343079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.3452343079
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.537376382
Short name T504
Test name
Test status
Simulation time 50190306 ps
CPU time 2.91 seconds
Started Mar 17 12:46:42 PM PDT 24
Finished Mar 17 12:46:45 PM PDT 24
Peak memory 219528 kb
Host smart-49e86364-76c4-407e-924d-6d7db75bf00f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537376382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.537376382
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2202172881
Short name T462
Test name
Test status
Simulation time 916145830 ps
CPU time 251.86 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:51:34 PM PDT 24
Peak memory 371036 kb
Host smart-69e3d5bb-c50f-4593-801d-64a3cc228c9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202172881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.2202172881
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.2782181685
Short name T237
Test name
Test status
Simulation time 16721530 ps
CPU time 0.65 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 202032 kb
Host smart-7070ffb2-2678-4545-8f1d-f13dd2e2fe25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782181685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.2782181685
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.1420289992
Short name T386
Test name
Test status
Simulation time 13833907449 ps
CPU time 81.18 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:48:45 PM PDT 24
Peak memory 203144 kb
Host smart-0c9d2274-eff3-45cb-bd43-fadf93cb8dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420289992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.1420289992
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.149081061
Short name T923
Test name
Test status
Simulation time 12939400379 ps
CPU time 1277.53 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 01:08:41 PM PDT 24
Peak memory 372948 kb
Host smart-e43b057b-58c3-4e5f-954a-55b9e8203dae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149081061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executabl
e.149081061
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.4229321100
Short name T937
Test name
Test status
Simulation time 927528024 ps
CPU time 5.98 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:47:34 PM PDT 24
Peak memory 203160 kb
Host smart-c408dbd1-f99a-42df-824d-a146a4c51b87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229321100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.4229321100
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.783704338
Short name T786
Test name
Test status
Simulation time 155139803 ps
CPU time 135.17 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:49:37 PM PDT 24
Peak memory 364644 kb
Host smart-679726e3-f282-4881-8c10-ff6b79ae987f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783704338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.sram_ctrl_max_throughput.783704338
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1542403922
Short name T625
Test name
Test status
Simulation time 1215636633 ps
CPU time 5.21 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:35 PM PDT 24
Peak memory 211448 kb
Host smart-49e67f58-06bc-4c7b-8cc7-8666e7bdb75f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542403922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.1542403922
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.1570473052
Short name T525
Test name
Test status
Simulation time 2801782758 ps
CPU time 5.78 seconds
Started Mar 17 12:47:34 PM PDT 24
Finished Mar 17 12:47:40 PM PDT 24
Peak memory 203204 kb
Host smart-2dbed8c0-73b5-40b6-8668-6bcf178cae2f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570473052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.1570473052
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.366992881
Short name T911
Test name
Test status
Simulation time 5424548370 ps
CPU time 797.06 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 01:00:40 PM PDT 24
Peak memory 371892 kb
Host smart-52debab4-5bd6-43f5-be47-f7e9f1e601c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366992881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip
le_keys.366992881
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.214600317
Short name T324
Test name
Test status
Simulation time 496184789 ps
CPU time 67.37 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:48:30 PM PDT 24
Peak memory 318520 kb
Host smart-649f47d6-ba66-4a8a-897c-7d15cebbacf6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214600317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.s
ram_ctrl_partial_access.214600317
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.492877615
Short name T809
Test name
Test status
Simulation time 12199074061 ps
CPU time 211.53 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:51:00 PM PDT 24
Peak memory 203272 kb
Host smart-135e10a3-2c15-443e-a21c-406b70b8a26d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492877615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.sram_ctrl_partial_access_b2b.492877615
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.3344304249
Short name T31
Test name
Test status
Simulation time 235214731 ps
CPU time 0.72 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 12:47:28 PM PDT 24
Peak memory 203268 kb
Host smart-3d522c80-b613-4ccd-81d9-7bdffcf4e8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344304249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3344304249
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.2643315247
Short name T758
Test name
Test status
Simulation time 1895493363 ps
CPU time 422.99 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:54:26 PM PDT 24
Peak memory 365668 kb
Host smart-a2d3785d-b71e-437d-bbf4-4ed5c1ab5740
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643315247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2643315247
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.1128275327
Short name T201
Test name
Test status
Simulation time 831017717 ps
CPU time 15.26 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:45 PM PDT 24
Peak memory 203116 kb
Host smart-5d9a2f60-d32e-44a1-88d5-5c37396a429d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128275327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.1128275327
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.154274143
Short name T713
Test name
Test status
Simulation time 37108462932 ps
CPU time 2080.7 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 01:22:05 PM PDT 24
Peak memory 375192 kb
Host smart-7d5d95bd-9a4c-470b-90e9-c38a3aa425fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154274143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_stress_all.154274143
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3853128461
Short name T353
Test name
Test status
Simulation time 877431996 ps
CPU time 22.26 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:47:53 PM PDT 24
Peak memory 211500 kb
Host smart-d36c7f75-4c02-40d7-9bbb-b320b498104f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3853128461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3853128461
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3316014974
Short name T293
Test name
Test status
Simulation time 2583847691 ps
CPU time 235.74 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:51:19 PM PDT 24
Peak memory 203268 kb
Host smart-99c0de08-1e84-4bb0-af1e-3cbb17462005
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316014974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.3316014974
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3568861317
Short name T611
Test name
Test status
Simulation time 456450304 ps
CPU time 48.6 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:48:13 PM PDT 24
Peak memory 325908 kb
Host smart-2fd01057-9db1-4f13-9069-0b81e09f5446
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568861317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3568861317
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3927970971
Short name T476
Test name
Test status
Simulation time 9889694441 ps
CPU time 543.86 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:56:35 PM PDT 24
Peak memory 373856 kb
Host smart-12d3a13e-8a82-43e9-bdb5-e5f08c3f2686
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927970971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.3927970971
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.1341800920
Short name T499
Test name
Test status
Simulation time 14698324 ps
CPU time 0.6 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:47:30 PM PDT 24
Peak memory 201996 kb
Host smart-0b7da5d3-81e2-41ac-9491-c9586f6109e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341800920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.1341800920
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.949970219
Short name T263
Test name
Test status
Simulation time 3456398702 ps
CPU time 48.73 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:48:13 PM PDT 24
Peak memory 203120 kb
Host smart-74c67760-5035-47a4-96f8-b39fa68062f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949970219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.
949970219
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.2480684482
Short name T137
Test name
Test status
Simulation time 44001308088 ps
CPU time 741.08 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:59:46 PM PDT 24
Peak memory 368884 kb
Host smart-218cb328-22bd-4ce1-9e2e-a7d7755f58a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480684482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.2480684482
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.338884855
Short name T211
Test name
Test status
Simulation time 3512075263 ps
CPU time 5.01 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:47:34 PM PDT 24
Peak memory 203252 kb
Host smart-555220dd-b629-48ad-8ae7-e3ab5ed00ba5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338884855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esc
alation.338884855
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.2948939667
Short name T744
Test name
Test status
Simulation time 633131777 ps
CPU time 88.74 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:48:55 PM PDT 24
Peak memory 343176 kb
Host smart-8d5ca721-cd3c-4997-892f-debc13ba0600
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948939667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.2948939667
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1676582341
Short name T602
Test name
Test status
Simulation time 194834295 ps
CPU time 2.87 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:47:28 PM PDT 24
Peak memory 211440 kb
Host smart-71d94203-4eb1-41ae-8428-57590ac4a851
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676582341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.1676582341
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.3154059313
Short name T721
Test name
Test status
Simulation time 1743108013 ps
CPU time 10.08 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:47:34 PM PDT 24
Peak memory 203180 kb
Host smart-fc7da13e-5e58-4606-ac8c-3116e393babe
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154059313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.3154059313
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.3535091564
Short name T870
Test name
Test status
Simulation time 42052726726 ps
CPU time 738.33 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:59:42 PM PDT 24
Peak memory 376080 kb
Host smart-54aeb1ec-fa4e-482c-9e2e-6d3501111d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535091564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.3535091564
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.2905303544
Short name T669
Test name
Test status
Simulation time 265297514 ps
CPU time 16.34 seconds
Started Mar 17 12:47:37 PM PDT 24
Finished Mar 17 12:47:53 PM PDT 24
Peak memory 262476 kb
Host smart-c9486a76-f759-4759-8737-270541ebcba5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905303544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.2905303544
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2990674307
Short name T456
Test name
Test status
Simulation time 19184812589 ps
CPU time 319.9 seconds
Started Mar 17 12:47:34 PM PDT 24
Finished Mar 17 12:52:54 PM PDT 24
Peak memory 203200 kb
Host smart-93db36fe-fd50-4617-8f36-4e76cc894ec9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990674307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.2990674307
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.4000603777
Short name T405
Test name
Test status
Simulation time 141562756 ps
CPU time 0.76 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:30 PM PDT 24
Peak memory 203088 kb
Host smart-532f5f9e-cad2-4cef-94d7-ef747a43452c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000603777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.4000603777
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.3585597557
Short name T907
Test name
Test status
Simulation time 8162091262 ps
CPU time 217.39 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:51:09 PM PDT 24
Peak memory 334108 kb
Host smart-8996f349-90f8-406b-b837-eb458f56ff5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585597557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3585597557
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.2322181241
Short name T360
Test name
Test status
Simulation time 162270110 ps
CPU time 129.78 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:49:33 PM PDT 24
Peak memory 367712 kb
Host smart-21658586-f726-48fa-a64b-fa176bf221ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322181241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2322181241
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.4252745000
Short name T720
Test name
Test status
Simulation time 9430061160 ps
CPU time 3025.78 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 01:37:53 PM PDT 24
Peak memory 376128 kb
Host smart-b06c14ee-1f21-4d77-8a85-d5d02b2834d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252745000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.sram_ctrl_stress_all.4252745000
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2378698722
Short name T706
Test name
Test status
Simulation time 1085976161 ps
CPU time 95.8 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:48:59 PM PDT 24
Peak memory 203152 kb
Host smart-2da72117-72b9-43b3-a7c2-80e5c5ab00f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378698722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.2378698722
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2673034003
Short name T868
Test name
Test status
Simulation time 301954508 ps
CPU time 109.81 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:49:18 PM PDT 24
Peak memory 369632 kb
Host smart-ae912eff-d946-4f6f-8d17-2eb6fbd50217
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673034003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2673034003
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2736703716
Short name T412
Test name
Test status
Simulation time 10781521781 ps
CPU time 1353.53 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 01:09:59 PM PDT 24
Peak memory 372660 kb
Host smart-22b1b5d3-3212-4e65-8273-d85a9f78eba0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736703716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.2736703716
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.3582985948
Short name T675
Test name
Test status
Simulation time 13256237 ps
CPU time 0.64 seconds
Started Mar 17 12:47:33 PM PDT 24
Finished Mar 17 12:47:34 PM PDT 24
Peak memory 202160 kb
Host smart-ee7d8f41-b164-4ae0-98aa-a4b669746db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582985948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.3582985948
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.1007116225
Short name T572
Test name
Test status
Simulation time 4365381704 ps
CPU time 47.63 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:48:11 PM PDT 24
Peak memory 203204 kb
Host smart-01167e6c-ec5b-4d6d-87a6-66fe0319f8c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007116225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.1007116225
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.744227394
Short name T39
Test name
Test status
Simulation time 40414373007 ps
CPU time 666.79 seconds
Started Mar 17 12:47:33 PM PDT 24
Finished Mar 17 12:58:40 PM PDT 24
Peak memory 375056 kb
Host smart-10ea7819-323e-445b-8592-93d58add0a3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744227394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl
e.744227394
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.98729460
Short name T638
Test name
Test status
Simulation time 2679519020 ps
CPU time 5.1 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:47:30 PM PDT 24
Peak memory 203168 kb
Host smart-a8a3c1d1-2841-4916-975c-f9c7f54c22d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98729460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esca
lation.98729460
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.296487755
Short name T802
Test name
Test status
Simulation time 543226676 ps
CPU time 118.41 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:49:23 PM PDT 24
Peak memory 369656 kb
Host smart-10c7f883-1d31-4cc0-97de-ad5f5f4badd5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296487755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.sram_ctrl_max_throughput.296487755
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1516891165
Short name T588
Test name
Test status
Simulation time 253252283 ps
CPU time 4.03 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:28 PM PDT 24
Peak memory 211268 kb
Host smart-8d212527-e219-41c8-9355-0fd095dc17c8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516891165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.1516891165
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.1141335217
Short name T795
Test name
Test status
Simulation time 594774158 ps
CPU time 8.55 seconds
Started Mar 17 12:47:32 PM PDT 24
Finished Mar 17 12:47:45 PM PDT 24
Peak memory 203192 kb
Host smart-b23f44e1-3f7b-4a4d-aef7-8fcfc6dbba02
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141335217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.1141335217
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.3631975370
Short name T622
Test name
Test status
Simulation time 2127139783 ps
CPU time 710.01 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:59:14 PM PDT 24
Peak memory 363592 kb
Host smart-74f4582d-9b9a-467e-967d-9d09f908f611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631975370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.3631975370
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.2022164459
Short name T1
Test name
Test status
Simulation time 688654095 ps
CPU time 12.24 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:47:40 PM PDT 24
Peak memory 203300 kb
Host smart-12e3b997-5586-45a1-8154-14cb7e6b5ef6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022164459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.2022164459
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.4147002394
Short name T853
Test name
Test status
Simulation time 22847814044 ps
CPU time 465.46 seconds
Started Mar 17 12:47:29 PM PDT 24
Finished Mar 17 12:55:15 PM PDT 24
Peak memory 203028 kb
Host smart-e9a9d898-045b-4fbf-b8b5-a60ccbca3bba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147002394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.4147002394
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.3841846769
Short name T167
Test name
Test status
Simulation time 43709267 ps
CPU time 0.72 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 203308 kb
Host smart-4c1f38c7-9963-4c4b-affb-0583dda7fc7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841846769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3841846769
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.2372753178
Short name T922
Test name
Test status
Simulation time 48961743827 ps
CPU time 1169.35 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 01:06:53 PM PDT 24
Peak memory 375812 kb
Host smart-bf7471b8-cda6-4943-b4d6-7675fc4d3292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372753178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2372753178
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.541417201
Short name T688
Test name
Test status
Simulation time 109986602 ps
CPU time 76.97 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 12:48:44 PM PDT 24
Peak memory 327820 kb
Host smart-1251d000-c829-4ce3-ac9c-0d18ce215636
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541417201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.541417201
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.2230072193
Short name T506
Test name
Test status
Simulation time 56095742420 ps
CPU time 2465.76 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 01:28:29 PM PDT 24
Peak memory 383192 kb
Host smart-2bd8a9ce-5803-4b34-8199-5f43fa0c8927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230072193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.2230072193
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.293430109
Short name T109
Test name
Test status
Simulation time 1154077832 ps
CPU time 109.24 seconds
Started Mar 17 12:47:35 PM PDT 24
Finished Mar 17 12:49:25 PM PDT 24
Peak memory 358624 kb
Host smart-13df9eb8-82c4-4451-b350-a7587c737b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=293430109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.293430109
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2774514739
Short name T99
Test name
Test status
Simulation time 11284969610 ps
CPU time 243.21 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:51:26 PM PDT 24
Peak memory 203228 kb
Host smart-d3013019-b8c5-4b9c-a17a-3f807cdbb524
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774514739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.2774514739
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.512884266
Short name T454
Test name
Test status
Simulation time 390398509 ps
CPU time 59.94 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:48:28 PM PDT 24
Peak memory 318568 kb
Host smart-e833933f-43d4-4917-9b19-e32ec0de9f55
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512884266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.512884266
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2365427198
Short name T477
Test name
Test status
Simulation time 17102456654 ps
CPU time 1096.99 seconds
Started Mar 17 12:47:36 PM PDT 24
Finished Mar 17 01:05:53 PM PDT 24
Peak memory 374136 kb
Host smart-f32feaf6-e47d-4cf7-b0b1-cc4456fd5106
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365427198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.2365427198
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.839256860
Short name T910
Test name
Test status
Simulation time 16239661 ps
CPU time 0.65 seconds
Started Mar 17 12:47:32 PM PDT 24
Finished Mar 17 12:47:32 PM PDT 24
Peak memory 202936 kb
Host smart-bc8ee461-3737-4bcc-803f-00c081a84e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839256860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.839256860
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.668560923
Short name T575
Test name
Test status
Simulation time 441784936 ps
CPU time 26.34 seconds
Started Mar 17 12:47:32 PM PDT 24
Finished Mar 17 12:47:58 PM PDT 24
Peak memory 203192 kb
Host smart-58931978-0fae-4927-9d4e-37f920a060a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668560923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.
668560923
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.1556902033
Short name T308
Test name
Test status
Simulation time 2528019558 ps
CPU time 978.06 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 374988 kb
Host smart-acbab171-46ef-415c-95bf-def8f7f54cdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556902033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.1556902033
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.504627196
Short name T248
Test name
Test status
Simulation time 4975636431 ps
CPU time 8.64 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:47:35 PM PDT 24
Peak memory 203368 kb
Host smart-c9bdff9d-8130-4578-a991-186efd2dfb6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504627196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_esc
alation.504627196
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.3419994269
Short name T208
Test name
Test status
Simulation time 198534928 ps
CPU time 51.77 seconds
Started Mar 17 12:47:32 PM PDT 24
Finished Mar 17 12:48:24 PM PDT 24
Peak memory 309920 kb
Host smart-bdcdff40-7571-4bb5-97a7-ee8c949029f4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419994269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.3419994269
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3989972785
Short name T306
Test name
Test status
Simulation time 86814450 ps
CPU time 2.52 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:47:30 PM PDT 24
Peak memory 211404 kb
Host smart-8ff4093b-6b81-409c-8965-f4d99780facc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989972785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.3989972785
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.675520351
Short name T14
Test name
Test status
Simulation time 875978668 ps
CPU time 9.43 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 12:47:37 PM PDT 24
Peak memory 203116 kb
Host smart-963da79d-98ea-40ea-a854-fd9306dcf1dc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675520351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl
_mem_walk.675520351
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.975234471
Short name T199
Test name
Test status
Simulation time 8900226122 ps
CPU time 1305.3 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 01:09:10 PM PDT 24
Peak memory 376024 kb
Host smart-3cc6c12a-a9e1-4f95-933b-7f586f180141
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975234471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip
le_keys.975234471
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.130206826
Short name T589
Test name
Test status
Simulation time 773793785 ps
CPU time 7.38 seconds
Started Mar 17 12:47:28 PM PDT 24
Finished Mar 17 12:47:36 PM PDT 24
Peak memory 203164 kb
Host smart-e5d74479-b18b-46d8-bb3a-e5f6c6e4863a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130206826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s
ram_ctrl_partial_access.130206826
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.166970758
Short name T584
Test name
Test status
Simulation time 9340144598 ps
CPU time 317.59 seconds
Started Mar 17 12:47:33 PM PDT 24
Finished Mar 17 12:52:51 PM PDT 24
Peak memory 203344 kb
Host smart-7ee54b1b-f1c8-4894-b49b-2c2c590de9b4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166970758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.sram_ctrl_partial_access_b2b.166970758
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.1806504617
Short name T160
Test name
Test status
Simulation time 150175114 ps
CPU time 0.78 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 12:47:33 PM PDT 24
Peak memory 203224 kb
Host smart-78f69eb4-f363-409e-b50f-c7edc19c68ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806504617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1806504617
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.4125783352
Short name T697
Test name
Test status
Simulation time 12601377517 ps
CPU time 455.17 seconds
Started Mar 17 12:47:25 PM PDT 24
Finished Mar 17 12:55:01 PM PDT 24
Peak memory 371364 kb
Host smart-3824887d-14a6-43cd-a46b-3ab6d799d723
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125783352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.4125783352
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.2748582213
Short name T290
Test name
Test status
Simulation time 252232762 ps
CPU time 126.63 seconds
Started Mar 17 12:47:32 PM PDT 24
Finished Mar 17 12:49:38 PM PDT 24
Peak memory 361996 kb
Host smart-72c7b4ff-3317-433a-aa3a-9a87c774fbcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748582213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2748582213
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2573884554
Short name T757
Test name
Test status
Simulation time 7721003719 ps
CPU time 1381.21 seconds
Started Mar 17 12:47:37 PM PDT 24
Finished Mar 17 01:10:39 PM PDT 24
Peak memory 383256 kb
Host smart-a263aaa7-5321-49fc-a6b1-8380b95f7ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2573884554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2573884554
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.51517846
Short name T766
Test name
Test status
Simulation time 2517185163 ps
CPU time 228.02 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:51:19 PM PDT 24
Peak memory 203220 kb
Host smart-46905c6f-4a8d-42f5-b35b-970d2f041862
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51517846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_stress_pipeline.51517846
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1377156724
Short name T250
Test name
Test status
Simulation time 368208396 ps
CPU time 18.01 seconds
Started Mar 17 12:47:27 PM PDT 24
Finished Mar 17 12:47:45 PM PDT 24
Peak memory 270624 kb
Host smart-cd479681-478b-4459-b8d3-725d0a039daf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377156724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1377156724
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.19561310
Short name T822
Test name
Test status
Simulation time 8120778146 ps
CPU time 571.86 seconds
Started Mar 17 12:47:38 PM PDT 24
Finished Mar 17 12:57:10 PM PDT 24
Peak memory 372708 kb
Host smart-02c08831-97da-421f-9671-ff4d73dea009
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19561310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.sram_ctrl_access_during_key_req.19561310
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.3426456
Short name T636
Test name
Test status
Simulation time 45291524 ps
CPU time 0.65 seconds
Started Mar 17 12:47:40 PM PDT 24
Finished Mar 17 12:47:41 PM PDT 24
Peak memory 202028 kb
Host smart-b90f6970-e685-4df5-b829-e48d7d70e8ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_alert_test.3426456
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.2982257340
Short name T213
Test name
Test status
Simulation time 41302880190 ps
CPU time 66.13 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:48:37 PM PDT 24
Peak memory 203188 kb
Host smart-3d8258b7-73e1-47b2-bac1-960d51dfcebc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982257340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.2982257340
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.3535965699
Short name T785
Test name
Test status
Simulation time 9060388810 ps
CPU time 244.59 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:51:36 PM PDT 24
Peak memory 351172 kb
Host smart-e5a851c7-5f32-4d25-9ba4-437c3a7849f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535965699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.3535965699
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.2423263375
Short name T488
Test name
Test status
Simulation time 3697856334 ps
CPU time 10.18 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:47:41 PM PDT 24
Peak memory 203344 kb
Host smart-44f43a97-6cd6-4f3d-9490-202fea49ade1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423263375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.2423263375
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.3354628842
Short name T816
Test name
Test status
Simulation time 321715885 ps
CPU time 14.5 seconds
Started Mar 17 12:47:34 PM PDT 24
Finished Mar 17 12:47:49 PM PDT 24
Peak memory 257368 kb
Host smart-50d0acd5-14d0-4305-b2bf-4998ed6c5185
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354628842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.3354628842
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2759981687
Short name T82
Test name
Test status
Simulation time 434821349 ps
CPU time 3.08 seconds
Started Mar 17 12:47:56 PM PDT 24
Finished Mar 17 12:47:59 PM PDT 24
Peak memory 211316 kb
Host smart-a82a2e89-9c0d-4540-a781-5aa849d866c7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759981687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.2759981687
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.764130981
Short name T178
Test name
Test status
Simulation time 1374938468 ps
CPU time 9.69 seconds
Started Mar 17 12:47:38 PM PDT 24
Finished Mar 17 12:47:48 PM PDT 24
Peak memory 203116 kb
Host smart-d16369c1-beeb-40ad-9ce6-93254e6b0816
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764130981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_mem_walk.764130981
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.2143980589
Short name T151
Test name
Test status
Simulation time 23920120416 ps
CPU time 530.92 seconds
Started Mar 17 12:47:33 PM PDT 24
Finished Mar 17 12:56:24 PM PDT 24
Peak memory 374864 kb
Host smart-34369271-7978-4079-b3e1-5b210b87567d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143980589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.2143980589
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.3350819113
Short name T788
Test name
Test status
Simulation time 213675055 ps
CPU time 1.32 seconds
Started Mar 17 12:47:30 PM PDT 24
Finished Mar 17 12:47:32 PM PDT 24
Peak memory 203340 kb
Host smart-49f2a971-6d88-4b45-ab63-95809f11447a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350819113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.3350819113
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3482061152
Short name T420
Test name
Test status
Simulation time 34896179096 ps
CPU time 339.46 seconds
Started Mar 17 12:47:34 PM PDT 24
Finished Mar 17 12:53:14 PM PDT 24
Peak memory 203328 kb
Host smart-d5a65c5e-2fec-4b31-8525-d79a1b4712a5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482061152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.3482061152
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.764651614
Short name T579
Test name
Test status
Simulation time 76598933 ps
CPU time 0.74 seconds
Started Mar 17 12:47:47 PM PDT 24
Finished Mar 17 12:47:48 PM PDT 24
Peak memory 203188 kb
Host smart-290967ba-7491-4ab7-8220-2ee8498ca30f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764651614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.764651614
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.292237561
Short name T336
Test name
Test status
Simulation time 7100906778 ps
CPU time 535.16 seconds
Started Mar 17 12:47:38 PM PDT 24
Finished Mar 17 12:56:33 PM PDT 24
Peak memory 348124 kb
Host smart-456fdf75-759d-4900-b2cb-6f5c834a8fd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292237561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.292237561
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.2394075661
Short name T355
Test name
Test status
Simulation time 413221606 ps
CPU time 2.88 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 203100 kb
Host smart-f8dbcd18-9f2b-4e61-a693-f69d1943237c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394075661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2394075661
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.512549843
Short name T498
Test name
Test status
Simulation time 15825829698 ps
CPU time 1365.58 seconds
Started Mar 17 12:47:49 PM PDT 24
Finished Mar 17 01:10:35 PM PDT 24
Peak memory 382488 kb
Host smart-876656c1-0632-4293-9424-dcc078babb0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512549843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_stress_all.512549843
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3260012035
Short name T452
Test name
Test status
Simulation time 370690534 ps
CPU time 56.28 seconds
Started Mar 17 12:47:43 PM PDT 24
Finished Mar 17 12:48:40 PM PDT 24
Peak memory 283024 kb
Host smart-3b1da4c1-3b99-4081-af5a-1df4a6b37b94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3260012035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3260012035
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2235899937
Short name T391
Test name
Test status
Simulation time 5786438529 ps
CPU time 88.14 seconds
Started Mar 17 12:47:34 PM PDT 24
Finished Mar 17 12:49:02 PM PDT 24
Peak memory 203256 kb
Host smart-f6a1b06d-a3a2-422d-a77d-11edc5d7969d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235899937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.2235899937
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1463766583
Short name T661
Test name
Test status
Simulation time 171148242 ps
CPU time 2.68 seconds
Started Mar 17 12:47:31 PM PDT 24
Finished Mar 17 12:47:34 PM PDT 24
Peak memory 219548 kb
Host smart-e6030e26-bd93-4956-b4b5-bf368079f5d5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463766583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1463766583
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.571799850
Short name T745
Test name
Test status
Simulation time 1989549090 ps
CPU time 895.45 seconds
Started Mar 17 12:47:55 PM PDT 24
Finished Mar 17 01:02:50 PM PDT 24
Peak memory 371972 kb
Host smart-ebeb15de-aca6-46d2-9eee-1075c7bb7129
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571799850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.sram_ctrl_access_during_key_req.571799850
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.1497811570
Short name T773
Test name
Test status
Simulation time 22328972 ps
CPU time 0.61 seconds
Started Mar 17 12:48:00 PM PDT 24
Finished Mar 17 12:48:01 PM PDT 24
Peak memory 202104 kb
Host smart-807d0bad-2f3e-4cbb-866f-507fc50828b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497811570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.1497811570
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.3965708444
Short name T352
Test name
Test status
Simulation time 694959165 ps
CPU time 39.66 seconds
Started Mar 17 12:47:39 PM PDT 24
Finished Mar 17 12:48:19 PM PDT 24
Peak memory 203108 kb
Host smart-123ec291-f0e8-4254-931c-2c6e9ddaafaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965708444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.3965708444
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.4000572910
Short name T305
Test name
Test status
Simulation time 1925279787 ps
CPU time 202.68 seconds
Started Mar 17 12:47:57 PM PDT 24
Finished Mar 17 12:51:19 PM PDT 24
Peak memory 350060 kb
Host smart-71bb3588-d4e5-4f6c-83e2-ecf698cb32c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000572910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.4000572910
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.1241424481
Short name T939
Test name
Test status
Simulation time 2458813970 ps
CPU time 7.62 seconds
Started Mar 17 12:47:46 PM PDT 24
Finished Mar 17 12:47:54 PM PDT 24
Peak memory 203148 kb
Host smart-122533d0-cc31-4e6f-8787-3a7da7deb658
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241424481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.1241424481
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.3535260598
Short name T737
Test name
Test status
Simulation time 76852873 ps
CPU time 23.35 seconds
Started Mar 17 12:47:45 PM PDT 24
Finished Mar 17 12:48:09 PM PDT 24
Peak memory 271692 kb
Host smart-cf7fed7a-a71c-41c8-9a10-c9f92cb5b81f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535260598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.3535260598
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3265069020
Short name T79
Test name
Test status
Simulation time 195332099 ps
CPU time 3.03 seconds
Started Mar 17 12:47:48 PM PDT 24
Finished Mar 17 12:47:51 PM PDT 24
Peak memory 211432 kb
Host smart-09130753-d469-4a2f-8916-7b0608e438c6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265069020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.3265069020
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.3994063983
Short name T184
Test name
Test status
Simulation time 466878713 ps
CPU time 4.92 seconds
Started Mar 17 12:47:43 PM PDT 24
Finished Mar 17 12:47:48 PM PDT 24
Peak memory 203164 kb
Host smart-a5e816c7-ec65-4e48-8de7-bf9dd2ebe74f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994063983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.3994063983
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.870847399
Short name T752
Test name
Test status
Simulation time 4471744874 ps
CPU time 572.27 seconds
Started Mar 17 12:47:38 PM PDT 24
Finished Mar 17 12:57:11 PM PDT 24
Peak memory 373992 kb
Host smart-8b6721d2-edcc-47a0-8f83-89d02d0860a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870847399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multip
le_keys.870847399
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.2344043964
Short name T898
Test name
Test status
Simulation time 2296766382 ps
CPU time 89.8 seconds
Started Mar 17 12:47:42 PM PDT 24
Finished Mar 17 12:49:12 PM PDT 24
Peak memory 341004 kb
Host smart-cfd69686-7fd3-4a67-b788-1e2141984184
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344043964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.2344043964
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2168244220
Short name T761
Test name
Test status
Simulation time 24879460872 ps
CPU time 277.44 seconds
Started Mar 17 12:47:39 PM PDT 24
Finished Mar 17 12:52:17 PM PDT 24
Peak memory 203268 kb
Host smart-308acd9b-b750-4a7d-ad89-595834a0efd6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168244220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.2168244220
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.2553654716
Short name T852
Test name
Test status
Simulation time 102061882 ps
CPU time 0.75 seconds
Started Mar 17 12:47:48 PM PDT 24
Finished Mar 17 12:47:49 PM PDT 24
Peak memory 203216 kb
Host smart-4fe39137-ca09-40f3-935b-03fc2d2dfded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553654716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2553654716
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.1414558627
Short name T569
Test name
Test status
Simulation time 2361496029 ps
CPU time 545.43 seconds
Started Mar 17 12:47:48 PM PDT 24
Finished Mar 17 12:56:53 PM PDT 24
Peak memory 367772 kb
Host smart-19d4fa45-8e71-4233-910e-6c2ed4012538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414558627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1414558627
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.2316353432
Short name T875
Test name
Test status
Simulation time 227007391 ps
CPU time 11.33 seconds
Started Mar 17 12:47:38 PM PDT 24
Finished Mar 17 12:47:49 PM PDT 24
Peak memory 203116 kb
Host smart-cdcf1446-5d0c-47c4-a4b8-06885ba37d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316353432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2316353432
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.4192325678
Short name T541
Test name
Test status
Simulation time 2253690353 ps
CPU time 205.29 seconds
Started Mar 17 12:47:39 PM PDT 24
Finished Mar 17 12:51:05 PM PDT 24
Peak memory 203252 kb
Host smart-62718627-9b65-4674-820a-b41cd50f94de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192325678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.4192325678
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1012644995
Short name T229
Test name
Test status
Simulation time 1099218348 ps
CPU time 36.47 seconds
Started Mar 17 12:47:53 PM PDT 24
Finished Mar 17 12:48:30 PM PDT 24
Peak memory 294100 kb
Host smart-7c0be0cd-9286-4885-b6af-aa8895d88aee
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012644995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1012644995
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.446869998
Short name T21
Test name
Test status
Simulation time 11224048398 ps
CPU time 611.47 seconds
Started Mar 17 12:47:46 PM PDT 24
Finished Mar 17 12:57:58 PM PDT 24
Peak memory 369716 kb
Host smart-0539a9e1-62db-4e15-8964-fe3bf89e6c52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446869998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.sram_ctrl_access_during_key_req.446869998
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.3907619886
Short name T395
Test name
Test status
Simulation time 15058178 ps
CPU time 0.65 seconds
Started Mar 17 12:48:00 PM PDT 24
Finished Mar 17 12:48:00 PM PDT 24
Peak memory 202340 kb
Host smart-98bebf7b-50e4-4e8d-98eb-c904155e3459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907619886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.3907619886
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.3036790264
Short name T145
Test name
Test status
Simulation time 2818535591 ps
CPU time 56.1 seconds
Started Mar 17 12:47:47 PM PDT 24
Finished Mar 17 12:48:44 PM PDT 24
Peak memory 203132 kb
Host smart-0ec3d257-876e-489d-8718-d5a20631feb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036790264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.3036790264
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.3864281569
Short name T616
Test name
Test status
Simulation time 21737047223 ps
CPU time 649.47 seconds
Started Mar 17 12:47:44 PM PDT 24
Finished Mar 17 12:58:34 PM PDT 24
Peak memory 367808 kb
Host smart-3ec9d9da-2172-487b-9e59-a9cb562b73bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864281569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.3864281569
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.496148959
Short name T847
Test name
Test status
Simulation time 3495813641 ps
CPU time 7.32 seconds
Started Mar 17 12:47:48 PM PDT 24
Finished Mar 17 12:47:55 PM PDT 24
Peak memory 203240 kb
Host smart-a5d2fbe8-963b-4271-9ac4-ec4e8e3a87fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496148959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esc
alation.496148959
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.3581745549
Short name T429
Test name
Test status
Simulation time 80863136 ps
CPU time 7.51 seconds
Started Mar 17 12:47:59 PM PDT 24
Finished Mar 17 12:48:07 PM PDT 24
Peak memory 239656 kb
Host smart-44a2dd1d-b62d-4602-a45b-df1d451f4014
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581745549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.3581745549
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2728570155
Short name T522
Test name
Test status
Simulation time 67578439 ps
CPU time 4.33 seconds
Started Mar 17 12:47:54 PM PDT 24
Finished Mar 17 12:47:58 PM PDT 24
Peak memory 211428 kb
Host smart-c42b8d40-ad1a-4158-8f39-a020f8006d4a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728570155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.2728570155
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.4177342622
Short name T510
Test name
Test status
Simulation time 1111416064 ps
CPU time 5.16 seconds
Started Mar 17 12:47:44 PM PDT 24
Finished Mar 17 12:47:49 PM PDT 24
Peak memory 203212 kb
Host smart-ea461c54-a3b8-4744-a0fd-61487dc72408
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177342622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.4177342622
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.325733311
Short name T940
Test name
Test status
Simulation time 50076953618 ps
CPU time 632.92 seconds
Started Mar 17 12:47:59 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 372952 kb
Host smart-2069e486-54c2-4e95-8da3-2a62f37183cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325733311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip
le_keys.325733311
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.2992607981
Short name T814
Test name
Test status
Simulation time 119774441 ps
CPU time 29.23 seconds
Started Mar 17 12:47:56 PM PDT 24
Finished Mar 17 12:48:25 PM PDT 24
Peak memory 282372 kb
Host smart-2778465f-626b-4090-8bd9-52c6b5c20c76
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992607981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.2992607981
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3191516071
Short name T296
Test name
Test status
Simulation time 7838538631 ps
CPU time 234.32 seconds
Started Mar 17 12:47:49 PM PDT 24
Finished Mar 17 12:51:43 PM PDT 24
Peak memory 203172 kb
Host smart-986e4459-2e20-4a22-8c33-dbb63455a3fd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191516071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.3191516071
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.2655739232
Short name T521
Test name
Test status
Simulation time 90400099 ps
CPU time 0.74 seconds
Started Mar 17 12:47:44 PM PDT 24
Finished Mar 17 12:47:45 PM PDT 24
Peak memory 203240 kb
Host smart-aafcc5d4-51de-4f50-9ffa-1ad471c1b772
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655739232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2655739232
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.706168725
Short name T177
Test name
Test status
Simulation time 15056870030 ps
CPU time 809.92 seconds
Started Mar 17 12:47:46 PM PDT 24
Finished Mar 17 01:01:17 PM PDT 24
Peak memory 374104 kb
Host smart-5a30a7b1-d82c-4246-a7bc-af6a77ab7039
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706168725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.706168725
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.3217813789
Short name T350
Test name
Test status
Simulation time 961356611 ps
CPU time 14.68 seconds
Started Mar 17 12:48:00 PM PDT 24
Finished Mar 17 12:48:14 PM PDT 24
Peak memory 203188 kb
Host smart-2d892882-2d3d-4bb0-bfc1-c8d62fe3400f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217813789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3217813789
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.1932571848
Short name T699
Test name
Test status
Simulation time 42195229159 ps
CPU time 4024.5 seconds
Started Mar 17 12:47:44 PM PDT 24
Finished Mar 17 01:54:49 PM PDT 24
Peak memory 376168 kb
Host smart-a4bbcb77-6a90-4a1f-b99f-c067fdbfc17f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932571848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.1932571848
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1320252050
Short name T317
Test name
Test status
Simulation time 1434099962 ps
CPU time 96.05 seconds
Started Mar 17 12:47:56 PM PDT 24
Finished Mar 17 12:49:32 PM PDT 24
Peak memory 308276 kb
Host smart-ad1af55f-e856-4e59-8b2e-777dd4aeb2e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1320252050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1320252050
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.4173098129
Short name T209
Test name
Test status
Simulation time 19988287886 ps
CPU time 133.24 seconds
Started Mar 17 12:47:59 PM PDT 24
Finished Mar 17 12:50:13 PM PDT 24
Peak memory 203160 kb
Host smart-8e07c08c-7908-45d8-84a1-799327b4dadb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173098129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.4173098129
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3724541258
Short name T687
Test name
Test status
Simulation time 216566171 ps
CPU time 5.43 seconds
Started Mar 17 12:47:53 PM PDT 24
Finished Mar 17 12:47:59 PM PDT 24
Peak memory 227068 kb
Host smart-5b7b10eb-c65b-46be-9baa-f77a239695a1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724541258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3724541258
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2537714441
Short name T601
Test name
Test status
Simulation time 5594763617 ps
CPU time 948.97 seconds
Started Mar 17 12:48:05 PM PDT 24
Finished Mar 17 01:03:54 PM PDT 24
Peak memory 372896 kb
Host smart-9e3086d7-23da-488c-a9f7-a65418d0a23a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537714441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.2537714441
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.3710585409
Short name T478
Test name
Test status
Simulation time 17835484 ps
CPU time 0.65 seconds
Started Mar 17 12:47:53 PM PDT 24
Finished Mar 17 12:47:54 PM PDT 24
Peak memory 202056 kb
Host smart-ada85090-cfed-4d2b-a149-f180dc173780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710585409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.3710585409
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.1912392610
Short name T512
Test name
Test status
Simulation time 4030651298 ps
CPU time 59.09 seconds
Started Mar 17 12:47:52 PM PDT 24
Finished Mar 17 12:48:51 PM PDT 24
Peak memory 203192 kb
Host smart-ad4db9f0-9a06-4853-acbd-40ecd56d1811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912392610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.1912392610
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.2506916540
Short name T272
Test name
Test status
Simulation time 7980681246 ps
CPU time 500.62 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 12:56:29 PM PDT 24
Peak memory 360664 kb
Host smart-9aae4a3a-b9ab-475c-ae9f-c499d3da5659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506916540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.2506916540
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.1624959537
Short name T54
Test name
Test status
Simulation time 220950863 ps
CPU time 3.16 seconds
Started Mar 17 12:47:58 PM PDT 24
Finished Mar 17 12:48:02 PM PDT 24
Peak memory 203148 kb
Host smart-39fa2bca-b992-416b-9b5b-a5804a2850e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624959537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.1624959537
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.3930117602
Short name T159
Test name
Test status
Simulation time 516419493 ps
CPU time 35.64 seconds
Started Mar 17 12:47:54 PM PDT 24
Finished Mar 17 12:48:30 PM PDT 24
Peak memory 288324 kb
Host smart-95bd4fca-bf2a-469c-b456-b191d02f7968
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930117602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.3930117602
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3616880222
Short name T479
Test name
Test status
Simulation time 87203705 ps
CPU time 2.98 seconds
Started Mar 17 12:47:53 PM PDT 24
Finished Mar 17 12:47:56 PM PDT 24
Peak memory 211352 kb
Host smart-945d0a50-cd14-4f7a-a7e0-a1b595ffc5c1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616880222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.3616880222
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.1202450554
Short name T181
Test name
Test status
Simulation time 304832966 ps
CPU time 5.41 seconds
Started Mar 17 12:47:57 PM PDT 24
Finished Mar 17 12:48:03 PM PDT 24
Peak memory 203280 kb
Host smart-fe327933-8e77-469d-b4a0-9e68a1ead501
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202450554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.1202450554
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.1237300712
Short name T362
Test name
Test status
Simulation time 5136543126 ps
CPU time 788.92 seconds
Started Mar 17 12:47:54 PM PDT 24
Finished Mar 17 01:01:03 PM PDT 24
Peak memory 376172 kb
Host smart-55528897-88f5-4ad5-a52e-67e85b03e707
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237300712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.1237300712
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.1736128246
Short name T918
Test name
Test status
Simulation time 321694817 ps
CPU time 23.8 seconds
Started Mar 17 12:47:54 PM PDT 24
Finished Mar 17 12:48:18 PM PDT 24
Peak memory 272724 kb
Host smart-ad0d6e36-2bb6-44b5-a841-3811926fe756
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736128246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.1736128246
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1782377294
Short name T563
Test name
Test status
Simulation time 4143669261 ps
CPU time 301.72 seconds
Started Mar 17 12:47:54 PM PDT 24
Finished Mar 17 12:52:56 PM PDT 24
Peak memory 203384 kb
Host smart-d8701d53-c7cd-4d6b-ac30-07c58c0a7727
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782377294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.1782377294
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.3972847575
Short name T38
Test name
Test status
Simulation time 72461799 ps
CPU time 0.75 seconds
Started Mar 17 12:47:54 PM PDT 24
Finished Mar 17 12:47:55 PM PDT 24
Peak memory 203448 kb
Host smart-8ef1b59d-a48e-4a49-99a6-8f3531879e82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972847575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3972847575
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.2536739189
Short name T114
Test name
Test status
Simulation time 17156186381 ps
CPU time 1011.26 seconds
Started Mar 17 12:47:51 PM PDT 24
Finished Mar 17 01:04:43 PM PDT 24
Peak memory 356100 kb
Host smart-f93aada3-f088-4f32-8948-ca9327fb793f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536739189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2536739189
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.1233592903
Short name T197
Test name
Test status
Simulation time 1646503058 ps
CPU time 29.73 seconds
Started Mar 17 12:47:54 PM PDT 24
Finished Mar 17 12:48:24 PM PDT 24
Peak memory 281732 kb
Host smart-de0e4bfd-e8f4-487b-a6ba-4b7d179cc655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233592903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1233592903
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.4069403896
Short name T53
Test name
Test status
Simulation time 23814417146 ps
CPU time 1767.75 seconds
Started Mar 17 12:47:51 PM PDT 24
Finished Mar 17 01:17:19 PM PDT 24
Peak memory 382852 kb
Host smart-6cb5b1cd-9acf-4bf4-ac14-1526607d3129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069403896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.4069403896
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3327768503
Short name T634
Test name
Test status
Simulation time 424977311 ps
CPU time 274.46 seconds
Started Mar 17 12:47:58 PM PDT 24
Finished Mar 17 12:52:33 PM PDT 24
Peak memory 377636 kb
Host smart-30093906-c3af-4449-bc8d-7100b2314096
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3327768503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3327768503
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3366766468
Short name T218
Test name
Test status
Simulation time 9276748878 ps
CPU time 218.59 seconds
Started Mar 17 12:47:58 PM PDT 24
Finished Mar 17 12:51:37 PM PDT 24
Peak memory 203268 kb
Host smart-2c90c94b-45d7-490b-a22c-2f0953bc532f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366766468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.3366766468
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.488597722
Short name T315
Test name
Test status
Simulation time 525195785 ps
CPU time 85.24 seconds
Started Mar 17 12:47:53 PM PDT 24
Finished Mar 17 12:49:19 PM PDT 24
Peak memory 346256 kb
Host smart-463b4a77-c457-4863-b9fc-3b3d1dc451a4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488597722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_throughput_w_partial_write.488597722
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.1041559846
Short name T620
Test name
Test status
Simulation time 4119704052 ps
CPU time 1063.16 seconds
Started Mar 17 12:47:58 PM PDT 24
Finished Mar 17 01:05:42 PM PDT 24
Peak memory 373000 kb
Host smart-089b1bff-9349-4603-80c8-444ea214562f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041559846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.1041559846
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.3865984217
Short name T430
Test name
Test status
Simulation time 25874628 ps
CPU time 0.7 seconds
Started Mar 17 12:48:04 PM PDT 24
Finished Mar 17 12:48:04 PM PDT 24
Peak memory 202296 kb
Host smart-6daf8e5b-bad2-4a6e-9b0b-da35437d3160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865984217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.3865984217
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.777000781
Short name T116
Test name
Test status
Simulation time 653030994 ps
CPU time 28.9 seconds
Started Mar 17 12:47:53 PM PDT 24
Finished Mar 17 12:48:22 PM PDT 24
Peak memory 203168 kb
Host smart-ed5719e4-4371-487b-a7da-78a3d7d9459c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777000781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.
777000781
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.38116851
Short name T135
Test name
Test status
Simulation time 62303702793 ps
CPU time 776.78 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 01:01:00 PM PDT 24
Peak memory 367908 kb
Host smart-ad4fbb78-a7d5-4f87-9e65-703564cde927
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38116851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable
.38116851
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.3744135068
Short name T514
Test name
Test status
Simulation time 395466802 ps
CPU time 4.97 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:48:08 PM PDT 24
Peak memory 203144 kb
Host smart-7879055f-5ebe-4765-aa5d-aa94d35ca546
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744135068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.3744135068
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.231554883
Short name T554
Test name
Test status
Simulation time 129756948 ps
CPU time 83.8 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:49:27 PM PDT 24
Peak memory 357696 kb
Host smart-2b02ace4-0ed2-4a75-bfef-0e892974bb80
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231554883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.sram_ctrl_max_throughput.231554883
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1072156095
Short name T837
Test name
Test status
Simulation time 165055424 ps
CPU time 4.86 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:48:08 PM PDT 24
Peak memory 211504 kb
Host smart-fe0a7465-ca32-4e6f-add8-7fed3a4d0294
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072156095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.1072156095
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.901492581
Short name T733
Test name
Test status
Simulation time 327900877 ps
CPU time 4.91 seconds
Started Mar 17 12:48:05 PM PDT 24
Finished Mar 17 12:48:10 PM PDT 24
Peak memory 203144 kb
Host smart-d565a478-30e8-42dc-b1b2-f7b145fbeba0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901492581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl
_mem_walk.901492581
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.947264939
Short name T326
Test name
Test status
Simulation time 3319449596 ps
CPU time 508.41 seconds
Started Mar 17 12:47:58 PM PDT 24
Finished Mar 17 12:56:27 PM PDT 24
Peak memory 374972 kb
Host smart-f5bf5631-92ed-45c2-b162-1066da6baa4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947264939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip
le_keys.947264939
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.279099773
Short name T671
Test name
Test status
Simulation time 340088332 ps
CPU time 8.95 seconds
Started Mar 17 12:47:58 PM PDT 24
Finished Mar 17 12:48:07 PM PDT 24
Peak memory 203172 kb
Host smart-04422da2-e13d-4d23-bbfc-6eb8093140e8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279099773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s
ram_ctrl_partial_access.279099773
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3245162170
Short name T835
Test name
Test status
Simulation time 43159194427 ps
CPU time 286.17 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:52:50 PM PDT 24
Peak memory 203244 kb
Host smart-89e4b660-5bb8-4ec9-a55a-f3af15b38d62
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245162170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.3245162170
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.2006259971
Short name T760
Test name
Test status
Simulation time 47029145 ps
CPU time 0.8 seconds
Started Mar 17 12:47:56 PM PDT 24
Finished Mar 17 12:47:57 PM PDT 24
Peak memory 203196 kb
Host smart-5d42a64e-12a6-4dcb-96f2-32eb1181b9a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006259971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2006259971
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.293426264
Short name T425
Test name
Test status
Simulation time 5179926842 ps
CPU time 571.47 seconds
Started Mar 17 12:47:59 PM PDT 24
Finished Mar 17 12:57:30 PM PDT 24
Peak memory 373908 kb
Host smart-ab4bf81e-d867-4b9f-88e5-162ad4a1d954
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293426264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.293426264
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.3585091657
Short name T17
Test name
Test status
Simulation time 198594969 ps
CPU time 136.74 seconds
Started Mar 17 12:47:54 PM PDT 24
Finished Mar 17 12:50:10 PM PDT 24
Peak memory 368696 kb
Host smart-76364287-33dc-4285-baa5-a4e02b451c55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585091657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3585091657
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.2626436297
Short name T726
Test name
Test status
Simulation time 92414793444 ps
CPU time 1395.24 seconds
Started Mar 17 12:47:58 PM PDT 24
Finished Mar 17 01:11:14 PM PDT 24
Peak memory 371928 kb
Host smart-990464e9-5030-4dd4-91c7-ab25b1270830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626436297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.2626436297
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1063619876
Short name T712
Test name
Test status
Simulation time 1235161369 ps
CPU time 182.09 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:51:05 PM PDT 24
Peak memory 314564 kb
Host smart-3009bd20-9b5b-4bac-8d23-034927b045b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1063619876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1063619876
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3305243299
Short name T341
Test name
Test status
Simulation time 2645643480 ps
CPU time 225.59 seconds
Started Mar 17 12:47:58 PM PDT 24
Finished Mar 17 12:51:43 PM PDT 24
Peak memory 203292 kb
Host smart-f6be570b-d63d-4409-9e09-4427a80923c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305243299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.3305243299
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2110899370
Short name T538
Test name
Test status
Simulation time 355573788 ps
CPU time 7.97 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:48:11 PM PDT 24
Peak memory 238060 kb
Host smart-eceac6a1-859b-44e4-9828-602fa2956620
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110899370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2110899370
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2398250061
Short name T23
Test name
Test status
Simulation time 12084939609 ps
CPU time 1314.44 seconds
Started Mar 17 12:48:05 PM PDT 24
Finished Mar 17 01:10:00 PM PDT 24
Peak memory 373988 kb
Host smart-1aa3a2ef-33a5-41c0-910c-996cc1fe006e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398250061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.2398250061
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.89633811
Short name T534
Test name
Test status
Simulation time 16425758 ps
CPU time 0.62 seconds
Started Mar 17 12:48:15 PM PDT 24
Finished Mar 17 12:48:18 PM PDT 24
Peak memory 202944 kb
Host smart-3ed16dc1-5620-4c1a-83d7-a274b223a40d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89633811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_alert_test.89633811
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.1878249899
Short name T813
Test name
Test status
Simulation time 691434486 ps
CPU time 18.63 seconds
Started Mar 17 12:48:04 PM PDT 24
Finished Mar 17 12:48:23 PM PDT 24
Peak memory 203128 kb
Host smart-f6657fde-b831-410a-ba6e-f1063414ff22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878249899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.1878249899
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.1265445033
Short name T284
Test name
Test status
Simulation time 34624288561 ps
CPU time 790.07 seconds
Started Mar 17 12:48:06 PM PDT 24
Finished Mar 17 01:01:17 PM PDT 24
Peak memory 342500 kb
Host smart-77dd757c-05e4-4985-9696-5b5229bdc08b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265445033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.1265445033
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.2981079487
Short name T895
Test name
Test status
Simulation time 362620605 ps
CPU time 1.64 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:48:11 PM PDT 24
Peak memory 203180 kb
Host smart-0a48edce-e5c5-40cc-b6ae-4960fb371a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981079487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.2981079487
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.1369870030
Short name T267
Test name
Test status
Simulation time 84705650 ps
CPU time 10.78 seconds
Started Mar 17 12:48:05 PM PDT 24
Finished Mar 17 12:48:15 PM PDT 24
Peak memory 252288 kb
Host smart-b7d2a018-e0bf-4cc0-bfb7-dc8a0116d9af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369870030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.1369870030
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1437134018
Short name T297
Test name
Test status
Simulation time 350199301 ps
CPU time 2.96 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:48:06 PM PDT 24
Peak memory 211492 kb
Host smart-05c6f624-f979-4c96-b194-ddd26658a3f5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437134018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.1437134018
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.2091234237
Short name T330
Test name
Test status
Simulation time 151620650 ps
CPU time 4.24 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:48:16 PM PDT 24
Peak memory 203184 kb
Host smart-b0817d01-2eb9-4559-9687-bd4ba5762723
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091234237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.2091234237
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.1383037265
Short name T742
Test name
Test status
Simulation time 61075700210 ps
CPU time 1315.95 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 01:10:00 PM PDT 24
Peak memory 374988 kb
Host smart-ef439b28-f570-455a-b9d2-1d51ad391031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383037265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.1383037265
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.2860882019
Short name T142
Test name
Test status
Simulation time 1574669812 ps
CPU time 142.99 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 12:50:31 PM PDT 24
Peak memory 367660 kb
Host smart-b3193416-c217-43c5-9ba7-2ba2b941fe0b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860882019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.2860882019
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.657595454
Short name T791
Test name
Test status
Simulation time 18756453114 ps
CPU time 319.09 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:53:28 PM PDT 24
Peak memory 203244 kb
Host smart-690b9aa4-fdf6-4fe4-a4ac-2296e6a44bcd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657595454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.sram_ctrl_partial_access_b2b.657595454
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.2671969120
Short name T265
Test name
Test status
Simulation time 47474970 ps
CPU time 0.73 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:48:04 PM PDT 24
Peak memory 203208 kb
Host smart-7d03823c-19e7-4b21-9189-5980e9c89259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671969120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2671969120
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.1431658497
Short name T896
Test name
Test status
Simulation time 2635670111 ps
CPU time 563.22 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:57:33 PM PDT 24
Peak memory 373984 kb
Host smart-e78d6df9-979f-4a76-9144-468b8f5b4da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431658497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1431658497
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.4226834519
Short name T322
Test name
Test status
Simulation time 1610601280 ps
CPU time 9.37 seconds
Started Mar 17 12:47:58 PM PDT 24
Finished Mar 17 12:48:08 PM PDT 24
Peak memory 203156 kb
Host smart-6e04dfa2-54e2-4bdb-b7c1-3845b54f36f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226834519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.4226834519
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.1992941258
Short name T772
Test name
Test status
Simulation time 10005322462 ps
CPU time 2809.38 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 01:34:53 PM PDT 24
Peak memory 374064 kb
Host smart-41a0153a-a7a3-40a9-85ac-ea5af139db48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992941258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.1992941258
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.678351843
Short name T106
Test name
Test status
Simulation time 8062126472 ps
CPU time 214.84 seconds
Started Mar 17 12:48:02 PM PDT 24
Finished Mar 17 12:51:37 PM PDT 24
Peak memory 379352 kb
Host smart-da505fe0-968d-43dc-b808-43f1b3e29840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=678351843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.678351843
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3670225807
Short name T96
Test name
Test status
Simulation time 10589018230 ps
CPU time 256.17 seconds
Started Mar 17 12:48:06 PM PDT 24
Finished Mar 17 12:52:23 PM PDT 24
Peak memory 203228 kb
Host smart-3ac9266a-e130-4940-b99c-08062b90285d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670225807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.3670225807
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.57758876
Short name T283
Test name
Test status
Simulation time 119406070 ps
CPU time 38.59 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 12:48:47 PM PDT 24
Peak memory 309868 kb
Host smart-c7b84756-83b7-4253-aa73-439b67f286db
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57758876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.sram_ctrl_throughput_w_partial_write.57758876
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.752127240
Short name T548
Test name
Test status
Simulation time 2260796591 ps
CPU time 543.33 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 12:56:05 PM PDT 24
Peak memory 376116 kb
Host smart-cc0d4225-2935-4e8d-bc24-83e2f9c7897a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752127240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_access_during_key_req.752127240
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.1649298439
Short name T24
Test name
Test status
Simulation time 41391220 ps
CPU time 0.64 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 12:47:02 PM PDT 24
Peak memory 202072 kb
Host smart-8edf8f5e-6ede-413b-b5ac-019b6fb362f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649298439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.1649298439
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.3009290388
Short name T551
Test name
Test status
Simulation time 3660799344 ps
CPU time 51.78 seconds
Started Mar 17 12:46:37 PM PDT 24
Finished Mar 17 12:47:29 PM PDT 24
Peak memory 203196 kb
Host smart-5789dd52-ba4b-4dff-ad2b-515c7bab8f61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009290388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
3009290388
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.1494536418
Short name T480
Test name
Test status
Simulation time 12804803224 ps
CPU time 753.02 seconds
Started Mar 17 12:46:59 PM PDT 24
Finished Mar 17 12:59:32 PM PDT 24
Peak memory 373264 kb
Host smart-a7a5f20e-2374-46b5-97ee-39fa03c50d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494536418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.1494536418
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.1771232404
Short name T707
Test name
Test status
Simulation time 92020663 ps
CPU time 1.07 seconds
Started Mar 17 12:47:05 PM PDT 24
Finished Mar 17 12:47:06 PM PDT 24
Peak memory 203024 kb
Host smart-23e42d1e-c0dd-4204-8259-f0d845d3622f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771232404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.1771232404
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.488840777
Short name T705
Test name
Test status
Simulation time 278393364 ps
CPU time 3.23 seconds
Started Mar 17 12:46:58 PM PDT 24
Finished Mar 17 12:47:01 PM PDT 24
Peak memory 219580 kb
Host smart-f8cafcaf-096b-462b-a12d-43a3494c67bd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488840777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.sram_ctrl_max_throughput.488840777
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2185038782
Short name T83
Test name
Test status
Simulation time 46766157 ps
CPU time 2.52 seconds
Started Mar 17 12:46:35 PM PDT 24
Finished Mar 17 12:46:37 PM PDT 24
Peak memory 211296 kb
Host smart-2a8b1618-e6a7-4249-aae2-4d6d4d9d26c1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185038782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.2185038782
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.2732889190
Short name T839
Test name
Test status
Simulation time 573217420 ps
CPU time 8.12 seconds
Started Mar 17 12:46:55 PM PDT 24
Finished Mar 17 12:47:03 PM PDT 24
Peak memory 203188 kb
Host smart-9ba3f695-08b7-4623-b163-f8fb1ca37e42
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732889190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.2732889190
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.390875958
Short name T389
Test name
Test status
Simulation time 1814413715 ps
CPU time 573.33 seconds
Started Mar 17 12:46:30 PM PDT 24
Finished Mar 17 12:56:03 PM PDT 24
Peak memory 353364 kb
Host smart-5209ac47-fa02-41c2-ba85-c68882ca0852
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390875958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl
e_keys.390875958
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.3828775550
Short name T928
Test name
Test status
Simulation time 827412141 ps
CPU time 10.57 seconds
Started Mar 17 12:46:37 PM PDT 24
Finished Mar 17 12:46:48 PM PDT 24
Peak memory 203116 kb
Host smart-898ab373-489e-4374-bc63-c5bf6e54ffd7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828775550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.3828775550
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.693044291
Short name T505
Test name
Test status
Simulation time 17329895665 ps
CPU time 308.15 seconds
Started Mar 17 12:46:38 PM PDT 24
Finished Mar 17 12:51:46 PM PDT 24
Peak memory 203328 kb
Host smart-978ae3a7-b669-4cee-a6ba-10bf66a327e3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693044291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.sram_ctrl_partial_access_b2b.693044291
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.3737063529
Short name T414
Test name
Test status
Simulation time 31384674 ps
CPU time 0.74 seconds
Started Mar 17 12:46:35 PM PDT 24
Finished Mar 17 12:46:36 PM PDT 24
Peak memory 203136 kb
Host smart-29f1d547-e4eb-492c-b9e3-be8b34e95a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737063529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3737063529
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1978298392
Short name T769
Test name
Test status
Simulation time 33993423737 ps
CPU time 1041.76 seconds
Started Mar 17 12:46:37 PM PDT 24
Finished Mar 17 01:03:59 PM PDT 24
Peak memory 374152 kb
Host smart-0ec85d1d-edf8-4a3f-9880-7d91886a673f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978298392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1978298392
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.4102784255
Short name T25
Test name
Test status
Simulation time 704833143 ps
CPU time 3.25 seconds
Started Mar 17 12:46:59 PM PDT 24
Finished Mar 17 12:47:03 PM PDT 24
Peak memory 222072 kb
Host smart-e7f3956f-3620-48bf-b1df-8a449dde5b56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102784255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.4102784255
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.3061073814
Short name T600
Test name
Test status
Simulation time 442100681 ps
CPU time 71.56 seconds
Started Mar 17 12:46:30 PM PDT 24
Finished Mar 17 12:47:41 PM PDT 24
Peak memory 352420 kb
Host smart-153f0e35-ba5b-4633-8699-09e87b736221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061073814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3061073814
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.783001330
Short name T556
Test name
Test status
Simulation time 5573758833 ps
CPU time 424.62 seconds
Started Mar 17 12:46:38 PM PDT 24
Finished Mar 17 12:53:43 PM PDT 24
Peak memory 386072 kb
Host smart-2d650cf1-21bd-4657-8d96-76e409d6937b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=783001330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.783001330
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1745628139
Short name T914
Test name
Test status
Simulation time 3388708850 ps
CPU time 319.93 seconds
Started Mar 17 12:46:56 PM PDT 24
Finished Mar 17 12:52:21 PM PDT 24
Peak memory 203272 kb
Host smart-148b1023-b4c7-419f-ad90-9f21eb732911
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745628139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.1745628139
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2915017861
Short name T301
Test name
Test status
Simulation time 153979530 ps
CPU time 119.72 seconds
Started Mar 17 12:46:57 PM PDT 24
Finished Mar 17 12:48:57 PM PDT 24
Peak memory 369728 kb
Host smart-9f5670d9-f9fe-4219-b31e-2e906cb54d4d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915017861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2915017861
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.544912639
Short name T444
Test name
Test status
Simulation time 13618039422 ps
CPU time 872.89 seconds
Started Mar 17 12:48:04 PM PDT 24
Finished Mar 17 01:02:37 PM PDT 24
Peak memory 373768 kb
Host smart-abfd9632-7450-4ff4-95e1-9f150a36eb70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544912639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 30.sram_ctrl_access_during_key_req.544912639
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.183665377
Short name T244
Test name
Test status
Simulation time 20181941 ps
CPU time 0.65 seconds
Started Mar 17 12:48:06 PM PDT 24
Finished Mar 17 12:48:07 PM PDT 24
Peak memory 202080 kb
Host smart-df4beeeb-25ce-45e9-9681-286f066f9845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183665377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.183665377
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.4166200203
Short name T899
Test name
Test status
Simulation time 2516301435 ps
CPU time 36.68 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:48:39 PM PDT 24
Peak memory 203232 kb
Host smart-3d7504a3-4a1f-4e12-93d8-67a25a12bc29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166200203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.4166200203
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.212338171
Short name T695
Test name
Test status
Simulation time 11482625000 ps
CPU time 636.75 seconds
Started Mar 17 12:48:01 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 373664 kb
Host smart-68736bc0-4d95-4283-bf49-5f7d9e82738a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212338171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl
e.212338171
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.1415205413
Short name T327
Test name
Test status
Simulation time 853516969 ps
CPU time 2.94 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:48:14 PM PDT 24
Peak memory 203204 kb
Host smart-0cede16b-f393-4b95-a7a6-efd7e1d2b28c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415205413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.1415205413
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.99885642
Short name T582
Test name
Test status
Simulation time 233262399 ps
CPU time 31.86 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:48:41 PM PDT 24
Peak memory 291108 kb
Host smart-4d2125e3-c6b3-4592-bdd0-4e7b6146fd2a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99885642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.sram_ctrl_max_throughput.99885642
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.1948076575
Short name T591
Test name
Test status
Simulation time 66053111 ps
CPU time 4.18 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:48:08 PM PDT 24
Peak memory 211388 kb
Host smart-02418dfd-b1ac-41e8-9135-5fe8474d3a5a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948076575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.1948076575
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.164091548
Short name T2
Test name
Test status
Simulation time 78238996 ps
CPU time 4.39 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:48:14 PM PDT 24
Peak memory 203224 kb
Host smart-9421707a-8fd6-4524-852d-0e15539668d6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164091548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl
_mem_walk.164091548
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.2855022414
Short name T434
Test name
Test status
Simulation time 217987831 ps
CPU time 151.12 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:50:35 PM PDT 24
Peak memory 366660 kb
Host smart-4a9ded9e-b55b-4b5d-b95b-57923f0aceee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855022414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.2855022414
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.2296800963
Short name T469
Test name
Test status
Simulation time 3032878375 ps
CPU time 16.24 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 12:48:24 PM PDT 24
Peak memory 203244 kb
Host smart-f9f70792-1b47-4619-9bb4-178ab60e3843
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296800963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.2296800963
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3103851406
Short name T681
Test name
Test status
Simulation time 68567672575 ps
CPU time 448.7 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:55:39 PM PDT 24
Peak memory 203300 kb
Host smart-d4ee92c5-e32d-418f-a7c7-63feade512bb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103851406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.3103851406
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.1051186145
Short name T709
Test name
Test status
Simulation time 317621168 ps
CPU time 0.76 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:48:11 PM PDT 24
Peak memory 203188 kb
Host smart-a2396948-55d4-44cf-82f5-264036adf498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051186145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1051186145
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.2289216561
Short name T238
Test name
Test status
Simulation time 641231401 ps
CPU time 176.63 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 12:51:05 PM PDT 24
Peak memory 311596 kb
Host smart-7bbe87a4-09cc-496e-86ed-b98e7d1b5f46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289216561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2289216561
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.1016870935
Short name T614
Test name
Test status
Simulation time 4426372507 ps
CPU time 93.8 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:49:37 PM PDT 24
Peak memory 353404 kb
Host smart-7af38e67-63a9-4a5d-978c-6d5a38a37325
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016870935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1016870935
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.3448195554
Short name T501
Test name
Test status
Simulation time 84173180651 ps
CPU time 2385.1 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 01:27:54 PM PDT 24
Peak memory 375136 kb
Host smart-ab82c079-0d82-4050-81b1-32e24ad4446b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448195554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.sram_ctrl_stress_all.3448195554
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.72749732
Short name T865
Test name
Test status
Simulation time 1939194030 ps
CPU time 227.6 seconds
Started Mar 17 12:48:04 PM PDT 24
Finished Mar 17 12:51:52 PM PDT 24
Peak memory 377672 kb
Host smart-4bb03339-5bef-4f08-a0cc-be9cff449900
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=72749732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.72749732
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1263645194
Short name T259
Test name
Test status
Simulation time 1747257110 ps
CPU time 163.23 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:50:46 PM PDT 24
Peak memory 203168 kb
Host smart-c2b8e664-2268-4403-ab54-1eb613cf6867
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263645194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.1263645194
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3182588123
Short name T372
Test name
Test status
Simulation time 167086928 ps
CPU time 106.74 seconds
Started Mar 17 12:48:06 PM PDT 24
Finished Mar 17 12:49:52 PM PDT 24
Peak memory 369368 kb
Host smart-78f229ae-aae9-4542-ac12-e8bf533fe320
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182588123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3182588123
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3099141355
Short name T384
Test name
Test status
Simulation time 8559486013 ps
CPU time 593.2 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:57:56 PM PDT 24
Peak memory 370824 kb
Host smart-9451b6d5-bbee-4197-9020-d820ea294875
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099141355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.3099141355
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.2307448445
Short name T626
Test name
Test status
Simulation time 11362247 ps
CPU time 0.63 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:48:10 PM PDT 24
Peak memory 202032 kb
Host smart-6d267e2b-0308-41be-a958-36ddbaf70814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307448445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.2307448445
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.2288335551
Short name T431
Test name
Test status
Simulation time 10391966628 ps
CPU time 44.94 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 12:48:54 PM PDT 24
Peak memory 203220 kb
Host smart-830faafd-b005-4e13-a729-8c8565c42758
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288335551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.2288335551
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.1589838053
Short name T673
Test name
Test status
Simulation time 41255582955 ps
CPU time 715.2 seconds
Started Mar 17 12:48:06 PM PDT 24
Finished Mar 17 01:00:02 PM PDT 24
Peak memory 371480 kb
Host smart-1b076537-97e9-40cf-86da-c59464eb4652
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589838053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.1589838053
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2918719857
Short name T597
Test name
Test status
Simulation time 589576276 ps
CPU time 3.62 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:48:13 PM PDT 24
Peak memory 202884 kb
Host smart-ab8f1a39-0055-4d4a-8a7d-2e8244eb3f9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918719857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2918719857
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.194632760
Short name T546
Test name
Test status
Simulation time 509436258 ps
CPU time 99.97 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:49:49 PM PDT 24
Peak memory 362652 kb
Host smart-d77d3a66-4e1a-4e8d-92e2-8e2d4fc33c85
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194632760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.sram_ctrl_max_throughput.194632760
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2151827789
Short name T447
Test name
Test status
Simulation time 67767316 ps
CPU time 4.32 seconds
Started Mar 17 12:48:01 PM PDT 24
Finished Mar 17 12:48:05 PM PDT 24
Peak memory 211376 kb
Host smart-c84f3359-7e49-413e-adaa-bb948bf2d3bf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151827789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.2151827789
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.668685188
Short name T170
Test name
Test status
Simulation time 234954327 ps
CPU time 5 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:48:17 PM PDT 24
Peak memory 203176 kb
Host smart-8523d1a9-5690-44db-b964-134e52a5de93
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668685188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl
_mem_walk.668685188
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.2157350927
Short name T411
Test name
Test status
Simulation time 75096490808 ps
CPU time 1205.26 seconds
Started Mar 17 12:48:04 PM PDT 24
Finished Mar 17 01:08:10 PM PDT 24
Peak memory 373692 kb
Host smart-dc2d142f-e9cd-4048-a87d-23f0b22066ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157350927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.2157350927
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.1438163715
Short name T6
Test name
Test status
Simulation time 303144706 ps
CPU time 14.5 seconds
Started Mar 17 12:48:06 PM PDT 24
Finished Mar 17 12:48:20 PM PDT 24
Peak memory 263012 kb
Host smart-1121750f-6f3d-4067-a2ea-fb9334e71d0b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438163715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.1438163715
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2579949769
Short name T635
Test name
Test status
Simulation time 14514464806 ps
CPU time 281.13 seconds
Started Mar 17 12:48:04 PM PDT 24
Finished Mar 17 12:52:45 PM PDT 24
Peak memory 203292 kb
Host smart-0d24b79c-2916-4793-92c9-6498020001c1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579949769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.2579949769
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.1726872689
Short name T603
Test name
Test status
Simulation time 50622730 ps
CPU time 0.77 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 12:48:09 PM PDT 24
Peak memory 203212 kb
Host smart-ced149ff-64f3-4e5f-838f-6e1478705fcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726872689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1726872689
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.3912396504
Short name T684
Test name
Test status
Simulation time 44544780531 ps
CPU time 926.16 seconds
Started Mar 17 12:48:06 PM PDT 24
Finished Mar 17 01:03:32 PM PDT 24
Peak memory 373968 kb
Host smart-fc1420c6-88c0-483e-9518-33c585afd66d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912396504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3912396504
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.2160510476
Short name T19
Test name
Test status
Simulation time 135385760 ps
CPU time 115.43 seconds
Started Mar 17 12:48:03 PM PDT 24
Finished Mar 17 12:49:59 PM PDT 24
Peak memory 355896 kb
Host smart-d8433418-54fc-42d0-9786-774903d8522b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160510476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2160510476
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.1173955843
Short name T936
Test name
Test status
Simulation time 53540558616 ps
CPU time 6683.08 seconds
Started Mar 17 12:48:05 PM PDT 24
Finished Mar 17 02:39:29 PM PDT 24
Peak memory 376208 kb
Host smart-10f0cbf1-9172-4995-99e9-c4b6b821f69c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173955843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.1173955843
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3449165334
Short name T28
Test name
Test status
Simulation time 1083018131 ps
CPU time 9.64 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:48:19 PM PDT 24
Peak memory 211440 kb
Host smart-334555df-3fc8-4a83-9689-9d18eec306ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3449165334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3449165334
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.339569014
Short name T380
Test name
Test status
Simulation time 12617363630 ps
CPU time 290.9 seconds
Started Mar 17 12:48:12 PM PDT 24
Finished Mar 17 12:53:03 PM PDT 24
Peak memory 203220 kb
Host smart-d940909f-9f49-47d2-9c61-ecc3d872f500
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339569014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.sram_ctrl_stress_pipeline.339569014
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3024427467
Short name T545
Test name
Test status
Simulation time 73092944 ps
CPU time 10.63 seconds
Started Mar 17 12:48:06 PM PDT 24
Finished Mar 17 12:48:16 PM PDT 24
Peak memory 252192 kb
Host smart-a10cc47e-55e5-417d-b73a-0b35925a0a03
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024427467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.3024427467
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2636480670
Short name T565
Test name
Test status
Simulation time 12449341255 ps
CPU time 631.41 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:58:41 PM PDT 24
Peak memory 372068 kb
Host smart-b8a571e4-31a0-4929-8da4-993dc90df424
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636480670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.2636480670
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.2170066589
Short name T10
Test name
Test status
Simulation time 33726395 ps
CPU time 0.61 seconds
Started Mar 17 12:48:12 PM PDT 24
Finished Mar 17 12:48:13 PM PDT 24
Peak memory 202120 kb
Host smart-a3f06015-b5da-4c02-91f7-3cdacd6a2e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170066589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.2170066589
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.1350773417
Short name T723
Test name
Test status
Simulation time 1470344539 ps
CPU time 45.68 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:48:56 PM PDT 24
Peak memory 203120 kb
Host smart-48715cbc-b97e-4409-bf12-335baa917f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350773417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.1350773417
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.1821026673
Short name T138
Test name
Test status
Simulation time 30587082980 ps
CPU time 457.82 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:55:47 PM PDT 24
Peak memory 367568 kb
Host smart-921ee62f-b9e5-4e8f-96f8-3ee04b7973b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821026673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.1821026673
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.2737645498
Short name T416
Test name
Test status
Simulation time 2700556706 ps
CPU time 8.28 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 12:48:16 PM PDT 24
Peak memory 203240 kb
Host smart-2a93b777-d0fd-43c7-a411-98d1937bb31a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737645498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.2737645498
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.2402596293
Short name T481
Test name
Test status
Simulation time 1214974805 ps
CPU time 69.07 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:49:20 PM PDT 24
Peak memory 338124 kb
Host smart-884bf489-47a7-442b-b311-d0a498f32558
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402596293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.2402596293
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.4127301376
Short name T930
Test name
Test status
Simulation time 87866223 ps
CPU time 2.66 seconds
Started Mar 17 12:48:12 PM PDT 24
Finished Mar 17 12:48:15 PM PDT 24
Peak memory 211360 kb
Host smart-9893e9e9-83e7-4cc0-a1e4-b4ed9e7f123d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127301376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.4127301376
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.2046139449
Short name T196
Test name
Test status
Simulation time 152265914 ps
CPU time 4.5 seconds
Started Mar 17 12:48:15 PM PDT 24
Finished Mar 17 12:48:21 PM PDT 24
Peak memory 203216 kb
Host smart-656b25f0-f19e-4711-8f9b-221d18bad1c3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046139449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.2046139449
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.2507216710
Short name T612
Test name
Test status
Simulation time 4290685419 ps
CPU time 214.41 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:51:46 PM PDT 24
Peak memory 347400 kb
Host smart-4ee69f7c-1960-4b77-b1e5-f5fe732303df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507216710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.2507216710
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.2022830654
Short name T643
Test name
Test status
Simulation time 347716868 ps
CPU time 24.25 seconds
Started Mar 17 12:48:08 PM PDT 24
Finished Mar 17 12:48:33 PM PDT 24
Peak memory 268616 kb
Host smart-fa5ee281-b457-4587-ae53-1e6f267db4ef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022830654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.2022830654
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2096692714
Short name T559
Test name
Test status
Simulation time 79784931632 ps
CPU time 512.65 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:56:44 PM PDT 24
Peak memory 203208 kb
Host smart-42ec6b83-3db9-42ef-a8ab-950a0c9cca83
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096692714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.2096692714
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.3754558286
Short name T281
Test name
Test status
Simulation time 75770446 ps
CPU time 0.73 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:48:12 PM PDT 24
Peak memory 203176 kb
Host smart-8ec2856b-554f-4d88-a82b-9056073f4c3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754558286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3754558286
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.476561411
Short name T52
Test name
Test status
Simulation time 1995503157 ps
CPU time 166.14 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:50:56 PM PDT 24
Peak memory 334776 kb
Host smart-143ad144-3e6f-40bb-8200-4e6c8bb2afd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476561411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.476561411
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.1172861042
Short name T340
Test name
Test status
Simulation time 170514670 ps
CPU time 121.34 seconds
Started Mar 17 12:48:14 PM PDT 24
Finished Mar 17 12:50:16 PM PDT 24
Peak memory 358952 kb
Host smart-2d901b90-bbed-4990-97b0-df868b4b8f22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172861042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1172861042
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.276944265
Short name T615
Test name
Test status
Simulation time 45877791135 ps
CPU time 1220.4 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 01:08:30 PM PDT 24
Peak memory 375000 kb
Host smart-4b795058-f2f6-4789-ab70-564184b9b2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276944265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_stress_all.276944265
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3950494866
Short name T529
Test name
Test status
Simulation time 1203300438 ps
CPU time 335.97 seconds
Started Mar 17 12:48:13 PM PDT 24
Finished Mar 17 12:53:49 PM PDT 24
Peak memory 379236 kb
Host smart-566634df-7a5c-4f36-9bef-51bcb8fdbee1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3950494866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3950494866
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2757337387
Short name T547
Test name
Test status
Simulation time 909635262 ps
CPU time 77.63 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:49:28 PM PDT 24
Peak memory 203188 kb
Host smart-b7ffb405-41dd-4355-b4a4-40802743acd9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757337387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.2757337387
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2393935626
Short name T466
Test name
Test status
Simulation time 123046570 ps
CPU time 38.65 seconds
Started Mar 17 12:48:13 PM PDT 24
Finished Mar 17 12:48:53 PM PDT 24
Peak memory 301204 kb
Host smart-166b6a2f-ea4e-4e26-aaf7-eb4dcbae5798
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393935626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2393935626
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.545206427
Short name T439
Test name
Test status
Simulation time 26010264662 ps
CPU time 1097.27 seconds
Started Mar 17 12:48:13 PM PDT 24
Finished Mar 17 01:06:32 PM PDT 24
Peak memory 373744 kb
Host smart-36223905-a169-4d62-9f5b-b0b99953cd29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545206427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 33.sram_ctrl_access_during_key_req.545206427
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.1875828147
Short name T432
Test name
Test status
Simulation time 143909292 ps
CPU time 0.65 seconds
Started Mar 17 12:48:15 PM PDT 24
Finished Mar 17 12:48:18 PM PDT 24
Peak memory 202072 kb
Host smart-a6937e71-04d5-4eb9-a3f3-e7188f42b01c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875828147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.1875828147
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.2905508663
Short name T715
Test name
Test status
Simulation time 1824072107 ps
CPU time 24.51 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:48:34 PM PDT 24
Peak memory 203132 kb
Host smart-de9274fb-46d3-48eb-875d-29d4c4224cf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905508663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.2905508663
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.243787151
Short name T371
Test name
Test status
Simulation time 15446631263 ps
CPU time 175.92 seconds
Started Mar 17 12:48:13 PM PDT 24
Finished Mar 17 12:51:09 PM PDT 24
Peak memory 345812 kb
Host smart-aeadf553-f481-430e-be90-d8878e0c1a39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243787151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executabl
e.243787151
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.3972357210
Short name T819
Test name
Test status
Simulation time 2236115469 ps
CPU time 8.56 seconds
Started Mar 17 12:48:12 PM PDT 24
Finished Mar 17 12:48:20 PM PDT 24
Peak memory 203204 kb
Host smart-732a84df-40fd-4c6c-950d-32d9d79f3ccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972357210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.3972357210
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.2274435615
Short name T740
Test name
Test status
Simulation time 89182575 ps
CPU time 37.99 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:48:47 PM PDT 24
Peak memory 291096 kb
Host smart-481e3a96-ac18-4b07-b756-e12ec394be4c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274435615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.2274435615
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1219494635
Short name T80
Test name
Test status
Simulation time 217897676 ps
CPU time 2.66 seconds
Started Mar 17 12:48:12 PM PDT 24
Finished Mar 17 12:48:15 PM PDT 24
Peak memory 211360 kb
Host smart-27cfe2ca-7d9e-4a69-885b-bd9616a1dc8d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219494635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.1219494635
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.2838812701
Short name T440
Test name
Test status
Simulation time 201731304 ps
CPU time 4.43 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:48:14 PM PDT 24
Peak memory 203188 kb
Host smart-b3be4624-de75-406e-b62e-0bab97e36290
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838812701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.2838812701
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.111927705
Short name T455
Test name
Test status
Simulation time 55813907399 ps
CPU time 1040.32 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 01:05:30 PM PDT 24
Peak memory 375996 kb
Host smart-08dbf298-72b5-45ff-8cd8-4b69473ddb3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111927705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip
le_keys.111927705
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.3287504231
Short name T753
Test name
Test status
Simulation time 911676107 ps
CPU time 17.34 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:48:29 PM PDT 24
Peak memory 203276 kb
Host smart-e7690c2c-9f3a-40e5-88c4-4ffc5c40d6ca
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287504231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.3287504231
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1036599033
Short name T369
Test name
Test status
Simulation time 19508843509 ps
CPU time 466.49 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:55:58 PM PDT 24
Peak memory 203236 kb
Host smart-e0cdbd9d-21fc-43a3-bacb-b27a6417075b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036599033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.1036599033
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.642466705
Short name T775
Test name
Test status
Simulation time 30859734 ps
CPU time 0.75 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:48:11 PM PDT 24
Peak memory 203188 kb
Host smart-21e0918a-74bd-4c82-b225-86dc0a849da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642466705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.642466705
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.1614188826
Short name T243
Test name
Test status
Simulation time 8578870507 ps
CPU time 1147.53 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 01:07:17 PM PDT 24
Peak memory 375808 kb
Host smart-dfb630c8-3a89-4e0f-9a65-ee5c89c4d80d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614188826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1614188826
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.1412370785
Short name T233
Test name
Test status
Simulation time 2796868897 ps
CPU time 11.45 seconds
Started Mar 17 12:48:14 PM PDT 24
Finished Mar 17 12:48:27 PM PDT 24
Peak memory 203228 kb
Host smart-7d98aca6-d402-4e53-a05b-5d52356a8a87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412370785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1412370785
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.2199459407
Short name T777
Test name
Test status
Simulation time 49984361701 ps
CPU time 3980.91 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 01:54:33 PM PDT 24
Peak memory 375944 kb
Host smart-0316371f-f632-45ed-8876-f15c8fb17f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199459407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.2199459407
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.536874459
Short name T422
Test name
Test status
Simulation time 1910622542 ps
CPU time 105.65 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:49:56 PM PDT 24
Peak memory 332900 kb
Host smart-d0ff0da0-7f78-46ae-b94e-cd6f867b0ffc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=536874459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.536874459
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3291135575
Short name T508
Test name
Test status
Simulation time 9060434696 ps
CPU time 305.22 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:53:17 PM PDT 24
Peak memory 203268 kb
Host smart-0bc6b8ab-52cd-4fbf-ae88-dba203e4b801
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291135575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.3291135575
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1060008389
Short name T239
Test name
Test status
Simulation time 56926634 ps
CPU time 1.85 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:48:12 PM PDT 24
Peak memory 211356 kb
Host smart-8584da6b-2fc7-4539-9260-8574a442698e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060008389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1060008389
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2563490246
Short name T329
Test name
Test status
Simulation time 1483104703 ps
CPU time 472.78 seconds
Started Mar 17 12:48:17 PM PDT 24
Finished Mar 17 12:56:11 PM PDT 24
Peak memory 372868 kb
Host smart-3638bbf7-b432-4a76-afb2-87ef83b734e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563490246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2563490246
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.3442192744
Short name T558
Test name
Test status
Simulation time 21915767 ps
CPU time 0.64 seconds
Started Mar 17 12:48:16 PM PDT 24
Finished Mar 17 12:48:18 PM PDT 24
Peak memory 202096 kb
Host smart-86120bb2-031d-453d-aaa4-af30e93d368c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442192744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.3442192744
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.1026300664
Short name T274
Test name
Test status
Simulation time 1137419447 ps
CPU time 68.59 seconds
Started Mar 17 12:48:14 PM PDT 24
Finished Mar 17 12:49:23 PM PDT 24
Peak memory 203120 kb
Host smart-ad28f3dd-aaae-4242-8f2e-3cb9e57eabff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026300664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.1026300664
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.2927395689
Short name T840
Test name
Test status
Simulation time 32444605538 ps
CPU time 1157.6 seconds
Started Mar 17 12:48:21 PM PDT 24
Finished Mar 17 01:07:38 PM PDT 24
Peak memory 372108 kb
Host smart-9a46eeab-e073-43b2-8497-2e654eee95d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927395689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.2927395689
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.2423938436
Short name T292
Test name
Test status
Simulation time 978271257 ps
CPU time 2.24 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:48:12 PM PDT 24
Peak memory 203200 kb
Host smart-b3a6f70f-3fc4-4a70-ba23-9b88a8eebe34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423938436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.2423938436
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.1182585451
Short name T833
Test name
Test status
Simulation time 546668329 ps
CPU time 73.48 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:49:24 PM PDT 24
Peak memory 369440 kb
Host smart-e6cb71f0-ed20-4d66-a4ba-845fea658d17
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182585451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.1182585451
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2491675970
Short name T590
Test name
Test status
Simulation time 382439125 ps
CPU time 3.12 seconds
Started Mar 17 12:48:16 PM PDT 24
Finished Mar 17 12:48:22 PM PDT 24
Peak memory 211380 kb
Host smart-1b49b9a1-1487-43f6-bb33-d661d0f9a84d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491675970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.2491675970
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.183383254
Short name T633
Test name
Test status
Simulation time 1040786137 ps
CPU time 5.74 seconds
Started Mar 17 12:48:17 PM PDT 24
Finished Mar 17 12:48:24 PM PDT 24
Peak memory 203100 kb
Host smart-4d6f902f-6a55-4742-bce6-e301b9902fe0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183383254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl
_mem_walk.183383254
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.2708865668
Short name T728
Test name
Test status
Simulation time 25055267266 ps
CPU time 1825.65 seconds
Started Mar 17 12:48:14 PM PDT 24
Finished Mar 17 01:18:41 PM PDT 24
Peak memory 375520 kb
Host smart-a8991b4a-32f3-4e68-bfdb-e4d2f1cf36f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708865668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.2708865668
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.3052407999
Short name T925
Test name
Test status
Simulation time 364598417 ps
CPU time 29.55 seconds
Started Mar 17 12:48:10 PM PDT 24
Finished Mar 17 12:48:40 PM PDT 24
Peak memory 283912 kb
Host smart-e73d2381-4e98-4223-a302-5a3c0bad8e85
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052407999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.3052407999
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.4217070188
Short name T262
Test name
Test status
Simulation time 18388861130 ps
CPU time 469.53 seconds
Started Mar 17 12:48:13 PM PDT 24
Finished Mar 17 12:56:04 PM PDT 24
Peak memory 203232 kb
Host smart-36a3cada-5260-4f05-b20d-14785f7d779d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217070188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.4217070188
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.1575663864
Short name T457
Test name
Test status
Simulation time 46877436 ps
CPU time 0.74 seconds
Started Mar 17 12:48:17 PM PDT 24
Finished Mar 17 12:48:18 PM PDT 24
Peak memory 203216 kb
Host smart-8c934b5d-fe8e-4adc-9889-f344168f0bdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575663864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1575663864
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.4219334836
Short name T378
Test name
Test status
Simulation time 29604284363 ps
CPU time 562.92 seconds
Started Mar 17 12:48:18 PM PDT 24
Finished Mar 17 12:57:42 PM PDT 24
Peak memory 375420 kb
Host smart-96185207-c652-4366-a156-746004dc058a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219334836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.4219334836
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.919809533
Short name T755
Test name
Test status
Simulation time 1556624173 ps
CPU time 24.81 seconds
Started Mar 17 12:48:14 PM PDT 24
Finished Mar 17 12:48:40 PM PDT 24
Peak memory 273984 kb
Host smart-f43770dd-f4d1-4dfc-9d6b-dc163ba1bb0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919809533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.919809533
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.3206115711
Short name T544
Test name
Test status
Simulation time 132035854081 ps
CPU time 2612.89 seconds
Started Mar 17 12:48:19 PM PDT 24
Finished Mar 17 01:31:53 PM PDT 24
Peak memory 382984 kb
Host smart-e2bb66a6-8918-445b-ac6b-180620aeda16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206115711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.3206115711
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.566969864
Short name T46
Test name
Test status
Simulation time 4717273142 ps
CPU time 142.89 seconds
Started Mar 17 12:48:16 PM PDT 24
Finished Mar 17 12:50:41 PM PDT 24
Peak memory 369764 kb
Host smart-cc532eda-dd70-4c3f-91e4-93fe6b479c85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=566969864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.566969864
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1681060651
Short name T16
Test name
Test status
Simulation time 3147570763 ps
CPU time 287.52 seconds
Started Mar 17 12:48:11 PM PDT 24
Finished Mar 17 12:52:58 PM PDT 24
Peak memory 203212 kb
Host smart-203a81c1-0b42-4ed5-8117-08985a14381b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681060651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.1681060651
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3632272298
Short name T408
Test name
Test status
Simulation time 50050383 ps
CPU time 4.05 seconds
Started Mar 17 12:48:09 PM PDT 24
Finished Mar 17 12:48:13 PM PDT 24
Peak memory 222320 kb
Host smart-65511948-5219-4353-9363-a93c241a5b78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632272298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3632272298
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3473569120
Short name T764
Test name
Test status
Simulation time 4647755868 ps
CPU time 1145.1 seconds
Started Mar 17 12:48:16 PM PDT 24
Finished Mar 17 01:07:23 PM PDT 24
Peak memory 373004 kb
Host smart-1d5266bc-3eed-49b8-88f6-30405a045153
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473569120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.3473569120
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.3451284155
Short name T906
Test name
Test status
Simulation time 38121986 ps
CPU time 0.63 seconds
Started Mar 17 12:48:22 PM PDT 24
Finished Mar 17 12:48:23 PM PDT 24
Peak memory 202088 kb
Host smart-c8513482-2b89-4e93-9f31-38b1a1b1b0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451284155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.3451284155
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.709480666
Short name T148
Test name
Test status
Simulation time 1577057064 ps
CPU time 44.72 seconds
Started Mar 17 12:48:16 PM PDT 24
Finished Mar 17 12:49:02 PM PDT 24
Peak memory 203048 kb
Host smart-48f902fa-0132-450e-9b75-36c40f7fc6b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709480666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.
709480666
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.1943737596
Short name T140
Test name
Test status
Simulation time 9617786616 ps
CPU time 615.05 seconds
Started Mar 17 12:48:17 PM PDT 24
Finished Mar 17 12:58:34 PM PDT 24
Peak memory 365388 kb
Host smart-b71bfb33-dce9-4a0c-b267-df0ea63da56f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943737596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.1943737596
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.2844807474
Short name T566
Test name
Test status
Simulation time 1170532123 ps
CPU time 4.21 seconds
Started Mar 17 12:48:16 PM PDT 24
Finished Mar 17 12:48:21 PM PDT 24
Peak memory 203248 kb
Host smart-ae403139-57b2-4c23-b520-80c23a7ebb39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844807474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.2844807474
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.1816384204
Short name T216
Test name
Test status
Simulation time 134509425 ps
CPU time 89.97 seconds
Started Mar 17 12:48:18 PM PDT 24
Finished Mar 17 12:49:48 PM PDT 24
Peak memory 366652 kb
Host smart-ecb3c4d4-b58f-405a-9554-8f8c72daffca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816384204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.1816384204
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.945619070
Short name T884
Test name
Test status
Simulation time 61492623 ps
CPU time 4.29 seconds
Started Mar 17 12:48:19 PM PDT 24
Finished Mar 17 12:48:25 PM PDT 24
Peak memory 211440 kb
Host smart-46f1ec5e-ab7b-46b1-aa8f-b14c6f3a2e54
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945619070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_mem_partial_access.945619070
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.608562521
Short name T668
Test name
Test status
Simulation time 251535839 ps
CPU time 4.44 seconds
Started Mar 17 12:48:18 PM PDT 24
Finished Mar 17 12:48:23 PM PDT 24
Peak memory 203228 kb
Host smart-7faceaa8-81c4-48d5-80be-c383c8ba8fb6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608562521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl
_mem_walk.608562521
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.687608202
Short name T583
Test name
Test status
Simulation time 19998121461 ps
CPU time 1039.62 seconds
Started Mar 17 12:48:18 PM PDT 24
Finished Mar 17 01:05:39 PM PDT 24
Peak memory 372700 kb
Host smart-94ca223e-53a1-47c7-b9ab-3c4fbb53addd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687608202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip
le_keys.687608202
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.2702042992
Short name T493
Test name
Test status
Simulation time 1886174704 ps
CPU time 57.18 seconds
Started Mar 17 12:48:16 PM PDT 24
Finished Mar 17 12:49:15 PM PDT 24
Peak memory 311104 kb
Host smart-d483d5dd-0253-4d67-bed5-f78372dd2b5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702042992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.2702042992
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.483597789
Short name T465
Test name
Test status
Simulation time 20217398412 ps
CPU time 437.11 seconds
Started Mar 17 12:48:19 PM PDT 24
Finished Mar 17 12:55:37 PM PDT 24
Peak memory 203260 kb
Host smart-72559338-6c1d-4b2b-9707-8fde4afa73be
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483597789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.sram_ctrl_partial_access_b2b.483597789
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2602477517
Short name T646
Test name
Test status
Simulation time 99465898 ps
CPU time 0.73 seconds
Started Mar 17 12:48:18 PM PDT 24
Finished Mar 17 12:48:20 PM PDT 24
Peak memory 203228 kb
Host smart-052a00a9-9980-4c82-86af-f9dc681c4b88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602477517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2602477517
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.847632995
Short name T155
Test name
Test status
Simulation time 3485061444 ps
CPU time 1248.75 seconds
Started Mar 17 12:48:18 PM PDT 24
Finished Mar 17 01:09:08 PM PDT 24
Peak memory 374100 kb
Host smart-a6bc13ed-41af-4dd5-9b92-cd879388866b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847632995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.847632995
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.1172743311
Short name T490
Test name
Test status
Simulation time 89523234 ps
CPU time 2.1 seconds
Started Mar 17 12:48:16 PM PDT 24
Finished Mar 17 12:48:20 PM PDT 24
Peak memory 204348 kb
Host smart-02da35c4-0176-4650-8e6e-a675cd786c20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172743311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1172743311
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.4254482252
Short name T245
Test name
Test status
Simulation time 264044346362 ps
CPU time 3099.93 seconds
Started Mar 17 12:48:17 PM PDT 24
Finished Mar 17 01:39:59 PM PDT 24
Peak memory 376576 kb
Host smart-cd0a544e-fd46-458e-91d0-241718b9fb20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254482252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.4254482252
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4252155493
Short name T45
Test name
Test status
Simulation time 1228335061 ps
CPU time 228.59 seconds
Started Mar 17 12:48:22 PM PDT 24
Finished Mar 17 12:52:11 PM PDT 24
Peak memory 346352 kb
Host smart-a37083ed-9ba6-43a9-97ec-fc7ea35b7539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4252155493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.4252155493
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1030275671
Short name T581
Test name
Test status
Simulation time 6957298875 ps
CPU time 167.66 seconds
Started Mar 17 12:48:16 PM PDT 24
Finished Mar 17 12:51:05 PM PDT 24
Peak memory 203236 kb
Host smart-7ceeef69-d0e4-4d25-8fd3-c70adcbc1b4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030275671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.1030275671
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3593965217
Short name T515
Test name
Test status
Simulation time 107792710 ps
CPU time 34.67 seconds
Started Mar 17 12:48:17 PM PDT 24
Finished Mar 17 12:48:53 PM PDT 24
Peak memory 302376 kb
Host smart-1fed5002-aa58-4659-a253-14a1e6174523
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593965217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3593965217
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1386484447
Short name T811
Test name
Test status
Simulation time 12073711667 ps
CPU time 357.64 seconds
Started Mar 17 12:48:24 PM PDT 24
Finished Mar 17 12:54:22 PM PDT 24
Peak memory 374888 kb
Host smart-91e1eca9-d438-471f-a341-bba398fbf6d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386484447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.1386484447
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.1701547908
Short name T805
Test name
Test status
Simulation time 12875698 ps
CPU time 0.62 seconds
Started Mar 17 12:48:25 PM PDT 24
Finished Mar 17 12:48:26 PM PDT 24
Peak memory 202356 kb
Host smart-7d9daca9-01b1-4a3e-966a-d7c884202047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701547908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.1701547908
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.2896001149
Short name T862
Test name
Test status
Simulation time 11245299609 ps
CPU time 83.88 seconds
Started Mar 17 12:48:26 PM PDT 24
Finished Mar 17 12:49:50 PM PDT 24
Peak memory 203112 kb
Host smart-b5c72486-91ce-4c0c-8445-a4e3b8edd3de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896001149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.2896001149
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.4269875987
Short name T258
Test name
Test status
Simulation time 38962242490 ps
CPU time 1237.02 seconds
Started Mar 17 12:48:24 PM PDT 24
Finished Mar 17 01:09:02 PM PDT 24
Peak memory 373864 kb
Host smart-7df09082-bbfd-4b33-933a-1a0ef23dbbc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269875987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.4269875987
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.1237153819
Short name T708
Test name
Test status
Simulation time 501051115 ps
CPU time 4.33 seconds
Started Mar 17 12:48:24 PM PDT 24
Finished Mar 17 12:48:28 PM PDT 24
Peak memory 203172 kb
Host smart-bb96e660-6574-4a5b-80cd-cadbdfa286bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237153819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.1237153819
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.2262161775
Short name T277
Test name
Test status
Simulation time 683025154 ps
CPU time 132.34 seconds
Started Mar 17 12:48:25 PM PDT 24
Finished Mar 17 12:50:37 PM PDT 24
Peak memory 369724 kb
Host smart-65ea24c6-659b-4cd1-a58b-adb1ee8e41f7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262161775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.2262161775
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3068024317
Short name T242
Test name
Test status
Simulation time 563953466 ps
CPU time 4.29 seconds
Started Mar 17 12:48:26 PM PDT 24
Finished Mar 17 12:48:30 PM PDT 24
Peak memory 211432 kb
Host smart-09c981ca-4a88-4986-8784-7b9e247c55c8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068024317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.3068024317
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.746976867
Short name T793
Test name
Test status
Simulation time 553006638 ps
CPU time 7.88 seconds
Started Mar 17 12:48:30 PM PDT 24
Finished Mar 17 12:48:39 PM PDT 24
Peak memory 203176 kb
Host smart-8dc9f368-53d8-4e00-b4bf-bbd9cb8ebfa5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746976867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl
_mem_walk.746976867
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.3400400615
Short name T407
Test name
Test status
Simulation time 3190994059 ps
CPU time 234.13 seconds
Started Mar 17 12:48:18 PM PDT 24
Finished Mar 17 12:52:13 PM PDT 24
Peak memory 337060 kb
Host smart-a59ea04d-ab96-4d3f-a68f-022e0fb55f25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400400615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.3400400615
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.3958404552
Short name T574
Test name
Test status
Simulation time 820001380 ps
CPU time 6.89 seconds
Started Mar 17 12:48:23 PM PDT 24
Finished Mar 17 12:48:30 PM PDT 24
Peak memory 203188 kb
Host smart-7861e7cb-9460-470d-ad48-fe7468c9e0fa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958404552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.3958404552
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.1893207635
Short name T448
Test name
Test status
Simulation time 28930975 ps
CPU time 0.77 seconds
Started Mar 17 12:48:25 PM PDT 24
Finished Mar 17 12:48:26 PM PDT 24
Peak memory 203228 kb
Host smart-bbef527e-1d55-4260-a492-27bb307729c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893207635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1893207635
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.1813488434
Short name T5
Test name
Test status
Simulation time 10996412657 ps
CPU time 1084.82 seconds
Started Mar 17 12:48:24 PM PDT 24
Finished Mar 17 01:06:29 PM PDT 24
Peak memory 347884 kb
Host smart-ab85c7e5-66c4-47f3-ba94-e7dfaa8a76f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813488434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1813488434
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.1091823841
Short name T205
Test name
Test status
Simulation time 241919523 ps
CPU time 14.26 seconds
Started Mar 17 12:48:18 PM PDT 24
Finished Mar 17 12:48:34 PM PDT 24
Peak memory 203132 kb
Host smart-663d4776-f144-4fe7-9d2d-0fdc80b615df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091823841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1091823841
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.2572351341
Short name T121
Test name
Test status
Simulation time 76339679997 ps
CPU time 4213.55 seconds
Started Mar 17 12:48:25 PM PDT 24
Finished Mar 17 01:58:40 PM PDT 24
Peak memory 377024 kb
Host smart-c33679be-fb7f-40ca-b4bc-f924deae94da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572351341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.2572351341
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3570288090
Short name T531
Test name
Test status
Simulation time 5251538583 ps
CPU time 208.68 seconds
Started Mar 17 12:48:26 PM PDT 24
Finished Mar 17 12:51:55 PM PDT 24
Peak memory 377104 kb
Host smart-dfe62ab4-f76b-40dc-858f-1a0961b3503a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3570288090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3570288090
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1411792878
Short name T97
Test name
Test status
Simulation time 1735688561 ps
CPU time 169.33 seconds
Started Mar 17 12:48:26 PM PDT 24
Finished Mar 17 12:51:16 PM PDT 24
Peak memory 203168 kb
Host smart-8e4b0f4b-1c4b-4d17-bd30-93676d867a61
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411792878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.1411792878
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2951983651
Short name T215
Test name
Test status
Simulation time 626902552 ps
CPU time 124.12 seconds
Started Mar 17 12:48:26 PM PDT 24
Finished Mar 17 12:50:30 PM PDT 24
Peak memory 366676 kb
Host smart-ada2c99c-2264-4ac3-9e61-c436a9311931
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951983651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2951983651
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1232990936
Short name T658
Test name
Test status
Simulation time 9014229559 ps
CPU time 991.32 seconds
Started Mar 17 12:48:23 PM PDT 24
Finished Mar 17 01:04:54 PM PDT 24
Peak memory 376048 kb
Host smart-0c41faf4-9438-485b-9ccd-3edac48dd95e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232990936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.1232990936
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.365996693
Short name T428
Test name
Test status
Simulation time 15841405 ps
CPU time 0.65 seconds
Started Mar 17 12:48:32 PM PDT 24
Finished Mar 17 12:48:32 PM PDT 24
Peak memory 202036 kb
Host smart-2cd8b790-b479-4e11-9bd3-e1007defd17a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365996693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.365996693
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.3958264378
Short name T41
Test name
Test status
Simulation time 8441763014 ps
CPU time 45.76 seconds
Started Mar 17 12:48:29 PM PDT 24
Finished Mar 17 12:49:15 PM PDT 24
Peak memory 203188 kb
Host smart-f3f1c379-52f1-4fa1-837e-192ebe1d7529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958264378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.3958264378
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.3695520519
Short name T537
Test name
Test status
Simulation time 16748511408 ps
CPU time 1194.92 seconds
Started Mar 17 12:48:25 PM PDT 24
Finished Mar 17 01:08:20 PM PDT 24
Peak memory 373984 kb
Host smart-a90c5a98-a3d7-4d89-b544-ff954610f0dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695520519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.3695520519
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.797878499
Short name T665
Test name
Test status
Simulation time 894931504 ps
CPU time 5.51 seconds
Started Mar 17 12:48:27 PM PDT 24
Finished Mar 17 12:48:32 PM PDT 24
Peak memory 203164 kb
Host smart-5d5f3c0b-d89d-4a26-8447-366169ab80d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797878499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc
alation.797878499
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.1527985726
Short name T220
Test name
Test status
Simulation time 234697907 ps
CPU time 7.37 seconds
Started Mar 17 12:48:28 PM PDT 24
Finished Mar 17 12:48:36 PM PDT 24
Peak memory 238356 kb
Host smart-a04b5a8b-5d2e-4980-b847-c408565dd0ac
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527985726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.1527985726
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1971343772
Short name T81
Test name
Test status
Simulation time 63015388 ps
CPU time 4.47 seconds
Started Mar 17 12:48:31 PM PDT 24
Finished Mar 17 12:48:35 PM PDT 24
Peak memory 211416 kb
Host smart-e2602d82-8400-43b0-a2c8-b41882c9ad82
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971343772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.1971343772
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.1523432952
Short name T859
Test name
Test status
Simulation time 78269177 ps
CPU time 4.48 seconds
Started Mar 17 12:48:29 PM PDT 24
Finished Mar 17 12:48:33 PM PDT 24
Peak memory 203240 kb
Host smart-46b27394-d6a0-4b52-9266-2d953e51dd88
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523432952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.1523432952
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.1668763417
Short name T260
Test name
Test status
Simulation time 48910317576 ps
CPU time 551.47 seconds
Started Mar 17 12:48:25 PM PDT 24
Finished Mar 17 12:57:37 PM PDT 24
Peak memory 347380 kb
Host smart-43a566f6-48b5-49a9-a149-600a68ed20b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668763417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.1668763417
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.2533390464
Short name T190
Test name
Test status
Simulation time 853504061 ps
CPU time 8.94 seconds
Started Mar 17 12:48:24 PM PDT 24
Finished Mar 17 12:48:33 PM PDT 24
Peak memory 203212 kb
Host smart-173c7c87-0064-4eff-a6d3-8b0292eb35a6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533390464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.2533390464
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.481099403
Short name T387
Test name
Test status
Simulation time 35733096878 ps
CPU time 414.16 seconds
Started Mar 17 12:48:24 PM PDT 24
Finished Mar 17 12:55:19 PM PDT 24
Peak memory 203236 kb
Host smart-795d3302-0a35-42a3-8b09-544f6df4dd9e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481099403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.sram_ctrl_partial_access_b2b.481099403
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.2255021460
Short name T719
Test name
Test status
Simulation time 40188829 ps
CPU time 0.74 seconds
Started Mar 17 12:48:29 PM PDT 24
Finished Mar 17 12:48:31 PM PDT 24
Peak memory 203448 kb
Host smart-f88ec169-a761-410c-b439-1914e7621daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255021460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2255021460
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.3525673811
Short name T568
Test name
Test status
Simulation time 59076568002 ps
CPU time 1170.19 seconds
Started Mar 17 12:48:38 PM PDT 24
Finished Mar 17 01:08:09 PM PDT 24
Peak memory 372968 kb
Host smart-037dd6eb-3cf9-4009-8778-d964a5d0b295
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525673811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3525673811
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.518471406
Short name T165
Test name
Test status
Simulation time 432476023 ps
CPU time 9.68 seconds
Started Mar 17 12:48:22 PM PDT 24
Finished Mar 17 12:48:32 PM PDT 24
Peak memory 203136 kb
Host smart-68571e67-e420-473c-a976-d7f5301303e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518471406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.518471406
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.3853518823
Short name T320
Test name
Test status
Simulation time 34211881498 ps
CPU time 1003.76 seconds
Started Mar 17 12:48:36 PM PDT 24
Finished Mar 17 01:05:20 PM PDT 24
Peak memory 373044 kb
Host smart-66fe0eca-b4d6-458a-8fdd-7362509febb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853518823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.3853518823
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1578721527
Short name T309
Test name
Test status
Simulation time 4105645485 ps
CPU time 629.96 seconds
Started Mar 17 12:48:38 PM PDT 24
Finished Mar 17 12:59:08 PM PDT 24
Peak memory 375184 kb
Host smart-8f178826-4969-4462-87cc-59a1fbc055d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1578721527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1578721527
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1938575385
Short name T794
Test name
Test status
Simulation time 4111001041 ps
CPU time 369.04 seconds
Started Mar 17 12:48:27 PM PDT 24
Finished Mar 17 12:54:36 PM PDT 24
Peak memory 203228 kb
Host smart-51ccdaa4-6b73-4d49-b7a1-b2bcdeded6a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938575385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.1938575385
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.182461839
Short name T364
Test name
Test status
Simulation time 67810628 ps
CPU time 8.68 seconds
Started Mar 17 12:48:28 PM PDT 24
Finished Mar 17 12:48:37 PM PDT 24
Peak memory 239536 kb
Host smart-d5063955-2214-4b72-a640-4d9acc0f5e38
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182461839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.182461839
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2081913104
Short name T366
Test name
Test status
Simulation time 21825509087 ps
CPU time 2256.75 seconds
Started Mar 17 12:48:32 PM PDT 24
Finished Mar 17 01:26:10 PM PDT 24
Peak memory 373844 kb
Host smart-6bf6a77d-71bf-44e8-8c79-cd811e0c2ad5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081913104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.2081913104
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.341819188
Short name T743
Test name
Test status
Simulation time 10710489 ps
CPU time 0.64 seconds
Started Mar 17 12:48:43 PM PDT 24
Finished Mar 17 12:48:43 PM PDT 24
Peak memory 202260 kb
Host smart-df5aa424-dba0-4a2d-94b7-c15371202991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341819188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.341819188
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.4245491712
Short name T435
Test name
Test status
Simulation time 4222046712 ps
CPU time 22.92 seconds
Started Mar 17 12:48:36 PM PDT 24
Finished Mar 17 12:48:59 PM PDT 24
Peak memory 203184 kb
Host smart-88d0c722-f741-40ee-be91-6f9930cca701
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245491712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.4245491712
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.748058327
Short name T200
Test name
Test status
Simulation time 34518178652 ps
CPU time 866.89 seconds
Started Mar 17 12:48:30 PM PDT 24
Finished Mar 17 01:02:57 PM PDT 24
Peak memory 371872 kb
Host smart-eb80c791-5da5-4c0b-9a32-3006a443180d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748058327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executabl
e.748058327
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.1764461764
Short name T893
Test name
Test status
Simulation time 215009434 ps
CPU time 2.9 seconds
Started Mar 17 12:48:30 PM PDT 24
Finished Mar 17 12:48:34 PM PDT 24
Peak memory 203172 kb
Host smart-0b5069e7-839d-4ad6-b7d8-bd4bc83f8f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764461764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.1764461764
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.2698617018
Short name T605
Test name
Test status
Simulation time 980448664 ps
CPU time 96.19 seconds
Started Mar 17 12:48:30 PM PDT 24
Finished Mar 17 12:50:07 PM PDT 24
Peak memory 338428 kb
Host smart-cb26cbb4-9704-4509-87f8-f6d123b66a5f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698617018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.2698617018
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2751137774
Short name T656
Test name
Test status
Simulation time 147022333 ps
CPU time 2.53 seconds
Started Mar 17 12:48:43 PM PDT 24
Finished Mar 17 12:48:46 PM PDT 24
Peak memory 211260 kb
Host smart-daea5987-7fbf-4fc9-adf3-812c35da006c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751137774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.2751137774
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.2716845059
Short name T848
Test name
Test status
Simulation time 1362632186 ps
CPU time 10.22 seconds
Started Mar 17 12:48:43 PM PDT 24
Finished Mar 17 12:48:54 PM PDT 24
Peak memory 203176 kb
Host smart-28d02de4-a608-41f8-bb00-ae0b8cedc32f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716845059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.2716845059
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.4293755914
Short name T153
Test name
Test status
Simulation time 5230607565 ps
CPU time 235.22 seconds
Started Mar 17 12:48:31 PM PDT 24
Finished Mar 17 12:52:26 PM PDT 24
Peak memory 365860 kb
Host smart-cfb5d38d-ede2-442e-bd99-e15eaf4c5f83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293755914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.4293755914
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.452329507
Short name T392
Test name
Test status
Simulation time 127115907 ps
CPU time 6.4 seconds
Started Mar 17 12:48:30 PM PDT 24
Finished Mar 17 12:48:36 PM PDT 24
Peak memory 231640 kb
Host smart-bcb98e70-67d1-460d-aac3-e828b8053a24
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452329507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s
ram_ctrl_partial_access.452329507
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1658165977
Short name T716
Test name
Test status
Simulation time 3582983806 ps
CPU time 227.26 seconds
Started Mar 17 12:48:31 PM PDT 24
Finished Mar 17 12:52:19 PM PDT 24
Peak memory 203256 kb
Host smart-dcc1037f-be84-487a-aebd-41a78169be0c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658165977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.1658165977
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.2743289944
Short name T627
Test name
Test status
Simulation time 83298201 ps
CPU time 0.77 seconds
Started Mar 17 12:48:44 PM PDT 24
Finished Mar 17 12:48:45 PM PDT 24
Peak memory 203188 kb
Host smart-b8488088-cc5b-46b7-8aaa-e87373f227eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743289944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2743289944
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.1275217082
Short name T228
Test name
Test status
Simulation time 780333246 ps
CPU time 197.66 seconds
Started Mar 17 12:48:44 PM PDT 24
Finished Mar 17 12:52:02 PM PDT 24
Peak memory 372652 kb
Host smart-316c30ef-b0ca-494a-92af-0dbd9a96b636
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275217082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1275217082
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.2217139061
Short name T210
Test name
Test status
Simulation time 103705573 ps
CPU time 58.51 seconds
Started Mar 17 12:48:32 PM PDT 24
Finished Mar 17 12:49:31 PM PDT 24
Peak memory 304988 kb
Host smart-fb047503-2aee-4b3a-ab1c-892c99fd1d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217139061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2217139061
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.1056976688
Short name T860
Test name
Test status
Simulation time 13864051209 ps
CPU time 848.74 seconds
Started Mar 17 12:48:43 PM PDT 24
Finished Mar 17 01:02:52 PM PDT 24
Peak memory 375604 kb
Host smart-d6bb1703-c1ef-490e-b024-4a50ebd043fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056976688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.1056976688
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.434705517
Short name T345
Test name
Test status
Simulation time 5144787864 ps
CPU time 30.41 seconds
Started Mar 17 12:48:43 PM PDT 24
Finished Mar 17 12:49:14 PM PDT 24
Peak memory 212688 kb
Host smart-f9330600-1fda-4bfe-a57b-c43226db3c2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=434705517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.434705517
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3353976755
Short name T619
Test name
Test status
Simulation time 2663354030 ps
CPU time 240.17 seconds
Started Mar 17 12:48:32 PM PDT 24
Finished Mar 17 12:52:34 PM PDT 24
Peak memory 203256 kb
Host smart-3790175b-0f23-413b-8c43-a1ecefd5f1ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353976755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.3353976755
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1591814371
Short name T492
Test name
Test status
Simulation time 194630075 ps
CPU time 24.02 seconds
Started Mar 17 12:48:30 PM PDT 24
Finished Mar 17 12:48:54 PM PDT 24
Peak memory 280616 kb
Host smart-d46c47f6-42b4-4259-926a-7af46677d5fc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591814371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.1591814371
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2269774485
Short name T722
Test name
Test status
Simulation time 5598936260 ps
CPU time 249.76 seconds
Started Mar 17 12:48:44 PM PDT 24
Finished Mar 17 12:52:54 PM PDT 24
Peak memory 373576 kb
Host smart-337f6f32-ab2e-4d4b-bb45-e077878b73e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269774485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.2269774485
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.1230917146
Short name T571
Test name
Test status
Simulation time 70954684 ps
CPU time 0.63 seconds
Started Mar 17 12:48:50 PM PDT 24
Finished Mar 17 12:48:51 PM PDT 24
Peak memory 202932 kb
Host smart-909ab8de-2a84-4062-ac3d-0b090b4fe64b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230917146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.1230917146
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.424852954
Short name T316
Test name
Test status
Simulation time 6130769197 ps
CPU time 54.6 seconds
Started Mar 17 12:48:42 PM PDT 24
Finished Mar 17 12:49:37 PM PDT 24
Peak memory 203172 kb
Host smart-f49cd1b6-6d17-4611-8830-ed73d7083516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424852954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.
424852954
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.3244680243
Short name T252
Test name
Test status
Simulation time 114513270423 ps
CPU time 1601.56 seconds
Started Mar 17 12:48:44 PM PDT 24
Finished Mar 17 01:15:27 PM PDT 24
Peak memory 371580 kb
Host smart-2697f938-3182-4d5b-8c72-6e5e31082dbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244680243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.3244680243
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.3603634375
Short name T349
Test name
Test status
Simulation time 547409841 ps
CPU time 6.06 seconds
Started Mar 17 12:48:43 PM PDT 24
Finished Mar 17 12:48:49 PM PDT 24
Peak memory 214596 kb
Host smart-b41f3f04-8307-4877-958f-0372d51fa896
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603634375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.3603634375
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.595704031
Short name T40
Test name
Test status
Simulation time 163178335 ps
CPU time 16.59 seconds
Started Mar 17 12:48:45 PM PDT 24
Finished Mar 17 12:49:02 PM PDT 24
Peak memory 276780 kb
Host smart-861ae468-3d98-4bf9-8ad3-54f3a8313666
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595704031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.sram_ctrl_max_throughput.595704031
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.765408571
Short name T473
Test name
Test status
Simulation time 958617862 ps
CPU time 4.37 seconds
Started Mar 17 12:48:48 PM PDT 24
Finished Mar 17 12:48:53 PM PDT 24
Peak memory 211428 kb
Host smart-890b2846-856a-4127-a0ad-4146b2331aef
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765408571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_mem_partial_access.765408571
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.3827793348
Short name T15
Test name
Test status
Simulation time 147946324 ps
CPU time 4.35 seconds
Started Mar 17 12:48:49 PM PDT 24
Finished Mar 17 12:48:54 PM PDT 24
Peak memory 203188 kb
Host smart-7af94203-035b-4b8e-9b81-f946689817e5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827793348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.3827793348
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.3766305044
Short name T445
Test name
Test status
Simulation time 12206361116 ps
CPU time 974.94 seconds
Started Mar 17 12:48:42 PM PDT 24
Finished Mar 17 01:04:58 PM PDT 24
Peak memory 374020 kb
Host smart-b85855ed-6647-4f62-9e45-0f9404e8aa1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766305044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.3766305044
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.1195816358
Short name T164
Test name
Test status
Simulation time 141027883 ps
CPU time 5.4 seconds
Started Mar 17 12:48:43 PM PDT 24
Finished Mar 17 12:48:49 PM PDT 24
Peak memory 228236 kb
Host smart-bcd2fbc4-6d0a-4e47-a9e9-90ca0bc13d33
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195816358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.1195816358
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4068637884
Short name T672
Test name
Test status
Simulation time 42337280894 ps
CPU time 216.99 seconds
Started Mar 17 12:48:42 PM PDT 24
Finished Mar 17 12:52:20 PM PDT 24
Peak memory 203228 kb
Host smart-4673fdc9-c018-4e5d-8fe4-60643223f574
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068637884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.4068637884
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.3330231323
Short name T576
Test name
Test status
Simulation time 345936099 ps
CPU time 0.76 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:48:53 PM PDT 24
Peak memory 203200 kb
Host smart-f462c9fd-a6ab-43d6-9052-851bf4fd111a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330231323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3330231323
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.3167007415
Short name T379
Test name
Test status
Simulation time 42243113478 ps
CPU time 825.3 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 01:02:37 PM PDT 24
Peak memory 375468 kb
Host smart-b806fd5a-880c-4395-b35c-38d7600a64ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167007415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3167007415
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.1502121668
Short name T158
Test name
Test status
Simulation time 7315441900 ps
CPU time 10.94 seconds
Started Mar 17 12:48:44 PM PDT 24
Finished Mar 17 12:48:56 PM PDT 24
Peak memory 203196 kb
Host smart-41c1af01-9dbc-43d9-a2b3-f94518bf107d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502121668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1502121668
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.3411727019
Short name T561
Test name
Test status
Simulation time 11056293904 ps
CPU time 4039.18 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 01:56:14 PM PDT 24
Peak memory 383212 kb
Host smart-43a5d0a3-f728-4e36-9b5f-ddea8e2df5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411727019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.3411727019
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3825175916
Short name T107
Test name
Test status
Simulation time 583949796 ps
CPU time 8.55 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:49:00 PM PDT 24
Peak memory 211420 kb
Host smart-4aa8f155-657d-4175-a7de-4abe8956265c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3825175916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3825175916
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1017447923
Short name T338
Test name
Test status
Simulation time 1966423431 ps
CPU time 179.6 seconds
Started Mar 17 12:48:43 PM PDT 24
Finished Mar 17 12:51:42 PM PDT 24
Peak memory 203136 kb
Host smart-7345958c-5998-455e-b059-053529bf267f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017447923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.1017447923
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.956991481
Short name T765
Test name
Test status
Simulation time 162945474 ps
CPU time 127.26 seconds
Started Mar 17 12:48:44 PM PDT 24
Finished Mar 17 12:50:52 PM PDT 24
Peak memory 369288 kb
Host smart-b16651dc-6623-4294-b22c-c06d9e5a6f68
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956991481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.956991481
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3474952399
Short name T419
Test name
Test status
Simulation time 17963439294 ps
CPU time 1207.34 seconds
Started Mar 17 12:47:00 PM PDT 24
Finished Mar 17 01:07:08 PM PDT 24
Peak memory 374148 kb
Host smart-50a1b8b3-03a8-4e44-9cd0-8b301b5011e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474952399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.3474952399
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.3637647408
Short name T491
Test name
Test status
Simulation time 71505143 ps
CPU time 0.7 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 12:47:02 PM PDT 24
Peak memory 202096 kb
Host smart-8ed7231d-9135-454a-93c6-b500e9683515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637647408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.3637647408
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.1560557317
Short name T417
Test name
Test status
Simulation time 1257078936 ps
CPU time 21.4 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:47:42 PM PDT 24
Peak memory 203004 kb
Host smart-9cc4a78a-749d-48ef-a598-02d20819f649
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560557317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
1560557317
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.99264789
Short name T500
Test name
Test status
Simulation time 2257122929 ps
CPU time 590.15 seconds
Started Mar 17 12:47:11 PM PDT 24
Finished Mar 17 12:57:02 PM PDT 24
Peak memory 365888 kb
Host smart-f00a49cd-accd-4f54-88fc-facdaff439ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99264789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.99264789
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.2795589667
Short name T693
Test name
Test status
Simulation time 1624545836 ps
CPU time 7.62 seconds
Started Mar 17 12:46:59 PM PDT 24
Finished Mar 17 12:47:07 PM PDT 24
Peak memory 203144 kb
Host smart-109b1293-5126-49d2-bf5b-0e3a88875a9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795589667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.2795589667
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.4066327096
Short name T567
Test name
Test status
Simulation time 216625123 ps
CPU time 38.44 seconds
Started Mar 17 12:47:14 PM PDT 24
Finished Mar 17 12:47:53 PM PDT 24
Peak memory 301176 kb
Host smart-40232096-2934-4f37-904c-d162e2fe1854
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066327096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.4066327096
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2211306715
Short name T76
Test name
Test status
Simulation time 120045932 ps
CPU time 4.23 seconds
Started Mar 17 12:46:57 PM PDT 24
Finished Mar 17 12:47:02 PM PDT 24
Peak memory 211428 kb
Host smart-49eb5027-0ae0-4a9f-9d6b-d418ca0c871d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211306715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.2211306715
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.3722470400
Short name T750
Test name
Test status
Simulation time 1315270666 ps
CPU time 9.62 seconds
Started Mar 17 12:47:15 PM PDT 24
Finished Mar 17 12:47:26 PM PDT 24
Peak memory 203112 kb
Host smart-a7e04ac2-5bb5-4bd2-92c9-b354ff339f39
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722470400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.3722470400
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.1371117955
Short name T823
Test name
Test status
Simulation time 9456956982 ps
CPU time 1294.41 seconds
Started Mar 17 12:47:02 PM PDT 24
Finished Mar 17 01:08:41 PM PDT 24
Peak memory 375820 kb
Host smart-4ddf6229-d1bc-4c8a-93e6-3a9a0698b4f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371117955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.1371117955
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.3952170422
Short name T655
Test name
Test status
Simulation time 927996709 ps
CPU time 2.3 seconds
Started Mar 17 12:46:58 PM PDT 24
Finished Mar 17 12:47:00 PM PDT 24
Peak memory 203120 kb
Host smart-b7e88588-4519-4edb-b820-f96d2442cc03
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952170422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.3952170422
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.19588814
Short name T790
Test name
Test status
Simulation time 90626692374 ps
CPU time 353.07 seconds
Started Mar 17 12:47:00 PM PDT 24
Finished Mar 17 12:52:54 PM PDT 24
Peak memory 203300 kb
Host smart-74fc9f8b-5420-44dd-a110-fe2e4cfc5e9b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19588814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_partial_access_b2b.19588814
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.681741462
Short name T224
Test name
Test status
Simulation time 32367300 ps
CPU time 0.76 seconds
Started Mar 17 12:47:12 PM PDT 24
Finished Mar 17 12:47:13 PM PDT 24
Peak memory 203256 kb
Host smart-d6609dc4-7a34-49c9-9329-85c7964747dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681741462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.681741462
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.74012505
Short name T905
Test name
Test status
Simulation time 10735774932 ps
CPU time 636.97 seconds
Started Mar 17 12:47:04 PM PDT 24
Finished Mar 17 12:57:42 PM PDT 24
Peak memory 374988 kb
Host smart-ed5ce260-aa41-4e1f-8985-0139d651b2f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74012505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.74012505
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3020894784
Short name T32
Test name
Test status
Simulation time 238384581 ps
CPU time 1.94 seconds
Started Mar 17 12:47:02 PM PDT 24
Finished Mar 17 12:47:04 PM PDT 24
Peak memory 225012 kb
Host smart-15a8b4ca-7731-4286-8076-f0c7cd8b6770
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020894784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3020894784
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.2770989806
Short name T642
Test name
Test status
Simulation time 135957324 ps
CPU time 8.07 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 12:47:09 PM PDT 24
Peak memory 203092 kb
Host smart-a13e6d1f-496f-476e-8a88-756e9dcf49a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770989806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2770989806
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.1107076565
Short name T404
Test name
Test status
Simulation time 4498183020 ps
CPU time 723.57 seconds
Started Mar 17 12:47:13 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 363704 kb
Host smart-ff1001da-fbe0-4114-9a87-f8ddc0739027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107076565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.1107076565
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2952382553
Short name T112
Test name
Test status
Simulation time 318439041 ps
CPU time 9.88 seconds
Started Mar 17 12:46:39 PM PDT 24
Finished Mar 17 12:46:49 PM PDT 24
Peak memory 218824 kb
Host smart-11ba45b1-3b7c-460d-b2a3-9daa916c9f45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2952382553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2952382553
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.450252768
Short name T935
Test name
Test status
Simulation time 16989256632 ps
CPU time 426.33 seconds
Started Mar 17 12:46:56 PM PDT 24
Finished Mar 17 12:54:03 PM PDT 24
Peak memory 203196 kb
Host smart-6e154b18-791e-4525-a6ce-97bd968f6834
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450252768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_stress_pipeline.450252768
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2450491108
Short name T872
Test name
Test status
Simulation time 272808565 ps
CPU time 89.21 seconds
Started Mar 17 12:47:09 PM PDT 24
Finished Mar 17 12:48:38 PM PDT 24
Peak memory 346296 kb
Host smart-36fa04dd-c81b-418b-a9a6-7e9d2e69cf64
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450491108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.2450491108
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2641198932
Short name T727
Test name
Test status
Simulation time 19633690666 ps
CPU time 1668.81 seconds
Started Mar 17 12:48:50 PM PDT 24
Finished Mar 17 01:16:39 PM PDT 24
Peak memory 376128 kb
Host smart-42dfc8b1-7fb9-4e07-a730-ad612b2a910c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641198932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.2641198932
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.2957176721
Short name T596
Test name
Test status
Simulation time 10911668 ps
CPU time 0.64 seconds
Started Mar 17 12:48:53 PM PDT 24
Finished Mar 17 12:48:54 PM PDT 24
Peak memory 202284 kb
Host smart-03f7c2b1-5aa5-48ae-aa50-e0fcd1e28790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957176721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.2957176721
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.224030981
Short name T382
Test name
Test status
Simulation time 3081166707 ps
CPU time 42.98 seconds
Started Mar 17 12:48:50 PM PDT 24
Finished Mar 17 12:49:34 PM PDT 24
Peak memory 203208 kb
Host smart-e300f969-c088-47cb-a4aa-f76c17cb6221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224030981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.
224030981
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.3706961196
Short name T291
Test name
Test status
Simulation time 17244456068 ps
CPU time 1626.18 seconds
Started Mar 17 12:48:50 PM PDT 24
Finished Mar 17 01:15:56 PM PDT 24
Peak memory 374916 kb
Host smart-fccef66c-51c2-4d3e-b8ae-9827cfac669e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706961196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.3706961196
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.1713604162
Short name T460
Test name
Test status
Simulation time 595407757 ps
CPU time 5.9 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:48:58 PM PDT 24
Peak memory 211396 kb
Host smart-69a070dc-374f-4e6e-a9fe-019a38adbddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713604162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.1713604162
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.2961176331
Short name T718
Test name
Test status
Simulation time 205588228 ps
CPU time 36.98 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:49:35 PM PDT 24
Peak memory 304408 kb
Host smart-c8734a8b-4efa-4bf5-ae46-66fc9d95b0ff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961176331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.2961176331
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3904735575
Short name T77
Test name
Test status
Simulation time 68059047 ps
CPU time 4.23 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 12:48:56 PM PDT 24
Peak memory 211356 kb
Host smart-a8fbf065-0473-4bb8-a07c-90f4fc1ab9f0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904735575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.3904735575
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.4066781788
Short name T883
Test name
Test status
Simulation time 916686127 ps
CPU time 9.5 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 12:49:01 PM PDT 24
Peak memory 203188 kb
Host smart-f26c5171-bb35-4ab6-ac83-b56a188424f0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066781788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.4066781788
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.1512355739
Short name T654
Test name
Test status
Simulation time 3778231680 ps
CPU time 1097.23 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 01:07:09 PM PDT 24
Peak memory 366872 kb
Host smart-0fbb64f0-ec5a-4984-8614-46b527a5fa6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512355739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.1512355739
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.2416579713
Short name T485
Test name
Test status
Simulation time 1223552872 ps
CPU time 12.6 seconds
Started Mar 17 12:48:50 PM PDT 24
Finished Mar 17 12:49:03 PM PDT 24
Peak memory 203112 kb
Host smart-c5837ae0-4c5f-4134-b696-b31310ecbd5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416579713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.2416579713
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1777391280
Short name T118
Test name
Test status
Simulation time 22269563306 ps
CPU time 392.79 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:55:27 PM PDT 24
Peak memory 203240 kb
Host smart-5a372237-f1f3-475d-859b-bf9ec1e1697c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777391280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.1777391280
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.3412984038
Short name T677
Test name
Test status
Simulation time 27928768 ps
CPU time 0.74 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 12:48:53 PM PDT 24
Peak memory 203268 kb
Host smart-c3ac5658-508f-4cff-abf2-dbad7afb10f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412984038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3412984038
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.2372065015
Short name T520
Test name
Test status
Simulation time 1771189608 ps
CPU time 434.71 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:56:13 PM PDT 24
Peak memory 371720 kb
Host smart-5f826f9e-6023-4746-9dc9-0b17098f82bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372065015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2372065015
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.1084384595
Short name T180
Test name
Test status
Simulation time 1594175536 ps
CPU time 44.78 seconds
Started Mar 17 12:48:48 PM PDT 24
Finished Mar 17 12:49:34 PM PDT 24
Peak memory 294788 kb
Host smart-6ca2f409-2fcc-4f61-9f4c-e69e8e2f7a34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084384595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1084384595
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.4185093286
Short name T363
Test name
Test status
Simulation time 35209363082 ps
CPU time 1806.04 seconds
Started Mar 17 12:48:59 PM PDT 24
Finished Mar 17 01:19:05 PM PDT 24
Peak memory 382816 kb
Host smart-36f76031-b26b-4a65-bbdc-a019c1004c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185093286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.4185093286
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.895659359
Short name T800
Test name
Test status
Simulation time 6705217222 ps
CPU time 529.26 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 12:57:41 PM PDT 24
Peak memory 379440 kb
Host smart-307ba39c-1f7d-4f13-89d3-49986c2cb128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=895659359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.895659359
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2064928273
Short name T150
Test name
Test status
Simulation time 14136010386 ps
CPU time 335.49 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 12:54:27 PM PDT 24
Peak memory 203252 kb
Host smart-65081b1c-7040-4ff5-8769-5334f20ca2d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064928273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.2064928273
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2816666528
Short name T533
Test name
Test status
Simulation time 80016373 ps
CPU time 12.62 seconds
Started Mar 17 12:48:53 PM PDT 24
Finished Mar 17 12:49:06 PM PDT 24
Peak memory 257876 kb
Host smart-97a5d100-c551-4cfe-8a05-395de7eca888
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816666528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.2816666528
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.3986697198
Short name T678
Test name
Test status
Simulation time 21131059 ps
CPU time 0.6 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:48:54 PM PDT 24
Peak memory 202104 kb
Host smart-27c6c005-4ca6-4d71-8535-b9bb7daf8d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986697198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.3986697198
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.3837864711
Short name T67
Test name
Test status
Simulation time 3001969342 ps
CPU time 45.53 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:49:39 PM PDT 24
Peak memory 202700 kb
Host smart-f879c18f-1bcf-4b06-a33f-e264224798b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837864711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.3837864711
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.903818081
Short name T909
Test name
Test status
Simulation time 10222781007 ps
CPU time 475.61 seconds
Started Mar 17 12:48:53 PM PDT 24
Finished Mar 17 12:56:49 PM PDT 24
Peak memory 373736 kb
Host smart-81f6740a-7ffb-4ffa-80ff-1653e3f3282a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903818081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executabl
e.903818081
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.2536416637
Short name T539
Test name
Test status
Simulation time 174184124 ps
CPU time 2.16 seconds
Started Mar 17 12:48:50 PM PDT 24
Finished Mar 17 12:48:53 PM PDT 24
Peak memory 203288 kb
Host smart-5d853d1a-826f-4822-93c6-9ba8f6be7ec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536416637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.2536416637
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.2450387919
Short name T409
Test name
Test status
Simulation time 298810146 ps
CPU time 11.17 seconds
Started Mar 17 12:49:01 PM PDT 24
Finished Mar 17 12:49:12 PM PDT 24
Peak memory 253344 kb
Host smart-178cbc95-efc2-46a1-9f39-999718a7d757
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450387919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.2450387919
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.55240902
Short name T652
Test name
Test status
Simulation time 652904206 ps
CPU time 4.32 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 12:48:56 PM PDT 24
Peak memory 211352 kb
Host smart-77d9d49e-6d3e-407c-866a-8ba14144c351
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55240902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_mem_partial_access.55240902
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.3397554272
Short name T691
Test name
Test status
Simulation time 268317133 ps
CPU time 8.11 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:49:02 PM PDT 24
Peak memory 203188 kb
Host smart-1eb09dd7-480d-49e3-945f-1c161a190bca
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397554272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.3397554272
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.3501911297
Short name T458
Test name
Test status
Simulation time 19065107869 ps
CPU time 1312.05 seconds
Started Mar 17 12:48:50 PM PDT 24
Finished Mar 17 01:10:43 PM PDT 24
Peak memory 375880 kb
Host smart-b0808ee0-a0d2-4361-a76e-538f428b1c33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501911297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.3501911297
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.1893122625
Short name T343
Test name
Test status
Simulation time 1693902073 ps
CPU time 16.04 seconds
Started Mar 17 12:48:50 PM PDT 24
Finished Mar 17 12:49:06 PM PDT 24
Peak memory 203284 kb
Host smart-51a5b2b6-acc1-4024-92ee-de6d4a4adc3a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893122625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.1893122625
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1742824715
Short name T437
Test name
Test status
Simulation time 25062718072 ps
CPU time 310.83 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:54:09 PM PDT 24
Peak memory 203276 kb
Host smart-13959faf-3ac0-4dd3-8bbe-db35093e57b6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742824715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.1742824715
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.1790672103
Short name T497
Test name
Test status
Simulation time 48556197 ps
CPU time 0.74 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:48:54 PM PDT 24
Peak memory 202692 kb
Host smart-43d634ca-ed9b-461c-8277-37d39a9c504c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790672103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1790672103
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.1189118162
Short name T27
Test name
Test status
Simulation time 17899239149 ps
CPU time 515.58 seconds
Started Mar 17 12:48:59 PM PDT 24
Finished Mar 17 12:57:35 PM PDT 24
Peak memory 370268 kb
Host smart-882adee7-5973-464a-893b-202ed90a5260
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189118162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1189118162
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.932568691
Short name T901
Test name
Test status
Simulation time 250746426 ps
CPU time 14.2 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 12:49:09 PM PDT 24
Peak memory 203160 kb
Host smart-55f87877-05bc-466b-83a1-8bf789ec618f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932568691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.932568691
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.2221609951
Short name T832
Test name
Test status
Simulation time 11879428530 ps
CPU time 3244.17 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 01:42:56 PM PDT 24
Peak memory 383168 kb
Host smart-7b163c07-54a2-4951-9542-f1f396475025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221609951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.2221609951
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2339976444
Short name T804
Test name
Test status
Simulation time 4125381067 ps
CPU time 1240.68 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 01:09:39 PM PDT 24
Peak memory 383296 kb
Host smart-2db3554b-63ca-418d-a0f4-a2342fc554aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2339976444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2339976444
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2808038560
Short name T599
Test name
Test status
Simulation time 3611656180 ps
CPU time 337.93 seconds
Started Mar 17 12:48:51 PM PDT 24
Finished Mar 17 12:54:30 PM PDT 24
Peak memory 203196 kb
Host smart-c9f039b8-3f83-4339-9490-9f49252fd309
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808038560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.2808038560
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2085628916
Short name T892
Test name
Test status
Simulation time 133977150 ps
CPU time 91.11 seconds
Started Mar 17 12:48:53 PM PDT 24
Finished Mar 17 12:50:25 PM PDT 24
Peak memory 338116 kb
Host smart-900f8ce4-9295-4082-b8e0-98e33de12754
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085628916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2085628916
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1944044321
Short name T670
Test name
Test status
Simulation time 12494847897 ps
CPU time 334.72 seconds
Started Mar 17 12:48:57 PM PDT 24
Finished Mar 17 12:54:32 PM PDT 24
Peak memory 373688 kb
Host smart-2e0f2fb2-b395-419c-9880-6fe52b48f49e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944044321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.1944044321
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.3492421915
Short name T550
Test name
Test status
Simulation time 17842990 ps
CPU time 0.62 seconds
Started Mar 17 12:48:57 PM PDT 24
Finished Mar 17 12:48:58 PM PDT 24
Peak memory 202296 kb
Host smart-7feeab44-d27d-4b23-b9e0-c0efb18ffab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492421915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.3492421915
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.199720640
Short name T275
Test name
Test status
Simulation time 4572336724 ps
CPU time 39.85 seconds
Started Mar 17 12:48:52 PM PDT 24
Finished Mar 17 12:49:32 PM PDT 24
Peak memory 203188 kb
Host smart-dd3c12ce-7031-429d-bd1e-99c7b015353a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199720640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.
199720640
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.3363632946
Short name T516
Test name
Test status
Simulation time 11817781407 ps
CPU time 831.34 seconds
Started Mar 17 12:48:57 PM PDT 24
Finished Mar 17 01:02:49 PM PDT 24
Peak memory 365788 kb
Host smart-f0e218bc-df23-46d1-a92e-b279719f85a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363632946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.3363632946
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.2216853797
Short name T861
Test name
Test status
Simulation time 2448447416 ps
CPU time 6.88 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:49:05 PM PDT 24
Peak memory 203216 kb
Host smart-9d6d7cab-1937-4f88-98bd-f48db5dcf5cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216853797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.2216853797
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.1399461991
Short name T644
Test name
Test status
Simulation time 81039009 ps
CPU time 3.93 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:49:03 PM PDT 24
Peak memory 222804 kb
Host smart-6a09174c-449c-401e-8258-02d478587bde
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399461991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.1399461991
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2929329240
Short name T662
Test name
Test status
Simulation time 125295546 ps
CPU time 2.51 seconds
Started Mar 17 12:48:56 PM PDT 24
Finished Mar 17 12:48:59 PM PDT 24
Peak memory 211328 kb
Host smart-f1be7de8-e044-4715-8f58-569fbbc2ef56
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929329240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.2929329240
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.309766463
Short name T759
Test name
Test status
Simulation time 4838479057 ps
CPU time 10.68 seconds
Started Mar 17 12:48:56 PM PDT 24
Finished Mar 17 12:49:07 PM PDT 24
Peak memory 203244 kb
Host smart-038c4d6d-e3da-4462-869c-aa0c342a2648
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309766463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl
_mem_walk.309766463
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.2127267171
Short name T845
Test name
Test status
Simulation time 13230185559 ps
CPU time 331.26 seconds
Started Mar 17 12:49:01 PM PDT 24
Finished Mar 17 12:54:32 PM PDT 24
Peak memory 355644 kb
Host smart-d9d16b23-22e0-4eb9-b825-1f5e35498f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127267171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.2127267171
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.2062999982
Short name T271
Test name
Test status
Simulation time 934163564 ps
CPU time 17.91 seconds
Started Mar 17 12:48:55 PM PDT 24
Finished Mar 17 12:49:13 PM PDT 24
Peak memory 203240 kb
Host smart-7c952a4e-da83-4578-89f7-d0b5f97138f2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062999982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.2062999982
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1845632647
Short name T222
Test name
Test status
Simulation time 35964476760 ps
CPU time 395.81 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:55:34 PM PDT 24
Peak memory 203320 kb
Host smart-38c268a6-e350-49fe-8b23-2fd12a12b084
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845632647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1845632647
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.1099720712
Short name T637
Test name
Test status
Simulation time 86303346 ps
CPU time 0.74 seconds
Started Mar 17 12:49:03 PM PDT 24
Finished Mar 17 12:49:04 PM PDT 24
Peak memory 203192 kb
Host smart-56964d79-0bb9-4f4c-bd69-20fede0c79bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099720712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1099720712
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.3509914457
Short name T511
Test name
Test status
Simulation time 1401704482 ps
CPU time 136.85 seconds
Started Mar 17 12:48:57 PM PDT 24
Finished Mar 17 12:51:14 PM PDT 24
Peak memory 335004 kb
Host smart-834ab267-183e-4a5f-a98d-872ef192f6c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509914457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3509914457
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.3973487455
Short name T692
Test name
Test status
Simulation time 265665327 ps
CPU time 1.98 seconds
Started Mar 17 12:48:59 PM PDT 24
Finished Mar 17 12:49:01 PM PDT 24
Peak memory 203160 kb
Host smart-f3af54ec-511c-445c-8a82-7aab8b986d1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973487455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3973487455
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.309477143
Short name T351
Test name
Test status
Simulation time 56992487332 ps
CPU time 2107.72 seconds
Started Mar 17 12:48:55 PM PDT 24
Finished Mar 17 01:24:03 PM PDT 24
Peak memory 383212 kb
Host smart-9cbe69e7-225e-4764-9af2-bc3839564419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309477143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_stress_all.309477143
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.730588225
Short name T342
Test name
Test status
Simulation time 210770546 ps
CPU time 8.1 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:49:06 PM PDT 24
Peak memory 212760 kb
Host smart-7a383996-16b9-4c16-84a4-9fd5e6c4d2ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=730588225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.730588225
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1470002380
Short name T461
Test name
Test status
Simulation time 2003707214 ps
CPU time 187.92 seconds
Started Mar 17 12:49:01 PM PDT 24
Finished Mar 17 12:52:09 PM PDT 24
Peak memory 203184 kb
Host smart-794f744d-8106-4917-98eb-3054bb61f85d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470002380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.1470002380
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1839214484
Short name T808
Test name
Test status
Simulation time 602266052 ps
CPU time 114.14 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:50:53 PM PDT 24
Peak memory 362636 kb
Host smart-2db970a5-4d13-43b7-a6d1-937ea62f70fe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839214484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1839214484
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2026800060
Short name T700
Test name
Test status
Simulation time 265963090 ps
CPU time 163 seconds
Started Mar 17 12:48:57 PM PDT 24
Finished Mar 17 12:51:41 PM PDT 24
Peak memory 369792 kb
Host smart-6e33e713-e567-4f99-8bb4-ab0e1546dce4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026800060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.2026800060
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.577639066
Short name T858
Test name
Test status
Simulation time 86156201 ps
CPU time 0.65 seconds
Started Mar 17 12:49:03 PM PDT 24
Finished Mar 17 12:49:04 PM PDT 24
Peak memory 202120 kb
Host smart-f84177b2-71f1-4ecb-95b5-faafb57bfe8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577639066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.577639066
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.3909773459
Short name T335
Test name
Test status
Simulation time 13250696191 ps
CPU time 72.29 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:50:11 PM PDT 24
Peak memory 203100 kb
Host smart-fb8d5ed1-fc81-40d8-b448-7a937447b92e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909773459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.3909773459
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.616490599
Short name T365
Test name
Test status
Simulation time 3844690081 ps
CPU time 729.78 seconds
Started Mar 17 12:48:59 PM PDT 24
Finished Mar 17 01:01:10 PM PDT 24
Peak memory 374752 kb
Host smart-0d9e7a8e-21b6-4df6-89f8-4fab2f972730
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616490599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl
e.616490599
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.3307781098
Short name T278
Test name
Test status
Simulation time 2673899564 ps
CPU time 8.68 seconds
Started Mar 17 12:48:57 PM PDT 24
Finished Mar 17 12:49:06 PM PDT 24
Peak memory 203188 kb
Host smart-9a33dbde-7523-42f0-a633-9494b63b3c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307781098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.3307781098
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.3977429560
Short name T185
Test name
Test status
Simulation time 237056918 ps
CPU time 29.07 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:49:28 PM PDT 24
Peak memory 293144 kb
Host smart-64ed6943-304b-4502-b60f-977ada6293fc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977429560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.3977429560
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2956470113
Short name T433
Test name
Test status
Simulation time 322436267 ps
CPU time 5.23 seconds
Started Mar 17 12:49:04 PM PDT 24
Finished Mar 17 12:49:09 PM PDT 24
Peak memory 211348 kb
Host smart-ea6aa191-108d-477f-a5f6-ae1be4933d43
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956470113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.2956470113
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.1476943729
Short name T188
Test name
Test status
Simulation time 238596838 ps
CPU time 5.14 seconds
Started Mar 17 12:49:05 PM PDT 24
Finished Mar 17 12:49:10 PM PDT 24
Peak memory 203216 kb
Host smart-41949d85-398c-45c3-afac-67363d2403b8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476943729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.1476943729
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.1371564862
Short name T264
Test name
Test status
Simulation time 70586741380 ps
CPU time 1581.41 seconds
Started Mar 17 12:48:57 PM PDT 24
Finished Mar 17 01:15:19 PM PDT 24
Peak memory 374020 kb
Host smart-484c1554-07f3-4f89-be9a-0cb7f3ea0522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371564862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.1371564862
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.2681963818
Short name T117
Test name
Test status
Simulation time 96510638 ps
CPU time 10.71 seconds
Started Mar 17 12:48:55 PM PDT 24
Finished Mar 17 12:49:06 PM PDT 24
Peak memory 240012 kb
Host smart-67523a84-096a-4278-af39-0ddbc2ca2e04
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681963818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.2681963818
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3066132786
Short name T830
Test name
Test status
Simulation time 3012325527 ps
CPU time 199.82 seconds
Started Mar 17 12:48:57 PM PDT 24
Finished Mar 17 12:52:18 PM PDT 24
Peak memory 203280 kb
Host smart-3894222e-220c-4b0f-a48b-01c3cf6d3493
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066132786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.3066132786
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.125114138
Short name T219
Test name
Test status
Simulation time 28104736 ps
CPU time 0.76 seconds
Started Mar 17 12:49:03 PM PDT 24
Finished Mar 17 12:49:04 PM PDT 24
Peak memory 203264 kb
Host smart-bd841581-f01a-4632-b890-e0dbf73eb679
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125114138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.125114138
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.322330924
Short name T256
Test name
Test status
Simulation time 68909723712 ps
CPU time 740.4 seconds
Started Mar 17 12:48:59 PM PDT 24
Finished Mar 17 01:01:20 PM PDT 24
Peak memory 374776 kb
Host smart-ea52e503-2574-4709-9001-8603b8c13e38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322330924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.322330924
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.4071259631
Short name T394
Test name
Test status
Simulation time 598382070 ps
CPU time 121.25 seconds
Started Mar 17 12:49:00 PM PDT 24
Finished Mar 17 12:51:01 PM PDT 24
Peak memory 351060 kb
Host smart-bea6adf0-ba49-4842-a793-ab44468b0d6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071259631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.4071259631
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.3739241274
Short name T887
Test name
Test status
Simulation time 42671839739 ps
CPU time 2938.74 seconds
Started Mar 17 12:49:05 PM PDT 24
Finished Mar 17 01:38:04 PM PDT 24
Peak memory 377100 kb
Host smart-98871afb-81f0-4da0-9078-e353b6ed0784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739241274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.sram_ctrl_stress_all.3739241274
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2383645707
Short name T48
Test name
Test status
Simulation time 2473485520 ps
CPU time 199.66 seconds
Started Mar 17 12:49:03 PM PDT 24
Finished Mar 17 12:52:23 PM PDT 24
Peak memory 377960 kb
Host smart-958cfe0b-6c55-4b3a-a353-42d699deaf79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2383645707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.2383645707
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2469717367
Short name T347
Test name
Test status
Simulation time 7130167097 ps
CPU time 343.81 seconds
Started Mar 17 12:48:59 PM PDT 24
Finished Mar 17 12:54:44 PM PDT 24
Peak memory 203312 kb
Host smart-cc83655a-4613-48ce-8457-9e30109b63fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469717367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.2469717367
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3188237724
Short name T120
Test name
Test status
Simulation time 53017799 ps
CPU time 3.83 seconds
Started Mar 17 12:48:58 PM PDT 24
Finished Mar 17 12:49:02 PM PDT 24
Peak memory 223072 kb
Host smart-e7b695b2-99d8-4531-b557-e74aee4867a1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188237724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3188237724
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1592807288
Short name T370
Test name
Test status
Simulation time 3199931985 ps
CPU time 1245.28 seconds
Started Mar 17 12:49:03 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 371980 kb
Host smart-1ac5ee63-7842-4ced-b3e7-d003f37a4578
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592807288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.1592807288
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.391691585
Short name T549
Test name
Test status
Simulation time 12018407 ps
CPU time 0.64 seconds
Started Mar 17 12:49:04 PM PDT 24
Finished Mar 17 12:49:05 PM PDT 24
Peak memory 203164 kb
Host smart-9407dbb1-5a69-45dd-906c-566104d8ef8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391691585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.391691585
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.2063920518
Short name T836
Test name
Test status
Simulation time 1409379495 ps
CPU time 20.92 seconds
Started Mar 17 12:49:04 PM PDT 24
Finished Mar 17 12:49:25 PM PDT 24
Peak memory 203196 kb
Host smart-9d0facb2-4927-4ced-b4d5-ccf84d834d25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063920518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.2063920518
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.1659039345
Short name T402
Test name
Test status
Simulation time 10968691038 ps
CPU time 909.66 seconds
Started Mar 17 12:49:05 PM PDT 24
Finished Mar 17 01:04:15 PM PDT 24
Peak memory 364240 kb
Host smart-3f51be9e-262c-45f0-a320-10f6d32c2643
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659039345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab
le.1659039345
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.1647628255
Short name T557
Test name
Test status
Simulation time 1250149578 ps
CPU time 3.96 seconds
Started Mar 17 12:49:05 PM PDT 24
Finished Mar 17 12:49:09 PM PDT 24
Peak memory 203216 kb
Host smart-0b089c66-ac14-4b54-9070-d88410fe7b7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647628255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.1647628255
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.2512962021
Short name T285
Test name
Test status
Simulation time 94426848 ps
CPU time 42.8 seconds
Started Mar 17 12:49:05 PM PDT 24
Finished Mar 17 12:49:48 PM PDT 24
Peak memory 300968 kb
Host smart-ec1ea552-f461-4bc0-918a-6dab0d9816b7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512962021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.2512962021
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3596784009
Short name T74
Test name
Test status
Simulation time 87654883 ps
CPU time 2.91 seconds
Started Mar 17 12:49:05 PM PDT 24
Finished Mar 17 12:49:08 PM PDT 24
Peak memory 211420 kb
Host smart-a5b0c322-b97f-40c6-b797-ccc0d4349a5a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596784009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.3596784009
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.2317534407
Short name T162
Test name
Test status
Simulation time 224630280 ps
CPU time 8.26 seconds
Started Mar 17 12:49:04 PM PDT 24
Finished Mar 17 12:49:12 PM PDT 24
Peak memory 203180 kb
Host smart-2e14b735-7bb3-4123-993e-cece41e1457d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317534407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.2317534407
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.1421116510
Short name T623
Test name
Test status
Simulation time 49057568633 ps
CPU time 1190.33 seconds
Started Mar 17 12:49:05 PM PDT 24
Finished Mar 17 01:08:56 PM PDT 24
Peak memory 374972 kb
Host smart-d4a3d30d-69ba-433f-a558-3010aec8b73c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421116510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.1421116510
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.901292310
Short name T406
Test name
Test status
Simulation time 796581467 ps
CPU time 112.26 seconds
Started Mar 17 12:49:18 PM PDT 24
Finished Mar 17 12:51:10 PM PDT 24
Peak memory 368696 kb
Host smart-eea47aad-8fce-4b77-8d51-5c9626a77391
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901292310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s
ram_ctrl_partial_access.901292310
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3290541459
Short name T573
Test name
Test status
Simulation time 2341063848 ps
CPU time 156.2 seconds
Started Mar 17 12:49:03 PM PDT 24
Finished Mar 17 12:51:39 PM PDT 24
Peak memory 203228 kb
Host smart-7980f8af-90fc-46b5-9487-fc3cfc64d461
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290541459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.3290541459
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.1694293053
Short name T803
Test name
Test status
Simulation time 26867505 ps
CPU time 0.77 seconds
Started Mar 17 12:49:03 PM PDT 24
Finished Mar 17 12:49:04 PM PDT 24
Peak memory 203260 kb
Host smart-988e00b9-f379-43cf-83ef-f34d42d382c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694293053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1694293053
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.2000827787
Short name T774
Test name
Test status
Simulation time 5606445695 ps
CPU time 647.64 seconds
Started Mar 17 12:49:06 PM PDT 24
Finished Mar 17 12:59:53 PM PDT 24
Peak memory 366164 kb
Host smart-c40bcc21-dba4-4b69-9f84-5cfa350d69e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000827787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2000827787
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.834216123
Short name T470
Test name
Test status
Simulation time 135625581 ps
CPU time 7.25 seconds
Started Mar 17 12:49:18 PM PDT 24
Finished Mar 17 12:49:25 PM PDT 24
Peak memory 203180 kb
Host smart-9bb719df-79bc-486a-9329-53a81ff3e4dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834216123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.834216123
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.226597529
Short name T381
Test name
Test status
Simulation time 5649442062 ps
CPU time 120.74 seconds
Started Mar 17 12:49:05 PM PDT 24
Finished Mar 17 12:51:06 PM PDT 24
Peak memory 325184 kb
Host smart-9e233e3b-9eab-431b-9629-1836825f21e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=226597529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.226597529
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2896382069
Short name T518
Test name
Test status
Simulation time 24178845558 ps
CPU time 298.42 seconds
Started Mar 17 12:49:02 PM PDT 24
Finished Mar 17 12:54:01 PM PDT 24
Peak memory 203192 kb
Host smart-8a30348d-a642-4c8d-b0b4-9a1ce6f6669a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896382069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.2896382069
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2514153861
Short name T517
Test name
Test status
Simulation time 426880752 ps
CPU time 76.83 seconds
Started Mar 17 12:49:05 PM PDT 24
Finished Mar 17 12:50:22 PM PDT 24
Peak memory 337484 kb
Host smart-9e1b4c7e-7096-40f7-a3d8-2908ecbdac1d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514153861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.2514153861
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1505949080
Short name T869
Test name
Test status
Simulation time 1267373051 ps
CPU time 301.67 seconds
Started Mar 17 12:49:09 PM PDT 24
Finished Mar 17 12:54:10 PM PDT 24
Peak memory 373948 kb
Host smart-acbeb1f1-cb4f-4b17-be72-497e94a86d18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505949080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.1505949080
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.34582663
Short name T357
Test name
Test status
Simulation time 15671132 ps
CPU time 0.7 seconds
Started Mar 17 12:49:18 PM PDT 24
Finished Mar 17 12:49:19 PM PDT 24
Peak memory 202340 kb
Host smart-7f0c5ed8-edda-4323-8180-4b4cf2b410a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_alert_test.34582663
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.4257197669
Short name T194
Test name
Test status
Simulation time 5295288820 ps
CPU time 42.61 seconds
Started Mar 17 12:49:17 PM PDT 24
Finished Mar 17 12:50:00 PM PDT 24
Peak memory 203248 kb
Host smart-69c68103-09f2-4f61-90d8-750fb498ac11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257197669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.4257197669
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.3375822804
Short name T325
Test name
Test status
Simulation time 11376478958 ps
CPU time 995.09 seconds
Started Mar 17 12:49:08 PM PDT 24
Finished Mar 17 01:05:43 PM PDT 24
Peak memory 374916 kb
Host smart-6ae963ec-2cf3-4a31-88e7-c6b572f85eaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375822804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.3375822804
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.1977046900
Short name T679
Test name
Test status
Simulation time 395161288 ps
CPU time 4.96 seconds
Started Mar 17 12:49:10 PM PDT 24
Finished Mar 17 12:49:15 PM PDT 24
Peak memory 203144 kb
Host smart-3cfa13c3-31b2-427a-9625-bc34365fed89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977046900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.1977046900
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.2540508647
Short name T459
Test name
Test status
Simulation time 329109707 ps
CPU time 35.42 seconds
Started Mar 17 12:49:12 PM PDT 24
Finished Mar 17 12:49:47 PM PDT 24
Peak memory 289084 kb
Host smart-63e36183-ce2c-4915-b8b0-ba217ec66497
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540508647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.2540508647
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.4163066489
Short name T941
Test name
Test status
Simulation time 171677350 ps
CPU time 2.6 seconds
Started Mar 17 12:49:08 PM PDT 24
Finished Mar 17 12:49:11 PM PDT 24
Peak memory 211360 kb
Host smart-87031ca1-a38e-4292-b4ac-ae66b6cb4105
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163066489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.4163066489
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.3262991134
Short name T731
Test name
Test status
Simulation time 594031580 ps
CPU time 4.98 seconds
Started Mar 17 12:49:11 PM PDT 24
Finished Mar 17 12:49:16 PM PDT 24
Peak memory 203204 kb
Host smart-fef067ac-e56a-484e-a4df-5ec5b09374d3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262991134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.3262991134
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.974943331
Short name T732
Test name
Test status
Simulation time 1179690172 ps
CPU time 560.58 seconds
Started Mar 17 12:49:17 PM PDT 24
Finished Mar 17 12:58:37 PM PDT 24
Peak memory 368516 kb
Host smart-578c2581-09ef-480f-834a-50938bb01e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974943331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip
le_keys.974943331
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.568518944
Short name T253
Test name
Test status
Simulation time 684458019 ps
CPU time 11.57 seconds
Started Mar 17 12:49:17 PM PDT 24
Finished Mar 17 12:49:28 PM PDT 24
Peak memory 203244 kb
Host smart-ef8eca1b-c473-4e77-807a-f03d71125dc9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568518944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.s
ram_ctrl_partial_access.568518944
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.710285219
Short name T535
Test name
Test status
Simulation time 114661015657 ps
CPU time 423.22 seconds
Started Mar 17 12:49:11 PM PDT 24
Finished Mar 17 12:56:15 PM PDT 24
Peak memory 203204 kb
Host smart-f45fa9e3-5850-4d90-8644-a62209c16b9a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710285219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.sram_ctrl_partial_access_b2b.710285219
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.1600231369
Short name T187
Test name
Test status
Simulation time 35825440 ps
CPU time 0.8 seconds
Started Mar 17 12:49:13 PM PDT 24
Finished Mar 17 12:49:14 PM PDT 24
Peak memory 203128 kb
Host smart-b4e6b2b3-ab71-4986-900b-6b328c6da381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600231369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1600231369
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.3123403291
Short name T321
Test name
Test status
Simulation time 1696634421 ps
CPU time 580 seconds
Started Mar 17 12:49:09 PM PDT 24
Finished Mar 17 12:58:50 PM PDT 24
Peak memory 373592 kb
Host smart-e46f48d3-63c7-42f1-bf63-c2d85fff10ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123403291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3123403291
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.3220029865
Short name T854
Test name
Test status
Simulation time 727667992 ps
CPU time 8.05 seconds
Started Mar 17 12:49:18 PM PDT 24
Finished Mar 17 12:49:26 PM PDT 24
Peak memory 203152 kb
Host smart-2755f0fa-6d39-47f9-8fd9-9e68e9c522ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220029865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3220029865
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.2362830932
Short name T807
Test name
Test status
Simulation time 49631357868 ps
CPU time 3712.82 seconds
Started Mar 17 12:49:11 PM PDT 24
Finished Mar 17 01:51:04 PM PDT 24
Peak memory 383264 kb
Host smart-2cc0a010-d64d-48cb-8cf4-f13864c0c8c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362830932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.2362830932
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1684792872
Short name T108
Test name
Test status
Simulation time 3656892232 ps
CPU time 145.43 seconds
Started Mar 17 12:49:09 PM PDT 24
Finished Mar 17 12:51:34 PM PDT 24
Peak memory 334132 kb
Host smart-8ce4ca5d-575c-409e-982b-6f60b7568a4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1684792872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1684792872
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.908981748
Short name T747
Test name
Test status
Simulation time 20632008263 ps
CPU time 248.43 seconds
Started Mar 17 12:49:09 PM PDT 24
Finished Mar 17 12:53:18 PM PDT 24
Peak memory 203372 kb
Host smart-55e2dd1d-1091-4077-b9e1-fb77b31b8229
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908981748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_stress_pipeline.908981748
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1138871682
Short name T577
Test name
Test status
Simulation time 163466525 ps
CPU time 118.62 seconds
Started Mar 17 12:49:09 PM PDT 24
Finished Mar 17 12:51:07 PM PDT 24
Peak memory 357824 kb
Host smart-fc79851c-5da1-4f0a-a0a5-d01246454a2e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138871682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1138871682
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2636813825
Short name T509
Test name
Test status
Simulation time 29987807718 ps
CPU time 200.53 seconds
Started Mar 17 12:49:14 PM PDT 24
Finished Mar 17 12:52:35 PM PDT 24
Peak memory 314636 kb
Host smart-95f934fd-e4e1-4654-b865-f768c17776a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636813825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.2636813825
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.800376330
Short name T503
Test name
Test status
Simulation time 14655740 ps
CPU time 0.62 seconds
Started Mar 17 12:49:14 PM PDT 24
Finished Mar 17 12:49:15 PM PDT 24
Peak memory 202944 kb
Host smart-5080209e-3cd8-4cb3-9d25-836817e20c15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800376330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.800376330
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.925591155
Short name T304
Test name
Test status
Simulation time 4117030057 ps
CPU time 71.19 seconds
Started Mar 17 12:49:15 PM PDT 24
Finished Mar 17 12:50:26 PM PDT 24
Peak memory 203260 kb
Host smart-1afaa7e5-d71f-4372-b361-eda29a5257a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925591155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.
925591155
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.94898083
Short name T401
Test name
Test status
Simulation time 89848067792 ps
CPU time 762.31 seconds
Started Mar 17 12:49:15 PM PDT 24
Finished Mar 17 01:01:57 PM PDT 24
Peak memory 371880 kb
Host smart-0d8dd184-cebd-4b34-aa23-1f19ab0f9d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94898083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable
.94898083
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.2738937780
Short name T115
Test name
Test status
Simulation time 522319593 ps
CPU time 5.77 seconds
Started Mar 17 12:49:16 PM PDT 24
Finished Mar 17 12:49:22 PM PDT 24
Peak memory 203120 kb
Host smart-3781a367-b92b-4f62-ae2d-fd085bd8446d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738937780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.2738937780
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.2192037322
Short name T540
Test name
Test status
Simulation time 367232981 ps
CPU time 81.36 seconds
Started Mar 17 12:49:15 PM PDT 24
Finished Mar 17 12:50:37 PM PDT 24
Peak memory 332948 kb
Host smart-2bd45b04-7e42-49a8-a61b-4ddbbabe4e40
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192037322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.2192037322
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1613866512
Short name T663
Test name
Test status
Simulation time 101500256 ps
CPU time 2.61 seconds
Started Mar 17 12:49:15 PM PDT 24
Finished Mar 17 12:49:17 PM PDT 24
Peak memory 211320 kb
Host smart-06756d33-3ae2-47a0-9044-b91f9a1e05e9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613866512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.1613866512
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.1622264770
Short name T564
Test name
Test status
Simulation time 3613249210 ps
CPU time 5.75 seconds
Started Mar 17 12:49:15 PM PDT 24
Finished Mar 17 12:49:21 PM PDT 24
Peak memory 203252 kb
Host smart-45f11f04-3f72-49da-bc5e-cfbe6adc0ce4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622264770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.1622264770
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.925149343
Short name T838
Test name
Test status
Simulation time 95198186159 ps
CPU time 1181.47 seconds
Started Mar 17 12:49:11 PM PDT 24
Finished Mar 17 01:08:53 PM PDT 24
Peak memory 371932 kb
Host smart-b99c5ee0-a096-43f2-b69d-930731d06ed3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925149343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip
le_keys.925149343
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.1893561155
Short name T751
Test name
Test status
Simulation time 178298378 ps
CPU time 8.05 seconds
Started Mar 17 12:49:12 PM PDT 24
Finished Mar 17 12:49:20 PM PDT 24
Peak memory 203160 kb
Host smart-a2a565f5-57ca-46ee-8da8-e31a0b666e0b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893561155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.1893561155
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3209067543
Short name T385
Test name
Test status
Simulation time 13117594303 ps
CPU time 147.34 seconds
Started Mar 17 12:49:09 PM PDT 24
Finished Mar 17 12:51:39 PM PDT 24
Peak memory 203252 kb
Host smart-566697c1-e243-47e7-80e5-40921913d6a9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209067543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.3209067543
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.2093695308
Short name T702
Test name
Test status
Simulation time 86752652 ps
CPU time 0.78 seconds
Started Mar 17 12:49:17 PM PDT 24
Finished Mar 17 12:49:18 PM PDT 24
Peak memory 203124 kb
Host smart-023dc310-8d76-47e4-81e6-e11fb6ad06b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093695308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2093695308
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.2363272033
Short name T487
Test name
Test status
Simulation time 34254260842 ps
CPU time 475.8 seconds
Started Mar 17 12:49:15 PM PDT 24
Finished Mar 17 12:57:11 PM PDT 24
Peak memory 356628 kb
Host smart-78efb947-8d36-40de-aca9-2d9bf90c3cad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363272033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2363272033
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.254836028
Short name T193
Test name
Test status
Simulation time 480920210 ps
CPU time 16 seconds
Started Mar 17 12:49:13 PM PDT 24
Finished Mar 17 12:49:29 PM PDT 24
Peak memory 257308 kb
Host smart-14e268dc-51c2-4508-b5a5-aef686e2a6c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254836028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.254836028
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.2005791336
Short name T8
Test name
Test status
Simulation time 185657625872 ps
CPU time 2563.79 seconds
Started Mar 17 12:49:14 PM PDT 24
Finished Mar 17 01:31:58 PM PDT 24
Peak memory 374264 kb
Host smart-98e67fa7-67dc-49f0-a714-33f484827ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005791336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.2005791336
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2589591770
Short name T110
Test name
Test status
Simulation time 4320693304 ps
CPU time 48.72 seconds
Started Mar 17 12:49:16 PM PDT 24
Finished Mar 17 12:50:05 PM PDT 24
Peak memory 293264 kb
Host smart-36034c45-cf01-4055-ace5-c70d648c6d85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2589591770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2589591770
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1635902098
Short name T528
Test name
Test status
Simulation time 2360498212 ps
CPU time 221.97 seconds
Started Mar 17 12:49:11 PM PDT 24
Finished Mar 17 12:52:53 PM PDT 24
Peak memory 203280 kb
Host smart-7a11934f-5748-4803-8afb-78bbf81c23d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635902098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.1635902098
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3884709395
Short name T358
Test name
Test status
Simulation time 169072672 ps
CPU time 3.31 seconds
Started Mar 17 12:49:17 PM PDT 24
Finished Mar 17 12:49:20 PM PDT 24
Peak memory 219524 kb
Host smart-42e25e75-98f2-4f37-bac4-40421712c087
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884709395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3884709395
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2979205548
Short name T376
Test name
Test status
Simulation time 4101123935 ps
CPU time 1506.38 seconds
Started Mar 17 12:49:36 PM PDT 24
Finished Mar 17 01:14:42 PM PDT 24
Peak memory 375072 kb
Host smart-ab8754e8-cad3-48f1-8cbe-154d14656353
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979205548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.2979205548
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.781661136
Short name T232
Test name
Test status
Simulation time 13619696 ps
CPU time 0.67 seconds
Started Mar 17 12:49:28 PM PDT 24
Finished Mar 17 12:49:29 PM PDT 24
Peak memory 202068 kb
Host smart-71589508-8130-4685-80bf-bbd7883b5610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781661136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.781661136
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.936644780
Short name T855
Test name
Test status
Simulation time 618512893 ps
CPU time 35.48 seconds
Started Mar 17 12:49:19 PM PDT 24
Finished Mar 17 12:49:55 PM PDT 24
Peak memory 203072 kb
Host smart-838ad559-6884-4ba7-b59f-7ec55d518dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936644780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.
936644780
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.2837968622
Short name T724
Test name
Test status
Simulation time 19984415791 ps
CPU time 2280.19 seconds
Started Mar 17 12:49:21 PM PDT 24
Finished Mar 17 01:27:22 PM PDT 24
Peak memory 374640 kb
Host smart-e410b892-b935-44a1-94c7-fbe68bba99b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837968622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.2837968622
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.75791837
Short name T739
Test name
Test status
Simulation time 374793833 ps
CPU time 4.64 seconds
Started Mar 17 12:49:36 PM PDT 24
Finished Mar 17 12:49:40 PM PDT 24
Peak memory 203192 kb
Host smart-59058a7b-4877-437e-a165-b92f58171b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75791837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esca
lation.75791837
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.759554237
Short name T738
Test name
Test status
Simulation time 905992062 ps
CPU time 90.52 seconds
Started Mar 17 12:49:20 PM PDT 24
Finished Mar 17 12:50:51 PM PDT 24
Peak memory 334932 kb
Host smart-5258d3df-e9d4-4113-ba21-480b1f272e8f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759554237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.sram_ctrl_max_throughput.759554237
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3644423656
Short name T36
Test name
Test status
Simulation time 148936549 ps
CPU time 2.65 seconds
Started Mar 17 12:49:28 PM PDT 24
Finished Mar 17 12:49:30 PM PDT 24
Peak memory 210976 kb
Host smart-de5c943f-4b93-4dbe-8e30-f73c69ffa4db
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644423656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.3644423656
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.292637073
Short name T415
Test name
Test status
Simulation time 2719796399 ps
CPU time 10.95 seconds
Started Mar 17 12:49:27 PM PDT 24
Finished Mar 17 12:49:38 PM PDT 24
Peak memory 203332 kb
Host smart-73177ea3-08ac-4cc9-8053-6da110a88752
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292637073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl
_mem_walk.292637073
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.1440258510
Short name T694
Test name
Test status
Simulation time 782554602 ps
CPU time 23.69 seconds
Started Mar 17 12:49:36 PM PDT 24
Finished Mar 17 12:49:59 PM PDT 24
Peak memory 262728 kb
Host smart-4acf4f57-b1c0-411a-8274-2084d0cb4197
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440258510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.1440258510
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.111596341
Short name T423
Test name
Test status
Simulation time 417417336 ps
CPU time 2.29 seconds
Started Mar 17 12:49:19 PM PDT 24
Finished Mar 17 12:49:21 PM PDT 24
Peak memory 203180 kb
Host smart-132e5c05-4ce2-4fda-84f4-0617a3c07704
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111596341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s
ram_ctrl_partial_access.111596341
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1398640497
Short name T917
Test name
Test status
Simulation time 30799135376 ps
CPU time 355.48 seconds
Started Mar 17 12:49:36 PM PDT 24
Finished Mar 17 12:55:31 PM PDT 24
Peak memory 203268 kb
Host smart-b57be1b9-3e3e-4e81-abd1-8500d2736d45
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398640497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.1398640497
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.3163131805
Short name T446
Test name
Test status
Simulation time 28500167 ps
CPU time 0.77 seconds
Started Mar 17 12:49:36 PM PDT 24
Finished Mar 17 12:49:37 PM PDT 24
Peak memory 203300 kb
Host smart-2d599789-fa75-4409-af82-23af176cfe49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163131805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3163131805
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.3294321248
Short name T299
Test name
Test status
Simulation time 12981849657 ps
CPU time 1301.82 seconds
Started Mar 17 12:49:20 PM PDT 24
Finished Mar 17 01:11:02 PM PDT 24
Peak memory 370800 kb
Host smart-08e4270d-b6e8-41e9-8b26-87e807e9c096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294321248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3294321248
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.3672974808
Short name T288
Test name
Test status
Simulation time 1333625451 ps
CPU time 117.07 seconds
Started Mar 17 12:49:36 PM PDT 24
Finished Mar 17 12:51:33 PM PDT 24
Peak memory 362072 kb
Host smart-c5223d7f-b322-45a0-a369-ce8c2073278a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672974808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3672974808
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.77255443
Short name T464
Test name
Test status
Simulation time 192028318679 ps
CPU time 4675.42 seconds
Started Mar 17 12:49:28 PM PDT 24
Finished Mar 17 02:07:25 PM PDT 24
Peak memory 376096 kb
Host smart-05f7259d-3822-4165-bfbd-0a1acdae0c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77255443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.sram_ctrl_stress_all.77255443
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3858953568
Short name T850
Test name
Test status
Simulation time 923750417 ps
CPU time 23.91 seconds
Started Mar 17 12:49:27 PM PDT 24
Finished Mar 17 12:49:51 PM PDT 24
Peak memory 211392 kb
Host smart-e050224e-4493-4fc3-ae46-46d0048019ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3858953568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3858953568
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2110616807
Short name T183
Test name
Test status
Simulation time 3869108403 ps
CPU time 354.11 seconds
Started Mar 17 12:49:21 PM PDT 24
Finished Mar 17 12:55:15 PM PDT 24
Peak memory 203240 kb
Host smart-dc492489-b0d2-4509-a35b-7707d711ccd0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110616807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.2110616807
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.944658351
Short name T631
Test name
Test status
Simulation time 48527691 ps
CPU time 2.25 seconds
Started Mar 17 12:49:36 PM PDT 24
Finished Mar 17 12:49:38 PM PDT 24
Peak memory 212420 kb
Host smart-f498945a-33a8-4ef8-885d-5a49233ddcac
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944658351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.944658351
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1029723131
Short name T645
Test name
Test status
Simulation time 46412214008 ps
CPU time 949.41 seconds
Started Mar 17 12:49:28 PM PDT 24
Finished Mar 17 01:05:17 PM PDT 24
Peak memory 371632 kb
Host smart-c04c74d0-6417-44bb-a68a-b48d3b11b2f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029723131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.1029723131
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.327996325
Short name T913
Test name
Test status
Simulation time 14722456 ps
CPU time 0.66 seconds
Started Mar 17 12:49:34 PM PDT 24
Finished Mar 17 12:49:35 PM PDT 24
Peak memory 202972 kb
Host smart-cde397a4-5e79-4123-9f67-22fbdc928d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327996325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.327996325
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.4016028006
Short name T323
Test name
Test status
Simulation time 2122832743 ps
CPU time 43.89 seconds
Started Mar 17 12:49:28 PM PDT 24
Finished Mar 17 12:50:12 PM PDT 24
Peak memory 203160 kb
Host smart-0b1dd3c6-39eb-4e5a-a273-e242f222626a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016028006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.4016028006
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.937741921
Short name T927
Test name
Test status
Simulation time 214867362145 ps
CPU time 1455.21 seconds
Started Mar 17 12:49:27 PM PDT 24
Finished Mar 17 01:13:43 PM PDT 24
Peak memory 367848 kb
Host smart-419822bf-bf64-464e-997e-4ef451d69899
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937741921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl
e.937741921
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.2411390436
Short name T453
Test name
Test status
Simulation time 8238036072 ps
CPU time 9.23 seconds
Started Mar 17 12:49:29 PM PDT 24
Finished Mar 17 12:49:38 PM PDT 24
Peak memory 203188 kb
Host smart-6e7c2a03-7481-46b0-b6a0-9db91a6e7fab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411390436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.2411390436
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.1440689016
Short name T149
Test name
Test status
Simulation time 131170889 ps
CPU time 102.75 seconds
Started Mar 17 12:49:28 PM PDT 24
Finished Mar 17 12:51:10 PM PDT 24
Peak memory 360524 kb
Host smart-3dc2879e-f282-4fa4-a4b8-7993017b55d5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440689016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.1440689016
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2512572306
Short name T729
Test name
Test status
Simulation time 47809659 ps
CPU time 2.57 seconds
Started Mar 17 12:49:33 PM PDT 24
Finished Mar 17 12:49:36 PM PDT 24
Peak memory 211508 kb
Host smart-be62afae-a77d-4200-ba07-457cd77f9637
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512572306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.2512572306
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.505855224
Short name T234
Test name
Test status
Simulation time 675151655 ps
CPU time 10.32 seconds
Started Mar 17 12:49:33 PM PDT 24
Finished Mar 17 12:49:43 PM PDT 24
Peak memory 203224 kb
Host smart-c8015c2f-396e-4300-ad7d-137fbf2dbb2c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505855224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl
_mem_walk.505855224
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.4146359770
Short name T595
Test name
Test status
Simulation time 5816658106 ps
CPU time 268.96 seconds
Started Mar 17 12:49:27 PM PDT 24
Finished Mar 17 12:53:56 PM PDT 24
Peak memory 360732 kb
Host smart-b2511801-620f-4a37-aefc-b6ce2839063d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146359770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.4146359770
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.2159495103
Short name T50
Test name
Test status
Simulation time 356295286 ps
CPU time 3.19 seconds
Started Mar 17 12:49:27 PM PDT 24
Finished Mar 17 12:49:31 PM PDT 24
Peak memory 210596 kb
Host smart-f9a839fa-d25b-4d91-9f89-0c2484803716
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159495103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.2159495103
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3548593209
Short name T798
Test name
Test status
Simulation time 4345967293 ps
CPU time 145.53 seconds
Started Mar 17 12:49:25 PM PDT 24
Finished Mar 17 12:51:51 PM PDT 24
Peak memory 203200 kb
Host smart-f09c2e36-e909-485e-8183-39307885a6a9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548593209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.3548593209
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.2302982319
Short name T195
Test name
Test status
Simulation time 57596989 ps
CPU time 0.76 seconds
Started Mar 17 12:49:33 PM PDT 24
Finished Mar 17 12:49:33 PM PDT 24
Peak memory 203220 kb
Host smart-dc4ea9c7-7976-4ad4-8fdf-32e9b8b48883
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302982319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2302982319
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.2510930080
Short name T287
Test name
Test status
Simulation time 2721820310 ps
CPU time 930.65 seconds
Started Mar 17 12:49:32 PM PDT 24
Finished Mar 17 01:05:03 PM PDT 24
Peak memory 358584 kb
Host smart-418e1104-6164-40a0-8008-03f95f6bdfbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510930080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2510930080
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.2513524679
Short name T374
Test name
Test status
Simulation time 257747616 ps
CPU time 62.63 seconds
Started Mar 17 12:49:27 PM PDT 24
Finished Mar 17 12:50:30 PM PDT 24
Peak memory 313520 kb
Host smart-ff3a03d1-2c27-4d34-a3d6-5936e4175d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513524679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2513524679
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.784286438
Short name T43
Test name
Test status
Simulation time 981558825 ps
CPU time 105.64 seconds
Started Mar 17 12:49:33 PM PDT 24
Finished Mar 17 12:51:19 PM PDT 24
Peak memory 363844 kb
Host smart-e53bf5c9-0bb6-4fc5-b5bd-f1e65c75f423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=784286438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.784286438
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.92831151
Short name T810
Test name
Test status
Simulation time 10739383120 ps
CPU time 245.79 seconds
Started Mar 17 12:49:27 PM PDT 24
Finished Mar 17 12:53:33 PM PDT 24
Peak memory 203224 kb
Host smart-712597e3-2ef0-4464-a94a-fa46a296f4ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92831151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_stress_pipeline.92831151
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1797958087
Short name T174
Test name
Test status
Simulation time 151664314 ps
CPU time 104.07 seconds
Started Mar 17 12:49:30 PM PDT 24
Finished Mar 17 12:51:15 PM PDT 24
Peak memory 365812 kb
Host smart-3fa960c7-0da7-4d63-8afd-643a28f17f37
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797958087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1797958087
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1165131040
Short name T367
Test name
Test status
Simulation time 12527715883 ps
CPU time 1099.78 seconds
Started Mar 17 12:49:32 PM PDT 24
Finished Mar 17 01:07:52 PM PDT 24
Peak memory 375036 kb
Host smart-4e78e7ee-8a00-47f4-996f-ee67c5b9d619
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165131040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.1165131040
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.3351252045
Short name T532
Test name
Test status
Simulation time 36675332 ps
CPU time 0.64 seconds
Started Mar 17 12:49:32 PM PDT 24
Finished Mar 17 12:49:33 PM PDT 24
Peak memory 202956 kb
Host smart-3eb13ab7-2d2d-45a5-9db9-fc8add2e4f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351252045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.3351252045
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.1663436444
Short name T152
Test name
Test status
Simulation time 12548754634 ps
CPU time 63.79 seconds
Started Mar 17 12:49:34 PM PDT 24
Finished Mar 17 12:50:39 PM PDT 24
Peak memory 203180 kb
Host smart-bc1dbc2c-abf6-4263-a0f3-e218ee3df160
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663436444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.1663436444
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.413111987
Short name T915
Test name
Test status
Simulation time 1630985621 ps
CPU time 740.61 seconds
Started Mar 17 12:49:33 PM PDT 24
Finished Mar 17 01:01:53 PM PDT 24
Peak memory 373928 kb
Host smart-b58a1c02-6916-4258-8beb-c3cf175da15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413111987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executabl
e.413111987
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.70109836
Short name T319
Test name
Test status
Simulation time 122824491 ps
CPU time 1.6 seconds
Started Mar 17 12:49:34 PM PDT 24
Finished Mar 17 12:49:36 PM PDT 24
Peak memory 203200 kb
Host smart-55cce093-d7e3-4fe7-a42f-6700084ffd03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70109836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_esca
lation.70109836
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.1956433538
Short name T359
Test name
Test status
Simulation time 303082710 ps
CPU time 23.09 seconds
Started Mar 17 12:49:31 PM PDT 24
Finished Mar 17 12:49:55 PM PDT 24
Peak memory 278168 kb
Host smart-5def7632-8a16-4d3d-b2b6-b42524bbc0db
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956433538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.1956433538
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2682557550
Short name T254
Test name
Test status
Simulation time 41696429 ps
CPU time 2.5 seconds
Started Mar 17 12:49:39 PM PDT 24
Finished Mar 17 12:49:42 PM PDT 24
Peak memory 211400 kb
Host smart-3c1a091f-01c1-4dc1-acdd-0f41c22b28f0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682557550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.2682557550
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.1395766489
Short name T377
Test name
Test status
Simulation time 1687299935 ps
CPU time 9.19 seconds
Started Mar 17 12:49:33 PM PDT 24
Finished Mar 17 12:49:42 PM PDT 24
Peak memory 203196 kb
Host smart-1d168801-4b93-43d1-9ebd-88462147e21a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395766489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.1395766489
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.2468981212
Short name T736
Test name
Test status
Simulation time 4643422863 ps
CPU time 984.58 seconds
Started Mar 17 12:49:34 PM PDT 24
Finished Mar 17 01:05:59 PM PDT 24
Peak memory 372924 kb
Host smart-41826001-b4ba-402d-b4a1-8c69d6ccb8dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468981212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.2468981212
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.463587486
Short name T783
Test name
Test status
Simulation time 103982674 ps
CPU time 4.5 seconds
Started Mar 17 12:49:33 PM PDT 24
Finished Mar 17 12:49:38 PM PDT 24
Peak memory 203120 kb
Host smart-e94a1aca-c4e0-400d-a19a-d8aff558d6ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463587486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.s
ram_ctrl_partial_access.463587486
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.121161583
Short name T486
Test name
Test status
Simulation time 25122575135 ps
CPU time 160.65 seconds
Started Mar 17 12:49:32 PM PDT 24
Finished Mar 17 12:52:13 PM PDT 24
Peak memory 203240 kb
Host smart-7ce58aa7-4f04-4565-8a5e-21161c176fc3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121161583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.sram_ctrl_partial_access_b2b.121161583
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.1202244241
Short name T214
Test name
Test status
Simulation time 90069714 ps
CPU time 0.75 seconds
Started Mar 17 12:49:34 PM PDT 24
Finished Mar 17 12:49:35 PM PDT 24
Peak memory 203216 kb
Host smart-40141ecc-e9f6-414d-bc3a-10a8a0775508
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202244241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1202244241
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.198515588
Short name T877
Test name
Test status
Simulation time 25855627818 ps
CPU time 923.44 seconds
Started Mar 17 12:49:33 PM PDT 24
Finished Mar 17 01:04:57 PM PDT 24
Peak memory 373740 kb
Host smart-6ea791db-0e31-49b3-9529-e39de8fdd5c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198515588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.198515588
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.3171397965
Short name T204
Test name
Test status
Simulation time 2647418089 ps
CPU time 76.51 seconds
Started Mar 17 12:49:33 PM PDT 24
Finished Mar 17 12:50:50 PM PDT 24
Peak memory 366332 kb
Host smart-dc3a3ce7-6891-425a-bb3f-d2a5e34e71b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171397965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3171397965
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.3251011471
Short name T368
Test name
Test status
Simulation time 155305584942 ps
CPU time 2911.67 seconds
Started Mar 17 12:49:30 PM PDT 24
Finished Mar 17 01:38:02 PM PDT 24
Peak memory 375096 kb
Host smart-e8ddfd79-62b5-4b80-bbec-56dd8ec4d6f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251011471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.3251011471
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1371074424
Short name T762
Test name
Test status
Simulation time 237952331 ps
CPU time 16.3 seconds
Started Mar 17 12:49:32 PM PDT 24
Finished Mar 17 12:49:48 PM PDT 24
Peak memory 211424 kb
Host smart-d717795e-ffa7-4f37-b723-ae6c95f7695c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1371074424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1371074424
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2489892212
Short name T495
Test name
Test status
Simulation time 7261790043 ps
CPU time 331.71 seconds
Started Mar 17 12:49:34 PM PDT 24
Finished Mar 17 12:55:07 PM PDT 24
Peak memory 203252 kb
Host smart-5c19f36c-09e4-4d2e-b582-e4d693112467
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489892212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.2489892212
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2313799344
Short name T666
Test name
Test status
Simulation time 371090071 ps
CPU time 23.04 seconds
Started Mar 17 12:49:34 PM PDT 24
Finished Mar 17 12:49:57 PM PDT 24
Peak memory 285020 kb
Host smart-6eb2faa1-b5c2-4d55-be32-aa26327cd088
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313799344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2313799344
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2009568882
Short name T78
Test name
Test status
Simulation time 2008997310 ps
CPU time 145.55 seconds
Started Mar 17 12:46:45 PM PDT 24
Finished Mar 17 12:49:11 PM PDT 24
Peak memory 373096 kb
Host smart-acdc251e-63b4-40bc-afd1-558552600fac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009568882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.2009568882
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.1708738275
Short name T657
Test name
Test status
Simulation time 11045397 ps
CPU time 0.62 seconds
Started Mar 17 12:47:14 PM PDT 24
Finished Mar 17 12:47:15 PM PDT 24
Peak memory 202904 kb
Host smart-1f3a5b56-8565-448f-bb6d-2e683573438b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708738275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.1708738275
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.1059531566
Short name T182
Test name
Test status
Simulation time 800212544 ps
CPU time 36.64 seconds
Started Mar 17 12:47:02 PM PDT 24
Finished Mar 17 12:47:39 PM PDT 24
Peak memory 203132 kb
Host smart-d5969e8e-4005-493f-8ac4-41fc0673fd28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059531566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
1059531566
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.3419298624
Short name T770
Test name
Test status
Simulation time 11698077071 ps
CPU time 948 seconds
Started Mar 17 12:47:03 PM PDT 24
Finished Mar 17 01:02:51 PM PDT 24
Peak memory 374164 kb
Host smart-fc877126-5092-4348-9ec4-872317f0eaf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419298624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.3419298624
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.351809053
Short name T787
Test name
Test status
Simulation time 813455807 ps
CPU time 8.66 seconds
Started Mar 17 12:47:13 PM PDT 24
Finished Mar 17 12:47:23 PM PDT 24
Peak memory 203148 kb
Host smart-f42cb9d2-4a24-4545-82d9-e90757457295
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351809053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esca
lation.351809053
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.2054998547
Short name T711
Test name
Test status
Simulation time 491596566 ps
CPU time 111.76 seconds
Started Mar 17 12:46:59 PM PDT 24
Finished Mar 17 12:48:51 PM PDT 24
Peak memory 370720 kb
Host smart-e760dcf4-8d10-4d6d-b528-e14401c50511
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054998547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.2054998547
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4083010017
Short name T886
Test name
Test status
Simulation time 366243230 ps
CPU time 2.77 seconds
Started Mar 17 12:47:00 PM PDT 24
Finished Mar 17 12:47:03 PM PDT 24
Peak memory 211348 kb
Host smart-c47c1cf7-de54-4b67-8787-9d2b717a3a79
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083010017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.4083010017
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.389339902
Short name T172
Test name
Test status
Simulation time 337159819 ps
CPU time 5.32 seconds
Started Mar 17 12:46:55 PM PDT 24
Finished Mar 17 12:47:01 PM PDT 24
Peak memory 203120 kb
Host smart-186cabdf-7391-47f8-baa8-2b594876950d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389339902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_
mem_walk.389339902
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.223300565
Short name T676
Test name
Test status
Simulation time 2820470275 ps
CPU time 779.81 seconds
Started Mar 17 12:46:56 PM PDT 24
Finished Mar 17 12:59:56 PM PDT 24
Peak memory 373964 kb
Host smart-5e00ae42-44cc-4d8e-8ed8-1492937c245a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223300565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl
e_keys.223300565
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.3496740488
Short name T698
Test name
Test status
Simulation time 511077218 ps
CPU time 54.99 seconds
Started Mar 17 12:47:15 PM PDT 24
Finished Mar 17 12:48:11 PM PDT 24
Peak memory 328376 kb
Host smart-6c3012cd-0a29-4f77-a375-1163f3793561
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496740488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.3496740488
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2408453383
Short name T141
Test name
Test status
Simulation time 16218192531 ps
CPU time 346.98 seconds
Started Mar 17 12:46:55 PM PDT 24
Finished Mar 17 12:52:47 PM PDT 24
Peak memory 203156 kb
Host smart-823f17a2-e505-408b-ac27-8d6f529e5eab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408453383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.2408453383
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.1485622750
Short name T778
Test name
Test status
Simulation time 25828716 ps
CPU time 0.76 seconds
Started Mar 17 12:46:57 PM PDT 24
Finished Mar 17 12:46:58 PM PDT 24
Peak memory 203128 kb
Host smart-85f4f2fb-24fc-44cb-8831-70f79d30a4ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485622750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1485622750
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.3221040808
Short name T882
Test name
Test status
Simulation time 63624760249 ps
CPU time 656.15 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:58:17 PM PDT 24
Peak memory 368064 kb
Host smart-d1d658b2-bb78-44b6-89c3-bb3f4e3403b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221040808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3221040808
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.2111565824
Short name T268
Test name
Test status
Simulation time 62436627 ps
CPU time 1.56 seconds
Started Mar 17 12:46:47 PM PDT 24
Finished Mar 17 12:46:49 PM PDT 24
Peak memory 203096 kb
Host smart-d043c182-72ba-47cf-8a03-1b2e55d8c4f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111565824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2111565824
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2058873063
Short name T111
Test name
Test status
Simulation time 2958766425 ps
CPU time 60.38 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:48:25 PM PDT 24
Peak memory 293228 kb
Host smart-aa936bae-5792-4c13-ab25-ab1fa4deb475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2058873063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2058873063
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3784915983
Short name T834
Test name
Test status
Simulation time 2584677233 ps
CPU time 242.59 seconds
Started Mar 17 12:47:17 PM PDT 24
Finished Mar 17 12:51:20 PM PDT 24
Peak memory 203224 kb
Host smart-cddf4034-e267-4fcc-8c3f-55851b6b6d55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784915983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.3784915983
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.981199987
Short name T849
Test name
Test status
Simulation time 441422174 ps
CPU time 34.83 seconds
Started Mar 17 12:47:06 PM PDT 24
Finished Mar 17 12:47:41 PM PDT 24
Peak memory 293716 kb
Host smart-43a9bc83-505b-45b9-accd-6e92bceb8eb2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981199987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.981199987
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3124322376
Short name T734
Test name
Test status
Simulation time 21244197039 ps
CPU time 789.38 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 01:00:33 PM PDT 24
Peak memory 367712 kb
Host smart-bd728c06-7e2d-4f9b-8f55-64e8b8257295
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124322376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.3124322376
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.3012512795
Short name T912
Test name
Test status
Simulation time 31641863 ps
CPU time 0.61 seconds
Started Mar 17 12:47:08 PM PDT 24
Finished Mar 17 12:47:08 PM PDT 24
Peak memory 202872 kb
Host smart-fe5203f1-9372-469c-831b-76c00aaad14e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012512795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.3012512795
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.583028659
Short name T328
Test name
Test status
Simulation time 1592158364 ps
CPU time 24.3 seconds
Started Mar 17 12:47:14 PM PDT 24
Finished Mar 17 12:47:38 PM PDT 24
Peak memory 203156 kb
Host smart-b6cd4e75-2011-4f9f-85f6-82dd63d0f951
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583028659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.583028659
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.1011827385
Short name T249
Test name
Test status
Simulation time 6097832488 ps
CPU time 494.99 seconds
Started Mar 17 12:47:02 PM PDT 24
Finished Mar 17 12:55:18 PM PDT 24
Peak memory 366380 kb
Host smart-6a9a4dad-00eb-4c8f-b4ff-1e1880b2bb90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011827385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.1011827385
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.4074371620
Short name T841
Test name
Test status
Simulation time 2766934917 ps
CPU time 3.56 seconds
Started Mar 17 12:47:16 PM PDT 24
Finished Mar 17 12:47:20 PM PDT 24
Peak memory 203268 kb
Host smart-e70dc101-fa33-487d-9455-bd38a4a9337e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074371620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.4074371620
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.1811787682
Short name T217
Test name
Test status
Simulation time 417259836 ps
CPU time 28.69 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:47:54 PM PDT 24
Peak memory 284952 kb
Host smart-23126d3c-a218-430d-aff3-af55ae8d4213
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811787682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.1811787682
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1044234784
Short name T421
Test name
Test status
Simulation time 44214223 ps
CPU time 2.48 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 12:47:03 PM PDT 24
Peak memory 211376 kb
Host smart-e5ffe2d6-6e9b-4553-9bce-edd484e9d41f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044234784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.1044234784
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3011251522
Short name T225
Test name
Test status
Simulation time 1444254795 ps
CPU time 5.56 seconds
Started Mar 17 12:46:58 PM PDT 24
Finished Mar 17 12:47:04 PM PDT 24
Peak memory 203132 kb
Host smart-20e65f43-eccc-42a1-8d6f-7602daa5a26d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011251522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3011251522
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.3146549206
Short name T763
Test name
Test status
Simulation time 15850382535 ps
CPU time 993.35 seconds
Started Mar 17 12:47:00 PM PDT 24
Finished Mar 17 01:03:33 PM PDT 24
Peak memory 372088 kb
Host smart-3c19bb37-b205-4add-9c8b-8bf176609678
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146549206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.3146549206
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.505374502
Short name T49
Test name
Test status
Simulation time 91292688 ps
CPU time 12.57 seconds
Started Mar 17 12:47:04 PM PDT 24
Finished Mar 17 12:47:16 PM PDT 24
Peak memory 257572 kb
Host smart-042d5461-c2ed-4f1f-a9d8-cdc75b265f6a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505374502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr
am_ctrl_partial_access.505374502
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1495716744
Short name T938
Test name
Test status
Simulation time 13006287610 ps
CPU time 288.27 seconds
Started Mar 17 12:47:00 PM PDT 24
Finished Mar 17 12:51:48 PM PDT 24
Peak memory 203228 kb
Host smart-2b78f1fc-c245-4f25-9089-b68413961456
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495716744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.1495716744
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.2567200172
Short name T690
Test name
Test status
Simulation time 89559109 ps
CPU time 0.75 seconds
Started Mar 17 12:47:16 PM PDT 24
Finished Mar 17 12:47:18 PM PDT 24
Peak memory 203264 kb
Host smart-40dc04ff-186c-4440-ad24-49035bf3032f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567200172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2567200172
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.3085309449
Short name T578
Test name
Test status
Simulation time 76018996582 ps
CPU time 662.35 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 12:58:03 PM PDT 24
Peak memory 351424 kb
Host smart-2b7383fd-80f1-4d46-b473-d51dcd430873
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085309449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3085309449
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.4208512444
Short name T463
Test name
Test status
Simulation time 542635928 ps
CPU time 9.41 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:47:30 PM PDT 24
Peak memory 203116 kb
Host smart-8d48be3c-9840-41c7-ac8e-37cb2d36a395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208512444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.4208512444
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.2993870603
Short name T812
Test name
Test status
Simulation time 48111026688 ps
CPU time 3056.96 seconds
Started Mar 17 12:47:10 PM PDT 24
Finished Mar 17 01:38:07 PM PDT 24
Peak memory 376904 kb
Host smart-2c230a6a-a2b9-43c7-8d49-208f8952c225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993870603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.2993870603
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1352209495
Short name T519
Test name
Test status
Simulation time 2758963138 ps
CPU time 159.11 seconds
Started Mar 17 12:47:15 PM PDT 24
Finished Mar 17 12:49:55 PM PDT 24
Peak memory 302420 kb
Host smart-0056d160-4b57-4bf1-84cf-99a0c7ec9861
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1352209495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1352209495
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.747266886
Short name T900
Test name
Test status
Simulation time 3829199710 ps
CPU time 177.26 seconds
Started Mar 17 12:47:07 PM PDT 24
Finished Mar 17 12:50:04 PM PDT 24
Peak memory 203284 kb
Host smart-f0411016-9761-45dd-9835-17221265bcf8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747266886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
sram_ctrl_stress_pipeline.747266886
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.794521929
Short name T621
Test name
Test status
Simulation time 658246263 ps
CPU time 45.72 seconds
Started Mar 17 12:46:58 PM PDT 24
Finished Mar 17 12:47:44 PM PDT 24
Peak memory 309064 kb
Host smart-1282b30b-a539-4def-b7d1-036623643f7d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794521929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.794521929
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3374509090
Short name T300
Test name
Test status
Simulation time 1210417378 ps
CPU time 431.75 seconds
Started Mar 17 12:47:15 PM PDT 24
Finished Mar 17 12:54:28 PM PDT 24
Peak memory 372496 kb
Host smart-5b225f40-e80d-4618-8aac-5b9aacd7733b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374509090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.3374509090
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.880823195
Short name T586
Test name
Test status
Simulation time 22449463 ps
CPU time 0.64 seconds
Started Mar 17 12:47:14 PM PDT 24
Finished Mar 17 12:47:15 PM PDT 24
Peak memory 202944 kb
Host smart-243e365e-554b-477c-9a1a-0747d79e224c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880823195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.880823195
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.1195012680
Short name T146
Test name
Test status
Simulation time 702247618 ps
CPU time 45.26 seconds
Started Mar 17 12:46:59 PM PDT 24
Finished Mar 17 12:47:45 PM PDT 24
Peak memory 203092 kb
Host smart-420f912f-399f-405f-91a8-959ad2b636cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195012680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
1195012680
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.2857610188
Short name T136
Test name
Test status
Simulation time 19130715693 ps
CPU time 638.82 seconds
Started Mar 17 12:46:59 PM PDT 24
Finished Mar 17 12:57:39 PM PDT 24
Peak memory 336356 kb
Host smart-53cdc26a-fe45-4525-b6bc-a4981f0213ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857610188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl
e.2857610188
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.1552754587
Short name T189
Test name
Test status
Simulation time 374283966 ps
CPU time 4.42 seconds
Started Mar 17 12:47:02 PM PDT 24
Finished Mar 17 12:47:07 PM PDT 24
Peak memory 203088 kb
Host smart-94848e81-a162-41c9-b127-b3501e7ce040
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552754587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.1552754587
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.628283346
Short name T536
Test name
Test status
Simulation time 140939114 ps
CPU time 115.18 seconds
Started Mar 17 12:47:03 PM PDT 24
Finished Mar 17 12:48:58 PM PDT 24
Peak memory 369652 kb
Host smart-ddb16906-f7d0-4514-87ba-5598f7613fd2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628283346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.sram_ctrl_max_throughput.628283346
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1406021794
Short name T241
Test name
Test status
Simulation time 347748851 ps
CPU time 2.88 seconds
Started Mar 17 12:47:08 PM PDT 24
Finished Mar 17 12:47:11 PM PDT 24
Peak memory 211372 kb
Host smart-f529c0e0-56f4-42b0-ad68-df64f0610c65
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406021794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.1406021794
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.1896284977
Short name T442
Test name
Test status
Simulation time 76024797 ps
CPU time 4.45 seconds
Started Mar 17 12:47:12 PM PDT 24
Finished Mar 17 12:47:16 PM PDT 24
Peak memory 203204 kb
Host smart-1eba6ce3-5815-4825-bf12-a554708740ea
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896284977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.1896284977
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.2025821451
Short name T908
Test name
Test status
Simulation time 66043300357 ps
CPU time 1381.44 seconds
Started Mar 17 12:47:00 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 375888 kb
Host smart-86feaf1e-0cbf-4a6e-9f87-5593bd628229
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025821451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.2025821451
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.3553423180
Short name T781
Test name
Test status
Simulation time 2333854234 ps
CPU time 44.36 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:48:05 PM PDT 24
Peak memory 310908 kb
Host smart-0e754670-f872-4409-971b-1864745fed99
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553423180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.3553423180
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3723772026
Short name T483
Test name
Test status
Simulation time 80405972298 ps
CPU time 463.32 seconds
Started Mar 17 12:47:07 PM PDT 24
Finished Mar 17 12:54:50 PM PDT 24
Peak memory 203240 kb
Host smart-a2753887-1c70-4eb9-96ee-12a4eae3e643
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723772026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.3723772026
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3591228731
Short name T413
Test name
Test status
Simulation time 40037289 ps
CPU time 0.75 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:47:22 PM PDT 24
Peak memory 203124 kb
Host smart-450c6d45-f64d-49d6-b887-f60068608d38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591228731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3591228731
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.243778892
Short name T827
Test name
Test status
Simulation time 99236572149 ps
CPU time 799.35 seconds
Started Mar 17 12:47:14 PM PDT 24
Finished Mar 17 01:00:34 PM PDT 24
Peak memory 374712 kb
Host smart-83c59d7e-c170-4f6b-a775-bd606bd797dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243778892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.243778892
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.4060569073
Short name T784
Test name
Test status
Simulation time 676891453 ps
CPU time 7.36 seconds
Started Mar 17 12:47:01 PM PDT 24
Finished Mar 17 12:47:09 PM PDT 24
Peak memory 233720 kb
Host smart-d887e328-a513-4409-8507-0570cc5dd864
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060569073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.4060569073
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.2798146840
Short name T223
Test name
Test status
Simulation time 17032707300 ps
CPU time 1236.87 seconds
Started Mar 17 12:47:08 PM PDT 24
Finished Mar 17 01:07:45 PM PDT 24
Peak memory 370948 kb
Host smart-5411db19-ea3d-4561-a829-492355ee95cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798146840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.2798146840
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.545460254
Short name T919
Test name
Test status
Simulation time 770354368 ps
CPU time 238.99 seconds
Started Mar 17 12:47:07 PM PDT 24
Finished Mar 17 12:51:06 PM PDT 24
Peak memory 350568 kb
Host smart-381ab4cb-9713-4f0e-af4c-e23be7d88db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=545460254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.545460254
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1087408481
Short name T198
Test name
Test status
Simulation time 2879760454 ps
CPU time 259.83 seconds
Started Mar 17 12:47:05 PM PDT 24
Finished Mar 17 12:51:25 PM PDT 24
Peak memory 203288 kb
Host smart-c84b0b8d-0456-4674-bd14-d9ed9a2f98e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087408481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.1087408481
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2322539261
Short name T507
Test name
Test status
Simulation time 228417168 ps
CPU time 6.43 seconds
Started Mar 17 12:47:05 PM PDT 24
Finished Mar 17 12:47:12 PM PDT 24
Peak memory 235852 kb
Host smart-ac1e94ca-7d27-4dc2-b7c3-731809150e1d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322539261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2322539261
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.879828043
Short name T396
Test name
Test status
Simulation time 3912062898 ps
CPU time 1145.65 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 01:06:27 PM PDT 24
Peak memory 375100 kb
Host smart-f9f6be07-2d3d-4053-a0a9-93d1609a2998
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879828043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.sram_ctrl_access_during_key_req.879828043
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.1557779728
Short name T273
Test name
Test status
Simulation time 103534867 ps
CPU time 0.65 seconds
Started Mar 17 12:47:11 PM PDT 24
Finished Mar 17 12:47:12 PM PDT 24
Peak memory 202952 kb
Host smart-7204d968-7ce9-4778-ad16-eae4b3f56eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557779728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.1557779728
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.3405466620
Short name T11
Test name
Test status
Simulation time 1228077274 ps
CPU time 19.31 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:47:39 PM PDT 24
Peak memory 203108 kb
Host smart-e0d171b3-2455-4a36-b460-4b191d69ef81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405466620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
3405466620
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.3795614299
Short name T842
Test name
Test status
Simulation time 1305149006 ps
CPU time 6.42 seconds
Started Mar 17 12:47:03 PM PDT 24
Finished Mar 17 12:47:10 PM PDT 24
Peak memory 203188 kb
Host smart-cf61b906-95b0-46ee-9e2a-e3b494e69bda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795614299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.3795614299
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.824096595
Short name T203
Test name
Test status
Simulation time 108235582 ps
CPU time 59.7 seconds
Started Mar 17 12:47:00 PM PDT 24
Finished Mar 17 12:48:00 PM PDT 24
Peak memory 326872 kb
Host smart-cc1d4485-3c03-4151-854c-2dff113d69cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824096595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.sram_ctrl_max_throughput.824096595
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.962799620
Short name T667
Test name
Test status
Simulation time 143929747 ps
CPU time 4.34 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:47:29 PM PDT 24
Peak memory 211436 kb
Host smart-ea2e94d0-987c-48c3-ad36-748e9d228ec4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962799620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
sram_ctrl_mem_partial_access.962799620
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.50452316
Short name T604
Test name
Test status
Simulation time 345455347 ps
CPU time 5.63 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 12:47:26 PM PDT 24
Peak memory 203192 kb
Host smart-9b39c7d9-3ed1-4240-b386-9bffe654f7a1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50452316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_m
em_walk.50452316
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.17760315
Short name T484
Test name
Test status
Simulation time 48176161049 ps
CPU time 769.25 seconds
Started Mar 17 12:47:15 PM PDT 24
Finished Mar 17 01:00:05 PM PDT 24
Peak memory 375780 kb
Host smart-c3af678a-8e3e-4a0c-98fb-c549df12325e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17760315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple
_keys.17760315
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.3821871176
Short name T441
Test name
Test status
Simulation time 517739185 ps
CPU time 4.85 seconds
Started Mar 17 12:47:02 PM PDT 24
Finished Mar 17 12:47:07 PM PDT 24
Peak memory 219640 kb
Host smart-62e17c6e-d0b1-467c-b9e7-61c2abe06f04
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821871176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.3821871176
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4216563142
Short name T227
Test name
Test status
Simulation time 7017244352 ps
CPU time 194.13 seconds
Started Mar 17 12:47:03 PM PDT 24
Finished Mar 17 12:50:17 PM PDT 24
Peak memory 203280 kb
Host smart-304c7fec-3ac9-4759-aebe-86e92b597210
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216563142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.4216563142
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.896398332
Short name T874
Test name
Test status
Simulation time 19616452195 ps
CPU time 1489.73 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 01:12:09 PM PDT 24
Peak memory 372024 kb
Host smart-3b23d8a7-cbee-4a09-8dda-f5079b1788ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896398332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.896398332
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.3913864485
Short name T66
Test name
Test status
Simulation time 188761643 ps
CPU time 8.18 seconds
Started Mar 17 12:47:04 PM PDT 24
Finished Mar 17 12:47:13 PM PDT 24
Peak memory 234856 kb
Host smart-3f8cff13-249b-4541-b8dc-7de534ac691c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913864485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3913864485
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.4203054942
Short name T393
Test name
Test status
Simulation time 161009874179 ps
CPU time 3746.81 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 01:49:50 PM PDT 24
Peak memory 383256 kb
Host smart-2331ebf7-f770-46e3-a5c1-7b89fd18820b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203054942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.4203054942
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3123482529
Short name T47
Test name
Test status
Simulation time 5927618177 ps
CPU time 34.37 seconds
Started Mar 17 12:47:23 PM PDT 24
Finished Mar 17 12:47:59 PM PDT 24
Peak memory 212528 kb
Host smart-b14a3af4-6c52-433c-818f-7cb0ddce71d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3123482529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3123482529
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.4036169298
Short name T397
Test name
Test status
Simulation time 5154187601 ps
CPU time 244.15 seconds
Started Mar 17 12:47:14 PM PDT 24
Finished Mar 17 12:51:18 PM PDT 24
Peak memory 203256 kb
Host smart-393a0089-0faf-4773-a004-c995381d317e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036169298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.4036169298
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.674924403
Short name T846
Test name
Test status
Simulation time 540925349 ps
CPU time 47.16 seconds
Started Mar 17 12:47:17 PM PDT 24
Finished Mar 17 12:48:06 PM PDT 24
Peak memory 328660 kb
Host smart-78c70ef1-6371-4701-81df-b66ec7c03951
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674924403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_throughput_w_partial_write.674924403
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.4171742665
Short name T617
Test name
Test status
Simulation time 12769292750 ps
CPU time 844.57 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 01:01:28 PM PDT 24
Peak memory 368776 kb
Host smart-58edd20a-efbc-4c36-ab76-8c6069e26bc4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171742665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.4171742665
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.3878787007
Short name T348
Test name
Test status
Simulation time 77263761 ps
CPU time 0.63 seconds
Started Mar 17 12:47:24 PM PDT 24
Finished Mar 17 12:47:25 PM PDT 24
Peak memory 202144 kb
Host smart-0a9ba4f7-6428-46bc-88fb-c679344cec07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878787007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.3878787007
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.465746217
Short name T921
Test name
Test status
Simulation time 5941326231 ps
CPU time 28.48 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:47:51 PM PDT 24
Peak memory 203172 kb
Host smart-986f254a-4e46-4806-bcb5-6bf816c3dcd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465746217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.465746217
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.1793707668
Short name T756
Test name
Test status
Simulation time 22680578045 ps
CPU time 998.7 seconds
Started Mar 17 12:47:18 PM PDT 24
Finished Mar 17 01:03:58 PM PDT 24
Peak memory 369812 kb
Host smart-0517e7b8-1987-440d-9374-d0d2b1aa695d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793707668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.1793707668
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.2144833868
Short name T704
Test name
Test status
Simulation time 1217213538 ps
CPU time 3.99 seconds
Started Mar 17 12:47:12 PM PDT 24
Finished Mar 17 12:47:17 PM PDT 24
Peak memory 203116 kb
Host smart-f7e71f28-168c-4b74-ba28-c824012e7a25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144833868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.2144833868
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.4053637765
Short name T176
Test name
Test status
Simulation time 163690280 ps
CPU time 3.18 seconds
Started Mar 17 12:47:13 PM PDT 24
Finished Mar 17 12:47:16 PM PDT 24
Peak memory 219564 kb
Host smart-faf9b415-029d-44f1-bd51-5c3aad6a9f8e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053637765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.4053637765
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.660882831
Short name T344
Test name
Test status
Simulation time 62142818 ps
CPU time 4.48 seconds
Started Mar 17 12:47:11 PM PDT 24
Finished Mar 17 12:47:16 PM PDT 24
Peak memory 211436 kb
Host smart-e2ad0b04-47bb-40c5-a280-60fb612b9405
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660882831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_mem_partial_access.660882831
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.3646503639
Short name T294
Test name
Test status
Simulation time 139024956 ps
CPU time 4.21 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:27 PM PDT 24
Peak memory 203200 kb
Host smart-672d5722-a1cf-42a1-9847-4be73dd34d0b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646503639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.3646503639
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.3538753664
Short name T632
Test name
Test status
Simulation time 1848293449 ps
CPU time 527.47 seconds
Started Mar 17 12:47:19 PM PDT 24
Finished Mar 17 12:56:09 PM PDT 24
Peak memory 371972 kb
Host smart-a364459c-ea47-486b-98a6-5e64df7214a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538753664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.3538753664
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.1498484006
Short name T166
Test name
Test status
Simulation time 135109120 ps
CPU time 19.38 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:47:45 PM PDT 24
Peak memory 272128 kb
Host smart-f0d6fa84-05e8-4f5c-afe1-fc23d81cde8b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498484006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.1498484006
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.923557505
Short name T144
Test name
Test status
Simulation time 11695175219 ps
CPU time 255.2 seconds
Started Mar 17 12:47:26 PM PDT 24
Finished Mar 17 12:51:41 PM PDT 24
Peak memory 203276 kb
Host smart-f77ab8d4-4701-4c89-95b8-7e36238ceaba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923557505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.sram_ctrl_partial_access_b2b.923557505
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.2298478905
Short name T889
Test name
Test status
Simulation time 30071498 ps
CPU time 0.74 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 12:47:24 PM PDT 24
Peak memory 203448 kb
Host smart-d652c059-81c7-494e-95d7-b1a5ece87ad1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298478905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2298478905
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.1632078309
Short name T863
Test name
Test status
Simulation time 65317030851 ps
CPU time 677.32 seconds
Started Mar 17 12:48:54 PM PDT 24
Finished Mar 17 01:00:12 PM PDT 24
Peak memory 363996 kb
Host smart-d0083e1e-aae0-432a-8012-7d23d22a6ab6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632078309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1632078309
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.2077477644
Short name T685
Test name
Test status
Simulation time 1052588306 ps
CPU time 10.79 seconds
Started Mar 17 12:47:13 PM PDT 24
Finished Mar 17 12:47:25 PM PDT 24
Peak memory 203168 kb
Host smart-006d4ed6-d160-41df-a144-4de5b92054de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077477644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2077477644
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.3438891006
Short name T310
Test name
Test status
Simulation time 43171973612 ps
CPU time 852.64 seconds
Started Mar 17 12:47:21 PM PDT 24
Finished Mar 17 01:01:36 PM PDT 24
Peak memory 363856 kb
Host smart-b6ce4655-c37b-4dcf-9029-ffba96844f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438891006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.3438891006
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4091939055
Short name T29
Test name
Test status
Simulation time 2444207420 ps
CPU time 186.02 seconds
Started Mar 17 12:47:20 PM PDT 24
Finished Mar 17 12:50:28 PM PDT 24
Peak memory 380160 kb
Host smart-b71814e2-68a0-41ba-a256-1871e058e4c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4091939055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.4091939055
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.256096966
Short name T933
Test name
Test status
Simulation time 2158277430 ps
CPU time 202.13 seconds
Started Mar 17 12:47:22 PM PDT 24
Finished Mar 17 12:50:46 PM PDT 24
Peak memory 203248 kb
Host smart-08116e0e-22aa-466c-aafc-e11c288f36db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256096966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_stress_pipeline.256096966
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.677710413
Short name T782
Test name
Test status
Simulation time 378896660 ps
CPU time 26.84 seconds
Started Mar 17 12:47:05 PM PDT 24
Finished Mar 17 12:47:32 PM PDT 24
Peak memory 293760 kb
Host smart-2d520ab6-0f9a-4355-9cfd-bede3072cbed
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677710413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_throughput_w_partial_write.677710413
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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