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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.81 97.10 100.00 100.00 98.58 99.70 98.52


Total test records in report: 1032
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T801 /workspace/coverage/default/7.sram_ctrl_lc_escalation.2774731220 Mar 24 01:17:20 PM PDT 24 Mar 24 01:17:24 PM PDT 24 1536145772 ps
T802 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1385953057 Mar 24 01:18:36 PM PDT 24 Mar 24 01:25:33 PM PDT 24 74750414843 ps
T803 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2704948131 Mar 24 01:17:25 PM PDT 24 Mar 24 01:21:55 PM PDT 24 780240576 ps
T804 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1118087058 Mar 24 01:18:27 PM PDT 24 Mar 24 01:24:01 PM PDT 24 6167571790 ps
T805 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1011842150 Mar 24 01:18:23 PM PDT 24 Mar 24 01:25:11 PM PDT 24 31402713678 ps
T806 /workspace/coverage/default/12.sram_ctrl_mem_walk.1553457788 Mar 24 01:17:26 PM PDT 24 Mar 24 01:17:36 PM PDT 24 902090526 ps
T807 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4144524507 Mar 24 01:20:06 PM PDT 24 Mar 24 01:35:01 PM PDT 24 7683706179 ps
T808 /workspace/coverage/default/36.sram_ctrl_partial_access.1756822715 Mar 24 01:18:53 PM PDT 24 Mar 24 01:18:57 PM PDT 24 185015420 ps
T809 /workspace/coverage/default/30.sram_ctrl_mem_walk.776143456 Mar 24 01:18:28 PM PDT 24 Mar 24 01:18:33 PM PDT 24 83973224 ps
T810 /workspace/coverage/default/41.sram_ctrl_bijection.2870897325 Mar 24 01:19:21 PM PDT 24 Mar 24 01:20:19 PM PDT 24 1252460025 ps
T811 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2228395204 Mar 24 01:19:37 PM PDT 24 Mar 24 01:22:11 PM PDT 24 4416261696 ps
T812 /workspace/coverage/default/43.sram_ctrl_ram_cfg.205752134 Mar 24 01:19:27 PM PDT 24 Mar 24 01:19:28 PM PDT 24 88108004 ps
T813 /workspace/coverage/default/25.sram_ctrl_smoke.1813658048 Mar 24 01:18:09 PM PDT 24 Mar 24 01:18:17 PM PDT 24 250581562 ps
T814 /workspace/coverage/default/35.sram_ctrl_multiple_keys.1214137176 Mar 24 01:18:58 PM PDT 24 Mar 24 01:27:58 PM PDT 24 10427905821 ps
T815 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2688775135 Mar 24 01:16:45 PM PDT 24 Mar 24 01:19:18 PM PDT 24 1909245796 ps
T816 /workspace/coverage/default/33.sram_ctrl_ram_cfg.3406337571 Mar 24 01:18:45 PM PDT 24 Mar 24 01:18:46 PM PDT 24 31953811 ps
T817 /workspace/coverage/default/26.sram_ctrl_multiple_keys.2925109905 Mar 24 01:18:14 PM PDT 24 Mar 24 01:37:26 PM PDT 24 17078494306 ps
T818 /workspace/coverage/default/30.sram_ctrl_executable.578099909 Mar 24 01:18:29 PM PDT 24 Mar 24 01:35:22 PM PDT 24 45374926469 ps
T819 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3651181391 Mar 24 01:18:11 PM PDT 24 Mar 24 01:19:49 PM PDT 24 266005659 ps
T820 /workspace/coverage/default/49.sram_ctrl_max_throughput.2440954418 Mar 24 01:20:08 PM PDT 24 Mar 24 01:20:27 PM PDT 24 81519725 ps
T821 /workspace/coverage/default/4.sram_ctrl_stress_all.3574412855 Mar 24 01:17:10 PM PDT 24 Mar 24 01:57:18 PM PDT 24 35102311880 ps
T822 /workspace/coverage/default/22.sram_ctrl_max_throughput.2107175188 Mar 24 01:18:04 PM PDT 24 Mar 24 01:18:06 PM PDT 24 45834540 ps
T823 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.4008256438 Mar 24 01:17:13 PM PDT 24 Mar 24 01:17:16 PM PDT 24 87118986 ps
T824 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1003229968 Mar 24 01:17:01 PM PDT 24 Mar 24 01:17:42 PM PDT 24 609961058 ps
T825 /workspace/coverage/default/33.sram_ctrl_multiple_keys.1892711888 Mar 24 01:18:46 PM PDT 24 Mar 24 01:40:25 PM PDT 24 3498273075 ps
T826 /workspace/coverage/default/29.sram_ctrl_executable.2579812769 Mar 24 01:18:24 PM PDT 24 Mar 24 01:26:43 PM PDT 24 3406677246 ps
T827 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3690951244 Mar 24 01:19:49 PM PDT 24 Mar 24 01:26:23 PM PDT 24 46637653093 ps
T828 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1789446260 Mar 24 01:18:59 PM PDT 24 Mar 24 01:24:38 PM PDT 24 14068765350 ps
T829 /workspace/coverage/default/48.sram_ctrl_multiple_keys.2051693070 Mar 24 01:19:52 PM PDT 24 Mar 24 01:20:15 PM PDT 24 3781331694 ps
T830 /workspace/coverage/default/18.sram_ctrl_bijection.2549818755 Mar 24 01:17:42 PM PDT 24 Mar 24 01:18:16 PM PDT 24 2087487245 ps
T831 /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3125416977 Mar 24 01:17:06 PM PDT 24 Mar 24 01:27:43 PM PDT 24 2466806504 ps
T832 /workspace/coverage/default/48.sram_ctrl_lc_escalation.3549524057 Mar 24 01:19:58 PM PDT 24 Mar 24 01:20:04 PM PDT 24 517448316 ps
T833 /workspace/coverage/default/19.sram_ctrl_stress_all.1000380513 Mar 24 01:17:54 PM PDT 24 Mar 24 01:31:15 PM PDT 24 9814103138 ps
T834 /workspace/coverage/default/34.sram_ctrl_partial_access.2656163573 Mar 24 01:18:48 PM PDT 24 Mar 24 01:19:03 PM PDT 24 1714274677 ps
T835 /workspace/coverage/default/36.sram_ctrl_executable.1677364188 Mar 24 01:19:02 PM PDT 24 Mar 24 01:34:38 PM PDT 24 4272936636 ps
T836 /workspace/coverage/default/26.sram_ctrl_partial_access.3848602551 Mar 24 01:18:16 PM PDT 24 Mar 24 01:18:31 PM PDT 24 258928637 ps
T837 /workspace/coverage/default/48.sram_ctrl_mem_walk.1927310438 Mar 24 01:19:55 PM PDT 24 Mar 24 01:20:00 PM PDT 24 230953271 ps
T838 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3596844397 Mar 24 01:19:07 PM PDT 24 Mar 24 01:19:12 PM PDT 24 148380302 ps
T839 /workspace/coverage/default/48.sram_ctrl_executable.766150962 Mar 24 01:19:55 PM PDT 24 Mar 24 01:57:16 PM PDT 24 18032194781 ps
T840 /workspace/coverage/default/34.sram_ctrl_max_throughput.2567855483 Mar 24 01:18:51 PM PDT 24 Mar 24 01:18:54 PM PDT 24 159858089 ps
T841 /workspace/coverage/default/31.sram_ctrl_lc_escalation.1419089681 Mar 24 01:18:31 PM PDT 24 Mar 24 01:18:40 PM PDT 24 2471303691 ps
T842 /workspace/coverage/default/45.sram_ctrl_lc_escalation.2148648485 Mar 24 01:19:41 PM PDT 24 Mar 24 01:19:47 PM PDT 24 480489995 ps
T843 /workspace/coverage/default/39.sram_ctrl_ram_cfg.1965592885 Mar 24 01:19:12 PM PDT 24 Mar 24 01:19:13 PM PDT 24 36550441 ps
T844 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1434020969 Mar 24 01:18:38 PM PDT 24 Mar 24 01:24:07 PM PDT 24 2352984156 ps
T845 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3053935536 Mar 24 01:19:20 PM PDT 24 Mar 24 01:19:25 PM PDT 24 172451529 ps
T846 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.703580215 Mar 24 01:18:59 PM PDT 24 Mar 24 01:21:56 PM PDT 24 7586933126 ps
T847 /workspace/coverage/default/33.sram_ctrl_regwen.1704837663 Mar 24 01:18:45 PM PDT 24 Mar 24 01:45:14 PM PDT 24 110422699299 ps
T848 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.429972789 Mar 24 01:18:01 PM PDT 24 Mar 24 01:32:44 PM PDT 24 3373450994 ps
T849 /workspace/coverage/default/34.sram_ctrl_smoke.440553335 Mar 24 01:18:47 PM PDT 24 Mar 24 01:18:50 PM PDT 24 177625448 ps
T850 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2800116788 Mar 24 01:18:31 PM PDT 24 Mar 24 01:19:06 PM PDT 24 420088015 ps
T851 /workspace/coverage/default/8.sram_ctrl_regwen.1622762700 Mar 24 01:17:24 PM PDT 24 Mar 24 01:32:05 PM PDT 24 10651059415 ps
T84 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2656979775 Mar 24 01:18:09 PM PDT 24 Mar 24 01:18:13 PM PDT 24 67613093 ps
T852 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3048439458 Mar 24 01:17:23 PM PDT 24 Mar 24 01:19:14 PM PDT 24 1576475879 ps
T853 /workspace/coverage/default/13.sram_ctrl_smoke.1870870679 Mar 24 01:17:30 PM PDT 24 Mar 24 01:17:47 PM PDT 24 3831900455 ps
T854 /workspace/coverage/default/28.sram_ctrl_alert_test.2791296064 Mar 24 01:18:25 PM PDT 24 Mar 24 01:18:25 PM PDT 24 14346918 ps
T855 /workspace/coverage/default/33.sram_ctrl_bijection.2978984133 Mar 24 01:18:47 PM PDT 24 Mar 24 01:19:48 PM PDT 24 4215297033 ps
T856 /workspace/coverage/default/48.sram_ctrl_bijection.3250242876 Mar 24 01:19:51 PM PDT 24 Mar 24 01:20:55 PM PDT 24 17114516204 ps
T857 /workspace/coverage/default/17.sram_ctrl_regwen.3181588306 Mar 24 01:17:36 PM PDT 24 Mar 24 01:26:35 PM PDT 24 9463111293 ps
T858 /workspace/coverage/default/29.sram_ctrl_partial_access.3235364878 Mar 24 01:18:23 PM PDT 24 Mar 24 01:18:24 PM PDT 24 67036789 ps
T859 /workspace/coverage/default/23.sram_ctrl_partial_access.2894472243 Mar 24 01:18:05 PM PDT 24 Mar 24 01:19:24 PM PDT 24 639816406 ps
T860 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3845644960 Mar 24 01:19:51 PM PDT 24 Mar 24 01:22:37 PM PDT 24 1713533131 ps
T861 /workspace/coverage/default/20.sram_ctrl_executable.2456220432 Mar 24 01:17:56 PM PDT 24 Mar 24 01:39:41 PM PDT 24 18799941015 ps
T862 /workspace/coverage/default/14.sram_ctrl_lc_escalation.2290951545 Mar 24 01:17:27 PM PDT 24 Mar 24 01:17:34 PM PDT 24 2017615162 ps
T863 /workspace/coverage/default/6.sram_ctrl_mem_walk.3914099316 Mar 24 01:17:23 PM PDT 24 Mar 24 01:17:28 PM PDT 24 1855917224 ps
T864 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2108912174 Mar 24 01:17:25 PM PDT 24 Mar 24 01:19:52 PM PDT 24 1027665843 ps
T865 /workspace/coverage/default/8.sram_ctrl_partial_access.3654075590 Mar 24 01:17:25 PM PDT 24 Mar 24 01:17:48 PM PDT 24 124512244 ps
T866 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2656385687 Mar 24 01:18:13 PM PDT 24 Mar 24 01:24:38 PM PDT 24 6128168729 ps
T867 /workspace/coverage/default/41.sram_ctrl_partial_access.1084163106 Mar 24 01:19:20 PM PDT 24 Mar 24 01:19:27 PM PDT 24 409850969 ps
T868 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3439803427 Mar 24 01:16:41 PM PDT 24 Mar 24 01:17:39 PM PDT 24 1146646686 ps
T869 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2921418260 Mar 24 01:17:23 PM PDT 24 Mar 24 01:18:51 PM PDT 24 1677808495 ps
T870 /workspace/coverage/default/8.sram_ctrl_max_throughput.2396897803 Mar 24 01:17:21 PM PDT 24 Mar 24 01:17:24 PM PDT 24 210226484 ps
T871 /workspace/coverage/default/34.sram_ctrl_mem_walk.3256931897 Mar 24 01:18:47 PM PDT 24 Mar 24 01:18:53 PM PDT 24 929737048 ps
T872 /workspace/coverage/default/10.sram_ctrl_regwen.1683614794 Mar 24 01:17:28 PM PDT 24 Mar 24 01:37:45 PM PDT 24 55621325408 ps
T873 /workspace/coverage/default/16.sram_ctrl_partial_access.403139929 Mar 24 01:17:36 PM PDT 24 Mar 24 01:17:49 PM PDT 24 1035587009 ps
T874 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2674124167 Mar 24 01:17:06 PM PDT 24 Mar 24 01:17:12 PM PDT 24 297131174 ps
T875 /workspace/coverage/default/40.sram_ctrl_stress_all.1114081245 Mar 24 01:19:14 PM PDT 24 Mar 24 02:31:39 PM PDT 24 193532328372 ps
T876 /workspace/coverage/default/23.sram_ctrl_stress_all.3138174422 Mar 24 01:18:08 PM PDT 24 Mar 24 01:48:39 PM PDT 24 27275175009 ps
T877 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3711879876 Mar 24 01:17:26 PM PDT 24 Mar 24 01:17:32 PM PDT 24 941281594 ps
T878 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.559026894 Mar 24 01:19:03 PM PDT 24 Mar 24 01:19:17 PM PDT 24 132760156 ps
T879 /workspace/coverage/default/49.sram_ctrl_stress_all.3890997333 Mar 24 01:20:00 PM PDT 24 Mar 24 02:17:53 PM PDT 24 267246505280 ps
T85 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1550141506 Mar 24 01:18:12 PM PDT 24 Mar 24 01:18:14 PM PDT 24 97854247 ps
T880 /workspace/coverage/default/7.sram_ctrl_partial_access.4209379786 Mar 24 01:17:23 PM PDT 24 Mar 24 01:17:43 PM PDT 24 444373701 ps
T881 /workspace/coverage/default/19.sram_ctrl_multiple_keys.177656112 Mar 24 01:17:43 PM PDT 24 Mar 24 01:31:53 PM PDT 24 10278447659 ps
T882 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.690541081 Mar 24 01:18:44 PM PDT 24 Mar 24 01:19:58 PM PDT 24 1771483551 ps
T883 /workspace/coverage/default/32.sram_ctrl_alert_test.3491898223 Mar 24 01:18:46 PM PDT 24 Mar 24 01:18:48 PM PDT 24 14277589 ps
T884 /workspace/coverage/default/47.sram_ctrl_alert_test.2886535940 Mar 24 01:19:56 PM PDT 24 Mar 24 01:19:57 PM PDT 24 41691848 ps
T885 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1922820972 Mar 24 01:19:23 PM PDT 24 Mar 24 01:42:36 PM PDT 24 14424171889 ps
T886 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3088072488 Mar 24 01:19:58 PM PDT 24 Mar 24 01:20:04 PM PDT 24 670605512 ps
T887 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3952532004 Mar 24 01:18:11 PM PDT 24 Mar 24 01:25:56 PM PDT 24 19839590159 ps
T888 /workspace/coverage/default/15.sram_ctrl_alert_test.3290952936 Mar 24 01:17:30 PM PDT 24 Mar 24 01:17:31 PM PDT 24 31072935 ps
T36 /workspace/coverage/default/3.sram_ctrl_sec_cm.3125270310 Mar 24 01:17:03 PM PDT 24 Mar 24 01:17:06 PM PDT 24 244673700 ps
T889 /workspace/coverage/default/13.sram_ctrl_lc_escalation.2567381011 Mar 24 01:17:29 PM PDT 24 Mar 24 01:17:31 PM PDT 24 176962455 ps
T86 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2512872968 Mar 24 01:19:23 PM PDT 24 Mar 24 01:19:25 PM PDT 24 103804824 ps
T890 /workspace/coverage/default/1.sram_ctrl_smoke.2221334607 Mar 24 01:16:43 PM PDT 24 Mar 24 01:16:45 PM PDT 24 216736001 ps
T891 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.925959454 Mar 24 01:18:42 PM PDT 24 Mar 24 01:18:47 PM PDT 24 655613263 ps
T892 /workspace/coverage/default/31.sram_ctrl_alert_test.3478036216 Mar 24 01:18:34 PM PDT 24 Mar 24 01:18:35 PM PDT 24 12868970 ps
T893 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3054186640 Mar 24 01:17:53 PM PDT 24 Mar 24 01:17:58 PM PDT 24 2718550337 ps
T894 /workspace/coverage/default/16.sram_ctrl_regwen.4104314135 Mar 24 01:17:39 PM PDT 24 Mar 24 01:24:35 PM PDT 24 9261157972 ps
T895 /workspace/coverage/default/16.sram_ctrl_max_throughput.1477030023 Mar 24 01:17:30 PM PDT 24 Mar 24 01:17:32 PM PDT 24 41409816 ps
T896 /workspace/coverage/default/19.sram_ctrl_mem_walk.1549397633 Mar 24 01:17:50 PM PDT 24 Mar 24 01:17:59 PM PDT 24 730514856 ps
T897 /workspace/coverage/default/8.sram_ctrl_mem_walk.1686887665 Mar 24 01:17:25 PM PDT 24 Mar 24 01:17:35 PM PDT 24 1055683641 ps
T898 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1495803492 Mar 24 01:19:49 PM PDT 24 Mar 24 01:22:19 PM PDT 24 10994729519 ps
T899 /workspace/coverage/default/17.sram_ctrl_executable.3384908907 Mar 24 01:17:35 PM PDT 24 Mar 24 01:21:32 PM PDT 24 3578889151 ps
T900 /workspace/coverage/default/3.sram_ctrl_lc_escalation.120731378 Mar 24 01:17:00 PM PDT 24 Mar 24 01:17:06 PM PDT 24 2174819494 ps
T901 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2221333877 Mar 24 01:19:46 PM PDT 24 Mar 24 01:22:24 PM PDT 24 24504472912 ps
T902 /workspace/coverage/default/9.sram_ctrl_multiple_keys.2758099367 Mar 24 01:17:24 PM PDT 24 Mar 24 01:28:04 PM PDT 24 5959339936 ps
T903 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.477161690 Mar 24 01:17:26 PM PDT 24 Mar 24 01:17:36 PM PDT 24 1057094739 ps
T904 /workspace/coverage/default/41.sram_ctrl_regwen.1875329 Mar 24 01:19:22 PM PDT 24 Mar 24 01:29:55 PM PDT 24 10728743324 ps
T905 /workspace/coverage/default/20.sram_ctrl_regwen.2932316592 Mar 24 01:17:54 PM PDT 24 Mar 24 01:35:49 PM PDT 24 10399661901 ps
T906 /workspace/coverage/default/9.sram_ctrl_executable.1794033527 Mar 24 01:17:25 PM PDT 24 Mar 24 01:21:58 PM PDT 24 524670168 ps
T907 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2114714478 Mar 24 01:18:56 PM PDT 24 Mar 24 01:20:15 PM PDT 24 566510472 ps
T908 /workspace/coverage/default/14.sram_ctrl_mem_walk.1218805537 Mar 24 01:17:32 PM PDT 24 Mar 24 01:17:43 PM PDT 24 4707654947 ps
T909 /workspace/coverage/default/38.sram_ctrl_max_throughput.1278111735 Mar 24 01:19:05 PM PDT 24 Mar 24 01:19:56 PM PDT 24 197312260 ps
T910 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2476035167 Mar 24 01:19:18 PM PDT 24 Mar 24 01:19:41 PM PDT 24 1469957453 ps
T911 /workspace/coverage/default/27.sram_ctrl_multiple_keys.2854655495 Mar 24 01:18:16 PM PDT 24 Mar 24 01:33:10 PM PDT 24 39853237599 ps
T912 /workspace/coverage/default/27.sram_ctrl_bijection.918587722 Mar 24 01:18:15 PM PDT 24 Mar 24 01:18:39 PM PDT 24 735663506 ps
T913 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1223015353 Mar 24 01:19:36 PM PDT 24 Mar 24 01:20:01 PM PDT 24 188358317 ps
T914 /workspace/coverage/default/42.sram_ctrl_smoke.4205852715 Mar 24 01:19:24 PM PDT 24 Mar 24 01:19:33 PM PDT 24 7845916066 ps
T915 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3502085457 Mar 24 01:17:32 PM PDT 24 Mar 24 01:32:49 PM PDT 24 23246256125 ps
T916 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.4215635024 Mar 24 01:19:18 PM PDT 24 Mar 24 01:41:52 PM PDT 24 20732917623 ps
T917 /workspace/coverage/default/9.sram_ctrl_max_throughput.2139986122 Mar 24 01:17:25 PM PDT 24 Mar 24 01:20:00 PM PDT 24 134713986 ps
T918 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4168095300 Mar 24 01:20:01 PM PDT 24 Mar 24 01:33:32 PM PDT 24 5732544993 ps
T919 /workspace/coverage/default/47.sram_ctrl_regwen.1308139773 Mar 24 01:19:51 PM PDT 24 Mar 24 01:32:53 PM PDT 24 3234258663 ps
T920 /workspace/coverage/default/16.sram_ctrl_executable.2916390635 Mar 24 01:17:36 PM PDT 24 Mar 24 01:45:57 PM PDT 24 3809004419 ps
T921 /workspace/coverage/default/35.sram_ctrl_ram_cfg.2015196342 Mar 24 01:18:52 PM PDT 24 Mar 24 01:18:52 PM PDT 24 296156684 ps
T922 /workspace/coverage/default/5.sram_ctrl_ram_cfg.3179314795 Mar 24 01:17:08 PM PDT 24 Mar 24 01:17:09 PM PDT 24 53524298 ps
T923 /workspace/coverage/default/29.sram_ctrl_alert_test.1438739398 Mar 24 01:18:27 PM PDT 24 Mar 24 01:18:28 PM PDT 24 52229230 ps
T924 /workspace/coverage/default/30.sram_ctrl_max_throughput.1965402616 Mar 24 01:18:29 PM PDT 24 Mar 24 01:18:31 PM PDT 24 529116261 ps
T925 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2476356942 Mar 24 01:17:30 PM PDT 24 Mar 24 01:19:05 PM PDT 24 137130112 ps
T926 /workspace/coverage/default/15.sram_ctrl_executable.1410278745 Mar 24 01:17:30 PM PDT 24 Mar 24 02:11:16 PM PDT 24 19222855647 ps
T927 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4183147371 Mar 24 01:17:28 PM PDT 24 Mar 24 01:25:20 PM PDT 24 154471653672 ps
T928 /workspace/coverage/default/8.sram_ctrl_lc_escalation.2672291710 Mar 24 01:17:23 PM PDT 24 Mar 24 01:17:33 PM PDT 24 2802582239 ps
T929 /workspace/coverage/default/33.sram_ctrl_stress_all.3671251849 Mar 24 01:18:48 PM PDT 24 Mar 24 01:47:11 PM PDT 24 114553127484 ps
T930 /workspace/coverage/default/2.sram_ctrl_regwen.169847285 Mar 24 01:16:56 PM PDT 24 Mar 24 01:43:48 PM PDT 24 17159208360 ps
T931 /workspace/coverage/default/28.sram_ctrl_smoke.2894736896 Mar 24 01:18:17 PM PDT 24 Mar 24 01:18:31 PM PDT 24 817849923 ps
T932 /workspace/coverage/default/45.sram_ctrl_alert_test.2737983501 Mar 24 01:19:42 PM PDT 24 Mar 24 01:19:43 PM PDT 24 39267653 ps
T933 /workspace/coverage/default/27.sram_ctrl_regwen.176692431 Mar 24 01:18:13 PM PDT 24 Mar 24 01:18:38 PM PDT 24 936966404 ps
T934 /workspace/coverage/default/5.sram_ctrl_stress_all.3513746968 Mar 24 01:17:13 PM PDT 24 Mar 24 02:10:43 PM PDT 24 111571276893 ps
T935 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1454391175 Mar 24 01:17:01 PM PDT 24 Mar 24 01:23:09 PM PDT 24 74038652171 ps
T936 /workspace/coverage/default/17.sram_ctrl_max_throughput.252761766 Mar 24 01:17:34 PM PDT 24 Mar 24 01:18:20 PM PDT 24 105429244 ps
T937 /workspace/coverage/default/7.sram_ctrl_ram_cfg.1342776606 Mar 24 01:17:22 PM PDT 24 Mar 24 01:17:23 PM PDT 24 42704692 ps
T938 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2711678703 Mar 24 01:18:32 PM PDT 24 Mar 24 01:22:14 PM PDT 24 30546305393 ps
T939 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.179068518 Mar 24 01:17:21 PM PDT 24 Mar 24 01:22:42 PM PDT 24 16608871875 ps
T940 /workspace/coverage/default/37.sram_ctrl_smoke.113005002 Mar 24 01:18:57 PM PDT 24 Mar 24 01:19:05 PM PDT 24 1679700447 ps
T941 /workspace/coverage/default/36.sram_ctrl_alert_test.3463643768 Mar 24 01:19:04 PM PDT 24 Mar 24 01:19:05 PM PDT 24 40576370 ps
T942 /workspace/coverage/default/12.sram_ctrl_lc_escalation.3153575163 Mar 24 01:17:24 PM PDT 24 Mar 24 01:17:33 PM PDT 24 1810695174 ps
T943 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2688928609 Mar 24 01:19:27 PM PDT 24 Mar 24 01:26:40 PM PDT 24 74227919398 ps
T944 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2819851290 Mar 24 01:17:33 PM PDT 24 Mar 24 01:23:11 PM PDT 24 21520595882 ps
T945 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4276401824 Mar 24 12:35:22 PM PDT 24 Mar 24 12:35:23 PM PDT 24 43328996 ps
T102 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2006646980 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:02 PM PDT 24 15868966 ps
T107 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2753153725 Mar 24 12:35:20 PM PDT 24 Mar 24 12:35:23 PM PDT 24 946412730 ps
T946 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4290187619 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:17 PM PDT 24 44572349 ps
T947 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3367612248 Mar 24 12:35:41 PM PDT 24 Mar 24 12:35:48 PM PDT 24 293834243 ps
T948 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3951210125 Mar 24 12:35:28 PM PDT 24 Mar 24 12:35:31 PM PDT 24 233431284 ps
T108 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.636879101 Mar 24 12:35:18 PM PDT 24 Mar 24 12:35:20 PM PDT 24 164520975 ps
T63 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2308016011 Mar 24 12:35:12 PM PDT 24 Mar 24 12:35:15 PM PDT 24 847517839 ps
T949 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4227224237 Mar 24 12:35:08 PM PDT 24 Mar 24 12:35:12 PM PDT 24 40844152 ps
T64 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.561528660 Mar 24 12:35:13 PM PDT 24 Mar 24 12:35:14 PM PDT 24 39079813 ps
T65 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3297683662 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:17 PM PDT 24 413495835 ps
T103 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.829893557 Mar 24 12:35:18 PM PDT 24 Mar 24 12:35:20 PM PDT 24 458450909 ps
T950 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3106062422 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:18 PM PDT 24 41084859 ps
T104 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4020313181 Mar 24 12:35:33 PM PDT 24 Mar 24 12:35:34 PM PDT 24 43899291 ps
T951 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3123499544 Mar 24 12:35:29 PM PDT 24 Mar 24 12:35:35 PM PDT 24 542886153 ps
T66 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.873997279 Mar 24 12:35:29 PM PDT 24 Mar 24 12:35:31 PM PDT 24 14796484 ps
T109 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.360671731 Mar 24 12:35:19 PM PDT 24 Mar 24 12:35:21 PM PDT 24 210082547 ps
T67 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1222717914 Mar 24 12:35:12 PM PDT 24 Mar 24 12:35:13 PM PDT 24 41046167 ps
T105 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2227953738 Mar 24 12:35:08 PM PDT 24 Mar 24 12:35:10 PM PDT 24 42461052 ps
T952 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1017323715 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:05 PM PDT 24 233501923 ps
T68 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.671045344 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:16 PM PDT 24 15536836 ps
T106 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1990533096 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:11 PM PDT 24 27669678 ps
T69 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2604417802 Mar 24 12:35:16 PM PDT 24 Mar 24 12:35:17 PM PDT 24 39954877 ps
T118 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1398825148 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:08 PM PDT 24 629659715 ps
T953 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3388715091 Mar 24 12:35:14 PM PDT 24 Mar 24 12:35:16 PM PDT 24 135795285 ps
T124 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.896787542 Mar 24 12:35:20 PM PDT 24 Mar 24 12:35:23 PM PDT 24 280841298 ps
T954 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3485284736 Mar 24 12:35:25 PM PDT 24 Mar 24 12:35:26 PM PDT 24 88123885 ps
T70 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2267045702 Mar 24 12:35:20 PM PDT 24 Mar 24 12:35:24 PM PDT 24 1402469239 ps
T955 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.311102592 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:19 PM PDT 24 14280048 ps
T71 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4119773874 Mar 24 12:35:08 PM PDT 24 Mar 24 12:35:10 PM PDT 24 68757541 ps
T72 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2484533310 Mar 24 12:34:51 PM PDT 24 Mar 24 12:34:52 PM PDT 24 15299191 ps
T74 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3392324252 Mar 24 12:35:14 PM PDT 24 Mar 24 12:35:15 PM PDT 24 45561320 ps
T956 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.456155949 Mar 24 12:35:23 PM PDT 24 Mar 24 12:35:24 PM PDT 24 253801138 ps
T957 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.751744309 Mar 24 12:35:30 PM PDT 24 Mar 24 12:35:31 PM PDT 24 39948402 ps
T95 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2024245181 Mar 24 12:34:55 PM PDT 24 Mar 24 12:35:00 PM PDT 24 3720245799 ps
T96 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.945421333 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:11 PM PDT 24 76326914 ps
T958 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1658074181 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:10 PM PDT 24 90484966 ps
T97 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2311899112 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:18 PM PDT 24 32501738 ps
T75 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4091596703 Mar 24 12:34:56 PM PDT 24 Mar 24 12:34:58 PM PDT 24 14450233 ps
T959 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3515114311 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:35 PM PDT 24 34204745 ps
T76 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.277549320 Mar 24 12:35:25 PM PDT 24 Mar 24 12:35:28 PM PDT 24 496526152 ps
T119 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2605416025 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:20 PM PDT 24 621883018 ps
T122 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3930610537 Mar 24 12:35:21 PM PDT 24 Mar 24 12:35:28 PM PDT 24 96446374 ps
T960 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2345110629 Mar 24 12:35:04 PM PDT 24 Mar 24 12:35:13 PM PDT 24 48455754 ps
T77 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.725127742 Mar 24 12:35:35 PM PDT 24 Mar 24 12:35:37 PM PDT 24 442515992 ps
T961 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2461043850 Mar 24 12:35:44 PM PDT 24 Mar 24 12:35:45 PM PDT 24 61519513 ps
T78 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3187954160 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:16 PM PDT 24 33655307 ps
T79 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1287410778 Mar 24 12:35:13 PM PDT 24 Mar 24 12:35:14 PM PDT 24 12422106 ps
T123 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.950884048 Mar 24 12:35:16 PM PDT 24 Mar 24 12:35:19 PM PDT 24 192702634 ps
T126 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1886885335 Mar 24 12:35:29 PM PDT 24 Mar 24 12:35:32 PM PDT 24 236369539 ps
T962 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1427586942 Mar 24 12:35:21 PM PDT 24 Mar 24 12:35:22 PM PDT 24 37922448 ps
T963 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1143215684 Mar 24 12:35:12 PM PDT 24 Mar 24 12:35:14 PM PDT 24 20464692 ps
T87 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1161355132 Mar 24 12:35:23 PM PDT 24 Mar 24 12:35:26 PM PDT 24 1431545640 ps
T964 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2155754918 Mar 24 12:35:26 PM PDT 24 Mar 24 12:35:27 PM PDT 24 25369564 ps
T965 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.253179135 Mar 24 12:34:48 PM PDT 24 Mar 24 12:34:50 PM PDT 24 319462088 ps
T966 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3925475155 Mar 24 12:35:14 PM PDT 24 Mar 24 12:35:15 PM PDT 24 12080218 ps
T967 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3505982003 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:12 PM PDT 24 447090273 ps
T968 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3311637633 Mar 24 12:35:01 PM PDT 24 Mar 24 12:35:04 PM PDT 24 91333461 ps
T969 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1420949035 Mar 24 12:34:51 PM PDT 24 Mar 24 12:34:52 PM PDT 24 20256888 ps
T970 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.705748907 Mar 24 12:35:19 PM PDT 24 Mar 24 12:35:22 PM PDT 24 547085201 ps
T120 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3309023507 Mar 24 12:35:18 PM PDT 24 Mar 24 12:35:21 PM PDT 24 981522126 ps
T971 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1682299850 Mar 24 12:35:18 PM PDT 24 Mar 24 12:35:20 PM PDT 24 97229168 ps
T972 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1259983402 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:09 PM PDT 24 16397791 ps
T973 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2627960513 Mar 24 12:35:16 PM PDT 24 Mar 24 12:35:20 PM PDT 24 577988675 ps
T974 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2113146243 Mar 24 12:35:31 PM PDT 24 Mar 24 12:35:33 PM PDT 24 361333833 ps
T975 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1600076204 Mar 24 12:35:39 PM PDT 24 Mar 24 12:35:39 PM PDT 24 17887933 ps
T976 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3306529968 Mar 24 12:35:20 PM PDT 24 Mar 24 12:35:22 PM PDT 24 60869474 ps
T977 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3839854983 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:12 PM PDT 24 209249050 ps
T978 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1617855404 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:18 PM PDT 24 161073954 ps
T88 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2931072147 Mar 24 12:35:19 PM PDT 24 Mar 24 12:35:22 PM PDT 24 398292126 ps
T979 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3514018087 Mar 24 12:35:08 PM PDT 24 Mar 24 12:35:12 PM PDT 24 190432506 ps
T89 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2248862227 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:06 PM PDT 24 13706042 ps
T980 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.359207798 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:16 PM PDT 24 63051876 ps
T981 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1631092582 Mar 24 12:35:47 PM PDT 24 Mar 24 12:35:55 PM PDT 24 123233367 ps
T982 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.237040320 Mar 24 12:35:14 PM PDT 24 Mar 24 12:35:15 PM PDT 24 18279104 ps
T92 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2122628221 Mar 24 12:35:19 PM PDT 24 Mar 24 12:35:22 PM PDT 24 432932807 ps
T983 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1240838006 Mar 24 12:35:16 PM PDT 24 Mar 24 12:35:19 PM PDT 24 113144733 ps
T984 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1311044694 Mar 24 12:35:22 PM PDT 24 Mar 24 12:35:22 PM PDT 24 18532549 ps
T985 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1839752331 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:19 PM PDT 24 1106869134 ps
T90 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2031315958 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:12 PM PDT 24 1602929061 ps
T986 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2465241282 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:14 PM PDT 24 48414149 ps
T987 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2529177113 Mar 24 12:35:09 PM PDT 24 Mar 24 12:35:14 PM PDT 24 399059466 ps
T988 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3078614868 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:11 PM PDT 24 97837833 ps
T989 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3610222932 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:16 PM PDT 24 35131363 ps
T990 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.249787703 Mar 24 12:35:16 PM PDT 24 Mar 24 12:35:23 PM PDT 24 120621469 ps
T128 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3588722991 Mar 24 12:35:13 PM PDT 24 Mar 24 12:35:15 PM PDT 24 163086533 ps
T991 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2009555909 Mar 24 12:35:16 PM PDT 24 Mar 24 12:35:17 PM PDT 24 34533284 ps
T992 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3436964508 Mar 24 12:35:06 PM PDT 24 Mar 24 12:35:10 PM PDT 24 56269563 ps
T993 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.752358575 Mar 24 12:35:14 PM PDT 24 Mar 24 12:35:16 PM PDT 24 34782460 ps
T994 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2556223872 Mar 24 12:35:10 PM PDT 24 Mar 24 12:35:11 PM PDT 24 12795482 ps
T995 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1799359587 Mar 24 12:35:27 PM PDT 24 Mar 24 12:35:28 PM PDT 24 18129882 ps
T91 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1101705286 Mar 24 12:35:15 PM PDT 24 Mar 24 12:35:18 PM PDT 24 834621233 ps
T996 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1361150332 Mar 24 12:35:12 PM PDT 24 Mar 24 12:35:13 PM PDT 24 15131005 ps
T127 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3150975543 Mar 24 12:35:00 PM PDT 24 Mar 24 12:35:03 PM PDT 24 99060056 ps
T997 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3213430592 Mar 24 12:35:23 PM PDT 24 Mar 24 12:35:24 PM PDT 24 38638653 ps
T998 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2280012898 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:25 PM PDT 24 108823301 ps
T999 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3626860992 Mar 24 12:35:05 PM PDT 24 Mar 24 12:35:08 PM PDT 24 373801636 ps
T1000 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2389638034 Mar 24 12:35:21 PM PDT 24 Mar 24 12:35:22 PM PDT 24 16636814 ps
T1001 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2551505921 Mar 24 12:35:23 PM PDT 24 Mar 24 12:35:28 PM PDT 24 266653162 ps
T1002 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.752803587 Mar 24 12:34:57 PM PDT 24 Mar 24 12:35:01 PM PDT 24 33848281 ps
T1003 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.248038721 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:14 PM PDT 24 494964088 ps
T1004 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.915414510 Mar 24 12:35:25 PM PDT 24 Mar 24 12:35:25 PM PDT 24 84307950 ps
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