Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.81 97.10 100.00 100.00 98.58 99.70 98.52


Total test records in report: 1032
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T1005 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1619649021 Mar 24 12:35:38 PM PDT 24 Mar 24 12:35:39 PM PDT 24 20567504 ps
T1006 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.183022802 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:04 PM PDT 24 14727533 ps
T1007 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3537354858 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:26 PM PDT 24 414660893 ps
T125 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3039151377 Mar 24 12:35:19 PM PDT 24 Mar 24 12:35:21 PM PDT 24 859830545 ps
T1008 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1702792398 Mar 24 12:35:07 PM PDT 24 Mar 24 12:35:11 PM PDT 24 228183358 ps
T1009 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2955342918 Mar 24 12:35:11 PM PDT 24 Mar 24 12:35:16 PM PDT 24 235661101 ps
T1010 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.311353177 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:36 PM PDT 24 827160063 ps
T1011 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3206013249 Mar 24 12:35:17 PM PDT 24 Mar 24 12:35:21 PM PDT 24 126301255 ps
T1012 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.635088355 Mar 24 12:35:19 PM PDT 24 Mar 24 12:35:21 PM PDT 24 33318255 ps
T1013 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1091977076 Mar 24 12:35:22 PM PDT 24 Mar 24 12:35:24 PM PDT 24 243727432 ps
T1014 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2418942008 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:35 PM PDT 24 182947128 ps
T1015 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2450766512 Mar 24 12:35:23 PM PDT 24 Mar 24 12:35:28 PM PDT 24 6396169185 ps
T1016 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.500850123 Mar 24 12:35:29 PM PDT 24 Mar 24 12:35:33 PM PDT 24 150447791 ps
T1017 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1679574108 Mar 24 12:35:34 PM PDT 24 Mar 24 12:35:37 PM PDT 24 69605180 ps
T93 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2249649101 Mar 24 12:34:53 PM PDT 24 Mar 24 12:34:55 PM PDT 24 31009003 ps
T121 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3384818536 Mar 24 12:35:09 PM PDT 24 Mar 24 12:35:12 PM PDT 24 530410831 ps
T1018 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2428919818 Mar 24 12:35:33 PM PDT 24 Mar 24 12:35:36 PM PDT 24 477786493 ps
T1019 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3461064244 Mar 24 12:34:52 PM PDT 24 Mar 24 12:34:53 PM PDT 24 48932888 ps
T1020 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1339615182 Mar 24 12:35:25 PM PDT 24 Mar 24 12:35:27 PM PDT 24 837231379 ps
T94 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.954041474 Mar 24 12:35:12 PM PDT 24 Mar 24 12:35:16 PM PDT 24 2450666963 ps
T1021 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.990967600 Mar 24 12:35:08 PM PDT 24 Mar 24 12:35:11 PM PDT 24 35797850 ps
T1022 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1766155976 Mar 24 12:35:14 PM PDT 24 Mar 24 12:35:17 PM PDT 24 64499855 ps
T1023 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3745977140 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:25 PM PDT 24 73109756 ps
T1024 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.489928790 Mar 24 12:35:33 PM PDT 24 Mar 24 12:35:38 PM PDT 24 261610286 ps
T1025 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2349032585 Mar 24 12:35:25 PM PDT 24 Mar 24 12:35:33 PM PDT 24 31692384 ps
T1026 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4253803882 Mar 24 12:35:20 PM PDT 24 Mar 24 12:35:21 PM PDT 24 22042407 ps
T1027 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4018893874 Mar 24 12:35:03 PM PDT 24 Mar 24 12:35:05 PM PDT 24 2131127353 ps
T1028 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2780724155 Mar 24 12:35:16 PM PDT 24 Mar 24 12:35:17 PM PDT 24 38196642 ps
T1029 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1525649102 Mar 24 12:35:12 PM PDT 24 Mar 24 12:35:18 PM PDT 24 68615195 ps
T1030 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1192922119 Mar 24 12:35:24 PM PDT 24 Mar 24 12:35:26 PM PDT 24 88897983 ps
T1031 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3560895281 Mar 24 12:35:21 PM PDT 24 Mar 24 12:35:22 PM PDT 24 19217189 ps
T1032 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1051575784 Mar 24 12:35:18 PM PDT 24 Mar 24 12:35:19 PM PDT 24 25665490 ps

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.768171882
Short name T11
Test name
Test status
Simulation time 27424952804 ps
CPU time 329.51 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:22:54 PM PDT 24
Peak memory 202148 kb
Host smart-5142dcf5-5821-4858-8a3f-63bfa71a4c39
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768171882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.768171882
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.3933178761
Short name T8
Test name
Test status
Simulation time 66556023848 ps
CPU time 1439.87 seconds
Started Mar 24 01:19:51 PM PDT 24
Finished Mar 24 01:43:52 PM PDT 24
Peak memory 383028 kb
Host smart-8c22224b-ad4e-4b6f-b547-cd3502c11a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933178761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.3933178761
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2616314821
Short name T46
Test name
Test status
Simulation time 4197003585 ps
CPU time 844.15 seconds
Started Mar 24 01:19:29 PM PDT 24
Finished Mar 24 01:33:34 PM PDT 24
Peak memory 383532 kb
Host smart-9e964cb9-74e6-486c-8f9c-3cc77ceed91e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2616314821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2616314821
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.2469430619
Short name T24
Test name
Test status
Simulation time 389864981 ps
CPU time 2.6 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 01:16:45 PM PDT 24
Peak memory 221748 kb
Host smart-8aee1591-34e4-44dd-b536-db097bf9e169
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469430619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.2469430619
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.3386221804
Short name T7
Test name
Test status
Simulation time 201661485815 ps
CPU time 4420.12 seconds
Started Mar 24 01:17:59 PM PDT 24
Finished Mar 24 02:31:39 PM PDT 24
Peak memory 382088 kb
Host smart-fdec0d9c-c117-49d1-bf68-558d4260fcb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386221804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.3386221804
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2753153725
Short name T107
Test name
Test status
Simulation time 946412730 ps
CPU time 2.15 seconds
Started Mar 24 12:35:20 PM PDT 24
Finished Mar 24 12:35:23 PM PDT 24
Peak memory 201884 kb
Host smart-d89c196d-69af-40fb-b293-f867278c6a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753153725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.2753153725
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.3283495828
Short name T13
Test name
Test status
Simulation time 15283880 ps
CPU time 0.66 seconds
Started Mar 24 01:17:05 PM PDT 24
Finished Mar 24 01:17:06 PM PDT 24
Peak memory 201136 kb
Host smart-34c9adde-4efc-444a-a6bc-89222561dc08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283495828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.3283495828
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.171788412
Short name T130
Test name
Test status
Simulation time 27445725860 ps
CPU time 963.09 seconds
Started Mar 24 01:17:09 PM PDT 24
Finished Mar 24 01:33:12 PM PDT 24
Peak memory 367772 kb
Host smart-fdec5e96-52bd-409d-a8bf-f2a5e8b7c457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171788412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.171788412
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3614387650
Short name T1
Test name
Test status
Simulation time 10990742388 ps
CPU time 508.99 seconds
Started Mar 24 01:17:55 PM PDT 24
Finished Mar 24 01:26:24 PM PDT 24
Peak memory 344008 kb
Host smart-904f3778-f95a-47f3-a882-990106e6c9c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614387650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.3614387650
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.583187773
Short name T138
Test name
Test status
Simulation time 33219085537 ps
CPU time 357.26 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 01:25:00 PM PDT 24
Peak memory 201992 kb
Host smart-b56ac21d-211f-4bfd-89a5-3e7c7a90a058
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583187773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.sram_ctrl_partial_access_b2b.583187773
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.965228062
Short name T135
Test name
Test status
Simulation time 54059145595 ps
CPU time 966.45 seconds
Started Mar 24 01:18:41 PM PDT 24
Finished Mar 24 01:34:47 PM PDT 24
Peak memory 372496 kb
Host smart-b7b83d67-af63-4d3c-8a96-72ca9c3786a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965228062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.965228062
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.650956454
Short name T29
Test name
Test status
Simulation time 1876164913 ps
CPU time 111.54 seconds
Started Mar 24 01:17:36 PM PDT 24
Finished Mar 24 01:19:28 PM PDT 24
Peak memory 312600 kb
Host smart-6112c96f-ffd7-486d-b389-70cd6f11d91c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=650956454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.650956454
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2308016011
Short name T63
Test name
Test status
Simulation time 847517839 ps
CPU time 1.76 seconds
Started Mar 24 12:35:12 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 201764 kb
Host smart-298cffc5-40ff-4ad8-848a-a514a743603d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308016011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2308016011
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.950884048
Short name T123
Test name
Test status
Simulation time 192702634 ps
CPU time 2.17 seconds
Started Mar 24 12:35:16 PM PDT 24
Finished Mar 24 12:35:19 PM PDT 24
Peak memory 201892 kb
Host smart-b3379f47-012c-49eb-9989-c6b9c4b8c737
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950884048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.sram_ctrl_tl_intg_err.950884048
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.358276379
Short name T262
Test name
Test status
Simulation time 45617125 ps
CPU time 0.79 seconds
Started Mar 24 01:17:35 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 202052 kb
Host smart-bcf439f5-1697-41b4-a3d5-9d956989b934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358276379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.358276379
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.1487874951
Short name T27
Test name
Test status
Simulation time 134974052190 ps
CPU time 809.59 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:30:59 PM PDT 24
Peak memory 373156 kb
Host smart-9e34f88c-16a0-4e38-87c9-ed32d9ff67c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487874951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.1487874951
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1382732242
Short name T49
Test name
Test status
Simulation time 1270218805 ps
CPU time 313.8 seconds
Started Mar 24 01:18:50 PM PDT 24
Finished Mar 24 01:24:04 PM PDT 24
Peak memory 373808 kb
Host smart-56ae8fe1-0d1d-4713-acf6-4d9aea65cb3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1382732242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.1382732242
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3309023507
Short name T120
Test name
Test status
Simulation time 981522126 ps
CPU time 2.58 seconds
Started Mar 24 12:35:18 PM PDT 24
Finished Mar 24 12:35:21 PM PDT 24
Peak memory 201968 kb
Host smart-e6dba234-c4cf-4b0c-92f3-897cfaedbe2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309023507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.3309023507
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3150975543
Short name T127
Test name
Test status
Simulation time 99060056 ps
CPU time 1.5 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:03 PM PDT 24
Peak memory 201932 kb
Host smart-aa375bc9-ab11-4b51-b5bd-2d58436d84fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150975543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.3150975543
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3588722991
Short name T128
Test name
Test status
Simulation time 163086533 ps
CPU time 1.56 seconds
Started Mar 24 12:35:13 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 202008 kb
Host smart-fbca6ab1-6479-43e1-800c-88a16804bae4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588722991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.3588722991
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2249649101
Short name T93
Test name
Test status
Simulation time 31009003 ps
CPU time 1.21 seconds
Started Mar 24 12:34:53 PM PDT 24
Finished Mar 24 12:34:55 PM PDT 24
Peak memory 201932 kb
Host smart-e06b5e90-2ea2-4172-8637-cae5ad3ec7db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249649101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.2249649101
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3461064244
Short name T1019
Test name
Test status
Simulation time 48932888 ps
CPU time 0.73 seconds
Started Mar 24 12:34:52 PM PDT 24
Finished Mar 24 12:34:53 PM PDT 24
Peak memory 200656 kb
Host smart-afac9e95-32f8-4e02-8c82-e22669edaa95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461064244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.3461064244
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1361150332
Short name T996
Test name
Test status
Simulation time 15131005 ps
CPU time 0.7 seconds
Started Mar 24 12:35:12 PM PDT 24
Finished Mar 24 12:35:13 PM PDT 24
Peak memory 201632 kb
Host smart-73fd295c-1c62-45c5-b90f-6769f2499cb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361150332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.1361150332
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.752803587
Short name T1002
Test name
Test status
Simulation time 33848281 ps
CPU time 1.16 seconds
Started Mar 24 12:34:57 PM PDT 24
Finished Mar 24 12:35:01 PM PDT 24
Peak memory 209840 kb
Host smart-0f9dcc8a-2d77-4f58-810d-7a9f663942d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752803587 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.752803587
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1799359587
Short name T995
Test name
Test status
Simulation time 18129882 ps
CPU time 0.65 seconds
Started Mar 24 12:35:27 PM PDT 24
Finished Mar 24 12:35:28 PM PDT 24
Peak memory 201548 kb
Host smart-b1f29f59-c78e-4ee0-8477-14479a7bfc3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799359587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.1799359587
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2024245181
Short name T95
Test name
Test status
Simulation time 3720245799 ps
CPU time 3.39 seconds
Started Mar 24 12:34:55 PM PDT 24
Finished Mar 24 12:35:00 PM PDT 24
Peak memory 202084 kb
Host smart-7337184b-e244-4658-98f5-70594c4afb9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024245181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2024245181
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1420949035
Short name T969
Test name
Test status
Simulation time 20256888 ps
CPU time 0.73 seconds
Started Mar 24 12:34:51 PM PDT 24
Finished Mar 24 12:34:52 PM PDT 24
Peak memory 201588 kb
Host smart-238b5c21-7576-45c4-95e2-96ea2c895eec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420949035 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1420949035
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1679574108
Short name T1017
Test name
Test status
Simulation time 69605180 ps
CPU time 3.05 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:37 PM PDT 24
Peak memory 201668 kb
Host smart-8b32db67-7fc0-4487-9ef6-1e1b4f74fd70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679574108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.1679574108
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2006646980
Short name T102
Test name
Test status
Simulation time 15868966 ps
CPU time 0.68 seconds
Started Mar 24 12:35:00 PM PDT 24
Finished Mar 24 12:35:02 PM PDT 24
Peak memory 200644 kb
Host smart-8744e572-4701-4c05-b413-c91f09b4f845
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006646980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.2006646980
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.253179135
Short name T965
Test name
Test status
Simulation time 319462088 ps
CPU time 1.45 seconds
Started Mar 24 12:34:48 PM PDT 24
Finished Mar 24 12:34:50 PM PDT 24
Peak memory 201900 kb
Host smart-44032c57-418a-4bd2-a627-37cca712f142
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253179135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_bit_bash.253179135
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1311044694
Short name T984
Test name
Test status
Simulation time 18532549 ps
CPU time 0.69 seconds
Started Mar 24 12:35:22 PM PDT 24
Finished Mar 24 12:35:22 PM PDT 24
Peak memory 201596 kb
Host smart-38db6672-e8eb-4286-8d30-c2bb2ed02023
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311044694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.1311044694
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1766155976
Short name T1022
Test name
Test status
Simulation time 64499855 ps
CPU time 2.07 seconds
Started Mar 24 12:35:14 PM PDT 24
Finished Mar 24 12:35:17 PM PDT 24
Peak memory 211236 kb
Host smart-d719ddf8-d06b-4d6a-a07c-6aea57db2262
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766155976 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1766155976
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3078614868
Short name T988
Test name
Test status
Simulation time 97837833 ps
CPU time 0.63 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:11 PM PDT 24
Peak memory 201720 kb
Host smart-c3a07fe6-45aa-4cc4-9ee5-ea0de310abf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078614868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.3078614868
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4018893874
Short name T1027
Test name
Test status
Simulation time 2131127353 ps
CPU time 1.92 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 201784 kb
Host smart-7e019196-953d-4036-b231-70555b0adb99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018893874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.4018893874
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.183022802
Short name T1006
Test name
Test status
Simulation time 14727533 ps
CPU time 0.64 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 201596 kb
Host smart-2f59cab7-ab5e-4a92-b522-1ef8acbb85d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183022802 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.183022802
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1617855404
Short name T978
Test name
Test status
Simulation time 161073954 ps
CPU time 1.85 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:18 PM PDT 24
Peak memory 201868 kb
Host smart-e956c6ed-d5b6-4c3d-871b-f64e4e0e8194
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617855404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.1617855404
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3626860992
Short name T999
Test name
Test status
Simulation time 373801636 ps
CPU time 2.06 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:08 PM PDT 24
Peak memory 212752 kb
Host smart-500309f2-9971-444e-b90e-f12c65b7c833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626860992 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3626860992
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4020313181
Short name T104
Test name
Test status
Simulation time 43899291 ps
CPU time 0.67 seconds
Started Mar 24 12:35:33 PM PDT 24
Finished Mar 24 12:35:34 PM PDT 24
Peak memory 201628 kb
Host smart-062ace93-2759-4eeb-808a-39efad952dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020313181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.4020313181
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1427586942
Short name T962
Test name
Test status
Simulation time 37922448 ps
CPU time 0.73 seconds
Started Mar 24 12:35:21 PM PDT 24
Finished Mar 24 12:35:22 PM PDT 24
Peak memory 201668 kb
Host smart-4711ac6f-ee60-4143-838a-c53923905aaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427586942 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.1427586942
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3514018087
Short name T979
Test name
Test status
Simulation time 190432506 ps
CPU time 2.6 seconds
Started Mar 24 12:35:08 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 201932 kb
Host smart-3bbd7431-17f5-4818-b6a3-0403093a4ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514018087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.3514018087
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2605416025
Short name T119
Test name
Test status
Simulation time 621883018 ps
CPU time 3.16 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:20 PM PDT 24
Peak memory 201964 kb
Host smart-67a64cf4-2ddf-4279-9008-0168541cf2d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605416025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.2605416025
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.752358575
Short name T993
Test name
Test status
Simulation time 34782460 ps
CPU time 1.78 seconds
Started Mar 24 12:35:14 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 214764 kb
Host smart-818a8bc6-b69b-4c16-82a4-258bc06e3bbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752358575 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.752358575
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3187954160
Short name T78
Test name
Test status
Simulation time 33655307 ps
CPU time 0.64 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 201660 kb
Host smart-3e3edc56-f00c-41b1-8112-36e69895781b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187954160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.3187954160
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1839752331
Short name T985
Test name
Test status
Simulation time 1106869134 ps
CPU time 3.28 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:19 PM PDT 24
Peak memory 202060 kb
Host smart-7f85d221-f6f5-43e6-9f17-6be527cce9a0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839752331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1839752331
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.671045344
Short name T68
Test name
Test status
Simulation time 15536836 ps
CPU time 0.64 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 201448 kb
Host smart-94ba3e81-8e3e-4164-bf30-635171f03bd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671045344 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.671045344
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1192922119
Short name T1030
Test name
Test status
Simulation time 88897983 ps
CPU time 2.14 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:26 PM PDT 24
Peak memory 201836 kb
Host smart-ba361c7c-b561-4a76-b6a6-fd05964f3ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192922119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.1192922119
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3306529968
Short name T976
Test name
Test status
Simulation time 60869474 ps
CPU time 1.76 seconds
Started Mar 24 12:35:20 PM PDT 24
Finished Mar 24 12:35:22 PM PDT 24
Peak memory 210308 kb
Host smart-78f65565-29f5-4e8f-8076-41eeb43eb12c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306529968 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3306529968
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.873997279
Short name T66
Test name
Test status
Simulation time 14796484 ps
CPU time 0.63 seconds
Started Mar 24 12:35:29 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 201600 kb
Host smart-46376fab-ca69-4e3c-af67-3939c1605358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873997279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 12.sram_ctrl_csr_rw.873997279
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2450766512
Short name T1015
Test name
Test status
Simulation time 6396169185 ps
CPU time 4.99 seconds
Started Mar 24 12:35:23 PM PDT 24
Finished Mar 24 12:35:28 PM PDT 24
Peak memory 202048 kb
Host smart-c2441fee-d4f5-4e06-b95d-ac8f1acd8b4d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450766512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2450766512
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2604417802
Short name T69
Test name
Test status
Simulation time 39954877 ps
CPU time 0.69 seconds
Started Mar 24 12:35:16 PM PDT 24
Finished Mar 24 12:35:17 PM PDT 24
Peak memory 201568 kb
Host smart-c8406711-2740-45ae-a81a-7302b080d5d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604417802 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2604417802
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2349032585
Short name T1025
Test name
Test status
Simulation time 31692384 ps
CPU time 2.21 seconds
Started Mar 24 12:35:25 PM PDT 24
Finished Mar 24 12:35:33 PM PDT 24
Peak memory 201920 kb
Host smart-fafbadd1-c847-4ceb-bf79-54495fcead58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349032585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.2349032585
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.635088355
Short name T1012
Test name
Test status
Simulation time 33318255 ps
CPU time 1.06 seconds
Started Mar 24 12:35:19 PM PDT 24
Finished Mar 24 12:35:21 PM PDT 24
Peak memory 209892 kb
Host smart-4990d701-cdfa-46ad-8d50-fa3c1b4d54f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635088355 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.635088355
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2556223872
Short name T994
Test name
Test status
Simulation time 12795482 ps
CPU time 0.62 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:11 PM PDT 24
Peak memory 201576 kb
Host smart-c0a0dd38-57e3-4842-8740-6330e96d6e07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556223872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.2556223872
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2931072147
Short name T88
Test name
Test status
Simulation time 398292126 ps
CPU time 3.1 seconds
Started Mar 24 12:35:19 PM PDT 24
Finished Mar 24 12:35:22 PM PDT 24
Peak memory 202028 kb
Host smart-245beacf-38fa-41c2-bf77-1f136a7f46a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931072147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2931072147
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1051575784
Short name T1032
Test name
Test status
Simulation time 25665490 ps
CPU time 0.73 seconds
Started Mar 24 12:35:18 PM PDT 24
Finished Mar 24 12:35:19 PM PDT 24
Peak memory 201704 kb
Host smart-839a4193-178c-4e4a-804a-fd10db5d3015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051575784 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.1051575784
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3951210125
Short name T948
Test name
Test status
Simulation time 233431284 ps
CPU time 3.29 seconds
Started Mar 24 12:35:28 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 202000 kb
Host smart-153f7c60-3baf-466c-a4bc-55e3bda69705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951210125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.3951210125
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3384818536
Short name T121
Test name
Test status
Simulation time 530410831 ps
CPU time 2.29 seconds
Started Mar 24 12:35:09 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 201928 kb
Host smart-6334e038-9979-497e-89fd-651d68033c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384818536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.3384818536
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3106062422
Short name T950
Test name
Test status
Simulation time 41084859 ps
CPU time 2.38 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:18 PM PDT 24
Peak memory 210060 kb
Host smart-541181f7-85a9-42b1-834b-bb7af7ca4702
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106062422 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3106062422
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1143215684
Short name T963
Test name
Test status
Simulation time 20464692 ps
CPU time 0.62 seconds
Started Mar 24 12:35:12 PM PDT 24
Finished Mar 24 12:35:14 PM PDT 24
Peak memory 201600 kb
Host smart-3c5f21c4-6ce6-4adc-a277-906a4ab3c437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143215684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.1143215684
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.277549320
Short name T76
Test name
Test status
Simulation time 496526152 ps
CPU time 3.26 seconds
Started Mar 24 12:35:25 PM PDT 24
Finished Mar 24 12:35:28 PM PDT 24
Peak memory 202024 kb
Host smart-582236ed-6eab-47d0-afbd-cc0775a24091
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277549320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.277549320
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2311899112
Short name T97
Test name
Test status
Simulation time 32501738 ps
CPU time 0.68 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:18 PM PDT 24
Peak memory 201632 kb
Host smart-b22b54ef-feca-463a-b800-ba2a3c36a880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311899112 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.2311899112
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3367612248
Short name T947
Test name
Test status
Simulation time 293834243 ps
CPU time 2.47 seconds
Started Mar 24 12:35:41 PM PDT 24
Finished Mar 24 12:35:48 PM PDT 24
Peak memory 201996 kb
Host smart-fd828fbf-d703-4431-9b11-98f91b77827c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367612248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.3367612248
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1682299850
Short name T971
Test name
Test status
Simulation time 97229168 ps
CPU time 1.51 seconds
Started Mar 24 12:35:18 PM PDT 24
Finished Mar 24 12:35:20 PM PDT 24
Peak memory 201912 kb
Host smart-f300b890-79b5-40bf-8ddb-3a1ccd7c730d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682299850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.1682299850
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.751744309
Short name T957
Test name
Test status
Simulation time 39948402 ps
CPU time 1.04 seconds
Started Mar 24 12:35:30 PM PDT 24
Finished Mar 24 12:35:31 PM PDT 24
Peak memory 209884 kb
Host smart-d2e38039-de48-4e60-bea6-df27f71f1f31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751744309 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.751744309
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2389638034
Short name T1000
Test name
Test status
Simulation time 16636814 ps
CPU time 0.67 seconds
Started Mar 24 12:35:21 PM PDT 24
Finished Mar 24 12:35:22 PM PDT 24
Peak memory 200644 kb
Host smart-e28263c5-7712-4d7a-b30a-c9920e907c46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389638034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.2389638034
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2031315958
Short name T90
Test name
Test status
Simulation time 1602929061 ps
CPU time 3.04 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 201984 kb
Host smart-c6380393-bec6-4e9c-8d4c-b82f661f3dcf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031315958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2031315958
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3213430592
Short name T997
Test name
Test status
Simulation time 38638653 ps
CPU time 0.74 seconds
Started Mar 24 12:35:23 PM PDT 24
Finished Mar 24 12:35:24 PM PDT 24
Peak memory 201652 kb
Host smart-6adfb981-9437-4da6-a67e-d7ff9a637c4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213430592 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.3213430592
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2955342918
Short name T1009
Test name
Test status
Simulation time 235661101 ps
CPU time 4.44 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 201920 kb
Host smart-0b0c3114-7d70-478d-9a29-ebb749c59dda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955342918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.2955342918
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2428919818
Short name T1018
Test name
Test status
Simulation time 477786493 ps
CPU time 2.74 seconds
Started Mar 24 12:35:33 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 201892 kb
Host smart-64d8fea3-b037-47cc-9779-55d2a0ad34ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428919818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.2428919818
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4276401824
Short name T945
Test name
Test status
Simulation time 43328996 ps
CPU time 1.22 seconds
Started Mar 24 12:35:22 PM PDT 24
Finished Mar 24 12:35:23 PM PDT 24
Peak memory 210064 kb
Host smart-366a70b2-3a07-42db-a2cb-5255dcb97bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276401824 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.4276401824
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1600076204
Short name T975
Test name
Test status
Simulation time 17887933 ps
CPU time 0.6 seconds
Started Mar 24 12:35:39 PM PDT 24
Finished Mar 24 12:35:39 PM PDT 24
Peak memory 200908 kb
Host smart-21bb174a-fb32-4a88-92f2-24b78a597402
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600076204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.1600076204
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.311353177
Short name T1010
Test name
Test status
Simulation time 827160063 ps
CPU time 2.14 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:36 PM PDT 24
Peak memory 201768 kb
Host smart-52487db5-ebd7-4fa7-bc21-27560f83583d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311353177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.311353177
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.359207798
Short name T980
Test name
Test status
Simulation time 63051876 ps
CPU time 0.71 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 201648 kb
Host smart-aba036d0-acec-4b9d-9b59-6316e5190a8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359207798 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.359207798
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.705748907
Short name T970
Test name
Test status
Simulation time 547085201 ps
CPU time 2.36 seconds
Started Mar 24 12:35:19 PM PDT 24
Finished Mar 24 12:35:22 PM PDT 24
Peak memory 201900 kb
Host smart-a52b70dd-3179-4898-a517-2325755455b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705748907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.705748907
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1091977076
Short name T1013
Test name
Test status
Simulation time 243727432 ps
CPU time 2 seconds
Started Mar 24 12:35:22 PM PDT 24
Finished Mar 24 12:35:24 PM PDT 24
Peak memory 201920 kb
Host smart-333fea63-c9a6-4baa-a855-94127c9000af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091977076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1091977076
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1287410778
Short name T79
Test name
Test status
Simulation time 12422106 ps
CPU time 0.63 seconds
Started Mar 24 12:35:13 PM PDT 24
Finished Mar 24 12:35:14 PM PDT 24
Peak memory 201604 kb
Host smart-4c83580d-74e9-4322-97ba-dfa8315464ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287410778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.1287410778
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1161355132
Short name T87
Test name
Test status
Simulation time 1431545640 ps
CPU time 3.01 seconds
Started Mar 24 12:35:23 PM PDT 24
Finished Mar 24 12:35:26 PM PDT 24
Peak memory 201992 kb
Host smart-e1ce8b2b-4463-4865-b5b3-d94a5bd38b09
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161355132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.1161355132
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4253803882
Short name T1026
Test name
Test status
Simulation time 22042407 ps
CPU time 0.7 seconds
Started Mar 24 12:35:20 PM PDT 24
Finished Mar 24 12:35:21 PM PDT 24
Peak memory 201568 kb
Host smart-c919fd9d-3f51-4dd8-8617-20b921185fa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253803882 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.4253803882
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1702792398
Short name T1008
Test name
Test status
Simulation time 228183358 ps
CPU time 2.24 seconds
Started Mar 24 12:35:07 PM PDT 24
Finished Mar 24 12:35:11 PM PDT 24
Peak memory 201768 kb
Host smart-28778857-2145-4a29-b1d3-327c188dd262
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702792398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1702792398
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.248038721
Short name T1003
Test name
Test status
Simulation time 494964088 ps
CPU time 2.5 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:14 PM PDT 24
Peak memory 201896 kb
Host smart-da71a4c4-67b3-4f9b-9ea7-fd4f06bd7e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248038721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.sram_ctrl_tl_intg_err.248038721
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.456155949
Short name T956
Test name
Test status
Simulation time 253801138 ps
CPU time 1.04 seconds
Started Mar 24 12:35:23 PM PDT 24
Finished Mar 24 12:35:24 PM PDT 24
Peak memory 201688 kb
Host smart-b3b6a7ba-fb83-4067-ace2-604245db6d37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456155949 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.456155949
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.311102592
Short name T955
Test name
Test status
Simulation time 14280048 ps
CPU time 0.64 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:19 PM PDT 24
Peak memory 201636 kb
Host smart-82d6be68-68fe-4122-9833-6f33885717b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311102592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.sram_ctrl_csr_rw.311102592
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1339615182
Short name T1020
Test name
Test status
Simulation time 837231379 ps
CPU time 2 seconds
Started Mar 24 12:35:25 PM PDT 24
Finished Mar 24 12:35:27 PM PDT 24
Peak memory 201704 kb
Host smart-9d1c1e45-5742-45b0-bfb7-6e2ddef989af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339615182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1339615182
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3925475155
Short name T966
Test name
Test status
Simulation time 12080218 ps
CPU time 0.67 seconds
Started Mar 24 12:35:14 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 201656 kb
Host smart-50010841-d5e0-484c-a505-9179dbf6e78f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925475155 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3925475155
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.489928790
Short name T1024
Test name
Test status
Simulation time 261610286 ps
CPU time 4.41 seconds
Started Mar 24 12:35:33 PM PDT 24
Finished Mar 24 12:35:38 PM PDT 24
Peak memory 201916 kb
Host smart-99006e65-e15a-4c0b-933e-b8d7f8c9454e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489928790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_tl_errors.489928790
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3039151377
Short name T125
Test name
Test status
Simulation time 859830545 ps
CPU time 1.72 seconds
Started Mar 24 12:35:19 PM PDT 24
Finished Mar 24 12:35:21 PM PDT 24
Peak memory 201928 kb
Host smart-df140a4c-11de-4c05-a986-fc3d9f0d4cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039151377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.3039151377
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.990967600
Short name T1021
Test name
Test status
Simulation time 35797850 ps
CPU time 2.24 seconds
Started Mar 24 12:35:08 PM PDT 24
Finished Mar 24 12:35:11 PM PDT 24
Peak memory 210080 kb
Host smart-b4664e07-f7cd-4c70-9614-70578923accf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990967600 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.990967600
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3560895281
Short name T1031
Test name
Test status
Simulation time 19217189 ps
CPU time 0.65 seconds
Started Mar 24 12:35:21 PM PDT 24
Finished Mar 24 12:35:22 PM PDT 24
Peak memory 201624 kb
Host smart-ba5194e8-22bf-436f-b844-89a8721547c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560895281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.3560895281
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2122628221
Short name T92
Test name
Test status
Simulation time 432932807 ps
CPU time 2.92 seconds
Started Mar 24 12:35:19 PM PDT 24
Finished Mar 24 12:35:22 PM PDT 24
Peak memory 202004 kb
Host smart-1f381e4e-47a8-4e29-ba6c-1bc2e084b5a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122628221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2122628221
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2461043850
Short name T961
Test name
Test status
Simulation time 61519513 ps
CPU time 0.71 seconds
Started Mar 24 12:35:44 PM PDT 24
Finished Mar 24 12:35:45 PM PDT 24
Peak memory 201684 kb
Host smart-3a08d4bc-82b3-47b3-ba2d-7adb3383735b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461043850 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2461043850
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2551505921
Short name T1001
Test name
Test status
Simulation time 266653162 ps
CPU time 4.91 seconds
Started Mar 24 12:35:23 PM PDT 24
Finished Mar 24 12:35:28 PM PDT 24
Peak memory 201932 kb
Host smart-d86a2f73-bc85-48a2-84e7-dffedb43207f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551505921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.2551505921
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.360671731
Short name T109
Test name
Test status
Simulation time 210082547 ps
CPU time 1.53 seconds
Started Mar 24 12:35:19 PM PDT 24
Finished Mar 24 12:35:21 PM PDT 24
Peak memory 201924 kb
Host smart-76ba2533-3f14-4468-819b-86bc362ee0d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360671731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.sram_ctrl_tl_intg_err.360671731
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3392324252
Short name T74
Test name
Test status
Simulation time 45561320 ps
CPU time 0.67 seconds
Started Mar 24 12:35:14 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 201660 kb
Host smart-b90523a4-d7a8-48de-a204-817db0cd33aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392324252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.3392324252
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.829893557
Short name T103
Test name
Test status
Simulation time 458450909 ps
CPU time 2.18 seconds
Started Mar 24 12:35:18 PM PDT 24
Finished Mar 24 12:35:20 PM PDT 24
Peak memory 201944 kb
Host smart-6b0aa9d1-0324-47cd-93f9-5c06ce6da174
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829893557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_bit_bash.829893557
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4091596703
Short name T75
Test name
Test status
Simulation time 14450233 ps
CPU time 0.65 seconds
Started Mar 24 12:34:56 PM PDT 24
Finished Mar 24 12:34:58 PM PDT 24
Peak memory 201760 kb
Host smart-245587b3-6c81-4367-a278-2083df77d409
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091596703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.4091596703
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3311637633
Short name T968
Test name
Test status
Simulation time 91333461 ps
CPU time 1.5 seconds
Started Mar 24 12:35:01 PM PDT 24
Finished Mar 24 12:35:04 PM PDT 24
Peak memory 210084 kb
Host smart-9251b174-40a2-4891-ab73-4cdb0088957f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311637633 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3311637633
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.561528660
Short name T64
Test name
Test status
Simulation time 39079813 ps
CPU time 0.63 seconds
Started Mar 24 12:35:13 PM PDT 24
Finished Mar 24 12:35:14 PM PDT 24
Peak memory 201700 kb
Host smart-700cd139-7297-4430-99b2-93394a1c9592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561528660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.sram_ctrl_csr_rw.561528660
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.954041474
Short name T94
Test name
Test status
Simulation time 2450666963 ps
CPU time 3.75 seconds
Started Mar 24 12:35:12 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 202092 kb
Host smart-efa5250f-9314-44e4-8a78-87ab760ecf00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954041474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.954041474
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2484533310
Short name T72
Test name
Test status
Simulation time 15299191 ps
CPU time 0.77 seconds
Started Mar 24 12:34:51 PM PDT 24
Finished Mar 24 12:34:52 PM PDT 24
Peak memory 201660 kb
Host smart-0f3a0571-af36-4821-9c13-8a4cd6c82e16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484533310 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.2484533310
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2345110629
Short name T960
Test name
Test status
Simulation time 48455754 ps
CPU time 3.35 seconds
Started Mar 24 12:35:04 PM PDT 24
Finished Mar 24 12:35:13 PM PDT 24
Peak memory 201888 kb
Host smart-22315405-e5df-473a-b66e-1abee10d96b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345110629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.2345110629
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1398825148
Short name T118
Test name
Test status
Simulation time 629659715 ps
CPU time 2.31 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:08 PM PDT 24
Peak memory 201944 kb
Host smart-11345802-8100-4133-80ef-1201fee8f39c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398825148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.1398825148
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4119773874
Short name T71
Test name
Test status
Simulation time 68757541 ps
CPU time 0.77 seconds
Started Mar 24 12:35:08 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 200768 kb
Host smart-f23aed81-c011-4c4c-bc82-770491aa598c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119773874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.4119773874
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1017323715
Short name T952
Test name
Test status
Simulation time 233501923 ps
CPU time 2.09 seconds
Started Mar 24 12:35:03 PM PDT 24
Finished Mar 24 12:35:05 PM PDT 24
Peak memory 201856 kb
Host smart-bffb3b58-9895-46bd-a59c-b2e1a090c305
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017323715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1017323715
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2009555909
Short name T991
Test name
Test status
Simulation time 34533284 ps
CPU time 0.65 seconds
Started Mar 24 12:35:16 PM PDT 24
Finished Mar 24 12:35:17 PM PDT 24
Peak memory 201640 kb
Host smart-c11cf91c-0172-4ef8-b7d5-d37aebaad509
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009555909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.2009555909
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2113146243
Short name T974
Test name
Test status
Simulation time 361333833 ps
CPU time 1.36 seconds
Started Mar 24 12:35:31 PM PDT 24
Finished Mar 24 12:35:33 PM PDT 24
Peak memory 210388 kb
Host smart-d5d19aaf-1100-4ba8-96ac-8969f816e320
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113146243 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2113146243
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1990533096
Short name T106
Test name
Test status
Simulation time 27669678 ps
CPU time 0.64 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:11 PM PDT 24
Peak memory 201604 kb
Host smart-cd5ea6cf-404b-482c-8c07-903c40a8a5bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990533096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.1990533096
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3839854983
Short name T977
Test name
Test status
Simulation time 209249050 ps
CPU time 1.91 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 201796 kb
Host smart-03d8984d-70e6-4963-8d13-3278bdff58f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839854983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3839854983
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.237040320
Short name T982
Test name
Test status
Simulation time 18279104 ps
CPU time 0.72 seconds
Started Mar 24 12:35:14 PM PDT 24
Finished Mar 24 12:35:15 PM PDT 24
Peak memory 201684 kb
Host smart-8ac80670-d128-42f3-bc77-26bb3473fd15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237040320 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.237040320
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1240838006
Short name T983
Test name
Test status
Simulation time 113144733 ps
CPU time 3.64 seconds
Started Mar 24 12:35:16 PM PDT 24
Finished Mar 24 12:35:19 PM PDT 24
Peak memory 201952 kb
Host smart-e58957a8-97cf-46d5-bf26-6b010330558f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240838006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.1240838006
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1886885335
Short name T126
Test name
Test status
Simulation time 236369539 ps
CPU time 2.33 seconds
Started Mar 24 12:35:29 PM PDT 24
Finished Mar 24 12:35:32 PM PDT 24
Peak memory 201904 kb
Host smart-d63af729-a69a-48c4-a700-fec7aea40f19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886885335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.1886885335
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2418942008
Short name T1014
Test name
Test status
Simulation time 182947128 ps
CPU time 0.72 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:35 PM PDT 24
Peak memory 201624 kb
Host smart-887da42b-205b-4e8f-92ae-1a09c1f4bed3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418942008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.2418942008
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3515114311
Short name T959
Test name
Test status
Simulation time 34204745 ps
CPU time 1.16 seconds
Started Mar 24 12:35:34 PM PDT 24
Finished Mar 24 12:35:35 PM PDT 24
Peak memory 201548 kb
Host smart-6223f37a-9e77-4343-83bb-6d4bc5fc8cd2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515114311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3515114311
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1259983402
Short name T972
Test name
Test status
Simulation time 16397791 ps
CPU time 0.66 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:09 PM PDT 24
Peak memory 201672 kb
Host smart-444d0989-4483-4b29-9861-c5a6df1742b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259983402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.1259983402
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.249787703
Short name T990
Test name
Test status
Simulation time 120621469 ps
CPU time 1.79 seconds
Started Mar 24 12:35:16 PM PDT 24
Finished Mar 24 12:35:23 PM PDT 24
Peak memory 210152 kb
Host smart-8a7315d3-556b-442f-b952-f744740417dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249787703 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.249787703
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2248862227
Short name T89
Test name
Test status
Simulation time 13706042 ps
CPU time 0.64 seconds
Started Mar 24 12:35:05 PM PDT 24
Finished Mar 24 12:35:06 PM PDT 24
Peak memory 201636 kb
Host smart-7bbd9398-d6e0-4a99-a8ea-2df441c23daf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248862227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.2248862227
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3297683662
Short name T65
Test name
Test status
Simulation time 413495835 ps
CPU time 1.93 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:17 PM PDT 24
Peak memory 201808 kb
Host smart-d8ed0739-e0c0-4c32-b78d-b352c36d5928
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297683662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.3297683662
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1222717914
Short name T67
Test name
Test status
Simulation time 41046167 ps
CPU time 0.68 seconds
Started Mar 24 12:35:12 PM PDT 24
Finished Mar 24 12:35:13 PM PDT 24
Peak memory 201712 kb
Host smart-f221903b-ff18-4a24-83a5-921a807cac23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222717914 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1222717914
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.500850123
Short name T1016
Test name
Test status
Simulation time 150447791 ps
CPU time 2.67 seconds
Started Mar 24 12:35:29 PM PDT 24
Finished Mar 24 12:35:33 PM PDT 24
Peak memory 201900 kb
Host smart-be767fda-5fe0-4498-a72e-f224abbcdcec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500850123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_tl_errors.500850123
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3505982003
Short name T967
Test name
Test status
Simulation time 447090273 ps
CPU time 2.23 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 201864 kb
Host smart-d0d348e6-034e-4016-be1a-7899422639ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505982003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.3505982003
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1658074181
Short name T958
Test name
Test status
Simulation time 90484966 ps
CPU time 1.08 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 209828 kb
Host smart-51ea825b-64cc-4f32-8cde-9552fde93478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658074181 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1658074181
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3610222932
Short name T989
Test name
Test status
Simulation time 35131363 ps
CPU time 0.62 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 201564 kb
Host smart-05110f1e-6995-41a1-b410-46eee7b0f747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610222932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.3610222932
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.725127742
Short name T77
Test name
Test status
Simulation time 442515992 ps
CPU time 2.06 seconds
Started Mar 24 12:35:35 PM PDT 24
Finished Mar 24 12:35:37 PM PDT 24
Peak memory 201812 kb
Host smart-bee251de-58c2-47e8-9cbc-19e97ab64121
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725127742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.725127742
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.915414510
Short name T1004
Test name
Test status
Simulation time 84307950 ps
CPU time 0.82 seconds
Started Mar 24 12:35:25 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 201672 kb
Host smart-53dcdc5f-87cd-4a57-a1b4-00b7a9930947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915414510 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.915414510
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2529177113
Short name T987
Test name
Test status
Simulation time 399059466 ps
CPU time 4.65 seconds
Started Mar 24 12:35:09 PM PDT 24
Finished Mar 24 12:35:14 PM PDT 24
Peak memory 201884 kb
Host smart-98e901eb-4ae6-44fe-9a32-0d995124219e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529177113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.2529177113
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2280012898
Short name T998
Test name
Test status
Simulation time 108823301 ps
CPU time 1.57 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 201920 kb
Host smart-f056c3bd-f897-470b-adca-6887f91d072e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280012898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.2280012898
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3388715091
Short name T953
Test name
Test status
Simulation time 135795285 ps
CPU time 1.29 seconds
Started Mar 24 12:35:14 PM PDT 24
Finished Mar 24 12:35:16 PM PDT 24
Peak memory 209884 kb
Host smart-e8a42e00-8291-4bed-9615-921b03a6bc43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388715091 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3388715091
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3745977140
Short name T1023
Test name
Test status
Simulation time 73109756 ps
CPU time 0.66 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:25 PM PDT 24
Peak memory 201664 kb
Host smart-5acb777c-7a92-4bb4-9fb2-439ebeaf4814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745977140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.3745977140
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3537354858
Short name T1007
Test name
Test status
Simulation time 414660893 ps
CPU time 1.91 seconds
Started Mar 24 12:35:24 PM PDT 24
Finished Mar 24 12:35:26 PM PDT 24
Peak memory 201792 kb
Host smart-e9efc12e-5dcd-4ba4-8f13-9688cd6b4c49
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537354858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3537354858
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.945421333
Short name T96
Test name
Test status
Simulation time 76326914 ps
CPU time 0.75 seconds
Started Mar 24 12:35:10 PM PDT 24
Finished Mar 24 12:35:11 PM PDT 24
Peak memory 201688 kb
Host smart-7677b015-61a0-403b-a4ad-c9f2fe94f347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945421333 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.945421333
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3123499544
Short name T951
Test name
Test status
Simulation time 542886153 ps
CPU time 5.24 seconds
Started Mar 24 12:35:29 PM PDT 24
Finished Mar 24 12:35:35 PM PDT 24
Peak memory 201860 kb
Host smart-ef21f876-d2c0-442b-96b6-3815b6766487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123499544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.3123499544
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3930610537
Short name T122
Test name
Test status
Simulation time 96446374 ps
CPU time 1.52 seconds
Started Mar 24 12:35:21 PM PDT 24
Finished Mar 24 12:35:28 PM PDT 24
Peak memory 202256 kb
Host smart-3b69d13e-17d0-4ef9-b260-8ae85091f2ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930610537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.3930610537
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1631092582
Short name T981
Test name
Test status
Simulation time 123233367 ps
CPU time 2.16 seconds
Started Mar 24 12:35:47 PM PDT 24
Finished Mar 24 12:35:55 PM PDT 24
Peak memory 211144 kb
Host smart-d41fa867-3c4c-4a57-87be-8293fb7051db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631092582 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1631092582
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2227953738
Short name T105
Test name
Test status
Simulation time 42461052 ps
CPU time 0.64 seconds
Started Mar 24 12:35:08 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 202024 kb
Host smart-cf2ade34-0455-49ad-94fb-2f1a5136dfcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227953738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.2227953738
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2267045702
Short name T70
Test name
Test status
Simulation time 1402469239 ps
CPU time 3.24 seconds
Started Mar 24 12:35:20 PM PDT 24
Finished Mar 24 12:35:24 PM PDT 24
Peak memory 202036 kb
Host smart-89353637-8fc3-4354-b2db-46e05093a0f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267045702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2267045702
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3436964508
Short name T992
Test name
Test status
Simulation time 56269563 ps
CPU time 0.68 seconds
Started Mar 24 12:35:06 PM PDT 24
Finished Mar 24 12:35:10 PM PDT 24
Peak memory 201668 kb
Host smart-8c0ddae6-f8a9-4634-a279-2c779c69ba0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436964508 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3436964508
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2465241282
Short name T986
Test name
Test status
Simulation time 48414149 ps
CPU time 2.53 seconds
Started Mar 24 12:35:11 PM PDT 24
Finished Mar 24 12:35:14 PM PDT 24
Peak memory 201900 kb
Host smart-be5df5ec-74f9-4567-b58b-d918d27dc607
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465241282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.2465241282
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.896787542
Short name T124
Test name
Test status
Simulation time 280841298 ps
CPU time 2.73 seconds
Started Mar 24 12:35:20 PM PDT 24
Finished Mar 24 12:35:23 PM PDT 24
Peak memory 201924 kb
Host smart-468da36f-1d94-4399-a3aa-d390b52d4e76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896787542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.sram_ctrl_tl_intg_err.896787542
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3485284736
Short name T954
Test name
Test status
Simulation time 88123885 ps
CPU time 0.91 seconds
Started Mar 24 12:35:25 PM PDT 24
Finished Mar 24 12:35:26 PM PDT 24
Peak memory 202032 kb
Host smart-830d58f2-eb35-4f02-863c-6561c5704cdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485284736 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3485284736
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2155754918
Short name T964
Test name
Test status
Simulation time 25369564 ps
CPU time 0.67 seconds
Started Mar 24 12:35:26 PM PDT 24
Finished Mar 24 12:35:27 PM PDT 24
Peak memory 201624 kb
Host smart-d10ecc5b-06dd-4054-810c-d6a265040da6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155754918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.2155754918
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2627960513
Short name T973
Test name
Test status
Simulation time 577988675 ps
CPU time 3.46 seconds
Started Mar 24 12:35:16 PM PDT 24
Finished Mar 24 12:35:20 PM PDT 24
Peak memory 201960 kb
Host smart-6167e685-2051-490b-aead-01d00ce6006a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627960513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.2627960513
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1525649102
Short name T1029
Test name
Test status
Simulation time 68615195 ps
CPU time 0.82 seconds
Started Mar 24 12:35:12 PM PDT 24
Finished Mar 24 12:35:18 PM PDT 24
Peak memory 201652 kb
Host smart-54fcaeca-ce46-49ce-81dd-25c2ac5d9b3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525649102 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1525649102
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4227224237
Short name T949
Test name
Test status
Simulation time 40844152 ps
CPU time 3.37 seconds
Started Mar 24 12:35:08 PM PDT 24
Finished Mar 24 12:35:12 PM PDT 24
Peak memory 201948 kb
Host smart-1e5d57d4-9663-41ea-a35a-8e458cfeb98c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227224237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.4227224237
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4290187619
Short name T946
Test name
Test status
Simulation time 44572349 ps
CPU time 1.08 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:17 PM PDT 24
Peak memory 210912 kb
Host smart-b7c41ff1-9579-456d-9bf6-2248c898f215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290187619 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.4290187619
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1619649021
Short name T1005
Test name
Test status
Simulation time 20567504 ps
CPU time 0.68 seconds
Started Mar 24 12:35:38 PM PDT 24
Finished Mar 24 12:35:39 PM PDT 24
Peak memory 201604 kb
Host smart-7f45caf1-1ec5-4390-81f4-259423cc2b3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619649021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.1619649021
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1101705286
Short name T91
Test name
Test status
Simulation time 834621233 ps
CPU time 2.1 seconds
Started Mar 24 12:35:15 PM PDT 24
Finished Mar 24 12:35:18 PM PDT 24
Peak memory 201780 kb
Host smart-3b812c7f-c976-4476-9b46-6bde2d2449c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101705286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1101705286
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2780724155
Short name T1028
Test name
Test status
Simulation time 38196642 ps
CPU time 0.73 seconds
Started Mar 24 12:35:16 PM PDT 24
Finished Mar 24 12:35:17 PM PDT 24
Peak memory 201664 kb
Host smart-674494f9-8967-4290-b779-a7063a433c78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780724155 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2780724155
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3206013249
Short name T1011
Test name
Test status
Simulation time 126301255 ps
CPU time 3.29 seconds
Started Mar 24 12:35:17 PM PDT 24
Finished Mar 24 12:35:21 PM PDT 24
Peak memory 201856 kb
Host smart-ce772a8f-dd11-4a79-9cbe-7ff83ef32135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206013249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.3206013249
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.636879101
Short name T108
Test name
Test status
Simulation time 164520975 ps
CPU time 1.53 seconds
Started Mar 24 12:35:18 PM PDT 24
Finished Mar 24 12:35:20 PM PDT 24
Peak memory 201928 kb
Host smart-87c4cd9b-7f7f-466a-abde-3644bd25a9bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636879101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.sram_ctrl_tl_intg_err.636879101
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.413095921
Short name T785
Test name
Test status
Simulation time 8367278466 ps
CPU time 1214.24 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 01:36:56 PM PDT 24
Peak memory 370796 kb
Host smart-9c3d4d56-72b2-425a-8b51-51763e9415c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413095921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.sram_ctrl_access_during_key_req.413095921
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.3504365468
Short name T537
Test name
Test status
Simulation time 43735013 ps
CPU time 0.64 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:16:44 PM PDT 24
Peak memory 201012 kb
Host smart-61c4dcb8-c74c-4a39-9281-7f2cea71d4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504365468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.3504365468
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.3068994197
Short name T715
Test name
Test status
Simulation time 1803468700 ps
CPU time 58.81 seconds
Started Mar 24 01:16:41 PM PDT 24
Finished Mar 24 01:17:40 PM PDT 24
Peak memory 202048 kb
Host smart-7be38faf-a175-4bfc-8398-289cb9a7f3eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068994197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
3068994197
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.2089920508
Short name T576
Test name
Test status
Simulation time 23094145313 ps
CPU time 1039.91 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:34:03 PM PDT 24
Peak memory 372496 kb
Host smart-294796c1-f29b-4daf-8a0d-7f798ef5cfd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089920508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.2089920508
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.2447678008
Short name T516
Test name
Test status
Simulation time 1390533765 ps
CPU time 8.34 seconds
Started Mar 24 01:16:50 PM PDT 24
Finished Mar 24 01:16:59 PM PDT 24
Peak memory 202016 kb
Host smart-4419154a-0ad3-4ccd-93cc-61f82f7cf0aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447678008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.2447678008
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.3027089108
Short name T208
Test name
Test status
Simulation time 495563426 ps
CPU time 106.23 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 01:18:28 PM PDT 24
Peak memory 360464 kb
Host smart-db944cf4-27f4-4748-9b53-2cb86b127c32
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027089108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.3027089108
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1310491841
Short name T507
Test name
Test status
Simulation time 178776723 ps
CPU time 2.93 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:16:47 PM PDT 24
Peak memory 210132 kb
Host smart-8646915a-d3df-4430-be4e-8fdac1c122db
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310491841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.1310491841
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.1094382126
Short name T169
Test name
Test status
Simulation time 451019048 ps
CPU time 9.05 seconds
Started Mar 24 01:16:44 PM PDT 24
Finished Mar 24 01:16:53 PM PDT 24
Peak memory 201924 kb
Host smart-9a4b8dec-4f02-4bcc-a5a6-ea12d287bdb0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094382126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.1094382126
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.1416070289
Short name T157
Test name
Test status
Simulation time 16557279756 ps
CPU time 1279.52 seconds
Started Mar 24 01:16:58 PM PDT 24
Finished Mar 24 01:38:18 PM PDT 24
Peak memory 373620 kb
Host smart-694c0b20-85e2-463a-8dec-d8d83961ea1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416070289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.1416070289
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.1805101744
Short name T332
Test name
Test status
Simulation time 2713674786 ps
CPU time 16.77 seconds
Started Mar 24 01:16:40 PM PDT 24
Finished Mar 24 01:16:57 PM PDT 24
Peak memory 202060 kb
Host smart-3674684d-ef1c-40bb-b1d8-20625907674c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805101744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.1805101744
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1568319324
Short name T468
Test name
Test status
Simulation time 17078336424 ps
CPU time 387.82 seconds
Started Mar 24 01:16:41 PM PDT 24
Finished Mar 24 01:23:09 PM PDT 24
Peak memory 202044 kb
Host smart-2714c2ac-1bd9-4c8c-b873-99ab5d047183
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568319324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.1568319324
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.3572688222
Short name T326
Test name
Test status
Simulation time 192221662 ps
CPU time 0.76 seconds
Started Mar 24 01:16:47 PM PDT 24
Finished Mar 24 01:16:48 PM PDT 24
Peak memory 202132 kb
Host smart-c7e204db-66da-4e28-a97e-918ec4898569
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572688222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3572688222
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.1221133934
Short name T459
Test name
Test status
Simulation time 24361633828 ps
CPU time 1304.22 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 01:38:27 PM PDT 24
Peak memory 370816 kb
Host smart-2a5578e0-d624-46e4-9724-1cda30f11ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221133934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1221133934
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.4273831999
Short name T787
Test name
Test status
Simulation time 58570236 ps
CPU time 6.23 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 01:16:48 PM PDT 24
Peak memory 231624 kb
Host smart-4e9bbb3e-65f0-4177-ad46-a06ad7b01b38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273831999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.4273831999
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.3157034406
Short name T315
Test name
Test status
Simulation time 9768775168 ps
CPU time 2976.2 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 02:06:19 PM PDT 24
Peak memory 374884 kb
Host smart-135d3f35-89d3-43f9-a888-6e32cd63cde2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157034406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.sram_ctrl_stress_all.3157034406
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1003229968
Short name T824
Test name
Test status
Simulation time 609961058 ps
CPU time 40.94 seconds
Started Mar 24 01:17:01 PM PDT 24
Finished Mar 24 01:17:42 PM PDT 24
Peak memory 302056 kb
Host smart-c5297ce2-4db5-4a27-bc87-fb6d0a3ed31b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1003229968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1003229968
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3884665858
Short name T462
Test name
Test status
Simulation time 2342509288 ps
CPU time 211.3 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:20:14 PM PDT 24
Peak memory 202108 kb
Host smart-63503c22-88e5-4091-ba53-cb1e6a77b59a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884665858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.3884665858
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1402259274
Short name T171
Test name
Test status
Simulation time 110136434 ps
CPU time 34.46 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:17:18 PM PDT 24
Peak memory 304532 kb
Host smart-80179461-2ce9-4ae3-ab90-5f3a038e118c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402259274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1402259274
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2688775135
Short name T815
Test name
Test status
Simulation time 1909245796 ps
CPU time 153.25 seconds
Started Mar 24 01:16:45 PM PDT 24
Finished Mar 24 01:19:18 PM PDT 24
Peak memory 334884 kb
Host smart-f90dda52-2346-4fed-a396-2ca71f8cb162
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688775135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.2688775135
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.3852062882
Short name T249
Test name
Test status
Simulation time 12751231 ps
CPU time 0.63 seconds
Started Mar 24 01:16:46 PM PDT 24
Finished Mar 24 01:16:47 PM PDT 24
Peak memory 201832 kb
Host smart-a8a05f8d-f8eb-4f03-9660-6c6598ecfa29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852062882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.3852062882
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.3937346498
Short name T413
Test name
Test status
Simulation time 1532628070 ps
CPU time 23.1 seconds
Started Mar 24 01:16:49 PM PDT 24
Finished Mar 24 01:17:12 PM PDT 24
Peak memory 201956 kb
Host smart-d420d792-785d-4445-8808-ab8a51f6b264
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937346498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
3937346498
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.2936295956
Short name T18
Test name
Test status
Simulation time 5043545948 ps
CPU time 1772.8 seconds
Started Mar 24 01:16:41 PM PDT 24
Finished Mar 24 01:46:14 PM PDT 24
Peak memory 372868 kb
Host smart-8d007a52-b21b-4890-b829-082e5d1f1253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936295956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.2936295956
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.4072020301
Short name T555
Test name
Test status
Simulation time 767901304 ps
CPU time 2.62 seconds
Started Mar 24 01:16:44 PM PDT 24
Finished Mar 24 01:16:47 PM PDT 24
Peak memory 213008 kb
Host smart-b77f078a-0519-4d1b-9732-718711825684
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072020301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.4072020301
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.1700630546
Short name T653
Test name
Test status
Simulation time 78495204 ps
CPU time 10.36 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:16:54 PM PDT 24
Peak memory 251108 kb
Host smart-c27bbeaf-bc11-4a5e-af44-c7ec50511a73
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700630546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.1700630546
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.920366573
Short name T748
Test name
Test status
Simulation time 65788876 ps
CPU time 4.41 seconds
Started Mar 24 01:16:57 PM PDT 24
Finished Mar 24 01:17:01 PM PDT 24
Peak memory 210192 kb
Host smart-985f55c7-db77-4a3e-9d2b-047267d947cf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920366573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_mem_partial_access.920366573
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.1628621017
Short name T438
Test name
Test status
Simulation time 3270923643 ps
CPU time 9.73 seconds
Started Mar 24 01:16:45 PM PDT 24
Finished Mar 24 01:16:55 PM PDT 24
Peak memory 201996 kb
Host smart-d231fc4d-f94a-4b65-8965-738cfab8ea9c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628621017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.1628621017
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2980886821
Short name T303
Test name
Test status
Simulation time 3494169638 ps
CPU time 348 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 01:22:30 PM PDT 24
Peak memory 370772 kb
Host smart-a18a76c2-96d3-4faf-ad0f-bc633e499ebf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980886821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2980886821
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.1181267183
Short name T683
Test name
Test status
Simulation time 171494228 ps
CPU time 8.33 seconds
Started Mar 24 01:16:56 PM PDT 24
Finished Mar 24 01:17:05 PM PDT 24
Peak memory 201868 kb
Host smart-35207d86-77e5-4f9b-92c9-b18c4efe7bf8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181267183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.1181267183
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2239236113
Short name T514
Test name
Test status
Simulation time 5213005972 ps
CPU time 373.75 seconds
Started Mar 24 01:16:41 PM PDT 24
Finished Mar 24 01:22:55 PM PDT 24
Peak memory 202056 kb
Host smart-3e04822f-371a-44c6-b10a-4911492299fb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239236113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.2239236113
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.3991501081
Short name T759
Test name
Test status
Simulation time 87303464 ps
CPU time 0.72 seconds
Started Mar 24 01:16:45 PM PDT 24
Finished Mar 24 01:16:46 PM PDT 24
Peak memory 202148 kb
Host smart-dc17e96e-9a94-4ce4-9e0f-4e10925cb3d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991501081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3991501081
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3066669584
Short name T519
Test name
Test status
Simulation time 12657747095 ps
CPU time 997.57 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:33:20 PM PDT 24
Peak memory 372768 kb
Host smart-5ae7f6ba-d3f5-4016-b987-af210642c5ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066669584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3066669584
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.3559034144
Short name T25
Test name
Test status
Simulation time 190652446 ps
CPU time 2.04 seconds
Started Mar 24 01:16:45 PM PDT 24
Finished Mar 24 01:16:47 PM PDT 24
Peak memory 220812 kb
Host smart-c623b203-362d-47b7-a1df-e2ee669931f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559034144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.3559034144
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.2221334607
Short name T890
Test name
Test status
Simulation time 216736001 ps
CPU time 1.31 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:16:45 PM PDT 24
Peak memory 202060 kb
Host smart-fdf8ac87-f24c-45f9-9e33-aca74187093e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221334607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2221334607
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.2926049110
Short name T40
Test name
Test status
Simulation time 22825445364 ps
CPU time 435.3 seconds
Started Mar 24 01:16:58 PM PDT 24
Finished Mar 24 01:24:13 PM PDT 24
Peak memory 357400 kb
Host smart-a6ebd4a7-5c57-487e-97b0-ea1d50177526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926049110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.2926049110
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2674124167
Short name T874
Test name
Test status
Simulation time 297131174 ps
CPU time 5.34 seconds
Started Mar 24 01:17:06 PM PDT 24
Finished Mar 24 01:17:12 PM PDT 24
Peak memory 210388 kb
Host smart-8cfd290f-364b-4e7e-8ee2-0c7a289e621b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2674124167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2674124167
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2357754257
Short name T603
Test name
Test status
Simulation time 3218713965 ps
CPU time 299.7 seconds
Started Mar 24 01:16:50 PM PDT 24
Finished Mar 24 01:21:50 PM PDT 24
Peak memory 202012 kb
Host smart-17dd7424-a64a-4df6-9ea0-5234c9251ae7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357754257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.2357754257
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3439803427
Short name T868
Test name
Test status
Simulation time 1146646686 ps
CPU time 57.46 seconds
Started Mar 24 01:16:41 PM PDT 24
Finished Mar 24 01:17:39 PM PDT 24
Peak memory 336932 kb
Host smart-e9b3d72c-cc36-454a-8e2f-fe37bce861e9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439803427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3439803427
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.75142531
Short name T666
Test name
Test status
Simulation time 44705366093 ps
CPU time 1115.37 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:36:01 PM PDT 24
Peak memory 371776 kb
Host smart-9f6c4511-6b68-4373-b634-e80fe989e0fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75142531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.sram_ctrl_access_during_key_req.75142531
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.2799200550
Short name T322
Test name
Test status
Simulation time 13687558 ps
CPU time 0.63 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:27 PM PDT 24
Peak memory 201816 kb
Host smart-2171529a-4e1d-4bb6-9fbf-12ac719d7aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799200550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.2799200550
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.45698149
Short name T583
Test name
Test status
Simulation time 6886718510 ps
CPU time 30.48 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:56 PM PDT 24
Peak memory 202104 kb
Host smart-f4c51109-f657-48ff-b8b0-f05a83bf75ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45698149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.45698149
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.755759408
Short name T423
Test name
Test status
Simulation time 7882251341 ps
CPU time 1404.62 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:40:52 PM PDT 24
Peak memory 371864 kb
Host smart-b61cecf7-0272-4f53-b403-659d83047221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755759408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl
e.755759408
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.3918362929
Short name T440
Test name
Test status
Simulation time 9212251998 ps
CPU time 8.56 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 202112 kb
Host smart-3117c5f8-4b62-4fb6-be5e-efaa9ecf329d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918362929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.3918362929
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.2185507542
Short name T712
Test name
Test status
Simulation time 560008255 ps
CPU time 119.11 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:19:25 PM PDT 24
Peak memory 361536 kb
Host smart-13e3d638-e2de-4174-9138-a652d4e1d877
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185507542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.2185507542
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3625467871
Short name T626
Test name
Test status
Simulation time 47736045 ps
CPU time 2.59 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:28 PM PDT 24
Peak memory 210192 kb
Host smart-5c3e5326-6831-4884-90a5-d591a4262915
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625467871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.3625467871
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.1259702006
Short name T431
Test name
Test status
Simulation time 131260579 ps
CPU time 4.45 seconds
Started Mar 24 01:17:22 PM PDT 24
Finished Mar 24 01:17:27 PM PDT 24
Peak memory 201976 kb
Host smart-9c7c874d-330b-451e-8605-49cb86dc71f4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259702006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.1259702006
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.2957956468
Short name T772
Test name
Test status
Simulation time 21182351312 ps
CPU time 159.11 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:20:05 PM PDT 24
Peak memory 347264 kb
Host smart-154819e6-a496-4159-8f8d-edd8d221e157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957956468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.2957956468
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.2044394853
Short name T52
Test name
Test status
Simulation time 1021582919 ps
CPU time 13.27 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:39 PM PDT 24
Peak memory 251272 kb
Host smart-d78b727f-6863-43a5-a11e-7995d37f5f5f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044394853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.2044394853
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4183147371
Short name T927
Test name
Test status
Simulation time 154471653672 ps
CPU time 471.82 seconds
Started Mar 24 01:17:28 PM PDT 24
Finished Mar 24 01:25:20 PM PDT 24
Peak memory 202064 kb
Host smart-b0ac43fe-e402-42b0-85ff-f68ceb84c076
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183147371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.4183147371
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.1186226007
Short name T658
Test name
Test status
Simulation time 30295826 ps
CPU time 0.76 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:27 PM PDT 24
Peak memory 202164 kb
Host smart-dba2682a-117c-4a6e-ae7f-76bf24f577a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186226007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1186226007
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1683614794
Short name T872
Test name
Test status
Simulation time 55621325408 ps
CPU time 1217.01 seconds
Started Mar 24 01:17:28 PM PDT 24
Finished Mar 24 01:37:45 PM PDT 24
Peak memory 366660 kb
Host smart-c8ed5360-8d08-4bcc-8527-0a3f199a05ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683614794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1683614794
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.3425428656
Short name T500
Test name
Test status
Simulation time 182902502 ps
CPU time 10.18 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:17:37 PM PDT 24
Peak memory 202048 kb
Host smart-4452992b-7e22-4387-88dd-9afdba2b7443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425428656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3425428656
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.831851796
Short name T704
Test name
Test status
Simulation time 46122867014 ps
CPU time 208.95 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:21:01 PM PDT 24
Peak memory 356776 kb
Host smart-a73e78e1-798b-4720-bec0-703ca44723c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831851796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_stress_all.831851796
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2704948131
Short name T803
Test name
Test status
Simulation time 780240576 ps
CPU time 269.76 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:21:55 PM PDT 24
Peak memory 367508 kb
Host smart-b681bfa5-496b-4fc3-aab7-f67e9919ac18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2704948131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.2704948131
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2662465300
Short name T311
Test name
Test status
Simulation time 19683077929 ps
CPU time 251.28 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:21:42 PM PDT 24
Peak memory 202128 kb
Host smart-304d0695-c3e8-4cf0-ac41-260a3d51843c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662465300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.2662465300
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.493594203
Short name T598
Test name
Test status
Simulation time 149290311 ps
CPU time 38.84 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:18:03 PM PDT 24
Peak memory 295656 kb
Host smart-c3c9e567-ddb9-4294-a65e-f0dcedef4cbc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493594203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.493594203
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2619123918
Short name T737
Test name
Test status
Simulation time 30233755023 ps
CPU time 201.98 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:20:48 PM PDT 24
Peak memory 342512 kb
Host smart-0fc69bd9-a05a-4e8f-b4de-8ab23a1f8a94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619123918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.2619123918
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.3678195137
Short name T727
Test name
Test status
Simulation time 23341082 ps
CPU time 0.65 seconds
Started Mar 24 01:17:28 PM PDT 24
Finished Mar 24 01:17:29 PM PDT 24
Peak memory 201812 kb
Host smart-c020ff7a-bb4b-4005-b4c8-64db951b446a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678195137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.3678195137
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.2660600485
Short name T708
Test name
Test status
Simulation time 1079094646 ps
CPU time 34.03 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:18:05 PM PDT 24
Peak memory 202084 kb
Host smart-74ee3366-df48-42c5-bef1-5f2064f11edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660600485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.2660600485
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.3898573251
Short name T551
Test name
Test status
Simulation time 58989433707 ps
CPU time 953.1 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:33:16 PM PDT 24
Peak memory 372916 kb
Host smart-5f167365-fccb-4c2b-b8d2-2bdd12b30ae9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898573251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.3898573251
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.2420940279
Short name T546
Test name
Test status
Simulation time 152368270 ps
CPU time 2.06 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:17:33 PM PDT 24
Peak memory 202092 kb
Host smart-98b21cd2-e326-4cd1-a834-9c65d0078e66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420940279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.2420940279
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.183286672
Short name T492
Test name
Test status
Simulation time 1214119837 ps
CPU time 68.23 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:18:35 PM PDT 24
Peak memory 334864 kb
Host smart-1c49850b-49c1-47a8-9ac5-ced3114a3909
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183286672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.sram_ctrl_max_throughput.183286672
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3005646794
Short name T405
Test name
Test status
Simulation time 171489785 ps
CPU time 5.13 seconds
Started Mar 24 01:17:28 PM PDT 24
Finished Mar 24 01:17:34 PM PDT 24
Peak memory 210140 kb
Host smart-8f712536-b3d3-4528-9ddb-d1e6d243b9f1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005646794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.3005646794
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.1467447580
Short name T559
Test name
Test status
Simulation time 1182714439 ps
CPU time 8.25 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:17:42 PM PDT 24
Peak memory 201912 kb
Host smart-4a411673-38a6-4669-be41-9193fb0857ce
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467447580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.1467447580
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.1739151943
Short name T794
Test name
Test status
Simulation time 13878766968 ps
CPU time 1358.47 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:40:09 PM PDT 24
Peak memory 367748 kb
Host smart-d1efe06e-c76d-42ea-ad3b-8bf990231d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739151943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.1739151943
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.3164627696
Short name T296
Test name
Test status
Simulation time 820397979 ps
CPU time 7.81 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:17:35 PM PDT 24
Peak memory 201972 kb
Host smart-f93760b5-2339-401b-82fa-a2e7ba410f10
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164627696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.3164627696
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.3661758243
Short name T774
Test name
Test status
Simulation time 80836263 ps
CPU time 0.77 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:17:34 PM PDT 24
Peak memory 202160 kb
Host smart-5c42dbbf-bb88-4582-8144-178e10d639ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661758243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3661758243
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.591818451
Short name T133
Test name
Test status
Simulation time 2519524655 ps
CPU time 1087.17 seconds
Started Mar 24 01:17:28 PM PDT 24
Finished Mar 24 01:35:36 PM PDT 24
Peak memory 370888 kb
Host smart-4290ca05-fcb4-478e-8fc0-6252bec798da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591818451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.591818451
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.3182043820
Short name T288
Test name
Test status
Simulation time 305957086 ps
CPU time 4.53 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:17:35 PM PDT 24
Peak memory 202052 kb
Host smart-77918b2d-c4d0-45af-abf7-3a5e59f38b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182043820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3182043820
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.3528699731
Short name T572
Test name
Test status
Simulation time 7230802921 ps
CPU time 310.2 seconds
Started Mar 24 01:17:28 PM PDT 24
Finished Mar 24 01:22:38 PM PDT 24
Peak memory 362100 kb
Host smart-f2bf6516-49fc-400c-9e7b-c9344b5f32ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528699731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.3528699731
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2921418260
Short name T869
Test name
Test status
Simulation time 1677808495 ps
CPU time 86.99 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:18:51 PM PDT 24
Peak memory 380924 kb
Host smart-decaa899-3751-47e0-b1f0-86a0943be177
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2921418260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2921418260
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.414047477
Short name T710
Test name
Test status
Simulation time 12256162602 ps
CPU time 245.93 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:21:31 PM PDT 24
Peak memory 202024 kb
Host smart-a766eb86-e934-4daf-8568-a3fc2f78060c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414047477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.sram_ctrl_stress_pipeline.414047477
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.274088112
Short name T178
Test name
Test status
Simulation time 48561755 ps
CPU time 2.48 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:29 PM PDT 24
Peak memory 216868 kb
Host smart-7cc84b08-5b5b-4f09-8e86-54458a32f5c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274088112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.274088112
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3502085457
Short name T915
Test name
Test status
Simulation time 23246256125 ps
CPU time 916.65 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:32:49 PM PDT 24
Peak memory 373516 kb
Host smart-1df22edc-7389-40ee-9e52-857d66a582df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502085457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.3502085457
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.2714690764
Short name T630
Test name
Test status
Simulation time 11140096 ps
CPU time 0.6 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:17:31 PM PDT 24
Peak memory 201128 kb
Host smart-610fef70-c0c7-4cb5-b6b2-8fad905ddc07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714690764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.2714690764
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.1402027250
Short name T569
Test name
Test status
Simulation time 3252756497 ps
CPU time 19.81 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:17:53 PM PDT 24
Peak memory 202080 kb
Host smart-159af31e-3420-4ae0-adcd-bb26855ac5ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402027250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.1402027250
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.679946977
Short name T647
Test name
Test status
Simulation time 7359925503 ps
CPU time 1213.62 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:37:39 PM PDT 24
Peak memory 369788 kb
Host smart-a9a44693-ae88-4e3a-976d-ac08171cc500
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679946977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executabl
e.679946977
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.3153575163
Short name T942
Test name
Test status
Simulation time 1810695174 ps
CPU time 7.96 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:17:33 PM PDT 24
Peak memory 202068 kb
Host smart-4f3087ad-6089-489d-b2d3-e3c8ba8c6833
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153575163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.3153575163
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.4289760192
Short name T645
Test name
Test status
Simulation time 141679686 ps
CPU time 118.37 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:19:25 PM PDT 24
Peak memory 367368 kb
Host smart-d66428de-3a60-4051-ab6f-d1cf83fbde4a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289760192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.4289760192
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2581820434
Short name T137
Test name
Test status
Simulation time 643880030 ps
CPU time 5.47 seconds
Started Mar 24 01:17:28 PM PDT 24
Finished Mar 24 01:17:34 PM PDT 24
Peak memory 210192 kb
Host smart-b6540ba3-2496-4b78-b828-0fc063a36f53
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581820434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.2581820434
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.1553457788
Short name T806
Test name
Test status
Simulation time 902090526 ps
CPU time 9.71 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 201900 kb
Host smart-6b907b36-8686-484e-b14c-755bbd016f65
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553457788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.1553457788
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.4163445462
Short name T520
Test name
Test status
Simulation time 9680488319 ps
CPU time 960.59 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:33:26 PM PDT 24
Peak memory 370876 kb
Host smart-380bdb13-3ee2-4458-abb5-d21c51b698de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163445462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.4163445462
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.3589293121
Short name T548
Test name
Test status
Simulation time 615745776 ps
CPU time 1.22 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:27 PM PDT 24
Peak memory 201824 kb
Host smart-d9cba1d6-58db-458e-ab14-021aa546321b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589293121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.3589293121
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1973340686
Short name T762
Test name
Test status
Simulation time 16884210394 ps
CPU time 318.37 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:22:44 PM PDT 24
Peak memory 202040 kb
Host smart-44b9ec17-c71b-4f0c-8f01-06344431b3c3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973340686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.1973340686
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.2841629804
Short name T700
Test name
Test status
Simulation time 136958361 ps
CPU time 0.82 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 202144 kb
Host smart-1d061c55-eee2-465c-85f8-5dad96d45fa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841629804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2841629804
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.289487531
Short name T723
Test name
Test status
Simulation time 1280864524 ps
CPU time 80.04 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:18:47 PM PDT 24
Peak memory 325380 kb
Host smart-374f1819-2fe0-40fc-872c-33229790915d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289487531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.289487531
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.3240292994
Short name T529
Test name
Test status
Simulation time 648318777 ps
CPU time 3.11 seconds
Started Mar 24 01:17:28 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 202048 kb
Host smart-4df19f2a-f98c-497f-bfca-6bbfe413e667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240292994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3240292994
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.16551605
Short name T677
Test name
Test status
Simulation time 30410696707 ps
CPU time 2206.54 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:54:20 PM PDT 24
Peak memory 375912 kb
Host smart-ce265b22-cc65-4b76-ad22-cc17f420913b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16551605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.sram_ctrl_stress_all.16551605
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2231352533
Short name T441
Test name
Test status
Simulation time 1400607263 ps
CPU time 37.56 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:18:09 PM PDT 24
Peak memory 227808 kb
Host smart-31e34558-60bf-4bc9-a7c1-c324c0f66415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2231352533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2231352533
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1946368901
Short name T451
Test name
Test status
Simulation time 3652775205 ps
CPU time 272.45 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:22:06 PM PDT 24
Peak memory 202028 kb
Host smart-eb1736fc-a134-4356-add8-73d27f91927d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946368901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.1946368901
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2476356942
Short name T925
Test name
Test status
Simulation time 137130112 ps
CPU time 94.76 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:19:05 PM PDT 24
Peak memory 344168 kb
Host smart-db930209-379f-4b02-aa2d-2934aefcbbc4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476356942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.2476356942
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1335762508
Short name T672
Test name
Test status
Simulation time 6540215935 ps
CPU time 1062.08 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:35:15 PM PDT 24
Peak memory 372864 kb
Host smart-7a577287-a814-49aa-adc5-8da11cf66476
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335762508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.1335762508
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.3362622136
Short name T615
Test name
Test status
Simulation time 55192083 ps
CPU time 0.65 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 201136 kb
Host smart-eb729bc4-e8f5-46f6-ab0c-cc5da6b7a8ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362622136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.3362622136
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.789740389
Short name T720
Test name
Test status
Simulation time 10175348738 ps
CPU time 59.37 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:18:32 PM PDT 24
Peak memory 202068 kb
Host smart-321f45f0-04b6-42b1-8c52-f3c94b940011
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789740389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.
789740389
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.4144371108
Short name T764
Test name
Test status
Simulation time 1706394941 ps
CPU time 403.9 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:24:15 PM PDT 24
Peak memory 372800 kb
Host smart-8a7c0921-43fd-4eed-b328-66fbbb6b47cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144371108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.4144371108
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.2567381011
Short name T889
Test name
Test status
Simulation time 176962455 ps
CPU time 1.31 seconds
Started Mar 24 01:17:29 PM PDT 24
Finished Mar 24 01:17:31 PM PDT 24
Peak memory 201828 kb
Host smart-3331f9b1-127a-4ce6-a3d1-cd15059bb92d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567381011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.2567381011
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.670993864
Short name T750
Test name
Test status
Simulation time 644613408 ps
CPU time 51.97 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:18:24 PM PDT 24
Peak memory 304332 kb
Host smart-d94c7b2d-a26e-4fa4-9250-79c35d21e3d2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670993864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.sram_ctrl_max_throughput.670993864
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2630069234
Short name T661
Test name
Test status
Simulation time 336185502 ps
CPU time 2.7 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 210420 kb
Host smart-f42f5920-26c0-414c-92b8-084feb02c719
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630069234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.2630069234
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.3783946370
Short name T536
Test name
Test status
Simulation time 907374295 ps
CPU time 5.09 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:17:38 PM PDT 24
Peak memory 201960 kb
Host smart-e08ff52e-44bf-44d4-bb9a-52ccfc89de0f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783946370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.3783946370
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.3913749687
Short name T268
Test name
Test status
Simulation time 8264547152 ps
CPU time 955.14 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:33:28 PM PDT 24
Peak memory 373860 kb
Host smart-e50a7d39-97c0-428f-9658-be9d1f8dc579
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913749687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.3913749687
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.2883386217
Short name T327
Test name
Test status
Simulation time 3433982574 ps
CPU time 14.45 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:17:45 PM PDT 24
Peak memory 202024 kb
Host smart-1020cb98-dd9a-428e-81de-ea50e5d83c1d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883386217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.2883386217
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.595415645
Short name T799
Test name
Test status
Simulation time 38955458044 ps
CPU time 446.06 seconds
Started Mar 24 01:17:35 PM PDT 24
Finished Mar 24 01:25:01 PM PDT 24
Peak memory 202004 kb
Host smart-71f492d6-5f46-4ca1-a127-cd755b4bd553
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595415645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.sram_ctrl_partial_access_b2b.595415645
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.1870870679
Short name T853
Test name
Test status
Simulation time 3831900455 ps
CPU time 16.89 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:17:47 PM PDT 24
Peak memory 202052 kb
Host smart-9223ccdb-c72f-4e6c-a4e3-b6ba331eaacb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870870679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1870870679
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.563707275
Short name T433
Test name
Test status
Simulation time 4250723147 ps
CPU time 520.35 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:26:13 PM PDT 24
Peak memory 356792 kb
Host smart-b20f9b65-ae64-4fa6-a7bd-1c1111bfd30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563707275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_stress_all.563707275
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.394018892
Short name T420
Test name
Test status
Simulation time 6304880017 ps
CPU time 73.61 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:18:40 PM PDT 24
Peak memory 307328 kb
Host smart-230ed901-292e-4e8b-bc1d-51f451a886dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=394018892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.394018892
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3034055984
Short name T316
Test name
Test status
Simulation time 2588283734 ps
CPU time 238.36 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:21:31 PM PDT 24
Peak memory 202032 kb
Host smart-c50f19fc-3faf-4d2e-9cdd-aa0cd8ee0ebb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034055984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.3034055984
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3491135050
Short name T12
Test name
Test status
Simulation time 557502623 ps
CPU time 105.11 seconds
Started Mar 24 01:17:35 PM PDT 24
Finished Mar 24 01:19:20 PM PDT 24
Peak memory 349208 kb
Host smart-6cb901c9-5e25-4025-9510-63eaebf41ee5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491135050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3491135050
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2552613105
Short name T477
Test name
Test status
Simulation time 1561137656 ps
CPU time 271.88 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:22:00 PM PDT 24
Peak memory 322488 kb
Host smart-125ed08a-dc4f-4e13-acc5-ff3a54a1aaa6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552613105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.2552613105
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.3346611254
Short name T22
Test name
Test status
Simulation time 37632303 ps
CPU time 0.65 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:17:33 PM PDT 24
Peak memory 201212 kb
Host smart-d2039fb8-7313-4a28-94f0-57790a52b42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346611254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.3346611254
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.2364451073
Short name T483
Test name
Test status
Simulation time 1178272265 ps
CPU time 26.07 seconds
Started Mar 24 01:17:34 PM PDT 24
Finished Mar 24 01:18:00 PM PDT 24
Peak memory 202056 kb
Host smart-809db6bc-82bb-459d-851a-b46262d4fb6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364451073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.2364451073
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.2481402541
Short name T212
Test name
Test status
Simulation time 25049438478 ps
CPU time 862.31 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:31:48 PM PDT 24
Peak memory 369764 kb
Host smart-993efa38-ca6a-4410-a318-df82e8de30ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481402541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.2481402541
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.2290951545
Short name T862
Test name
Test status
Simulation time 2017615162 ps
CPU time 6.79 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:17:34 PM PDT 24
Peak memory 202040 kb
Host smart-843846c7-7972-4732-98e4-9c32b0eec8a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290951545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.2290951545
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.2734045392
Short name T625
Test name
Test status
Simulation time 136988151 ps
CPU time 5.34 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:31 PM PDT 24
Peak memory 234204 kb
Host smart-0e0733b9-1ef6-4cea-973e-189a231a52ec
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734045392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.2734045392
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2869010945
Short name T273
Test name
Test status
Simulation time 48402372 ps
CPU time 2.46 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 210188 kb
Host smart-54970d08-fb1e-4ebd-860a-8dd0e843f4f3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869010945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.2869010945
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.1218805537
Short name T908
Test name
Test status
Simulation time 4707654947 ps
CPU time 10.25 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:17:43 PM PDT 24
Peak memory 202208 kb
Host smart-bde69da1-0c1f-44a9-a740-b80a4eba9a29
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218805537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.1218805537
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.3676239311
Short name T584
Test name
Test status
Simulation time 12211945918 ps
CPU time 682.75 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:28:50 PM PDT 24
Peak memory 359560 kb
Host smart-f6e1a60b-0ea6-44a7-9c4d-4dd1a16f4c3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676239311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.3676239311
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.733455695
Short name T526
Test name
Test status
Simulation time 942454390 ps
CPU time 39.47 seconds
Started Mar 24 01:17:34 PM PDT 24
Finished Mar 24 01:18:13 PM PDT 24
Peak memory 285324 kb
Host smart-b2300efd-2e49-446c-aaff-93a4b381b918
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733455695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s
ram_ctrl_partial_access.733455695
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.609936767
Short name T437
Test name
Test status
Simulation time 103475404308 ps
CPU time 574.37 seconds
Started Mar 24 01:17:35 PM PDT 24
Finished Mar 24 01:27:10 PM PDT 24
Peak memory 202004 kb
Host smart-a225a13e-2c6d-468a-b25d-f1ce85634336
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609936767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.sram_ctrl_partial_access_b2b.609936767
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.2650377260
Short name T210
Test name
Test status
Simulation time 85302875 ps
CPU time 0.75 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 202148 kb
Host smart-1c77696f-e804-420f-be2a-34ed068ec7fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650377260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2650377260
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.1653675342
Short name T476
Test name
Test status
Simulation time 23731398434 ps
CPU time 842.3 seconds
Started Mar 24 01:17:34 PM PDT 24
Finished Mar 24 01:31:36 PM PDT 24
Peak memory 374928 kb
Host smart-82b221f9-2c5e-4298-9bb5-79d678f12bc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653675342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1653675342
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.2666457057
Short name T746
Test name
Test status
Simulation time 625831168 ps
CPU time 12.61 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:17:43 PM PDT 24
Peak memory 202020 kb
Host smart-6d588cef-9993-4f77-8480-f662d50391b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666457057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2666457057
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.2099428243
Short name T489
Test name
Test status
Simulation time 8158689680 ps
CPU time 1736.02 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:46:27 PM PDT 24
Peak memory 366696 kb
Host smart-d2eba36e-80d1-48bc-ae65-d3030d2c5574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099428243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.2099428243
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1862121174
Short name T651
Test name
Test status
Simulation time 826472592 ps
CPU time 7.05 seconds
Started Mar 24 01:17:28 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 211328 kb
Host smart-87449f45-6532-40ba-ac94-5c1a515d809c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1862121174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1862121174
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.360880865
Short name T367
Test name
Test status
Simulation time 3898189375 ps
CPU time 190.81 seconds
Started Mar 24 01:17:35 PM PDT 24
Finished Mar 24 01:20:46 PM PDT 24
Peak memory 202004 kb
Host smart-4d74c09e-03dd-446a-bb9a-cd4dfef81bc0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360880865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.sram_ctrl_stress_pipeline.360880865
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3345000466
Short name T153
Test name
Test status
Simulation time 102177436 ps
CPU time 29.21 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:17:57 PM PDT 24
Peak memory 290428 kb
Host smart-9a477bde-3b05-4996-b166-237eacec1c91
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345000466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3345000466
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1388377368
Short name T701
Test name
Test status
Simulation time 6214932036 ps
CPU time 557.93 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:26:51 PM PDT 24
Peak memory 368672 kb
Host smart-303111c8-5878-4287-9e70-d46ab8535a79
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388377368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.1388377368
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.3290952936
Short name T888
Test name
Test status
Simulation time 31072935 ps
CPU time 0.59 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:17:31 PM PDT 24
Peak memory 201128 kb
Host smart-cd8d72ac-0d56-40f5-b8b2-7de770fc961c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290952936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.3290952936
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.869765913
Short name T194
Test name
Test status
Simulation time 556247807 ps
CPU time 16.59 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:17:48 PM PDT 24
Peak memory 202240 kb
Host smart-c156b5be-dacc-45f0-b414-23e6da4010b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869765913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.
869765913
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.1410278745
Short name T926
Test name
Test status
Simulation time 19222855647 ps
CPU time 3225.38 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 02:11:16 PM PDT 24
Peak memory 373860 kb
Host smart-400b3cb1-4f69-4d9e-9a67-ea8365150e1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410278745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.1410278745
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.1138009831
Short name T619
Test name
Test status
Simulation time 115525491 ps
CPU time 1.73 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:17:34 PM PDT 24
Peak memory 202060 kb
Host smart-84c020f0-4c9c-4d94-9fe9-ab53aa2de9c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138009831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.1138009831
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.3472256324
Short name T359
Test name
Test status
Simulation time 470511132 ps
CPU time 28.66 seconds
Started Mar 24 01:17:29 PM PDT 24
Finished Mar 24 01:17:57 PM PDT 24
Peak memory 290228 kb
Host smart-2fd9e9cd-cec0-443b-83ca-4f89cca12649
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472256324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.3472256324
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3939490053
Short name T220
Test name
Test status
Simulation time 297374780 ps
CPU time 2.8 seconds
Started Mar 24 01:17:36 PM PDT 24
Finished Mar 24 01:17:39 PM PDT 24
Peak memory 209736 kb
Host smart-5d0ebaad-e301-49c9-afb2-622b96c36680
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939490053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.3939490053
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.2903481055
Short name T255
Test name
Test status
Simulation time 596563104 ps
CPU time 9.98 seconds
Started Mar 24 01:17:34 PM PDT 24
Finished Mar 24 01:17:44 PM PDT 24
Peak memory 201920 kb
Host smart-c45fd280-6095-487e-8e2e-49dd1e610062
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903481055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.2903481055
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.3902688210
Short name T648
Test name
Test status
Simulation time 1178787170 ps
CPU time 13.96 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:17:47 PM PDT 24
Peak memory 208528 kb
Host smart-b500e19a-19d2-414a-8421-5933a58ad894
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902688210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.3902688210
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.599616062
Short name T608
Test name
Test status
Simulation time 3564112793 ps
CPU time 16.95 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:17:48 PM PDT 24
Peak memory 201980 kb
Host smart-c24a03c0-5ded-46fe-887d-64888fbe5db4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599616062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s
ram_ctrl_partial_access.599616062
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3240295912
Short name T213
Test name
Test status
Simulation time 16100939526 ps
CPU time 269 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:22:02 PM PDT 24
Peak memory 202220 kb
Host smart-ca43226f-8ec1-46cc-9463-29ff518a08f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240295912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.3240295912
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.1075502080
Short name T776
Test name
Test status
Simulation time 139049964 ps
CPU time 0.81 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 202108 kb
Host smart-d0eb2e6e-22e1-41d2-9a49-fc0af230f060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075502080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1075502080
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.234182860
Short name T41
Test name
Test status
Simulation time 8786295140 ps
CPU time 841.05 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:31:32 PM PDT 24
Peak memory 370848 kb
Host smart-03f21ead-5f61-4a6d-a5c9-5cb34756a0df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234182860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.234182860
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.589705897
Short name T604
Test name
Test status
Simulation time 78939136 ps
CPU time 18.29 seconds
Started Mar 24 01:17:35 PM PDT 24
Finished Mar 24 01:17:53 PM PDT 24
Peak memory 273360 kb
Host smart-b0dbea1a-7594-4ddc-a930-2ed52e966509
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589705897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.589705897
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.786604890
Short name T523
Test name
Test status
Simulation time 230707765276 ps
CPU time 5210.31 seconds
Started Mar 24 01:17:38 PM PDT 24
Finished Mar 24 02:44:29 PM PDT 24
Peak memory 382208 kb
Host smart-9b3a115d-5c5f-4b2c-8aa5-968fc7aa5677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786604890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_stress_all.786604890
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1536212823
Short name T116
Test name
Test status
Simulation time 989605199 ps
CPU time 26.97 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:17:59 PM PDT 24
Peak memory 210392 kb
Host smart-f47acf32-b43f-4963-ab57-ef302b2d4db5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1536212823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.1536212823
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.493584238
Short name T209
Test name
Test status
Simulation time 8587647162 ps
CPU time 200.66 seconds
Started Mar 24 01:17:34 PM PDT 24
Finished Mar 24 01:20:54 PM PDT 24
Peak memory 202100 kb
Host smart-003fe1fc-db7e-4744-9b2e-ea6f5cf776b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493584238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_stress_pipeline.493584238
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4068243663
Short name T235
Test name
Test status
Simulation time 120529705 ps
CPU time 5.99 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:17:38 PM PDT 24
Peak memory 234776 kb
Host smart-0d9a24a9-3bce-4de9-97ae-07b81f1a8aeb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068243663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.4068243663
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2951282467
Short name T81
Test name
Test status
Simulation time 4588653696 ps
CPU time 1068.08 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:35:18 PM PDT 24
Peak memory 372808 kb
Host smart-3bf0e230-5c2d-4965-a324-9f7f08a9fd39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951282467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.2951282467
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.3310752666
Short name T760
Test name
Test status
Simulation time 18183114 ps
CPU time 0.63 seconds
Started Mar 24 01:17:35 PM PDT 24
Finished Mar 24 01:17:35 PM PDT 24
Peak memory 201804 kb
Host smart-76dc0169-935e-4704-b5fd-2dd68f0d07f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310752666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.3310752666
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1381187546
Short name T226
Test name
Test status
Simulation time 3617882233 ps
CPU time 79.08 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:18:53 PM PDT 24
Peak memory 202084 kb
Host smart-3575bbde-d982-4cd6-9836-6e1dfadc7df8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381187546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1381187546
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.2916390635
Short name T920
Test name
Test status
Simulation time 3809004419 ps
CPU time 1701.39 seconds
Started Mar 24 01:17:36 PM PDT 24
Finished Mar 24 01:45:57 PM PDT 24
Peak memory 372832 kb
Host smart-47bafb0c-9234-4004-81e7-1304ffee950e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916390635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.2916390635
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.3149348527
Short name T571
Test name
Test status
Simulation time 800245871 ps
CPU time 8.2 seconds
Started Mar 24 01:17:32 PM PDT 24
Finished Mar 24 01:17:40 PM PDT 24
Peak memory 202092 kb
Host smart-c4390b85-d1c8-4025-9426-51a8bc6099ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149348527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.3149348527
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.1477030023
Short name T895
Test name
Test status
Simulation time 41409816 ps
CPU time 1.85 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 210756 kb
Host smart-cab94f86-5a9f-44a8-8269-0308f7a1a534
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477030023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.1477030023
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1981544329
Short name T242
Test name
Test status
Simulation time 160693929 ps
CPU time 5.07 seconds
Started Mar 24 01:17:39 PM PDT 24
Finished Mar 24 01:17:44 PM PDT 24
Peak memory 210216 kb
Host smart-742a5b08-10f9-43b5-8411-7b2a97bb4eea
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981544329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.1981544329
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.1212668087
Short name T358
Test name
Test status
Simulation time 3265161235 ps
CPU time 10.3 seconds
Started Mar 24 01:17:37 PM PDT 24
Finished Mar 24 01:17:47 PM PDT 24
Peak memory 201992 kb
Host smart-bf218e07-78be-41bc-a50e-142969368d06
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212668087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.1212668087
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.1693422869
Short name T380
Test name
Test status
Simulation time 54014592840 ps
CPU time 633.96 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:28:07 PM PDT 24
Peak memory 373136 kb
Host smart-3b136e2d-e204-4fa3-b505-fffb055cd5a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693422869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.1693422869
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.403139929
Short name T873
Test name
Test status
Simulation time 1035587009 ps
CPU time 13.4 seconds
Started Mar 24 01:17:36 PM PDT 24
Finished Mar 24 01:17:49 PM PDT 24
Peak memory 245436 kb
Host smart-41f2f01d-d481-4ecb-9f68-621cb5242e34
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403139929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s
ram_ctrl_partial_access.403139929
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.311959525
Short name T342
Test name
Test status
Simulation time 61859621804 ps
CPU time 477.37 seconds
Started Mar 24 01:17:37 PM PDT 24
Finished Mar 24 01:25:35 PM PDT 24
Peak memory 202004 kb
Host smart-72e6647c-22d4-470b-8fc0-77ce9b928183
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311959525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.sram_ctrl_partial_access_b2b.311959525
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.3314590464
Short name T348
Test name
Test status
Simulation time 27917120 ps
CPU time 0.81 seconds
Started Mar 24 01:17:36 PM PDT 24
Finished Mar 24 01:17:37 PM PDT 24
Peak memory 202148 kb
Host smart-31873c82-bbe3-4e8c-a107-7f93aea1b6c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314590464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3314590464
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.4104314135
Short name T894
Test name
Test status
Simulation time 9261157972 ps
CPU time 415.02 seconds
Started Mar 24 01:17:39 PM PDT 24
Finished Mar 24 01:24:35 PM PDT 24
Peak memory 368744 kb
Host smart-0a56fb01-a113-4aff-91f6-8789162ef5b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104314135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.4104314135
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.1406052557
Short name T369
Test name
Test status
Simulation time 1807300641 ps
CPU time 7.65 seconds
Started Mar 24 01:17:31 PM PDT 24
Finished Mar 24 01:17:39 PM PDT 24
Peak memory 202028 kb
Host smart-1627f241-b762-4f3b-b650-2cf2e550d80f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406052557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1406052557
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.2017781478
Short name T595
Test name
Test status
Simulation time 12906518013 ps
CPU time 1256.21 seconds
Started Mar 24 01:17:40 PM PDT 24
Finished Mar 24 01:38:37 PM PDT 24
Peak memory 373800 kb
Host smart-0cf33f4a-0117-458e-b8e5-91b39f83d3fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017781478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.2017781478
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3261317321
Short name T313
Test name
Test status
Simulation time 3646697065 ps
CPU time 46.16 seconds
Started Mar 24 01:17:36 PM PDT 24
Finished Mar 24 01:18:23 PM PDT 24
Peak memory 302728 kb
Host smart-e4a52b80-8916-4d65-8e6e-c04a51ea1831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3261317321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3261317321
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2819851290
Short name T944
Test name
Test status
Simulation time 21520595882 ps
CPU time 337.37 seconds
Started Mar 24 01:17:33 PM PDT 24
Finished Mar 24 01:23:11 PM PDT 24
Peak memory 202056 kb
Host smart-e4ba6718-77f9-41e5-bc53-63268201cd5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819851290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.2819851290
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2860183475
Short name T400
Test name
Test status
Simulation time 238751491 ps
CPU time 36.43 seconds
Started Mar 24 01:17:30 PM PDT 24
Finished Mar 24 01:18:06 PM PDT 24
Peak memory 291284 kb
Host smart-51d5e66e-1a94-4ca7-9f86-491fa224ee74
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860183475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2860183475
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2485415229
Short name T678
Test name
Test status
Simulation time 2983781140 ps
CPU time 1020.22 seconds
Started Mar 24 01:17:37 PM PDT 24
Finished Mar 24 01:34:37 PM PDT 24
Peak memory 373644 kb
Host smart-6eb86949-dd5a-4e34-b01c-1893d172c662
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485415229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.2485415229
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.1801780235
Short name T172
Test name
Test status
Simulation time 19248752 ps
CPU time 0.63 seconds
Started Mar 24 01:17:43 PM PDT 24
Finished Mar 24 01:17:44 PM PDT 24
Peak memory 200940 kb
Host smart-06424741-237a-4c7a-ae8a-918e8f63d2df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801780235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.1801780235
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.1554800148
Short name T685
Test name
Test status
Simulation time 3171623680 ps
CPU time 54.28 seconds
Started Mar 24 01:17:34 PM PDT 24
Finished Mar 24 01:18:29 PM PDT 24
Peak memory 202140 kb
Host smart-667f672d-37ba-41fe-9286-13183069a741
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554800148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.1554800148
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.3384908907
Short name T899
Test name
Test status
Simulation time 3578889151 ps
CPU time 236.22 seconds
Started Mar 24 01:17:35 PM PDT 24
Finished Mar 24 01:21:32 PM PDT 24
Peak memory 362376 kb
Host smart-592e39e2-eacd-43bd-a631-91f1024f1998
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384908907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.3384908907
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.342309350
Short name T325
Test name
Test status
Simulation time 191498110 ps
CPU time 2.28 seconds
Started Mar 24 01:17:38 PM PDT 24
Finished Mar 24 01:17:40 PM PDT 24
Peak memory 202024 kb
Host smart-dee7f686-3b18-4b88-ad6e-28066ec35ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342309350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esc
alation.342309350
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.252761766
Short name T936
Test name
Test status
Simulation time 105429244 ps
CPU time 46.19 seconds
Started Mar 24 01:17:34 PM PDT 24
Finished Mar 24 01:18:20 PM PDT 24
Peak memory 301000 kb
Host smart-591990c1-a30b-4d22-87eb-2fa0a6ef678f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252761766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.sram_ctrl_max_throughput.252761766
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.513074981
Short name T82
Test name
Test status
Simulation time 102231994 ps
CPU time 2.79 seconds
Started Mar 24 01:17:40 PM PDT 24
Finished Mar 24 01:17:44 PM PDT 24
Peak memory 210160 kb
Host smart-27cc3684-b45c-40e0-9cee-51773c60342b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513074981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_mem_partial_access.513074981
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.3695126572
Short name T596
Test name
Test status
Simulation time 453892324 ps
CPU time 9.16 seconds
Started Mar 24 01:17:36 PM PDT 24
Finished Mar 24 01:17:45 PM PDT 24
Peak memory 201916 kb
Host smart-900e5265-9814-4c6a-b7d2-43a2c48e43f2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695126572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.3695126572
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.3890017471
Short name T350
Test name
Test status
Simulation time 49462031795 ps
CPU time 703.45 seconds
Started Mar 24 01:17:38 PM PDT 24
Finished Mar 24 01:29:21 PM PDT 24
Peak memory 370620 kb
Host smart-27c32081-26e8-4aa9-b812-3c300a43318e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890017471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.3890017471
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.1618422996
Short name T173
Test name
Test status
Simulation time 193341178 ps
CPU time 73.67 seconds
Started Mar 24 01:17:36 PM PDT 24
Finished Mar 24 01:18:49 PM PDT 24
Peak memory 339916 kb
Host smart-2aa8e809-1cda-4da1-b3ff-37f4b6319695
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618422996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.1618422996
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3567701227
Short name T530
Test name
Test status
Simulation time 13197243996 ps
CPU time 309.56 seconds
Started Mar 24 01:17:34 PM PDT 24
Finished Mar 24 01:22:44 PM PDT 24
Peak memory 202064 kb
Host smart-e110ff2f-7960-4012-9659-c9c404f987f5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567701227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.3567701227
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.2969213235
Short name T258
Test name
Test status
Simulation time 88054744 ps
CPU time 0.72 seconds
Started Mar 24 01:17:35 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 202136 kb
Host smart-1cc247ed-af3d-46b1-833c-359e8f4112fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969213235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2969213235
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.3181588306
Short name T857
Test name
Test status
Simulation time 9463111293 ps
CPU time 538.4 seconds
Started Mar 24 01:17:36 PM PDT 24
Finished Mar 24 01:26:35 PM PDT 24
Peak memory 369344 kb
Host smart-8b607385-70c7-4d8d-ba82-c77fb6dfc6df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181588306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3181588306
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.960570181
Short name T605
Test name
Test status
Simulation time 763854257 ps
CPU time 12.68 seconds
Started Mar 24 01:17:38 PM PDT 24
Finished Mar 24 01:17:51 PM PDT 24
Peak memory 201996 kb
Host smart-913481f8-d392-4f80-b49c-b66d7369696d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960570181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.960570181
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.2643944053
Short name T534
Test name
Test status
Simulation time 11169734064 ps
CPU time 3832.35 seconds
Started Mar 24 01:17:42 PM PDT 24
Finished Mar 24 02:21:35 PM PDT 24
Peak memory 381960 kb
Host smart-1c03aca5-c77a-4bed-a9ba-deb057c1c0f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643944053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.sram_ctrl_stress_all.2643944053
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.652414455
Short name T547
Test name
Test status
Simulation time 12317466957 ps
CPU time 262.44 seconds
Started Mar 24 01:17:40 PM PDT 24
Finished Mar 24 01:22:02 PM PDT 24
Peak memory 202108 kb
Host smart-91123438-d4cd-44c5-ab30-8ba3d0858a4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652414455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_stress_pipeline.652414455
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.489209643
Short name T180
Test name
Test status
Simulation time 838096931 ps
CPU time 123.64 seconds
Started Mar 24 01:17:38 PM PDT 24
Finished Mar 24 01:19:41 PM PDT 24
Peak memory 339876 kb
Host smart-5de3cd1e-faf6-4c50-a746-0cba879933c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489209643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_throughput_w_partial_write.489209643
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1612797470
Short name T399
Test name
Test status
Simulation time 4603478824 ps
CPU time 1081.58 seconds
Started Mar 24 01:17:43 PM PDT 24
Finished Mar 24 01:35:45 PM PDT 24
Peak memory 372720 kb
Host smart-3ad0ee06-1558-4341-9255-9a1ec5d66254
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612797470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.1612797470
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.788533447
Short name T20
Test name
Test status
Simulation time 33731335 ps
CPU time 0.6 seconds
Started Mar 24 01:17:43 PM PDT 24
Finished Mar 24 01:17:44 PM PDT 24
Peak memory 200936 kb
Host smart-2427d8bb-0184-47cb-9498-31a170db187b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788533447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.788533447
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.2549818755
Short name T830
Test name
Test status
Simulation time 2087487245 ps
CPU time 33.33 seconds
Started Mar 24 01:17:42 PM PDT 24
Finished Mar 24 01:18:16 PM PDT 24
Peak memory 202112 kb
Host smart-8f2ab4eb-64e1-4ac0-bd0c-fa48d9b22389
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549818755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.2549818755
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.2037009623
Short name T151
Test name
Test status
Simulation time 45834842744 ps
CPU time 1080.34 seconds
Started Mar 24 01:17:40 PM PDT 24
Finished Mar 24 01:35:41 PM PDT 24
Peak memory 373956 kb
Host smart-76b454af-b10c-498b-bc1d-3721828220ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037009623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.2037009623
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.691078125
Short name T401
Test name
Test status
Simulation time 247299172 ps
CPU time 2.39 seconds
Started Mar 24 01:17:42 PM PDT 24
Finished Mar 24 01:17:45 PM PDT 24
Peak memory 201980 kb
Host smart-0e373711-832d-421d-9285-ea30d37daa9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691078125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc
alation.691078125
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.961126195
Short name T211
Test name
Test status
Simulation time 176303458 ps
CPU time 34.95 seconds
Started Mar 24 01:17:41 PM PDT 24
Finished Mar 24 01:18:16 PM PDT 24
Peak memory 287784 kb
Host smart-3427c82c-0258-42d1-aadd-4a081e4905b2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961126195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.sram_ctrl_max_throughput.961126195
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.3220619620
Short name T238
Test name
Test status
Simulation time 2937001660 ps
CPU time 5.53 seconds
Started Mar 24 01:17:44 PM PDT 24
Finished Mar 24 01:17:49 PM PDT 24
Peak memory 210480 kb
Host smart-5ac1bf4d-0a5f-4e8d-9877-5fa898e89b8e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220619620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.3220619620
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.2379925063
Short name T540
Test name
Test status
Simulation time 1813855623 ps
CPU time 9.54 seconds
Started Mar 24 01:17:40 PM PDT 24
Finished Mar 24 01:17:49 PM PDT 24
Peak memory 201952 kb
Host smart-fa9bd78b-f79f-4f3f-9e11-f2887aae9a10
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379925063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.2379925063
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.146425645
Short name T140
Test name
Test status
Simulation time 90313193919 ps
CPU time 1978.95 seconds
Started Mar 24 01:17:42 PM PDT 24
Finished Mar 24 01:50:42 PM PDT 24
Peak memory 374872 kb
Host smart-badd5ef7-3a00-46c6-8526-3815cb0f439f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146425645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip
le_keys.146425645
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.2921099041
Short name T445
Test name
Test status
Simulation time 701995946 ps
CPU time 32.23 seconds
Started Mar 24 01:17:42 PM PDT 24
Finished Mar 24 01:18:15 PM PDT 24
Peak memory 283736 kb
Host smart-80254f1b-35a3-46ec-999a-0feffd4f5197
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921099041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.2921099041
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2574526802
Short name T613
Test name
Test status
Simulation time 18589223625 ps
CPU time 302.18 seconds
Started Mar 24 01:17:46 PM PDT 24
Finished Mar 24 01:22:49 PM PDT 24
Peak memory 202040 kb
Host smart-33fd38ac-51c6-4da9-9d0c-eb912f4cea97
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574526802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.2574526802
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.2708193162
Short name T452
Test name
Test status
Simulation time 28449266 ps
CPU time 0.75 seconds
Started Mar 24 01:17:40 PM PDT 24
Finished Mar 24 01:17:41 PM PDT 24
Peak memory 202176 kb
Host smart-db1b06b8-eff8-464b-8926-be532df51ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708193162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2708193162
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.1017074307
Short name T289
Test name
Test status
Simulation time 3483375348 ps
CPU time 298.01 seconds
Started Mar 24 01:17:44 PM PDT 24
Finished Mar 24 01:22:43 PM PDT 24
Peak memory 358552 kb
Host smart-f2c756c0-277b-4d79-89b2-aca399d7b7d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017074307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1017074307
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.1850463559
Short name T602
Test name
Test status
Simulation time 678073202 ps
CPU time 10.2 seconds
Started Mar 24 01:17:42 PM PDT 24
Finished Mar 24 01:17:53 PM PDT 24
Peak memory 202012 kb
Host smart-0f859561-d417-48a4-adb4-962b79617130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850463559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1850463559
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.1440566120
Short name T621
Test name
Test status
Simulation time 22982784382 ps
CPU time 929.17 seconds
Started Mar 24 01:17:44 PM PDT 24
Finished Mar 24 01:33:14 PM PDT 24
Peak memory 364028 kb
Host smart-dd34acc9-bbd8-47a4-90f4-f13e9f0b29cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440566120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.1440566120
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.361619609
Short name T111
Test name
Test status
Simulation time 2228758412 ps
CPU time 32.35 seconds
Started Mar 24 01:17:49 PM PDT 24
Finished Mar 24 01:18:22 PM PDT 24
Peak memory 211396 kb
Host smart-3ac7e731-a681-4305-8172-4eb2a2dbd0e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=361619609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.361619609
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1029282151
Short name T347
Test name
Test status
Simulation time 3141321256 ps
CPU time 297.51 seconds
Started Mar 24 01:17:43 PM PDT 24
Finished Mar 24 01:22:41 PM PDT 24
Peak memory 202052 kb
Host smart-3dfc7925-fd2f-4a7f-897e-eb0fb14fa723
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029282151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.1029282151
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3839759377
Short name T757
Test name
Test status
Simulation time 512733359 ps
CPU time 83.17 seconds
Started Mar 24 01:17:40 PM PDT 24
Finished Mar 24 01:19:04 PM PDT 24
Peak memory 352924 kb
Host smart-dcde0c22-669d-4728-acd2-1060fe919307
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839759377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3839759377
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.4064372913
Short name T528
Test name
Test status
Simulation time 6814934271 ps
CPU time 1186.8 seconds
Started Mar 24 01:17:52 PM PDT 24
Finished Mar 24 01:37:40 PM PDT 24
Peak memory 365648 kb
Host smart-021c29ae-d32d-4a05-b2cb-b3aebc5f21f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064372913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.4064372913
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.2409195242
Short name T241
Test name
Test status
Simulation time 10516643 ps
CPU time 0.65 seconds
Started Mar 24 01:17:53 PM PDT 24
Finished Mar 24 01:17:54 PM PDT 24
Peak memory 201804 kb
Host smart-251e78ee-d56d-41da-854a-0792f8bd18c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409195242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.2409195242
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.2812996928
Short name T290
Test name
Test status
Simulation time 854238920 ps
CPU time 52.1 seconds
Started Mar 24 01:17:51 PM PDT 24
Finished Mar 24 01:18:43 PM PDT 24
Peak memory 202028 kb
Host smart-cc3797a1-29b9-4d35-bed8-534f54e87452
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812996928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.2812996928
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.437208815
Short name T771
Test name
Test status
Simulation time 2407539283 ps
CPU time 72.13 seconds
Started Mar 24 01:17:49 PM PDT 24
Finished Mar 24 01:19:02 PM PDT 24
Peak memory 306704 kb
Host smart-266b9967-a7ff-458c-9dc8-7ca4ac03ba17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437208815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl
e.437208815
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.3054186640
Short name T893
Test name
Test status
Simulation time 2718550337 ps
CPU time 4.11 seconds
Started Mar 24 01:17:53 PM PDT 24
Finished Mar 24 01:17:58 PM PDT 24
Peak memory 202096 kb
Host smart-dfb939a0-36a3-4c64-80f4-31982c97f9b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054186640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.3054186640
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.3043525566
Short name T265
Test name
Test status
Simulation time 128392501 ps
CPU time 0.9 seconds
Started Mar 24 01:17:51 PM PDT 24
Finished Mar 24 01:17:52 PM PDT 24
Peak memory 201844 kb
Host smart-68853e0a-e23a-43f8-9239-ba95a24a0b6b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043525566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.3043525566
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1068197529
Short name T722
Test name
Test status
Simulation time 489430626 ps
CPU time 5.38 seconds
Started Mar 24 01:17:49 PM PDT 24
Finished Mar 24 01:17:54 PM PDT 24
Peak memory 210180 kb
Host smart-701035a4-8e46-46d0-bb10-845875635054
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068197529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.1068197529
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.1549397633
Short name T896
Test name
Test status
Simulation time 730514856 ps
CPU time 8.42 seconds
Started Mar 24 01:17:50 PM PDT 24
Finished Mar 24 01:17:59 PM PDT 24
Peak memory 201936 kb
Host smart-18016db8-9399-4898-ade3-6b4bdcdc23be
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549397633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.1549397633
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.177656112
Short name T881
Test name
Test status
Simulation time 10278447659 ps
CPU time 849.13 seconds
Started Mar 24 01:17:43 PM PDT 24
Finished Mar 24 01:31:53 PM PDT 24
Peak memory 373808 kb
Host smart-a4e34536-d843-4d29-9bed-5180c9573bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177656112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip
le_keys.177656112
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.2931077132
Short name T206
Test name
Test status
Simulation time 2372338097 ps
CPU time 126.13 seconds
Started Mar 24 01:17:47 PM PDT 24
Finished Mar 24 01:19:53 PM PDT 24
Peak memory 366572 kb
Host smart-8b9d1b8c-0945-455c-a735-8c997d4996fd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931077132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.2931077132
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.350304719
Short name T470
Test name
Test status
Simulation time 127573761891 ps
CPU time 247.21 seconds
Started Mar 24 01:17:43 PM PDT 24
Finished Mar 24 01:21:51 PM PDT 24
Peak memory 201992 kb
Host smart-421a6d0a-9657-494a-8801-b37671288b25
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350304719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.sram_ctrl_partial_access_b2b.350304719
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.1997500216
Short name T564
Test name
Test status
Simulation time 47727128 ps
CPU time 0.75 seconds
Started Mar 24 01:17:49 PM PDT 24
Finished Mar 24 01:17:50 PM PDT 24
Peak memory 202108 kb
Host smart-3dcc639a-8a5e-4506-b9b2-19dd25916daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997500216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1997500216
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.3755552188
Short name T488
Test name
Test status
Simulation time 47271538224 ps
CPU time 626.05 seconds
Started Mar 24 01:17:49 PM PDT 24
Finished Mar 24 01:28:15 PM PDT 24
Peak memory 368772 kb
Host smart-19be0464-0f5d-42e0-bcf7-dabb19d1cf93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755552188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3755552188
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.2337760730
Short name T487
Test name
Test status
Simulation time 622843242 ps
CPU time 9.82 seconds
Started Mar 24 01:17:45 PM PDT 24
Finished Mar 24 01:17:55 PM PDT 24
Peak memory 202024 kb
Host smart-baa2c592-4d59-4a0a-9f11-7ef39b38aca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337760730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2337760730
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.1000380513
Short name T833
Test name
Test status
Simulation time 9814103138 ps
CPU time 800.33 seconds
Started Mar 24 01:17:54 PM PDT 24
Finished Mar 24 01:31:15 PM PDT 24
Peak memory 373784 kb
Host smart-202c4177-17d4-4e4e-adaa-a766f658bf0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000380513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.sram_ctrl_stress_all.1000380513
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2855931636
Short name T773
Test name
Test status
Simulation time 603738470 ps
CPU time 370.42 seconds
Started Mar 24 01:17:58 PM PDT 24
Finished Mar 24 01:24:08 PM PDT 24
Peak memory 376600 kb
Host smart-40a966a2-7bce-4076-8430-81ea31a8105d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2855931636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2855931636
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.4070776467
Short name T448
Test name
Test status
Simulation time 4457582067 ps
CPU time 300.05 seconds
Started Mar 24 01:17:47 PM PDT 24
Finished Mar 24 01:22:47 PM PDT 24
Peak memory 202096 kb
Host smart-e6696a89-9cad-41f1-a4d8-d6bd28e4a2cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070776467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.4070776467
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.4123990551
Short name T406
Test name
Test status
Simulation time 167432489 ps
CPU time 10.41 seconds
Started Mar 24 01:17:43 PM PDT 24
Finished Mar 24 01:17:54 PM PDT 24
Peak memory 242396 kb
Host smart-ee109ea2-2d1e-488f-9ff1-7cc5ef1f404a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123990551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.4123990551
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.3125416977
Short name T831
Test name
Test status
Simulation time 2466806504 ps
CPU time 636.41 seconds
Started Mar 24 01:17:06 PM PDT 24
Finished Mar 24 01:27:43 PM PDT 24
Peak memory 366672 kb
Host smart-2d5ce45a-5f9d-4db3-8556-d17383794d74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125416977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.3125416977
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.4054485379
Short name T497
Test name
Test status
Simulation time 2125300087 ps
CPU time 47.17 seconds
Started Mar 24 01:16:44 PM PDT 24
Finished Mar 24 01:17:31 PM PDT 24
Peak memory 202108 kb
Host smart-124c4203-d0d6-405d-8138-3e9887d3ccfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054485379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
4054485379
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.751437510
Short name T334
Test name
Test status
Simulation time 16033452289 ps
CPU time 147.96 seconds
Started Mar 24 01:16:57 PM PDT 24
Finished Mar 24 01:19:25 PM PDT 24
Peak memory 335024 kb
Host smart-c128044f-f6af-494e-8686-0037074a1b19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751437510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable
.751437510
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.2110202031
Short name T481
Test name
Test status
Simulation time 1763462304 ps
CPU time 7.12 seconds
Started Mar 24 01:17:06 PM PDT 24
Finished Mar 24 01:17:14 PM PDT 24
Peak memory 202052 kb
Host smart-03f01c19-bf49-431b-993c-d3a2481c84fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110202031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.2110202031
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.1817289472
Short name T187
Test name
Test status
Simulation time 93156501 ps
CPU time 31.26 seconds
Started Mar 24 01:16:46 PM PDT 24
Finished Mar 24 01:17:18 PM PDT 24
Peak memory 283872 kb
Host smart-2480fb96-e0c1-4d2f-83cb-bf58f150e0f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817289472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.1817289472
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.4059094060
Short name T312
Test name
Test status
Simulation time 88568897 ps
CPU time 3.12 seconds
Started Mar 24 01:16:59 PM PDT 24
Finished Mar 24 01:17:02 PM PDT 24
Peak memory 210124 kb
Host smart-8232949b-8d86-45c6-b79e-cce950705daf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059094060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.4059094060
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.1913968449
Short name T581
Test name
Test status
Simulation time 589724404 ps
CPU time 9.53 seconds
Started Mar 24 01:16:50 PM PDT 24
Finished Mar 24 01:17:00 PM PDT 24
Peak memory 201932 kb
Host smart-e90df4e4-c158-4539-87ae-2f3d536e3048
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913968449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.1913968449
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.3775578789
Short name T756
Test name
Test status
Simulation time 90441250300 ps
CPU time 591.42 seconds
Started Mar 24 01:16:48 PM PDT 24
Finished Mar 24 01:26:40 PM PDT 24
Peak memory 372672 kb
Host smart-03dfb9a0-bfab-4326-875d-1b5da9ac5622
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775578789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.3775578789
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.2436737341
Short name T352
Test name
Test status
Simulation time 1169477842 ps
CPU time 19.28 seconds
Started Mar 24 01:16:46 PM PDT 24
Finished Mar 24 01:17:05 PM PDT 24
Peak memory 201984 kb
Host smart-f3836cbd-7e4d-4ea9-bb27-cf1da962e7b8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436737341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.2436737341
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.897697669
Short name T674
Test name
Test status
Simulation time 13391648108 ps
CPU time 326.77 seconds
Started Mar 24 01:16:59 PM PDT 24
Finished Mar 24 01:22:26 PM PDT 24
Peak memory 202080 kb
Host smart-2ea636e6-89ef-4e87-9022-2ca049c1a5e2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897697669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.sram_ctrl_partial_access_b2b.897697669
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.729324013
Short name T566
Test name
Test status
Simulation time 46905011 ps
CPU time 0.74 seconds
Started Mar 24 01:16:44 PM PDT 24
Finished Mar 24 01:16:45 PM PDT 24
Peak memory 202140 kb
Host smart-d729c529-78f1-40a9-a5e3-d1a364ca8252
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729324013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.729324013
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.169847285
Short name T930
Test name
Test status
Simulation time 17159208360 ps
CPU time 1611.21 seconds
Started Mar 24 01:16:56 PM PDT 24
Finished Mar 24 01:43:48 PM PDT 24
Peak memory 367684 kb
Host smart-9e84e601-7f57-4b13-8278-6927e4bc77ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169847285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.169847285
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.3300049572
Short name T23
Test name
Test status
Simulation time 897708222 ps
CPU time 2.22 seconds
Started Mar 24 01:16:53 PM PDT 24
Finished Mar 24 01:16:56 PM PDT 24
Peak memory 220924 kb
Host smart-8801835d-8297-43a6-96a1-3548a65c2997
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300049572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.3300049572
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.1505991747
Short name T291
Test name
Test status
Simulation time 69030585 ps
CPU time 3.77 seconds
Started Mar 24 01:16:46 PM PDT 24
Finished Mar 24 01:16:49 PM PDT 24
Peak memory 216364 kb
Host smart-18f2a98d-46da-4e70-80ea-852a86a8b798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505991747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1505991747
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.2793149183
Short name T139
Test name
Test status
Simulation time 81240742080 ps
CPU time 2022.54 seconds
Started Mar 24 01:16:53 PM PDT 24
Finished Mar 24 01:50:36 PM PDT 24
Peak memory 373936 kb
Host smart-0dbdb78e-e61a-4790-9f5b-5d0a725e2c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793149183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.2793149183
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1366504880
Short name T360
Test name
Test status
Simulation time 372330911 ps
CPU time 10.11 seconds
Started Mar 24 01:16:56 PM PDT 24
Finished Mar 24 01:17:07 PM PDT 24
Peak memory 210252 kb
Host smart-b97041de-bbb0-437e-95e2-15c94de8e442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1366504880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1366504880
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.3965265103
Short name T382
Test name
Test status
Simulation time 2789030969 ps
CPU time 266.04 seconds
Started Mar 24 01:16:46 PM PDT 24
Finished Mar 24 01:21:12 PM PDT 24
Peak memory 202008 kb
Host smart-22b51f82-98c2-4613-bbdc-2dbfa2c80a17
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965265103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.3965265103
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1435612770
Short name T693
Test name
Test status
Simulation time 49217833 ps
CPU time 3.16 seconds
Started Mar 24 01:17:04 PM PDT 24
Finished Mar 24 01:17:07 PM PDT 24
Peak memory 218408 kb
Host smart-24781de3-7ed3-48c1-850c-fc7c70d45c15
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435612770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1435612770
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.3271616786
Short name T578
Test name
Test status
Simulation time 39510443 ps
CPU time 0.62 seconds
Started Mar 24 01:18:00 PM PDT 24
Finished Mar 24 01:18:00 PM PDT 24
Peak memory 200928 kb
Host smart-42090566-c17f-4818-9055-74b7996f1d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271616786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.3271616786
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.3579399457
Short name T257
Test name
Test status
Simulation time 2887628890 ps
CPU time 60.29 seconds
Started Mar 24 01:17:55 PM PDT 24
Finished Mar 24 01:18:55 PM PDT 24
Peak memory 202076 kb
Host smart-eb84e53d-93eb-4189-bae2-92585fdb881b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579399457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.3579399457
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.2456220432
Short name T861
Test name
Test status
Simulation time 18799941015 ps
CPU time 1304.22 seconds
Started Mar 24 01:17:56 PM PDT 24
Finished Mar 24 01:39:41 PM PDT 24
Peak memory 374980 kb
Host smart-4a1b7c43-132a-41c1-847a-941d8fe7fe08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456220432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.2456220432
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.3548112942
Short name T502
Test name
Test status
Simulation time 504441398 ps
CPU time 3.74 seconds
Started Mar 24 01:17:54 PM PDT 24
Finished Mar 24 01:17:58 PM PDT 24
Peak memory 201960 kb
Host smart-1c76dc29-f8ed-4f3d-97e2-21904b93925a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548112942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.3548112942
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.100165929
Short name T355
Test name
Test status
Simulation time 77684154 ps
CPU time 14.57 seconds
Started Mar 24 01:17:55 PM PDT 24
Finished Mar 24 01:18:10 PM PDT 24
Peak memory 261388 kb
Host smart-4e4180aa-16ae-460d-9055-debe579143ae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100165929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.sram_ctrl_max_throughput.100165929
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.333019837
Short name T527
Test name
Test status
Simulation time 71318862 ps
CPU time 2.79 seconds
Started Mar 24 01:18:08 PM PDT 24
Finished Mar 24 01:18:11 PM PDT 24
Peak memory 210088 kb
Host smart-9d568033-999b-4490-9144-b68828e1d699
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333019837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.sram_ctrl_mem_partial_access.333019837
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.803923291
Short name T197
Test name
Test status
Simulation time 1275778171 ps
CPU time 5.19 seconds
Started Mar 24 01:17:56 PM PDT 24
Finished Mar 24 01:18:01 PM PDT 24
Peak memory 201920 kb
Host smart-845b4a82-7a06-437f-871d-cf5f05a30099
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803923291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl
_mem_walk.803923291
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.4118442487
Short name T243
Test name
Test status
Simulation time 5712873723 ps
CPU time 372.78 seconds
Started Mar 24 01:18:01 PM PDT 24
Finished Mar 24 01:24:15 PM PDT 24
Peak memory 363892 kb
Host smart-39b69638-be74-428f-9337-14df4c484820
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118442487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.4118442487
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.3440933353
Short name T740
Test name
Test status
Simulation time 41385996 ps
CPU time 1.32 seconds
Started Mar 24 01:17:53 PM PDT 24
Finished Mar 24 01:17:55 PM PDT 24
Peak memory 201828 kb
Host smart-11f4d338-adcc-4c76-af07-caef63c4c99e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440933353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.3440933353
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.902862681
Short name T766
Test name
Test status
Simulation time 5664980439 ps
CPU time 393.09 seconds
Started Mar 24 01:17:55 PM PDT 24
Finished Mar 24 01:24:28 PM PDT 24
Peak memory 202052 kb
Host smart-b764f6cf-3cfa-429d-9415-8641e7d8b87b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902862681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.sram_ctrl_partial_access_b2b.902862681
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.1464936457
Short name T442
Test name
Test status
Simulation time 102963864 ps
CPU time 0.8 seconds
Started Mar 24 01:17:56 PM PDT 24
Finished Mar 24 01:17:57 PM PDT 24
Peak memory 202144 kb
Host smart-51d87f6a-8160-412c-99e4-5176039e3a81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464936457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1464936457
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.2932316592
Short name T905
Test name
Test status
Simulation time 10399661901 ps
CPU time 1074.64 seconds
Started Mar 24 01:17:54 PM PDT 24
Finished Mar 24 01:35:49 PM PDT 24
Peak memory 375864 kb
Host smart-1a3b7efa-069b-4dd6-96f2-e3e7871c76df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932316592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2932316592
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.3426409541
Short name T675
Test name
Test status
Simulation time 196060167 ps
CPU time 4.25 seconds
Started Mar 24 01:17:55 PM PDT 24
Finished Mar 24 01:17:59 PM PDT 24
Peak memory 201984 kb
Host smart-f7cf7f7b-42e7-4eb2-aeae-26c080b73bd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426409541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3426409541
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3341428457
Short name T117
Test name
Test status
Simulation time 883316092 ps
CPU time 30.79 seconds
Started Mar 24 01:18:08 PM PDT 24
Finished Mar 24 01:18:39 PM PDT 24
Peak memory 258876 kb
Host smart-11bad46e-ecaa-4763-a4a1-bfe8e5d61e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3341428457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3341428457
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3955117652
Short name T402
Test name
Test status
Simulation time 3357943583 ps
CPU time 299.51 seconds
Started Mar 24 01:17:54 PM PDT 24
Finished Mar 24 01:22:54 PM PDT 24
Peak memory 202020 kb
Host smart-576bc23b-d49a-4ef9-8a3e-45dbee9bcb4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955117652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.3955117652
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.4273714346
Short name T159
Test name
Test status
Simulation time 415587372 ps
CPU time 53.68 seconds
Started Mar 24 01:17:54 PM PDT 24
Finished Mar 24 01:18:48 PM PDT 24
Peak memory 302288 kb
Host smart-fb37dbfd-daee-43f4-a84f-ac7530f343b2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273714346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.4273714346
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.429972789
Short name T848
Test name
Test status
Simulation time 3373450994 ps
CPU time 882.09 seconds
Started Mar 24 01:18:01 PM PDT 24
Finished Mar 24 01:32:44 PM PDT 24
Peak memory 372692 kb
Host smart-826362a5-34f5-4a89-812b-fa1be75d3ebd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429972789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.sram_ctrl_access_during_key_req.429972789
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.492735794
Short name T166
Test name
Test status
Simulation time 41135340 ps
CPU time 0.63 seconds
Started Mar 24 01:17:58 PM PDT 24
Finished Mar 24 01:17:59 PM PDT 24
Peak memory 201152 kb
Host smart-515998d7-b023-440e-a863-512e6c7021fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492735794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.492735794
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.1857946171
Short name T227
Test name
Test status
Simulation time 3543156823 ps
CPU time 50.27 seconds
Started Mar 24 01:17:59 PM PDT 24
Finished Mar 24 01:18:49 PM PDT 24
Peak memory 202016 kb
Host smart-fef402ed-1418-4527-b641-2138aed27e9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857946171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.1857946171
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.2498216741
Short name T790
Test name
Test status
Simulation time 6230938172 ps
CPU time 1573.29 seconds
Started Mar 24 01:18:02 PM PDT 24
Finished Mar 24 01:44:15 PM PDT 24
Peak memory 373940 kb
Host smart-da444d99-4c4b-4758-a59e-cd229541960c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498216741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.2498216741
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.4152316135
Short name T641
Test name
Test status
Simulation time 1345374389 ps
CPU time 5.6 seconds
Started Mar 24 01:17:58 PM PDT 24
Finished Mar 24 01:18:03 PM PDT 24
Peak memory 202004 kb
Host smart-10fad203-82db-4b97-896d-644aa6ba720b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152316135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.4152316135
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.1048192060
Short name T252
Test name
Test status
Simulation time 525365647 ps
CPU time 93.09 seconds
Started Mar 24 01:18:08 PM PDT 24
Finished Mar 24 01:19:41 PM PDT 24
Peak memory 367436 kb
Host smart-73dcf2cd-87fa-429d-a2fb-b513cd25bed5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048192060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.1048192060
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3677740502
Short name T511
Test name
Test status
Simulation time 810154407 ps
CPU time 4.24 seconds
Started Mar 24 01:18:04 PM PDT 24
Finished Mar 24 01:18:09 PM PDT 24
Peak memory 210124 kb
Host smart-a97a8d16-6ea8-4883-b523-bdd9292e62ea
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677740502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.3677740502
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.2748262756
Short name T590
Test name
Test status
Simulation time 1148568264 ps
CPU time 10.26 seconds
Started Mar 24 01:18:01 PM PDT 24
Finished Mar 24 01:18:12 PM PDT 24
Peak memory 201940 kb
Host smart-426ac6de-3495-4acd-9418-ce7276bef2dc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748262756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.2748262756
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.532732215
Short name T412
Test name
Test status
Simulation time 3886523261 ps
CPU time 532.04 seconds
Started Mar 24 01:18:00 PM PDT 24
Finished Mar 24 01:26:52 PM PDT 24
Peak memory 373076 kb
Host smart-b3da19f9-5e01-42e5-9e09-6a6aed093564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532732215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multip
le_keys.532732215
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.3033558723
Short name T568
Test name
Test status
Simulation time 437371003 ps
CPU time 3.94 seconds
Started Mar 24 01:18:03 PM PDT 24
Finished Mar 24 01:18:07 PM PDT 24
Peak memory 212120 kb
Host smart-03f10118-dff7-4924-8cbe-f4f9eaa6c869
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033558723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.3033558723
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1667405913
Short name T797
Test name
Test status
Simulation time 60163290350 ps
CPU time 386.34 seconds
Started Mar 24 01:18:04 PM PDT 24
Finished Mar 24 01:24:30 PM PDT 24
Peak memory 202000 kb
Host smart-844930f3-64b5-4f5e-9b71-6b9d2c592809
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667405913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.1667405913
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.2975849765
Short name T450
Test name
Test status
Simulation time 48928529 ps
CPU time 0.77 seconds
Started Mar 24 01:18:04 PM PDT 24
Finished Mar 24 01:18:04 PM PDT 24
Peak memory 202100 kb
Host smart-495efeab-9e0b-4902-bda1-1bc4412502b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975849765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2975849765
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.2836368978
Short name T403
Test name
Test status
Simulation time 23379351623 ps
CPU time 373.87 seconds
Started Mar 24 01:18:01 PM PDT 24
Finished Mar 24 01:24:15 PM PDT 24
Peak memory 313156 kb
Host smart-73724cb1-f40c-4ac5-8fcd-8e78b80d5fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836368978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2836368978
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.3812465980
Short name T391
Test name
Test status
Simulation time 536487111 ps
CPU time 70.4 seconds
Started Mar 24 01:17:59 PM PDT 24
Finished Mar 24 01:19:10 PM PDT 24
Peak memory 341384 kb
Host smart-f856924c-4b31-4e9c-ba8e-48ebe4c74b3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812465980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3812465980
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.1595996058
Short name T432
Test name
Test status
Simulation time 9673341980 ps
CPU time 2112.53 seconds
Started Mar 24 01:18:02 PM PDT 24
Finished Mar 24 01:53:15 PM PDT 24
Peak memory 372864 kb
Host smart-03f608e2-16a8-422e-9948-7705c021eb98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595996058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.sram_ctrl_stress_all.1595996058
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2719022561
Short name T114
Test name
Test status
Simulation time 9323542344 ps
CPU time 163.1 seconds
Started Mar 24 01:18:03 PM PDT 24
Finished Mar 24 01:20:46 PM PDT 24
Peak memory 358396 kb
Host smart-f289b84f-0ffa-4943-9126-8c3a6f159d63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2719022561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2719022561
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2468404779
Short name T219
Test name
Test status
Simulation time 10861360628 ps
CPU time 228.22 seconds
Started Mar 24 01:17:57 PM PDT 24
Finished Mar 24 01:21:45 PM PDT 24
Peak memory 202000 kb
Host smart-991a0b88-e172-41a0-a42e-88c900d7d9be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468404779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.2468404779
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.907755860
Short name T800
Test name
Test status
Simulation time 548516757 ps
CPU time 92.42 seconds
Started Mar 24 01:17:59 PM PDT 24
Finished Mar 24 01:19:31 PM PDT 24
Peak memory 343088 kb
Host smart-57db508d-8d48-4fbf-93ea-917c51439e87
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907755860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.907755860
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2650101463
Short name T654
Test name
Test status
Simulation time 2900225099 ps
CPU time 771.02 seconds
Started Mar 24 01:18:03 PM PDT 24
Finished Mar 24 01:30:55 PM PDT 24
Peak memory 372024 kb
Host smart-a6692cd0-85df-49c8-b7ec-835256344354
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650101463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.2650101463
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.1638972927
Short name T456
Test name
Test status
Simulation time 11708477 ps
CPU time 0.64 seconds
Started Mar 24 01:18:06 PM PDT 24
Finished Mar 24 01:18:07 PM PDT 24
Peak memory 201156 kb
Host smart-6992e8ef-5b5f-430e-9bf2-6df673b0f72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638972927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.1638972927
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.741403439
Short name T305
Test name
Test status
Simulation time 476101481 ps
CPU time 24.94 seconds
Started Mar 24 01:18:05 PM PDT 24
Finished Mar 24 01:18:30 PM PDT 24
Peak memory 201984 kb
Host smart-7c1a3e1c-77ab-4690-b8b1-237ac40588c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741403439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.
741403439
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.88262895
Short name T232
Test name
Test status
Simulation time 1452960497 ps
CPU time 345.68 seconds
Started Mar 24 01:18:07 PM PDT 24
Finished Mar 24 01:23:53 PM PDT 24
Peak memory 369612 kb
Host smart-8fdac3d9-12ae-4a29-ab92-ecfc3e872d40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88262895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable
.88262895
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.2891941802
Short name T545
Test name
Test status
Simulation time 5710846689 ps
CPU time 8.93 seconds
Started Mar 24 01:18:06 PM PDT 24
Finished Mar 24 01:18:15 PM PDT 24
Peak memory 202108 kb
Host smart-57bbfbf8-e378-405d-ad1f-43f3c945581c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891941802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.2891941802
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.2107175188
Short name T822
Test name
Test status
Simulation time 45834540 ps
CPU time 2.16 seconds
Started Mar 24 01:18:04 PM PDT 24
Finished Mar 24 01:18:06 PM PDT 24
Peak memory 215244 kb
Host smart-d8671a66-c997-40a2-930e-2cdc79841bca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107175188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.2107175188
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2656979775
Short name T84
Test name
Test status
Simulation time 67613093 ps
CPU time 4.29 seconds
Started Mar 24 01:18:09 PM PDT 24
Finished Mar 24 01:18:13 PM PDT 24
Peak memory 210128 kb
Host smart-9d412c4d-6da5-48d4-8c8a-57fb4902858b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656979775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.2656979775
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.987035024
Short name T640
Test name
Test status
Simulation time 917449613 ps
CPU time 5.36 seconds
Started Mar 24 01:18:09 PM PDT 24
Finished Mar 24 01:18:15 PM PDT 24
Peak memory 201940 kb
Host smart-51481104-1f9f-49f9-8386-2d5d4c7c64c7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987035024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl
_mem_walk.987035024
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.419454700
Short name T143
Test name
Test status
Simulation time 25423470454 ps
CPU time 2264.52 seconds
Started Mar 24 01:18:05 PM PDT 24
Finished Mar 24 01:55:50 PM PDT 24
Peak memory 373848 kb
Host smart-c4bb3c3d-1dbd-4fc1-b3fb-f6c33c79a731
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419454700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip
le_keys.419454700
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.2808237867
Short name T688
Test name
Test status
Simulation time 151391279 ps
CPU time 1.11 seconds
Started Mar 24 01:18:06 PM PDT 24
Finished Mar 24 01:18:07 PM PDT 24
Peak memory 201812 kb
Host smart-34051041-35bc-4da1-af5f-55d0a1975220
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808237867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.2808237867
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1392562309
Short name T461
Test name
Test status
Simulation time 78747848718 ps
CPU time 511.77 seconds
Started Mar 24 01:18:04 PM PDT 24
Finished Mar 24 01:26:36 PM PDT 24
Peak memory 202280 kb
Host smart-322e9941-26ea-491e-8e4f-582a38973c20
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392562309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.1392562309
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.4085260526
Short name T443
Test name
Test status
Simulation time 158694129 ps
CPU time 0.8 seconds
Started Mar 24 01:18:06 PM PDT 24
Finished Mar 24 01:18:07 PM PDT 24
Peak memory 202116 kb
Host smart-0aa609c2-77cf-48ad-96ca-81245e1d0e6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085260526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.4085260526
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.852802001
Short name T635
Test name
Test status
Simulation time 40793186960 ps
CPU time 1683.4 seconds
Started Mar 24 01:18:04 PM PDT 24
Finished Mar 24 01:46:08 PM PDT 24
Peak memory 373872 kb
Host smart-e72452b7-f001-4bf9-9f1d-bd31b35ca099
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852802001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.852802001
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.1568258968
Short name T644
Test name
Test status
Simulation time 179259402 ps
CPU time 90.09 seconds
Started Mar 24 01:18:03 PM PDT 24
Finished Mar 24 01:19:33 PM PDT 24
Peak memory 339932 kb
Host smart-b32a61e1-efa1-4219-b46e-80dced5bbbfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568258968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1568258968
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.1249457705
Short name T279
Test name
Test status
Simulation time 69236394790 ps
CPU time 4682.13 seconds
Started Mar 24 01:18:06 PM PDT 24
Finished Mar 24 02:36:09 PM PDT 24
Peak memory 374872 kb
Host smart-15883d24-f3e5-4d68-9bdf-c666bb884e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249457705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.1249457705
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.526253945
Short name T395
Test name
Test status
Simulation time 814205923 ps
CPU time 38.16 seconds
Started Mar 24 01:18:04 PM PDT 24
Finished Mar 24 01:18:42 PM PDT 24
Peak memory 294032 kb
Host smart-8eaaf794-8955-4615-be16-107d1ff051ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=526253945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.526253945
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.68635057
Short name T186
Test name
Test status
Simulation time 2845496492 ps
CPU time 274.32 seconds
Started Mar 24 01:18:05 PM PDT 24
Finished Mar 24 01:22:39 PM PDT 24
Peak memory 202088 kb
Host smart-7966902d-85bb-4559-ae59-ae88d50cb6a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68635057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_stress_pipeline.68635057
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.801822367
Short name T229
Test name
Test status
Simulation time 94148514 ps
CPU time 10.22 seconds
Started Mar 24 01:18:07 PM PDT 24
Finished Mar 24 01:18:17 PM PDT 24
Peak memory 250760 kb
Host smart-f636b002-061f-48c3-a2a7-a9ae562422d6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801822367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_throughput_w_partial_write.801822367
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1652752542
Short name T469
Test name
Test status
Simulation time 47386509763 ps
CPU time 1475.94 seconds
Started Mar 24 01:18:05 PM PDT 24
Finished Mar 24 01:42:41 PM PDT 24
Peak memory 372888 kb
Host smart-84372504-98d7-4304-9578-f878f2cff1e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652752542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.1652752542
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.1892848822
Short name T270
Test name
Test status
Simulation time 21198741 ps
CPU time 0.66 seconds
Started Mar 24 01:18:08 PM PDT 24
Finished Mar 24 01:18:09 PM PDT 24
Peak memory 201040 kb
Host smart-836a42d8-8213-45ee-9557-b855d0aeadbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892848822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.1892848822
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.719867759
Short name T791
Test name
Test status
Simulation time 3324703030 ps
CPU time 16.99 seconds
Started Mar 24 01:18:03 PM PDT 24
Finished Mar 24 01:18:20 PM PDT 24
Peak memory 202128 kb
Host smart-1ab436ec-89e0-49da-8e71-aa149decbec5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719867759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.
719867759
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.1091888644
Short name T263
Test name
Test status
Simulation time 1640683888 ps
CPU time 290.26 seconds
Started Mar 24 01:18:08 PM PDT 24
Finished Mar 24 01:22:58 PM PDT 24
Peak memory 355404 kb
Host smart-4276a3df-99c6-40d8-b282-c20f5fb3f239
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091888644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.1091888644
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.1535728215
Short name T254
Test name
Test status
Simulation time 854841741 ps
CPU time 7.76 seconds
Started Mar 24 01:18:06 PM PDT 24
Finished Mar 24 01:18:14 PM PDT 24
Peak memory 210284 kb
Host smart-be8bd6d3-64a0-4edc-a5d4-261b8bea2cfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535728215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.1535728215
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.1447299897
Short name T702
Test name
Test status
Simulation time 80650669 ps
CPU time 1.87 seconds
Started Mar 24 01:18:06 PM PDT 24
Finished Mar 24 01:18:08 PM PDT 24
Peak memory 210256 kb
Host smart-41cf356c-cd52-40f1-a93c-eeccb62ca622
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447299897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.1447299897
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.4003684911
Short name T247
Test name
Test status
Simulation time 303050329 ps
CPU time 4.8 seconds
Started Mar 24 01:18:07 PM PDT 24
Finished Mar 24 01:18:12 PM PDT 24
Peak memory 210172 kb
Host smart-f67ee51c-6a3b-445b-ad3f-049ceb3d6ebd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003684911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.4003684911
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.3963139427
Short name T671
Test name
Test status
Simulation time 1304293070 ps
CPU time 10.61 seconds
Started Mar 24 01:18:11 PM PDT 24
Finished Mar 24 01:18:22 PM PDT 24
Peak memory 201896 kb
Host smart-539d8eb1-40da-4a0c-a151-dfee6a2196a6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963139427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.3963139427
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.1505967855
Short name T160
Test name
Test status
Simulation time 10155324847 ps
CPU time 902.29 seconds
Started Mar 24 01:18:05 PM PDT 24
Finished Mar 24 01:33:08 PM PDT 24
Peak memory 373868 kb
Host smart-3a47deb7-78e5-4af4-b1a0-42f61cae4c47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505967855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.1505967855
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.2894472243
Short name T859
Test name
Test status
Simulation time 639816406 ps
CPU time 79.42 seconds
Started Mar 24 01:18:05 PM PDT 24
Finished Mar 24 01:19:24 PM PDT 24
Peak memory 355352 kb
Host smart-e9819140-1aa5-4ce4-9b83-36e2a7c780fd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894472243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.2894472243
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4194610644
Short name T17
Test name
Test status
Simulation time 13597498891 ps
CPU time 171.17 seconds
Started Mar 24 01:18:04 PM PDT 24
Finished Mar 24 01:20:56 PM PDT 24
Peak memory 202032 kb
Host smart-8e66ef99-6d77-451d-8c85-7cd455636829
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194610644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.4194610644
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.3589126867
Short name T454
Test name
Test status
Simulation time 74195288 ps
CPU time 0.71 seconds
Started Mar 24 01:18:07 PM PDT 24
Finished Mar 24 01:18:08 PM PDT 24
Peak memory 202104 kb
Host smart-ed87b5f2-83f6-4e2e-9bd6-ba30371e76de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589126867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3589126867
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.277667123
Short name T767
Test name
Test status
Simulation time 5896227717 ps
CPU time 594.93 seconds
Started Mar 24 01:18:09 PM PDT 24
Finished Mar 24 01:28:04 PM PDT 24
Peak memory 367672 kb
Host smart-57317383-4edf-4e4c-b644-4c891f12bde5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277667123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.277667123
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.2802898079
Short name T277
Test name
Test status
Simulation time 270845511 ps
CPU time 7.96 seconds
Started Mar 24 01:18:05 PM PDT 24
Finished Mar 24 01:18:13 PM PDT 24
Peak memory 202068 kb
Host smart-60bb92b9-4241-4f31-b276-f2799ef1ec75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802898079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2802898079
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.3138174422
Short name T876
Test name
Test status
Simulation time 27275175009 ps
CPU time 1830.56 seconds
Started Mar 24 01:18:08 PM PDT 24
Finished Mar 24 01:48:39 PM PDT 24
Peak memory 370796 kb
Host smart-784230e9-01eb-4991-880d-1c3a506240c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138174422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.3138174422
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.52607273
Short name T45
Test name
Test status
Simulation time 760075450 ps
CPU time 33.44 seconds
Started Mar 24 01:18:12 PM PDT 24
Finished Mar 24 01:18:46 PM PDT 24
Peak memory 275708 kb
Host smart-477714fd-7df6-437f-acff-5ed364886b95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=52607273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.52607273
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3535000618
Short name T287
Test name
Test status
Simulation time 7283625629 ps
CPU time 179.83 seconds
Started Mar 24 01:18:04 PM PDT 24
Finished Mar 24 01:21:04 PM PDT 24
Peak memory 202088 kb
Host smart-7bc9278d-5b6b-4688-ae17-06a5bd26666c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535000618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.3535000618
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3091532608
Short name T657
Test name
Test status
Simulation time 278798018 ps
CPU time 124.29 seconds
Started Mar 24 01:18:07 PM PDT 24
Finished Mar 24 01:20:11 PM PDT 24
Peak memory 368616 kb
Host smart-b8c25ae3-c19d-4b8d-8242-2b51fe10f03d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091532608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3091532608
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1220428222
Short name T218
Test name
Test status
Simulation time 6261326610 ps
CPU time 1310.61 seconds
Started Mar 24 01:18:11 PM PDT 24
Finished Mar 24 01:40:03 PM PDT 24
Peak memory 373784 kb
Host smart-3171a685-5067-4a4b-80fa-a3bcb19d5553
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220428222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.1220428222
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.575441656
Short name T198
Test name
Test status
Simulation time 19903205 ps
CPU time 0.63 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:18:15 PM PDT 24
Peak memory 200940 kb
Host smart-601528ae-a7be-4987-ac51-8ca1a97d07a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575441656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.575441656
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.3120835878
Short name T2
Test name
Test status
Simulation time 5296886688 ps
CPU time 29.28 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 01:18:42 PM PDT 24
Peak memory 202108 kb
Host smart-5ceb78f6-abab-4c17-ba01-d9dfed16d83e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120835878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.3120835878
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.3408462569
Short name T465
Test name
Test status
Simulation time 20538787902 ps
CPU time 669.07 seconds
Started Mar 24 01:18:08 PM PDT 24
Finished Mar 24 01:29:17 PM PDT 24
Peak memory 368248 kb
Host smart-b7eba304-ad1b-40b1-961f-87cba2849abc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408462569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.3408462569
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.1079391237
Short name T517
Test name
Test status
Simulation time 1802361874 ps
CPU time 4.98 seconds
Started Mar 24 01:18:12 PM PDT 24
Finished Mar 24 01:18:17 PM PDT 24
Peak memory 201952 kb
Host smart-0d2a0fca-7cdf-4049-b765-4fa27eb79284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079391237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.1079391237
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.2234520210
Short name T557
Test name
Test status
Simulation time 110465003 ps
CPU time 10.08 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 01:18:23 PM PDT 24
Peak memory 251108 kb
Host smart-54e67fa5-25b6-4039-aa11-8e942204d62d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234520210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.2234520210
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1550141506
Short name T85
Test name
Test status
Simulation time 97854247 ps
CPU time 2.41 seconds
Started Mar 24 01:18:12 PM PDT 24
Finished Mar 24 01:18:14 PM PDT 24
Peak memory 210192 kb
Host smart-dcca8805-9365-4ce0-8fce-dd09bcac984a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550141506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.1550141506
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.1217507928
Short name T711
Test name
Test status
Simulation time 841136975 ps
CPU time 4.76 seconds
Started Mar 24 01:18:08 PM PDT 24
Finished Mar 24 01:18:13 PM PDT 24
Peak memory 201940 kb
Host smart-5fdf0b43-149b-489a-adfb-18460f292cfd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217507928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.1217507928
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.4010916094
Short name T361
Test name
Test status
Simulation time 53633967850 ps
CPU time 790.9 seconds
Started Mar 24 01:18:10 PM PDT 24
Finished Mar 24 01:31:21 PM PDT 24
Peak memory 374864 kb
Host smart-7d15cfb5-32c8-4f77-8a8f-29765f0b424b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010916094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.4010916094
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.1562561618
Short name T616
Test name
Test status
Simulation time 3188118043 ps
CPU time 18.12 seconds
Started Mar 24 01:18:10 PM PDT 24
Finished Mar 24 01:18:28 PM PDT 24
Peak memory 202000 kb
Host smart-1266aa41-43f1-450d-b954-09792b674096
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562561618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.1562561618
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.680436073
Short name T632
Test name
Test status
Simulation time 21993445909 ps
CPU time 280.8 seconds
Started Mar 24 01:18:09 PM PDT 24
Finished Mar 24 01:22:51 PM PDT 24
Peak memory 202060 kb
Host smart-5b621299-55fd-403d-b780-abc49a6f3e45
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680436073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.sram_ctrl_partial_access_b2b.680436073
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.1753769727
Short name T426
Test name
Test status
Simulation time 87167786 ps
CPU time 0.77 seconds
Started Mar 24 01:18:12 PM PDT 24
Finished Mar 24 01:18:13 PM PDT 24
Peak memory 202164 kb
Host smart-8e37644c-81a1-405e-8991-81e577b824db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753769727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1753769727
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.28953903
Short name T248
Test name
Test status
Simulation time 52176217861 ps
CPU time 1236.02 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:38:53 PM PDT 24
Peak memory 372716 kb
Host smart-e42e4673-56b3-409f-af4e-7ff52d56c80b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28953903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.28953903
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.1340085415
Short name T662
Test name
Test status
Simulation time 532528661 ps
CPU time 21.85 seconds
Started Mar 24 01:18:09 PM PDT 24
Finished Mar 24 01:18:31 PM PDT 24
Peak memory 277396 kb
Host smart-900a0283-8d0a-4c10-90b9-cdc9023fe2a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340085415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1340085415
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.3741700374
Short name T491
Test name
Test status
Simulation time 3906303211 ps
CPU time 785.61 seconds
Started Mar 24 01:18:10 PM PDT 24
Finished Mar 24 01:31:16 PM PDT 24
Peak memory 369584 kb
Host smart-8bb8ccb5-998d-4b0c-921c-8073bd08dc1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741700374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.3741700374
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3955119339
Short name T729
Test name
Test status
Simulation time 3248705721 ps
CPU time 68.16 seconds
Started Mar 24 01:18:12 PM PDT 24
Finished Mar 24 01:19:21 PM PDT 24
Peak memory 318664 kb
Host smart-4e347760-e7ae-464a-9c5b-8e6f9c586dc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3955119339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3955119339
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1013791517
Short name T101
Test name
Test status
Simulation time 3215555184 ps
CPU time 309.02 seconds
Started Mar 24 01:18:10 PM PDT 24
Finished Mar 24 01:23:20 PM PDT 24
Peak memory 202056 kb
Host smart-5ff08323-7df5-43dd-b95d-f7e638d184b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013791517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.1013791517
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1459139306
Short name T376
Test name
Test status
Simulation time 262311300 ps
CPU time 85.47 seconds
Started Mar 24 01:18:12 PM PDT 24
Finished Mar 24 01:19:38 PM PDT 24
Peak memory 331008 kb
Host smart-1a604ad3-723c-484a-a585-e7818b20a9db
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459139306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1459139306
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2000472052
Short name T486
Test name
Test status
Simulation time 1567830382 ps
CPU time 409.96 seconds
Started Mar 24 01:18:10 PM PDT 24
Finished Mar 24 01:25:00 PM PDT 24
Peak memory 373400 kb
Host smart-a0f1f1f6-de1f-49bb-a58a-c123b90cd86f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000472052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.2000472052
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.919005768
Short name T282
Test name
Test status
Simulation time 18804879 ps
CPU time 0.62 seconds
Started Mar 24 01:18:16 PM PDT 24
Finished Mar 24 01:18:17 PM PDT 24
Peak memory 201796 kb
Host smart-3d940cf4-8884-4dc5-a5cd-c1bbae6379bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919005768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.919005768
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.62146084
Short name T789
Test name
Test status
Simulation time 1094849738 ps
CPU time 66.59 seconds
Started Mar 24 01:18:11 PM PDT 24
Finished Mar 24 01:19:17 PM PDT 24
Peak memory 202032 kb
Host smart-d400c001-de15-4b1d-aa7e-2cc0567b5720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62146084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.62146084
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.1109401926
Short name T429
Test name
Test status
Simulation time 19122750180 ps
CPU time 1481.45 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:42:57 PM PDT 24
Peak memory 373860 kb
Host smart-2822ad44-8861-4dde-ad2e-da931c6c9372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109401926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.1109401926
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.3049986826
Short name T269
Test name
Test status
Simulation time 685952267 ps
CPU time 6.35 seconds
Started Mar 24 01:18:09 PM PDT 24
Finished Mar 24 01:18:16 PM PDT 24
Peak memory 202236 kb
Host smart-7de4fe9e-ee78-4db2-b2fb-30bfa83e43bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049986826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.3049986826
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.817992315
Short name T329
Test name
Test status
Simulation time 126549216 ps
CPU time 2.11 seconds
Started Mar 24 01:18:10 PM PDT 24
Finished Mar 24 01:18:12 PM PDT 24
Peak memory 210264 kb
Host smart-104daac9-d11c-423d-916d-46f8ac296552
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817992315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.sram_ctrl_max_throughput.817992315
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2738537060
Short name T504
Test name
Test status
Simulation time 239926928 ps
CPU time 4.38 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:18:19 PM PDT 24
Peak memory 210176 kb
Host smart-288c6d44-f6cb-4c76-bd56-5cc5c12bb941
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738537060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.2738537060
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.581679192
Short name T586
Test name
Test status
Simulation time 927846400 ps
CPU time 5.16 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:18:20 PM PDT 24
Peak memory 201892 kb
Host smart-4ff8b234-5956-4cef-9735-1682ac4c9a12
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581679192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl
_mem_walk.581679192
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.3717794946
Short name T798
Test name
Test status
Simulation time 15793618174 ps
CPU time 1583.19 seconds
Started Mar 24 01:18:11 PM PDT 24
Finished Mar 24 01:44:35 PM PDT 24
Peak memory 374848 kb
Host smart-7d816be7-7c81-4ed5-8acc-97d7edcbc4ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717794946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.3717794946
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.4280020240
Short name T318
Test name
Test status
Simulation time 370303499 ps
CPU time 11.47 seconds
Started Mar 24 01:18:10 PM PDT 24
Finished Mar 24 01:18:22 PM PDT 24
Peak memory 202036 kb
Host smart-0c140f2a-30bc-45ff-b996-f315a45a1378
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280020240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.4280020240
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3952532004
Short name T887
Test name
Test status
Simulation time 19839590159 ps
CPU time 463.63 seconds
Started Mar 24 01:18:11 PM PDT 24
Finished Mar 24 01:25:56 PM PDT 24
Peak memory 202068 kb
Host smart-5252304a-6dcb-4476-9708-22535676cfd7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952532004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3952532004
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.1565778800
Short name T679
Test name
Test status
Simulation time 82785802 ps
CPU time 0.72 seconds
Started Mar 24 01:18:16 PM PDT 24
Finished Mar 24 01:18:17 PM PDT 24
Peak memory 202164 kb
Host smart-290bcf32-5972-42f3-9528-e9cb9a3b62d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565778800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1565778800
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.2998362829
Short name T259
Test name
Test status
Simulation time 58800614183 ps
CPU time 944.14 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:33:59 PM PDT 24
Peak memory 373536 kb
Host smart-d4fc439c-677d-4475-a4e8-248df3229007
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998362829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2998362829
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.1813658048
Short name T813
Test name
Test status
Simulation time 250581562 ps
CPU time 6.99 seconds
Started Mar 24 01:18:09 PM PDT 24
Finished Mar 24 01:18:17 PM PDT 24
Peak memory 202392 kb
Host smart-5e2cb062-48e4-47ef-ab54-5e48b1807a94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813658048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1813658048
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.1194374908
Short name T781
Test name
Test status
Simulation time 7163453264 ps
CPU time 3262.98 seconds
Started Mar 24 01:18:16 PM PDT 24
Finished Mar 24 02:12:39 PM PDT 24
Peak memory 372796 kb
Host smart-3ea02123-0e02-4a7a-b52b-f9ec63c18161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194374908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.sram_ctrl_stress_all.1194374908
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2471685802
Short name T47
Test name
Test status
Simulation time 340414385 ps
CPU time 19.94 seconds
Started Mar 24 01:18:11 PM PDT 24
Finished Mar 24 01:18:32 PM PDT 24
Peak memory 210260 kb
Host smart-9f446815-05db-4fb3-9f13-4e9964134572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2471685802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2471685802
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3324110795
Short name T649
Test name
Test status
Simulation time 11848791840 ps
CPU time 270.71 seconds
Started Mar 24 01:18:10 PM PDT 24
Finished Mar 24 01:22:41 PM PDT 24
Peak memory 202060 kb
Host smart-52453f2f-ee77-4610-88bd-a9c34f72d1eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324110795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.3324110795
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3651181391
Short name T819
Test name
Test status
Simulation time 266005659 ps
CPU time 97.3 seconds
Started Mar 24 01:18:11 PM PDT 24
Finished Mar 24 01:19:49 PM PDT 24
Peak memory 341020 kb
Host smart-8b0fe8b9-a957-41b7-8e04-6e07af47fe1f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651181391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.3651181391
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1715657835
Short name T524
Test name
Test status
Simulation time 3518542512 ps
CPU time 720.18 seconds
Started Mar 24 01:18:18 PM PDT 24
Finished Mar 24 01:30:19 PM PDT 24
Peak memory 368560 kb
Host smart-86ce615e-baa4-4636-8211-788dd31f5878
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715657835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.1715657835
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.2330665888
Short name T716
Test name
Test status
Simulation time 16762585 ps
CPU time 0.67 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:18:15 PM PDT 24
Peak memory 201008 kb
Host smart-305174e6-4880-4a5b-8ae6-9090a500fb83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330665888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.2330665888
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.569879212
Short name T285
Test name
Test status
Simulation time 1741544626 ps
CPU time 53.43 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:19:11 PM PDT 24
Peak memory 201960 kb
Host smart-94ed6802-2c0e-4a50-8b15-54744ff0e669
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569879212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.
569879212
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.2689860965
Short name T349
Test name
Test status
Simulation time 9285398442 ps
CPU time 710.94 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 01:30:04 PM PDT 24
Peak memory 349248 kb
Host smart-c4dccb24-b257-44be-8fd1-4cb04f874c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689860965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.2689860965
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.2081297856
Short name T417
Test name
Test status
Simulation time 135563934 ps
CPU time 2.13 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:18:16 PM PDT 24
Peak memory 202004 kb
Host smart-0bb53677-92d5-46af-8db2-a5f59dbb8083
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081297856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.2081297856
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.1305312038
Short name T266
Test name
Test status
Simulation time 414202553 ps
CPU time 81.3 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:19:37 PM PDT 24
Peak memory 348972 kb
Host smart-76d28b92-b8f6-4df3-b680-438256aae3dd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305312038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.1305312038
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2207865314
Short name T428
Test name
Test status
Simulation time 408566981 ps
CPU time 2.64 seconds
Started Mar 24 01:18:18 PM PDT 24
Finished Mar 24 01:18:21 PM PDT 24
Peak memory 210172 kb
Host smart-da37e243-33ab-4775-b774-f42149fd9c24
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207865314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.2207865314
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.2825697252
Short name T363
Test name
Test status
Simulation time 466233480 ps
CPU time 9.28 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 01:18:23 PM PDT 24
Peak memory 201968 kb
Host smart-d0b957b3-b0cb-40f5-beaf-7a36411972a8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825697252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.2825697252
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.2925109905
Short name T817
Test name
Test status
Simulation time 17078494306 ps
CPU time 1151.26 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:37:26 PM PDT 24
Peak memory 374840 kb
Host smart-ca7effaa-c556-4d96-99cf-d11f35985858
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925109905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.2925109905
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.3848602551
Short name T836
Test name
Test status
Simulation time 258928637 ps
CPU time 13.92 seconds
Started Mar 24 01:18:16 PM PDT 24
Finished Mar 24 01:18:31 PM PDT 24
Peak memory 247888 kb
Host smart-146178e4-b541-425b-919d-082abc01204b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848602551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.3848602551
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1924023852
Short name T713
Test name
Test status
Simulation time 71431585462 ps
CPU time 516.6 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:26:54 PM PDT 24
Peak memory 202080 kb
Host smart-95e9e947-79c7-4c05-9f24-6857e9b8bb51
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924023852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.1924023852
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.1545708305
Short name T618
Test name
Test status
Simulation time 169014740 ps
CPU time 0.77 seconds
Started Mar 24 01:18:15 PM PDT 24
Finished Mar 24 01:18:17 PM PDT 24
Peak memory 202116 kb
Host smart-77cf547c-ccf6-4db1-830e-e91340c75619
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545708305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1545708305
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.726166545
Short name T149
Test name
Test status
Simulation time 18708324623 ps
CPU time 1574.16 seconds
Started Mar 24 01:18:15 PM PDT 24
Finished Mar 24 01:44:30 PM PDT 24
Peak memory 373364 kb
Host smart-6eb2f8bc-9ff4-40cd-8eaa-e391d41fd820
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726166545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.726166545
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.2446556988
Short name T294
Test name
Test status
Simulation time 4124339015 ps
CPU time 13.69 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:18:31 PM PDT 24
Peak memory 202020 kb
Host smart-52dc6127-8440-4256-a6ed-ae0c560b9fe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446556988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2446556988
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.43088435
Short name T739
Test name
Test status
Simulation time 8874002367 ps
CPU time 3949.68 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 02:24:04 PM PDT 24
Peak memory 382068 kb
Host smart-9eea4851-52be-4295-be09-da72b387d2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43088435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.sram_ctrl_stress_all.43088435
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2656385687
Short name T866
Test name
Test status
Simulation time 6128168729 ps
CPU time 384.96 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 01:24:38 PM PDT 24
Peak memory 359656 kb
Host smart-01c4b236-1a50-47cd-9a60-920bd439941c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2656385687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.2656385687
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1581946920
Short name T494
Test name
Test status
Simulation time 12904246152 ps
CPU time 304.63 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:23:20 PM PDT 24
Peak memory 202072 kb
Host smart-fbf54ddf-ff74-4ee1-9dfb-89a16ce7813a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581946920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.1581946920
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3530077869
Short name T176
Test name
Test status
Simulation time 97836036 ps
CPU time 31.93 seconds
Started Mar 24 01:18:18 PM PDT 24
Finished Mar 24 01:18:50 PM PDT 24
Peak memory 284672 kb
Host smart-4ee84328-5bcb-4828-ac90-a757950502e5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530077869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3530077869
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1849287618
Short name T246
Test name
Test status
Simulation time 5585225267 ps
CPU time 1596.93 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:44:51 PM PDT 24
Peak memory 372740 kb
Host smart-91632578-70bf-4e94-8c95-443aef7f2b29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849287618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.1849287618
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.3741701408
Short name T656
Test name
Test status
Simulation time 139463439 ps
CPU time 0.7 seconds
Started Mar 24 01:18:18 PM PDT 24
Finished Mar 24 01:18:19 PM PDT 24
Peak memory 201804 kb
Host smart-c24c9224-35f5-41a7-8836-1e9f28887162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741701408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.3741701408
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.918587722
Short name T912
Test name
Test status
Simulation time 735663506 ps
CPU time 23.26 seconds
Started Mar 24 01:18:15 PM PDT 24
Finished Mar 24 01:18:39 PM PDT 24
Peak memory 202264 kb
Host smart-28e5b2ec-c2d1-4644-87a5-76c91985f8b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918587722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.
918587722
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.1867410000
Short name T365
Test name
Test status
Simulation time 13739046637 ps
CPU time 956.38 seconds
Started Mar 24 01:18:16 PM PDT 24
Finished Mar 24 01:34:13 PM PDT 24
Peak memory 372812 kb
Host smart-c802fa73-7670-43cb-b1dc-edaad33be53d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867410000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.1867410000
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.3529783070
Short name T9
Test name
Test status
Simulation time 380049727 ps
CPU time 4.98 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 01:18:19 PM PDT 24
Peak memory 202032 kb
Host smart-d332db66-642f-4b8d-88bf-b4ee92a14269
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529783070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.3529783070
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.2770118561
Short name T56
Test name
Test status
Simulation time 501933000 ps
CPU time 49.9 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:19:07 PM PDT 24
Peak memory 320468 kb
Host smart-a19b9433-43cf-4f09-9c54-2e23487521d3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770118561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.2770118561
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2324794316
Short name T60
Test name
Test status
Simulation time 371484709 ps
CPU time 2.93 seconds
Started Mar 24 01:18:20 PM PDT 24
Finished Mar 24 01:18:23 PM PDT 24
Peak memory 210168 kb
Host smart-862145f0-66b9-44e0-a21d-b94c5663ac68
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324794316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.2324794316
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.1112648743
Short name T222
Test name
Test status
Simulation time 139848256 ps
CPU time 8.06 seconds
Started Mar 24 01:18:18 PM PDT 24
Finished Mar 24 01:18:27 PM PDT 24
Peak memory 201952 kb
Host smart-f39fb0cb-9fc7-44f5-b621-4ce8215437c0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112648743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.1112648743
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.2854655495
Short name T911
Test name
Test status
Simulation time 39853237599 ps
CPU time 892.84 seconds
Started Mar 24 01:18:16 PM PDT 24
Finished Mar 24 01:33:10 PM PDT 24
Peak memory 373820 kb
Host smart-64a20eb8-aa89-4649-a3e1-aa3750a6d891
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854655495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.2854655495
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.733636460
Short name T297
Test name
Test status
Simulation time 884330921 ps
CPU time 12.63 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 01:18:26 PM PDT 24
Peak memory 202000 kb
Host smart-f597298f-81c6-48c5-9f21-508d6a085942
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733636460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.s
ram_ctrl_partial_access.733636460
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.4113930092
Short name T563
Test name
Test status
Simulation time 6181066875 ps
CPU time 208.87 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:21:47 PM PDT 24
Peak memory 202076 kb
Host smart-a37d71de-51f1-4619-b1f0-837013441991
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113930092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.4113930092
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.3980882118
Short name T175
Test name
Test status
Simulation time 93681383 ps
CPU time 0.74 seconds
Started Mar 24 01:18:14 PM PDT 24
Finished Mar 24 01:18:15 PM PDT 24
Peak memory 202144 kb
Host smart-c88d6e5a-0dc5-474f-b070-cb468b0cf81d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980882118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3980882118
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.176692431
Short name T933
Test name
Test status
Simulation time 936966404 ps
CPU time 24.7 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 01:18:38 PM PDT 24
Peak memory 202200 kb
Host smart-ea10c6ad-bfa6-4852-9cea-9108fe8d3131
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176692431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.176692431
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.1487033686
Short name T599
Test name
Test status
Simulation time 129702848 ps
CPU time 1.49 seconds
Started Mar 24 01:18:11 PM PDT 24
Finished Mar 24 01:18:13 PM PDT 24
Peak memory 202012 kb
Host smart-4be85656-a87a-4a37-8850-f8286095f07d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487033686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1487033686
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.261669967
Short name T240
Test name
Test status
Simulation time 75862618868 ps
CPU time 2266.13 seconds
Started Mar 24 01:18:21 PM PDT 24
Finished Mar 24 01:56:08 PM PDT 24
Peak memory 372804 kb
Host smart-654bee16-6997-4adb-85a5-f091469d3917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261669967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_stress_all.261669967
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3594930737
Short name T575
Test name
Test status
Simulation time 29046802691 ps
CPU time 356.52 seconds
Started Mar 24 01:18:13 PM PDT 24
Finished Mar 24 01:24:10 PM PDT 24
Peak memory 202056 kb
Host smart-03321cae-852b-4a25-ba48-122f651be8bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594930737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.3594930737
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4191739886
Short name T796
Test name
Test status
Simulation time 127399938 ps
CPU time 63.56 seconds
Started Mar 24 01:18:15 PM PDT 24
Finished Mar 24 01:19:19 PM PDT 24
Peak memory 323732 kb
Host smart-bb973501-934a-40e9-a12b-2de17e576666
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191739886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.4191739886
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.839970385
Short name T333
Test name
Test status
Simulation time 541704333 ps
CPU time 16.19 seconds
Started Mar 24 01:18:18 PM PDT 24
Finished Mar 24 01:18:34 PM PDT 24
Peak memory 202980 kb
Host smart-95417676-27dc-4ed5-8d84-3c43ee42e958
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839970385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.sram_ctrl_access_during_key_req.839970385
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.2791296064
Short name T854
Test name
Test status
Simulation time 14346918 ps
CPU time 0.64 seconds
Started Mar 24 01:18:25 PM PDT 24
Finished Mar 24 01:18:25 PM PDT 24
Peak memory 201144 kb
Host smart-7c496abe-f0ac-449d-b415-25136305daf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791296064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.2791296064
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.289512964
Short name T610
Test name
Test status
Simulation time 8067764090 ps
CPU time 20.38 seconds
Started Mar 24 01:18:18 PM PDT 24
Finished Mar 24 01:18:39 PM PDT 24
Peak memory 202064 kb
Host smart-5f92d978-2b73-440f-9e05-1a741e861989
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289512964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.
289512964
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.517102171
Short name T561
Test name
Test status
Simulation time 19908862084 ps
CPU time 776.45 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:31:14 PM PDT 24
Peak memory 373928 kb
Host smart-24b49c48-1c8b-4e1d-888a-a4404b52f33f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517102171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executabl
e.517102171
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.2775916856
Short name T479
Test name
Test status
Simulation time 1261482666 ps
CPU time 11.04 seconds
Started Mar 24 01:18:16 PM PDT 24
Finished Mar 24 01:18:28 PM PDT 24
Peak memory 202052 kb
Host smart-3d2ca30e-7dc6-46e6-884e-9edebb587477
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775916856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.2775916856
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.2169934557
Short name T307
Test name
Test status
Simulation time 231350319 ps
CPU time 8.71 seconds
Started Mar 24 01:18:18 PM PDT 24
Finished Mar 24 01:18:27 PM PDT 24
Peak memory 239676 kb
Host smart-274e2276-91f9-4478-aa87-f4ccc870268d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169934557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.2169934557
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.918873605
Short name T224
Test name
Test status
Simulation time 353250573 ps
CPU time 2.92 seconds
Started Mar 24 01:18:26 PM PDT 24
Finished Mar 24 01:18:29 PM PDT 24
Peak memory 210148 kb
Host smart-35327c11-e5b6-4c03-b5b9-f92c3e64cf38
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918873605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_mem_partial_access.918873605
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.2018585637
Short name T203
Test name
Test status
Simulation time 1430770471 ps
CPU time 5.36 seconds
Started Mar 24 01:18:22 PM PDT 24
Finished Mar 24 01:18:27 PM PDT 24
Peak memory 201884 kb
Host smart-268f0567-0b0c-4794-b4ee-c02f94f14a08
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018585637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.2018585637
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.382111415
Short name T4
Test name
Test status
Simulation time 3042418738 ps
CPU time 1142.96 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:37:20 PM PDT 24
Peak memory 373932 kb
Host smart-80e2e798-624e-417f-a4bb-e5b43bd15126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382111415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip
le_keys.382111415
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.1877555
Short name T416
Test name
Test status
Simulation time 54850468 ps
CPU time 1.32 seconds
Started Mar 24 01:18:16 PM PDT 24
Finished Mar 24 01:18:18 PM PDT 24
Peak memory 202216 kb
Host smart-d220cd87-3fdf-40f2-9816-ffafbf1ec163
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sra
m_ctrl_partial_access.1877555
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2753455345
Short name T629
Test name
Test status
Simulation time 24389028118 ps
CPU time 213.02 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:21:50 PM PDT 24
Peak memory 202056 kb
Host smart-3858abd7-ce28-483f-bf9b-375e7b09bb36
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753455345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.2753455345
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.3565007035
Short name T152
Test name
Test status
Simulation time 31572989 ps
CPU time 0.75 seconds
Started Mar 24 01:18:23 PM PDT 24
Finished Mar 24 01:18:24 PM PDT 24
Peak memory 202148 kb
Host smart-79b5e586-c3a8-4060-947f-b3c6fac9c69f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565007035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3565007035
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.3063321581
Short name T223
Test name
Test status
Simulation time 3228286151 ps
CPU time 937.83 seconds
Started Mar 24 01:18:18 PM PDT 24
Finished Mar 24 01:33:56 PM PDT 24
Peak memory 365580 kb
Host smart-4e42f561-79bb-49d8-ae6d-e8e5dccb7eeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063321581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3063321581
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.2894736896
Short name T931
Test name
Test status
Simulation time 817849923 ps
CPU time 13.49 seconds
Started Mar 24 01:18:17 PM PDT 24
Finished Mar 24 01:18:31 PM PDT 24
Peak memory 201992 kb
Host smart-71f0f5ba-70e4-4e6e-ba81-ad67b04f6cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894736896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2894736896
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.516363282
Short name T499
Test name
Test status
Simulation time 63276304128 ps
CPU time 1181.03 seconds
Started Mar 24 01:18:22 PM PDT 24
Finished Mar 24 01:38:03 PM PDT 24
Peak memory 381180 kb
Host smart-c3db391a-1f97-441d-a032-f4351df4a8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516363282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_stress_all.516363282
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2504680947
Short name T522
Test name
Test status
Simulation time 2054626074 ps
CPU time 238.26 seconds
Started Mar 24 01:18:23 PM PDT 24
Finished Mar 24 01:22:21 PM PDT 24
Peak memory 377924 kb
Host smart-d657b666-c51f-4a1f-8026-89663bf95b03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2504680947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2504680947
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.374766493
Short name T582
Test name
Test status
Simulation time 3179608562 ps
CPU time 288.78 seconds
Started Mar 24 01:18:16 PM PDT 24
Finished Mar 24 01:23:05 PM PDT 24
Peak memory 202072 kb
Host smart-12c5c235-e5d5-4fb9-a444-0b41855a50eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374766493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_stress_pipeline.374766493
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.661550788
Short name T58
Test name
Test status
Simulation time 61648432 ps
CPU time 2.61 seconds
Started Mar 24 01:18:23 PM PDT 24
Finished Mar 24 01:18:26 PM PDT 24
Peak memory 218364 kb
Host smart-8aac7179-6255-4677-acbd-c55cde3b562d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661550788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_throughput_w_partial_write.661550788
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1118087058
Short name T804
Test name
Test status
Simulation time 6167571790 ps
CPU time 334.47 seconds
Started Mar 24 01:18:27 PM PDT 24
Finished Mar 24 01:24:01 PM PDT 24
Peak memory 371756 kb
Host smart-fa7fed18-9f5b-446a-a431-27e55d5494c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118087058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.1118087058
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.1438739398
Short name T923
Test name
Test status
Simulation time 52229230 ps
CPU time 0.61 seconds
Started Mar 24 01:18:27 PM PDT 24
Finished Mar 24 01:18:28 PM PDT 24
Peak memory 200932 kb
Host smart-2e72f4d6-ed96-46fb-93b2-6af9b1151d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438739398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.1438739398
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.2907331287
Short name T509
Test name
Test status
Simulation time 2372889417 ps
CPU time 40.24 seconds
Started Mar 24 01:18:22 PM PDT 24
Finished Mar 24 01:19:03 PM PDT 24
Peak memory 202036 kb
Host smart-bd68e1a7-00da-4049-8a84-d07e2582bc4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907331287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.2907331287
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.2579812769
Short name T826
Test name
Test status
Simulation time 3406677246 ps
CPU time 499.25 seconds
Started Mar 24 01:18:24 PM PDT 24
Finished Mar 24 01:26:43 PM PDT 24
Peak memory 369488 kb
Host smart-cfab7ecc-f6cf-4928-b534-22d5ac9dfcab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579812769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.2579812769
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.3201657291
Short name T784
Test name
Test status
Simulation time 4487904071 ps
CPU time 5.67 seconds
Started Mar 24 01:18:24 PM PDT 24
Finished Mar 24 01:18:30 PM PDT 24
Peak memory 202168 kb
Host smart-b3806058-9b8c-4446-94cb-e0d608614a7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201657291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.3201657291
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.2351959211
Short name T324
Test name
Test status
Simulation time 280410078 ps
CPU time 13.57 seconds
Started Mar 24 01:18:22 PM PDT 24
Finished Mar 24 01:18:35 PM PDT 24
Peak memory 264008 kb
Host smart-baf62dc4-b14e-4747-bb8e-e9600c6db7e3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351959211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.2351959211
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.4119882407
Short name T346
Test name
Test status
Simulation time 492234218 ps
CPU time 2.91 seconds
Started Mar 24 01:18:40 PM PDT 24
Finished Mar 24 01:18:43 PM PDT 24
Peak memory 210416 kb
Host smart-f6030f6b-faf3-40f7-8b17-0243f5713b74
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119882407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.4119882407
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.1639001407
Short name T636
Test name
Test status
Simulation time 2779203057 ps
CPU time 6.19 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:18:40 PM PDT 24
Peak memory 201824 kb
Host smart-ef85e1be-f20e-4976-8708-b315534ed133
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639001407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.1639001407
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.3652879448
Short name T168
Test name
Test status
Simulation time 738459103 ps
CPU time 11.13 seconds
Started Mar 24 01:18:24 PM PDT 24
Finished Mar 24 01:18:35 PM PDT 24
Peak memory 202020 kb
Host smart-d7466d5b-2583-42b0-b153-bd5bce1cb7f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652879448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.3652879448
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.3235364878
Short name T858
Test name
Test status
Simulation time 67036789 ps
CPU time 0.92 seconds
Started Mar 24 01:18:23 PM PDT 24
Finished Mar 24 01:18:24 PM PDT 24
Peak memory 201824 kb
Host smart-5e797eee-a34c-449b-91e5-07176587bfce
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235364878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.3235364878
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1011842150
Short name T805
Test name
Test status
Simulation time 31402713678 ps
CPU time 407.51 seconds
Started Mar 24 01:18:23 PM PDT 24
Finished Mar 24 01:25:11 PM PDT 24
Peak memory 202072 kb
Host smart-d17db1ad-691d-41f6-9e2a-01ad68a5354c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011842150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.1011842150
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.1372706019
Short name T184
Test name
Test status
Simulation time 105657614 ps
CPU time 0.77 seconds
Started Mar 24 01:18:27 PM PDT 24
Finished Mar 24 01:18:28 PM PDT 24
Peak memory 202132 kb
Host smart-3dcc89ba-2721-4f2a-8a39-3853b1c41dd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372706019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1372706019
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.1725633060
Short name T770
Test name
Test status
Simulation time 17597068833 ps
CPU time 351.52 seconds
Started Mar 24 01:18:28 PM PDT 24
Finished Mar 24 01:24:20 PM PDT 24
Peak memory 363056 kb
Host smart-9d293f3b-af2a-49c7-b1d7-b13b142e277b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725633060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1725633060
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3487192856
Short name T385
Test name
Test status
Simulation time 753410741 ps
CPU time 36.23 seconds
Started Mar 24 01:18:26 PM PDT 24
Finished Mar 24 01:19:02 PM PDT 24
Peak memory 285856 kb
Host smart-b91a1618-c6b4-4986-9593-7de24045e11a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487192856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3487192856
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.974255016
Short name T687
Test name
Test status
Simulation time 49245595416 ps
CPU time 4055.18 seconds
Started Mar 24 01:18:28 PM PDT 24
Finished Mar 24 02:26:03 PM PDT 24
Peak memory 381840 kb
Host smart-6c4219d9-0747-4c98-9a3e-9431f73f084e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974255016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_stress_all.974255016
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3389591166
Short name T30
Test name
Test status
Simulation time 297742250 ps
CPU time 8.86 seconds
Started Mar 24 01:18:27 PM PDT 24
Finished Mar 24 01:18:36 PM PDT 24
Peak memory 210312 kb
Host smart-1bd5a377-bd37-4725-8d30-c705b7065e22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3389591166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3389591166
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1984488183
Short name T742
Test name
Test status
Simulation time 4840257808 ps
CPU time 224.99 seconds
Started Mar 24 01:18:22 PM PDT 24
Finished Mar 24 01:22:07 PM PDT 24
Peak memory 202072 kb
Host smart-42a41383-188c-4d0f-bb27-71255c247905
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984488183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.1984488183
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1640597691
Short name T205
Test name
Test status
Simulation time 171291235 ps
CPU time 1.31 seconds
Started Mar 24 01:18:25 PM PDT 24
Finished Mar 24 01:18:27 PM PDT 24
Peak memory 210440 kb
Host smart-6fcac75d-d294-4e4f-a4e3-3a4fc4679c0c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640597691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1640597691
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.638311980
Short name T744
Test name
Test status
Simulation time 1099293332 ps
CPU time 25.78 seconds
Started Mar 24 01:17:01 PM PDT 24
Finished Mar 24 01:17:27 PM PDT 24
Peak memory 250364 kb
Host smart-4edff610-f6a6-464e-a527-a883578ead31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638311980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_access_during_key_req.638311980
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.450050108
Short name T650
Test name
Test status
Simulation time 11883913 ps
CPU time 0.6 seconds
Started Mar 24 01:16:52 PM PDT 24
Finished Mar 24 01:16:52 PM PDT 24
Peak memory 201184 kb
Host smart-98abeddf-6a3e-4155-ab45-d6e254c06dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450050108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.450050108
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.3412823832
Short name T728
Test name
Test status
Simulation time 1599739028 ps
CPU time 33.53 seconds
Started Mar 24 01:16:51 PM PDT 24
Finished Mar 24 01:17:25 PM PDT 24
Peak memory 201984 kb
Host smart-77a213fb-6cd0-4ca2-8409-a7d2103fafe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412823832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
3412823832
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.3413279134
Short name T131
Test name
Test status
Simulation time 37974491338 ps
CPU time 663.77 seconds
Started Mar 24 01:16:54 PM PDT 24
Finished Mar 24 01:27:59 PM PDT 24
Peak memory 367000 kb
Host smart-5a13d8a4-1dfa-494a-847d-5f7926bc1956
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413279134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.3413279134
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.120731378
Short name T900
Test name
Test status
Simulation time 2174819494 ps
CPU time 6.42 seconds
Started Mar 24 01:17:00 PM PDT 24
Finished Mar 24 01:17:06 PM PDT 24
Peak memory 210224 kb
Host smart-b64bc304-0832-4ab7-abbe-90e8e2b837a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120731378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esca
lation.120731378
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.252723941
Short name T162
Test name
Test status
Simulation time 437481871 ps
CPU time 37.79 seconds
Started Mar 24 01:17:00 PM PDT 24
Finished Mar 24 01:17:38 PM PDT 24
Peak memory 305564 kb
Host smart-6216566a-fe04-41d4-9f2f-765a6c00099e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252723941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.sram_ctrl_max_throughput.252723941
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1055295365
Short name T611
Test name
Test status
Simulation time 166587614 ps
CPU time 2.76 seconds
Started Mar 24 01:16:59 PM PDT 24
Finished Mar 24 01:17:02 PM PDT 24
Peak memory 210168 kb
Host smart-fd402e77-3dfb-427b-bfb0-38758f8bc693
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055295365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.1055295365
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.2749264463
Short name T686
Test name
Test status
Simulation time 1368039754 ps
CPU time 10.17 seconds
Started Mar 24 01:16:53 PM PDT 24
Finished Mar 24 01:17:04 PM PDT 24
Peak memory 201936 kb
Host smart-db438670-f59f-480c-85ae-b2008d09d326
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749264463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.2749264463
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.1830101322
Short name T57
Test name
Test status
Simulation time 287005484 ps
CPU time 16.52 seconds
Started Mar 24 01:16:53 PM PDT 24
Finished Mar 24 01:17:10 PM PDT 24
Peak memory 202080 kb
Host smart-5655a43a-0f99-4bdc-981f-cb202cc391f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830101322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.1830101322
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.1611336915
Short name T408
Test name
Test status
Simulation time 190610817 ps
CPU time 2.39 seconds
Started Mar 24 01:16:53 PM PDT 24
Finished Mar 24 01:16:56 PM PDT 24
Peak memory 205352 kb
Host smart-53504dde-67f3-409c-8fc3-666ffcf5190e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611336915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.1611336915
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.195935410
Short name T531
Test name
Test status
Simulation time 19301938805 ps
CPU time 423.86 seconds
Started Mar 24 01:17:07 PM PDT 24
Finished Mar 24 01:24:11 PM PDT 24
Peak memory 202040 kb
Host smart-172db586-2359-44b8-8dfb-079fe955d761
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195935410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.sram_ctrl_partial_access_b2b.195935410
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.3034304695
Short name T758
Test name
Test status
Simulation time 80628320 ps
CPU time 0.72 seconds
Started Mar 24 01:16:55 PM PDT 24
Finished Mar 24 01:16:55 PM PDT 24
Peak memory 202108 kb
Host smart-8b4c4e68-4a49-456d-8692-3ff168e60347
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034304695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3034304695
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1841221517
Short name T609
Test name
Test status
Simulation time 30179950818 ps
CPU time 2750.45 seconds
Started Mar 24 01:16:53 PM PDT 24
Finished Mar 24 02:02:45 PM PDT 24
Peak memory 373764 kb
Host smart-f114a7ed-3eca-4edb-b2f1-0c34d81bc04d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841221517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1841221517
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.3125270310
Short name T36
Test name
Test status
Simulation time 244673700 ps
CPU time 3.29 seconds
Started Mar 24 01:17:03 PM PDT 24
Finished Mar 24 01:17:06 PM PDT 24
Peak memory 221900 kb
Host smart-938f95fb-149b-4a80-b30e-0fa435ac62ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125270310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.3125270310
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.314605971
Short name T207
Test name
Test status
Simulation time 750099799 ps
CPU time 16.61 seconds
Started Mar 24 01:16:57 PM PDT 24
Finished Mar 24 01:17:14 PM PDT 24
Peak memory 202068 kb
Host smart-0077f94a-e90a-4b2a-b29f-918d4086c4d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314605971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.314605971
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.2744059080
Short name T533
Test name
Test status
Simulation time 28952991463 ps
CPU time 3140.79 seconds
Started Mar 24 01:16:53 PM PDT 24
Finished Mar 24 02:09:14 PM PDT 24
Peak memory 373952 kb
Host smart-a92026ad-bed5-46ac-a8de-750670dfce84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744059080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.2744059080
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2817388928
Short name T26
Test name
Test status
Simulation time 347439891 ps
CPU time 11.21 seconds
Started Mar 24 01:17:04 PM PDT 24
Finished Mar 24 01:17:16 PM PDT 24
Peak memory 210292 kb
Host smart-383f3e27-9bb4-42e2-8133-bcecec77f3e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2817388928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2817388928
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.3191113450
Short name T188
Test name
Test status
Simulation time 14423845560 ps
CPU time 299.81 seconds
Started Mar 24 01:16:59 PM PDT 24
Finished Mar 24 01:21:59 PM PDT 24
Peak memory 202040 kb
Host smart-6910bbf3-45a3-4fe4-a416-b406637f9092
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191113450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.3191113450
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3481912370
Short name T449
Test name
Test status
Simulation time 1178899897 ps
CPU time 10.08 seconds
Started Mar 24 01:16:58 PM PDT 24
Finished Mar 24 01:17:08 PM PDT 24
Peak memory 242180 kb
Host smart-cf0e8b3c-cd40-45cd-9fed-b26a4412af1e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481912370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.3481912370
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3707399393
Short name T14
Test name
Test status
Simulation time 3991392029 ps
CPU time 224.47 seconds
Started Mar 24 01:18:29 PM PDT 24
Finished Mar 24 01:22:14 PM PDT 24
Peak memory 357448 kb
Host smart-178fbc0d-15a6-43a9-a495-6e41282a8adf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707399393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.3707399393
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.644236958
Short name T354
Test name
Test status
Simulation time 20253088 ps
CPU time 0.65 seconds
Started Mar 24 01:18:31 PM PDT 24
Finished Mar 24 01:18:33 PM PDT 24
Peak memory 201816 kb
Host smart-7a91acf0-ff07-460b-95c8-0716c9f5b3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644236958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.644236958
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.523759323
Short name T343
Test name
Test status
Simulation time 1381388834 ps
CPU time 40.61 seconds
Started Mar 24 01:18:30 PM PDT 24
Finished Mar 24 01:19:10 PM PDT 24
Peak memory 201988 kb
Host smart-93612a87-5572-4e26-826d-1fe095180dea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523759323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.
523759323
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.578099909
Short name T818
Test name
Test status
Simulation time 45374926469 ps
CPU time 1013.74 seconds
Started Mar 24 01:18:29 PM PDT 24
Finished Mar 24 01:35:22 PM PDT 24
Peak memory 365824 kb
Host smart-35fbd3a9-6c3e-46ab-80fb-357ad4019f2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578099909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl
e.578099909
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.914685524
Short name T371
Test name
Test status
Simulation time 1213229707 ps
CPU time 7.22 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:18:40 PM PDT 24
Peak memory 202008 kb
Host smart-a0ab2f35-c814-4449-9390-a464fe3029f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914685524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_esc
alation.914685524
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.1965402616
Short name T924
Test name
Test status
Simulation time 529116261 ps
CPU time 2.36 seconds
Started Mar 24 01:18:29 PM PDT 24
Finished Mar 24 01:18:31 PM PDT 24
Peak memory 216224 kb
Host smart-f275154f-aeb9-4066-a3c7-adc3d90e6074
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965402616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.1965402616
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.414550675
Short name T373
Test name
Test status
Simulation time 82386829 ps
CPU time 2.37 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:18:35 PM PDT 24
Peak memory 210180 kb
Host smart-d29667bc-eff9-4370-be96-1a099c3f66f8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414550675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.sram_ctrl_mem_partial_access.414550675
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.776143456
Short name T809
Test name
Test status
Simulation time 83973224 ps
CPU time 4.64 seconds
Started Mar 24 01:18:28 PM PDT 24
Finished Mar 24 01:18:33 PM PDT 24
Peak memory 201976 kb
Host smart-096751ba-f2fc-440f-b493-5f90a364c0f2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776143456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl
_mem_walk.776143456
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.544496192
Short name T174
Test name
Test status
Simulation time 18292070255 ps
CPU time 129.65 seconds
Started Mar 24 01:18:29 PM PDT 24
Finished Mar 24 01:20:39 PM PDT 24
Peak memory 343192 kb
Host smart-6409c47c-69f4-4be3-b5c8-c9bcf533b07c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544496192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multip
le_keys.544496192
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.2999158683
Short name T503
Test name
Test status
Simulation time 956758617 ps
CPU time 7.68 seconds
Started Mar 24 01:18:33 PM PDT 24
Finished Mar 24 01:18:41 PM PDT 24
Peak memory 201772 kb
Host smart-a93995fa-b00b-4fc3-8844-9302c14e3545
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999158683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.2999158683
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2711678703
Short name T938
Test name
Test status
Simulation time 30546305393 ps
CPU time 220.96 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:22:14 PM PDT 24
Peak memory 202040 kb
Host smart-1e6f5cdf-5c06-4c49-b9cc-a9acc49bf500
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711678703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.2711678703
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.3706912009
Short name T579
Test name
Test status
Simulation time 49587168 ps
CPU time 0.75 seconds
Started Mar 24 01:18:30 PM PDT 24
Finished Mar 24 01:18:31 PM PDT 24
Peak memory 202116 kb
Host smart-16ae08bf-6ef6-436e-8b42-661ff435e7d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706912009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3706912009
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.3234828046
Short name T747
Test name
Test status
Simulation time 4794569254 ps
CPU time 582.65 seconds
Started Mar 24 01:18:30 PM PDT 24
Finished Mar 24 01:28:13 PM PDT 24
Peak memory 371824 kb
Host smart-bc3a5bf3-402a-4cbe-b80b-e99fedae1566
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234828046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3234828046
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.2752428537
Short name T703
Test name
Test status
Simulation time 431175332 ps
CPU time 30.32 seconds
Started Mar 24 01:18:31 PM PDT 24
Finished Mar 24 01:19:01 PM PDT 24
Peak memory 286528 kb
Host smart-e9812077-ae41-42e7-9614-24e6762178b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752428537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2752428537
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.720656981
Short name T574
Test name
Test status
Simulation time 67641216261 ps
CPU time 2914.15 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 02:07:07 PM PDT 24
Peak memory 381752 kb
Host smart-af28fd44-5844-4c96-9e38-640b71036887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720656981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_stress_all.720656981
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4138032585
Short name T510
Test name
Test status
Simulation time 3785123682 ps
CPU time 461.96 seconds
Started Mar 24 01:18:34 PM PDT 24
Finished Mar 24 01:26:16 PM PDT 24
Peak memory 371612 kb
Host smart-85b33c20-2af3-493f-ac34-55a6ee7f7441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4138032585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.4138032585
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1437423794
Short name T706
Test name
Test status
Simulation time 4418617117 ps
CPU time 204.59 seconds
Started Mar 24 01:18:27 PM PDT 24
Finished Mar 24 01:21:52 PM PDT 24
Peak memory 202040 kb
Host smart-07751b56-e1ca-48d2-b885-d20336c133ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437423794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.1437423794
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1123377960
Short name T150
Test name
Test status
Simulation time 106635062 ps
CPU time 35.52 seconds
Started Mar 24 01:18:30 PM PDT 24
Finished Mar 24 01:19:06 PM PDT 24
Peak memory 292772 kb
Host smart-2cb085bd-c1d2-4d10-a99b-aa347c232d86
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123377960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1123377960
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2692472573
Short name T549
Test name
Test status
Simulation time 10820546213 ps
CPU time 698.02 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:30:11 PM PDT 24
Peak memory 366664 kb
Host smart-965e1d1d-b9e1-4806-a30f-3b000cd97285
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692472573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.2692472573
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.3478036216
Short name T892
Test name
Test status
Simulation time 12868970 ps
CPU time 0.61 seconds
Started Mar 24 01:18:34 PM PDT 24
Finished Mar 24 01:18:35 PM PDT 24
Peak memory 201768 kb
Host smart-5bc396da-93e8-4a0e-aa92-4a031a3508dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478036216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.3478036216
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.1372527554
Short name T508
Test name
Test status
Simulation time 16250113716 ps
CPU time 61.84 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:19:35 PM PDT 24
Peak memory 202084 kb
Host smart-c7387e98-f6dc-4d85-84d5-ae20771aab3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372527554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.1372527554
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.3042752075
Short name T698
Test name
Test status
Simulation time 6005458388 ps
CPU time 284.49 seconds
Started Mar 24 01:18:33 PM PDT 24
Finished Mar 24 01:23:18 PM PDT 24
Peak memory 350924 kb
Host smart-fde52c59-e5bf-4eb4-8389-c98bbc7cf4e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042752075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.3042752075
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.1419089681
Short name T841
Test name
Test status
Simulation time 2471303691 ps
CPU time 7.44 seconds
Started Mar 24 01:18:31 PM PDT 24
Finished Mar 24 01:18:40 PM PDT 24
Peak memory 210352 kb
Host smart-1c810073-8697-461a-a331-1a15f23ca97c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419089681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.1419089681
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.2309380212
Short name T10
Test name
Test status
Simulation time 139922623 ps
CPU time 119.31 seconds
Started Mar 24 01:18:34 PM PDT 24
Finished Mar 24 01:20:33 PM PDT 24
Peak memory 368848 kb
Host smart-e4227d08-27aa-430f-ac04-affb8fa23b5e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309380212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.2309380212
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.765350830
Short name T6
Test name
Test status
Simulation time 727663050 ps
CPU time 4.74 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:18:38 PM PDT 24
Peak memory 210056 kb
Host smart-7ac36b41-8b39-4dc0-bed9-ef45d6c6cc5c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765350830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.sram_ctrl_mem_partial_access.765350830
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.3899347820
Short name T414
Test name
Test status
Simulation time 2446694918 ps
CPU time 9.65 seconds
Started Mar 24 01:18:33 PM PDT 24
Finished Mar 24 01:18:43 PM PDT 24
Peak memory 201980 kb
Host smart-1936e4cb-1081-437a-ae17-f6903d529d1c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899347820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.3899347820
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.2216531864
Short name T633
Test name
Test status
Simulation time 24438171938 ps
CPU time 1357.69 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:41:11 PM PDT 24
Peak memory 373516 kb
Host smart-341053d6-3905-4ae1-8451-e36ac11d535c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216531864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.2216531864
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.3868254134
Short name T256
Test name
Test status
Simulation time 217952204 ps
CPU time 7.8 seconds
Started Mar 24 01:18:33 PM PDT 24
Finished Mar 24 01:18:41 PM PDT 24
Peak memory 202068 kb
Host smart-662985cc-7d6b-40a9-a51a-53f733ba0f41
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868254134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.3868254134
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2444258289
Short name T705
Test name
Test status
Simulation time 83379350196 ps
CPU time 514.5 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:27:07 PM PDT 24
Peak memory 202076 kb
Host smart-ef1e14e8-fe39-43ca-93e8-45869111b2b4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444258289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.2444258289
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.776325307
Short name T734
Test name
Test status
Simulation time 81476854 ps
CPU time 0.74 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:18:34 PM PDT 24
Peak memory 202052 kb
Host smart-507c03e4-4318-43a9-a930-16d6a2fcfa64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776325307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.776325307
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.708377476
Short name T292
Test name
Test status
Simulation time 84029603883 ps
CPU time 912.4 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:33:45 PM PDT 24
Peak memory 366752 kb
Host smart-468d281e-2859-409f-92c4-38655e1ee18d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708377476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.708377476
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.1196712672
Short name T320
Test name
Test status
Simulation time 37433959 ps
CPU time 1.53 seconds
Started Mar 24 01:18:30 PM PDT 24
Finished Mar 24 01:18:32 PM PDT 24
Peak memory 201984 kb
Host smart-107d7f0f-ba2b-4144-9b68-f5b2290ec856
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196712672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1196712672
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.1599243426
Short name T404
Test name
Test status
Simulation time 50116539294 ps
CPU time 2290.83 seconds
Started Mar 24 01:18:35 PM PDT 24
Finished Mar 24 01:56:47 PM PDT 24
Peak memory 373784 kb
Host smart-17eb092b-0057-4d4a-adaa-8c205c9e2ae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599243426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.1599243426
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3473887972
Short name T115
Test name
Test status
Simulation time 13512482162 ps
CPU time 145.38 seconds
Started Mar 24 01:18:36 PM PDT 24
Finished Mar 24 01:21:01 PM PDT 24
Peak memory 379868 kb
Host smart-2eed1e0f-5692-4a08-b598-997eb44baac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3473887972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3473887972
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2961103270
Short name T231
Test name
Test status
Simulation time 2407648213 ps
CPU time 115.18 seconds
Started Mar 24 01:18:32 PM PDT 24
Finished Mar 24 01:20:28 PM PDT 24
Peak memory 202008 kb
Host smart-bc8a148f-36ff-4977-b978-614b549fff27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961103270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.2961103270
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2800116788
Short name T850
Test name
Test status
Simulation time 420088015 ps
CPU time 35.51 seconds
Started Mar 24 01:18:31 PM PDT 24
Finished Mar 24 01:19:06 PM PDT 24
Peak memory 287944 kb
Host smart-01603a14-4dd1-4667-bb55-5e78a8fa46fb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800116788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2800116788
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1434020969
Short name T844
Test name
Test status
Simulation time 2352984156 ps
CPU time 329.02 seconds
Started Mar 24 01:18:38 PM PDT 24
Finished Mar 24 01:24:07 PM PDT 24
Peak memory 326828 kb
Host smart-7806dcea-ef7d-4521-a2b4-5170fc64b69e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434020969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.1434020969
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.3491898223
Short name T883
Test name
Test status
Simulation time 14277589 ps
CPU time 0.66 seconds
Started Mar 24 01:18:46 PM PDT 24
Finished Mar 24 01:18:48 PM PDT 24
Peak memory 200976 kb
Host smart-27806473-a0bd-42f6-80ce-1c0090f3b23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491898223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.3491898223
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.1026209049
Short name T478
Test name
Test status
Simulation time 5403487519 ps
CPU time 79.79 seconds
Started Mar 24 01:18:39 PM PDT 24
Finished Mar 24 01:19:58 PM PDT 24
Peak memory 202160 kb
Host smart-0fe5745d-dded-4f9a-960e-5247629e3415
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026209049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.1026209049
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.1150689766
Short name T743
Test name
Test status
Simulation time 9883688295 ps
CPU time 243.53 seconds
Started Mar 24 01:18:42 PM PDT 24
Finished Mar 24 01:22:45 PM PDT 24
Peak memory 346012 kb
Host smart-ca8c7d37-53c5-434c-afb8-6255412e2e36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150689766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.1150689766
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.1012397652
Short name T295
Test name
Test status
Simulation time 526386574 ps
CPU time 5.42 seconds
Started Mar 24 01:18:38 PM PDT 24
Finished Mar 24 01:18:44 PM PDT 24
Peak memory 202256 kb
Host smart-007d49fd-e179-4dd2-81b0-ac5abc34086f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012397652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.1012397652
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.2127243376
Short name T665
Test name
Test status
Simulation time 263002202 ps
CPU time 151.02 seconds
Started Mar 24 01:18:36 PM PDT 24
Finished Mar 24 01:21:07 PM PDT 24
Peak memory 369680 kb
Host smart-0fa3a109-840f-492a-a079-ffd8a7a603ec
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127243376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.2127243376
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.925959454
Short name T891
Test name
Test status
Simulation time 655613263 ps
CPU time 4.83 seconds
Started Mar 24 01:18:42 PM PDT 24
Finished Mar 24 01:18:47 PM PDT 24
Peak memory 210144 kb
Host smart-892cb4c1-8d55-4ee0-8fe6-bb7810dd31dc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925959454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_mem_partial_access.925959454
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.1319401358
Short name T278
Test name
Test status
Simulation time 494988640 ps
CPU time 4.73 seconds
Started Mar 24 01:18:40 PM PDT 24
Finished Mar 24 01:18:45 PM PDT 24
Peak memory 201944 kb
Host smart-c82c9176-341d-420c-8d98-92d03e026ea9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319401358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.1319401358
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.2398995394
Short name T274
Test name
Test status
Simulation time 5766513507 ps
CPU time 931.01 seconds
Started Mar 24 01:18:36 PM PDT 24
Finished Mar 24 01:34:07 PM PDT 24
Peak memory 372804 kb
Host smart-b2f581a2-0f7d-4b4d-ad00-487fbd16a5c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398995394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.2398995394
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.913063124
Short name T146
Test name
Test status
Simulation time 213460813 ps
CPU time 3.5 seconds
Started Mar 24 01:18:35 PM PDT 24
Finished Mar 24 01:18:38 PM PDT 24
Peak memory 211172 kb
Host smart-4efd78e0-e072-4006-ba78-94482e8df6d6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913063124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.s
ram_ctrl_partial_access.913063124
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1385953057
Short name T802
Test name
Test status
Simulation time 74750414843 ps
CPU time 416.39 seconds
Started Mar 24 01:18:36 PM PDT 24
Finished Mar 24 01:25:33 PM PDT 24
Peak memory 202016 kb
Host smart-7ace491a-c23b-4c88-8e9f-f2751f937029
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385953057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.1385953057
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.58355085
Short name T660
Test name
Test status
Simulation time 28716120 ps
CPU time 0.77 seconds
Started Mar 24 01:18:41 PM PDT 24
Finished Mar 24 01:18:42 PM PDT 24
Peak memory 202192 kb
Host smart-8f25eb06-4480-4d7d-a76b-c6b40fe2aa80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58355085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.58355085
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.3481399753
Short name T498
Test name
Test status
Simulation time 835985626 ps
CPU time 13.14 seconds
Started Mar 24 01:18:35 PM PDT 24
Finished Mar 24 01:18:49 PM PDT 24
Peak memory 246808 kb
Host smart-929f2f59-d2e2-46b6-aa61-3e2eb895fd0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481399753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3481399753
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.2843016413
Short name T142
Test name
Test status
Simulation time 166014442042 ps
CPU time 2670.57 seconds
Started Mar 24 01:18:41 PM PDT 24
Finished Mar 24 02:03:13 PM PDT 24
Peak memory 375948 kb
Host smart-9427b2bd-d074-4a9c-ad96-733f3d08706e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843016413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.sram_ctrl_stress_all.2843016413
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.690541081
Short name T882
Test name
Test status
Simulation time 1771483551 ps
CPU time 73.71 seconds
Started Mar 24 01:18:44 PM PDT 24
Finished Mar 24 01:19:58 PM PDT 24
Peak memory 349288 kb
Host smart-3086dd3c-6d2b-45b0-9746-b6fd620ddb7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=690541081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.690541081
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.903266842
Short name T752
Test name
Test status
Simulation time 4813897490 ps
CPU time 109.27 seconds
Started Mar 24 01:18:36 PM PDT 24
Finished Mar 24 01:20:26 PM PDT 24
Peak memory 202052 kb
Host smart-3124b448-3250-479f-906e-0d5711683f3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903266842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_stress_pipeline.903266842
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2501474223
Short name T755
Test name
Test status
Simulation time 55160215 ps
CPU time 1.53 seconds
Started Mar 24 01:18:35 PM PDT 24
Finished Mar 24 01:18:36 PM PDT 24
Peak memory 210204 kb
Host smart-b3bcfae3-04ad-4c1a-b206-d9be9364719f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501474223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2501474223
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.4045231520
Short name T447
Test name
Test status
Simulation time 1002328253 ps
CPU time 366.89 seconds
Started Mar 24 01:18:43 PM PDT 24
Finished Mar 24 01:24:51 PM PDT 24
Peak memory 372112 kb
Host smart-ec5c5656-64c4-4e2b-ad3b-6577e56d3ad4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045231520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.4045231520
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.1837194864
Short name T161
Test name
Test status
Simulation time 34873615 ps
CPU time 0.66 seconds
Started Mar 24 01:18:49 PM PDT 24
Finished Mar 24 01:18:50 PM PDT 24
Peak memory 201816 kb
Host smart-1f601d4a-3353-4a3c-a04a-7820a3598f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837194864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.1837194864
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.2978984133
Short name T855
Test name
Test status
Simulation time 4215297033 ps
CPU time 61.46 seconds
Started Mar 24 01:18:47 PM PDT 24
Finished Mar 24 01:19:48 PM PDT 24
Peak memory 202088 kb
Host smart-3f3029e6-8888-4001-9c9a-dfaefa1cfce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978984133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.2978984133
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.1681472056
Short name T482
Test name
Test status
Simulation time 68843027644 ps
CPU time 1512 seconds
Started Mar 24 01:18:46 PM PDT 24
Finished Mar 24 01:43:59 PM PDT 24
Peak memory 372956 kb
Host smart-cb163746-84ab-4146-86c7-64a113fb653b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681472056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.1681472056
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.3557888098
Short name T709
Test name
Test status
Simulation time 734323101 ps
CPU time 7.69 seconds
Started Mar 24 01:18:43 PM PDT 24
Finished Mar 24 01:18:51 PM PDT 24
Peak memory 202048 kb
Host smart-74f32440-bdf7-4227-a7eb-42a0dbbde719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557888098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.3557888098
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.1491667017
Short name T51
Test name
Test status
Simulation time 347245448 ps
CPU time 20.39 seconds
Started Mar 24 01:18:44 PM PDT 24
Finished Mar 24 01:19:04 PM PDT 24
Peak memory 284720 kb
Host smart-769fbe38-b56d-4a61-a1e7-fcdec9ec3eb8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491667017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.1491667017
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2047388621
Short name T136
Test name
Test status
Simulation time 366188070 ps
CPU time 3.15 seconds
Started Mar 24 01:18:50 PM PDT 24
Finished Mar 24 01:18:53 PM PDT 24
Peak memory 210180 kb
Host smart-e11fa412-4b35-49c3-b222-32c0734d00a8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047388621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.2047388621
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.2108732092
Short name T339
Test name
Test status
Simulation time 287216319 ps
CPU time 4.51 seconds
Started Mar 24 01:18:46 PM PDT 24
Finished Mar 24 01:18:52 PM PDT 24
Peak memory 201856 kb
Host smart-009f483b-deba-45ac-8158-7453f9f3543d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108732092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.2108732092
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1892711888
Short name T825
Test name
Test status
Simulation time 3498273075 ps
CPU time 1298.16 seconds
Started Mar 24 01:18:46 PM PDT 24
Finished Mar 24 01:40:25 PM PDT 24
Peak memory 368772 kb
Host smart-5c28334f-d942-4888-ad75-84a4696b7a83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892711888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1892711888
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.691168382
Short name T61
Test name
Test status
Simulation time 2495768176 ps
CPU time 132.93 seconds
Started Mar 24 01:18:50 PM PDT 24
Finished Mar 24 01:21:03 PM PDT 24
Peak memory 362532 kb
Host smart-73849ef1-5953-4966-b5e7-695973698bfe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691168382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.s
ram_ctrl_partial_access.691168382
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1563749954
Short name T718
Test name
Test status
Simulation time 36282451255 ps
CPU time 211.62 seconds
Started Mar 24 01:18:42 PM PDT 24
Finished Mar 24 01:22:14 PM PDT 24
Peak memory 202044 kb
Host smart-d6c5ee86-3350-4575-930e-67c0ce24a71d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563749954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.1563749954
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.3406337571
Short name T816
Test name
Test status
Simulation time 31953811 ps
CPU time 0.78 seconds
Started Mar 24 01:18:45 PM PDT 24
Finished Mar 24 01:18:46 PM PDT 24
Peak memory 202180 kb
Host smart-09f344ac-baf0-4a20-8e41-436a20570b3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406337571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3406337571
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.1704837663
Short name T847
Test name
Test status
Simulation time 110422699299 ps
CPU time 1588.35 seconds
Started Mar 24 01:18:45 PM PDT 24
Finished Mar 24 01:45:14 PM PDT 24
Peak memory 372896 kb
Host smart-29ef3a45-9745-42d1-896e-7223f116aa71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704837663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1704837663
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.3434307575
Short name T260
Test name
Test status
Simulation time 465244014 ps
CPU time 9.95 seconds
Started Mar 24 01:18:40 PM PDT 24
Finished Mar 24 01:18:50 PM PDT 24
Peak memory 202052 kb
Host smart-3245b61e-6fbf-4a7b-972e-731428da8532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434307575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3434307575
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.3671251849
Short name T929
Test name
Test status
Simulation time 114553127484 ps
CPU time 1702.55 seconds
Started Mar 24 01:18:48 PM PDT 24
Finished Mar 24 01:47:11 PM PDT 24
Peak memory 379008 kb
Host smart-bd4c71c4-33f5-4c08-abe9-7000747e5a14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671251849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.3671251849
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3551727318
Short name T48
Test name
Test status
Simulation time 2351070360 ps
CPU time 31.95 seconds
Started Mar 24 01:18:47 PM PDT 24
Finished Mar 24 01:19:19 PM PDT 24
Peak memory 210432 kb
Host smart-6b5cc255-b8dc-4d13-bf4b-03bb653e0305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3551727318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3551727318
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3220480468
Short name T181
Test name
Test status
Simulation time 6599876877 ps
CPU time 167.7 seconds
Started Mar 24 01:18:41 PM PDT 24
Finished Mar 24 01:21:30 PM PDT 24
Peak memory 202032 kb
Host smart-a6cb203d-a793-491a-8546-fd906ec8e1e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220480468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.3220480468
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2991175899
Short name T228
Test name
Test status
Simulation time 577483936 ps
CPU time 154.79 seconds
Started Mar 24 01:18:42 PM PDT 24
Finished Mar 24 01:21:17 PM PDT 24
Peak memory 368644 kb
Host smart-e3ea174f-1dc4-4be5-bc40-5b3aa101cc24
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991175899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2991175899
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3123073779
Short name T458
Test name
Test status
Simulation time 10340783865 ps
CPU time 859.13 seconds
Started Mar 24 01:18:47 PM PDT 24
Finished Mar 24 01:33:07 PM PDT 24
Peak memory 370836 kb
Host smart-95e2188b-4d5b-44e8-adbf-a52662459210
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123073779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.3123073779
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.2275053796
Short name T783
Test name
Test status
Simulation time 18961438 ps
CPU time 0.72 seconds
Started Mar 24 01:18:51 PM PDT 24
Finished Mar 24 01:18:52 PM PDT 24
Peak memory 201812 kb
Host smart-f892abae-06da-4fe4-84dd-36adc9bb2eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275053796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.2275053796
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.1383088212
Short name T204
Test name
Test status
Simulation time 1829749320 ps
CPU time 36.9 seconds
Started Mar 24 01:18:46 PM PDT 24
Finished Mar 24 01:19:23 PM PDT 24
Peak memory 201996 kb
Host smart-488b5e9a-63ef-4eaa-88f0-298c4d0d10e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383088212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.1383088212
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.1817663886
Short name T272
Test name
Test status
Simulation time 27496801098 ps
CPU time 863.91 seconds
Started Mar 24 01:18:46 PM PDT 24
Finished Mar 24 01:33:10 PM PDT 24
Peak memory 364972 kb
Host smart-8b2d7f07-1123-4b8a-bc43-43a7b28ba203
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817663886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.1817663886
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.1287590660
Short name T321
Test name
Test status
Simulation time 530737347 ps
CPU time 6.6 seconds
Started Mar 24 01:18:48 PM PDT 24
Finished Mar 24 01:18:55 PM PDT 24
Peak memory 202008 kb
Host smart-880577af-3d96-4ee3-96d5-38faa15e46cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287590660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.1287590660
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.2567855483
Short name T840
Test name
Test status
Simulation time 159858089 ps
CPU time 2.56 seconds
Started Mar 24 01:18:51 PM PDT 24
Finished Mar 24 01:18:54 PM PDT 24
Peak memory 218272 kb
Host smart-8fa182e0-30b4-4860-b440-3ec1ef1f6c50
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567855483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.2567855483
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2787929964
Short name T340
Test name
Test status
Simulation time 45912996 ps
CPU time 2.49 seconds
Started Mar 24 01:18:46 PM PDT 24
Finished Mar 24 01:18:49 PM PDT 24
Peak memory 210276 kb
Host smart-b8408220-c6bd-448a-905e-bd526fa682ff
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787929964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.2787929964
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.3256931897
Short name T871
Test name
Test status
Simulation time 929737048 ps
CPU time 5.04 seconds
Started Mar 24 01:18:47 PM PDT 24
Finished Mar 24 01:18:53 PM PDT 24
Peak memory 201972 kb
Host smart-51ef4790-3f01-4cee-a630-3ebeda8a8c4c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256931897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.3256931897
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.2422918755
Short name T141
Test name
Test status
Simulation time 25150271899 ps
CPU time 853 seconds
Started Mar 24 01:18:49 PM PDT 24
Finished Mar 24 01:33:02 PM PDT 24
Peak memory 371716 kb
Host smart-4585c293-8a5a-4205-9d2f-7ff94ad746e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422918755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.2422918755
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.2656163573
Short name T834
Test name
Test status
Simulation time 1714274677 ps
CPU time 14.65 seconds
Started Mar 24 01:18:48 PM PDT 24
Finished Mar 24 01:19:03 PM PDT 24
Peak memory 202008 kb
Host smart-e81866a6-eef3-4384-91df-f4e1828431e1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656163573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.2656163573
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3580894755
Short name T341
Test name
Test status
Simulation time 46648524068 ps
CPU time 517.77 seconds
Started Mar 24 01:18:47 PM PDT 24
Finished Mar 24 01:27:25 PM PDT 24
Peak memory 202028 kb
Host smart-4c718ab2-5042-478b-9850-0b6d7bbb7091
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580894755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.3580894755
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.2928843763
Short name T34
Test name
Test status
Simulation time 57948524 ps
CPU time 0.75 seconds
Started Mar 24 01:18:48 PM PDT 24
Finished Mar 24 01:18:49 PM PDT 24
Peak memory 202144 kb
Host smart-f0f4fb58-ec04-4958-b67d-f697186b094e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928843763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2928843763
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.3754742296
Short name T761
Test name
Test status
Simulation time 1255877280 ps
CPU time 277.46 seconds
Started Mar 24 01:18:45 PM PDT 24
Finished Mar 24 01:23:23 PM PDT 24
Peak memory 356168 kb
Host smart-5b6c9156-f359-4bbb-8814-9678efa71150
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754742296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3754742296
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.440553335
Short name T849
Test name
Test status
Simulation time 177625448 ps
CPU time 3.19 seconds
Started Mar 24 01:18:47 PM PDT 24
Finished Mar 24 01:18:50 PM PDT 24
Peak memory 214972 kb
Host smart-9945c600-10c2-4ff5-aa23-fb3eca5ae875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440553335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.440553335
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.724445671
Short name T788
Test name
Test status
Simulation time 12905253385 ps
CPU time 1073.92 seconds
Started Mar 24 01:18:52 PM PDT 24
Finished Mar 24 01:36:46 PM PDT 24
Peak memory 374700 kb
Host smart-79573b7e-8647-4b3e-840f-8c3e57a17cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724445671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_stress_all.724445671
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3807765425
Short name T721
Test name
Test status
Simulation time 175402458 ps
CPU time 14.15 seconds
Started Mar 24 01:18:51 PM PDT 24
Finished Mar 24 01:19:05 PM PDT 24
Peak memory 210244 kb
Host smart-c9982880-7cf9-4f6b-90e8-954bea6d6c82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3807765425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3807765425
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2698532855
Short name T170
Test name
Test status
Simulation time 3928232729 ps
CPU time 347.71 seconds
Started Mar 24 01:18:49 PM PDT 24
Finished Mar 24 01:24:37 PM PDT 24
Peak memory 202068 kb
Host smart-f361e44a-8548-411a-9941-dadceb66831f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698532855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.2698532855
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3755252468
Short name T749
Test name
Test status
Simulation time 110165627 ps
CPU time 3.16 seconds
Started Mar 24 01:18:49 PM PDT 24
Finished Mar 24 01:18:52 PM PDT 24
Peak memory 218268 kb
Host smart-c3ec808a-1f12-4156-b4b7-8b7326e3de78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755252468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3755252468
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3238501380
Short name T368
Test name
Test status
Simulation time 17536085985 ps
CPU time 897.63 seconds
Started Mar 24 01:18:51 PM PDT 24
Finished Mar 24 01:33:49 PM PDT 24
Peak memory 351296 kb
Host smart-6e89f3a0-f170-44f2-85a7-e3f2ea03e6a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238501380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.3238501380
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.1584175014
Short name T300
Test name
Test status
Simulation time 35505055 ps
CPU time 0.62 seconds
Started Mar 24 01:18:58 PM PDT 24
Finished Mar 24 01:18:59 PM PDT 24
Peak memory 200828 kb
Host smart-5e61fbc9-cffe-40da-957f-eb4ab65c18bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584175014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.1584175014
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.4067271207
Short name T643
Test name
Test status
Simulation time 2056758154 ps
CPU time 34.56 seconds
Started Mar 24 01:18:51 PM PDT 24
Finished Mar 24 01:19:26 PM PDT 24
Peak memory 202068 kb
Host smart-9fa43619-ae74-4976-be33-ce5d46cea904
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067271207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.4067271207
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.3103142013
Short name T110
Test name
Test status
Simulation time 7863162737 ps
CPU time 496.37 seconds
Started Mar 24 01:18:54 PM PDT 24
Finished Mar 24 01:27:11 PM PDT 24
Peak memory 360464 kb
Host smart-1c237f3c-9603-41fb-9316-bc8d4a695558
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103142013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.3103142013
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.1411780301
Short name T201
Test name
Test status
Simulation time 1611147272 ps
CPU time 7.14 seconds
Started Mar 24 01:18:53 PM PDT 24
Finished Mar 24 01:19:00 PM PDT 24
Peak memory 202036 kb
Host smart-fae21ef7-3699-41f3-80b9-557bf08cbf11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411780301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.1411780301
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.2833189216
Short name T357
Test name
Test status
Simulation time 214712902 ps
CPU time 4.44 seconds
Started Mar 24 01:18:58 PM PDT 24
Finished Mar 24 01:19:03 PM PDT 24
Peak memory 225600 kb
Host smart-60f0c589-3733-4de8-8d4f-6bf339abfdfa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833189216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.2833189216
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.1190075299
Short name T473
Test name
Test status
Simulation time 380770357 ps
CPU time 3.31 seconds
Started Mar 24 01:18:53 PM PDT 24
Finished Mar 24 01:18:56 PM PDT 24
Peak memory 210204 kb
Host smart-fdd5e5dc-dc6e-4890-aa4d-78c14e8c348a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190075299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.1190075299
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.187104823
Short name T308
Test name
Test status
Simulation time 267656184 ps
CPU time 7.87 seconds
Started Mar 24 01:18:50 PM PDT 24
Finished Mar 24 01:18:58 PM PDT 24
Peak memory 201928 kb
Host smart-ee10775e-ef3e-4589-911c-3f1d9a0d6fef
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187104823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl
_mem_walk.187104823
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.1214137176
Short name T814
Test name
Test status
Simulation time 10427905821 ps
CPU time 539.4 seconds
Started Mar 24 01:18:58 PM PDT 24
Finished Mar 24 01:27:58 PM PDT 24
Peak memory 369716 kb
Host smart-bcd8199b-58fa-46f4-a68e-21dd688559a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214137176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.1214137176
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.1823133722
Short name T286
Test name
Test status
Simulation time 477462602 ps
CPU time 8.54 seconds
Started Mar 24 01:18:58 PM PDT 24
Finished Mar 24 01:19:07 PM PDT 24
Peak memory 201840 kb
Host smart-55270bf8-bea1-4d83-9f79-a48ec623923e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823133722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.1823133722
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3799357238
Short name T793
Test name
Test status
Simulation time 4454424865 ps
CPU time 313.8 seconds
Started Mar 24 01:18:52 PM PDT 24
Finished Mar 24 01:24:06 PM PDT 24
Peak memory 202080 kb
Host smart-7475275e-265f-41f4-84b5-1c43ee0f9c42
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799357238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.3799357238
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2015196342
Short name T921
Test name
Test status
Simulation time 296156684 ps
CPU time 0.75 seconds
Started Mar 24 01:18:52 PM PDT 24
Finished Mar 24 01:18:52 PM PDT 24
Peak memory 202128 kb
Host smart-80c52eea-8a40-4a95-b06b-f09329d2121c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015196342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2015196342
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.2578393683
Short name T515
Test name
Test status
Simulation time 15491603052 ps
CPU time 259.08 seconds
Started Mar 24 01:18:59 PM PDT 24
Finished Mar 24 01:23:18 PM PDT 24
Peak memory 365076 kb
Host smart-93acae85-4987-4e59-b5a9-ce894c5a5a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578393683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2578393683
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.407442286
Short name T691
Test name
Test status
Simulation time 897353768 ps
CPU time 76.26 seconds
Started Mar 24 01:18:56 PM PDT 24
Finished Mar 24 01:20:13 PM PDT 24
Peak memory 316052 kb
Host smart-b3430178-2557-49c6-808f-39395394d9bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407442286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.407442286
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.3410461290
Short name T158
Test name
Test status
Simulation time 10992016896 ps
CPU time 1790.34 seconds
Started Mar 24 01:18:52 PM PDT 24
Finished Mar 24 01:48:42 PM PDT 24
Peak memory 373852 kb
Host smart-d3fee13d-5579-4e25-aa59-96ded53326b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410461290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.3410461290
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1789446260
Short name T828
Test name
Test status
Simulation time 14068765350 ps
CPU time 339.08 seconds
Started Mar 24 01:18:59 PM PDT 24
Finished Mar 24 01:24:38 PM PDT 24
Peak memory 202048 kb
Host smart-adbb534f-3938-4be3-bc5c-aa51e1854b1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789446260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.1789446260
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1213360510
Short name T782
Test name
Test status
Simulation time 336464801 ps
CPU time 19.53 seconds
Started Mar 24 01:18:51 PM PDT 24
Finished Mar 24 01:19:11 PM PDT 24
Peak memory 268496 kb
Host smart-155b7bd0-d387-4c7b-b1c2-7d0e80e830e3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213360510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.1213360510
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1627751029
Short name T565
Test name
Test status
Simulation time 25656031467 ps
CPU time 1180.12 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 01:38:43 PM PDT 24
Peak memory 373828 kb
Host smart-979d6bf1-c6f7-4223-92e2-372f882f27ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627751029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.1627751029
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.3463643768
Short name T941
Test name
Test status
Simulation time 40576370 ps
CPU time 0.68 seconds
Started Mar 24 01:19:04 PM PDT 24
Finished Mar 24 01:19:05 PM PDT 24
Peak memory 201820 kb
Host smart-703ebdef-d094-42af-b575-53ba48388202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463643768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.3463643768
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.3676869031
Short name T59
Test name
Test status
Simulation time 989052250 ps
CPU time 28.6 seconds
Started Mar 24 01:18:51 PM PDT 24
Finished Mar 24 01:19:20 PM PDT 24
Peak memory 202036 kb
Host smart-0765b704-fbe8-4353-af18-e1bdf04f6c30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676869031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.3676869031
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.1677364188
Short name T835
Test name
Test status
Simulation time 4272936636 ps
CPU time 935.09 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 01:34:38 PM PDT 24
Peak memory 367728 kb
Host smart-df090622-38b4-4c73-9644-e0ff68d0ab1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677364188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.1677364188
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.187989881
Short name T267
Test name
Test status
Simulation time 614680114 ps
CPU time 1.76 seconds
Started Mar 24 01:19:04 PM PDT 24
Finished Mar 24 01:19:06 PM PDT 24
Peak memory 202048 kb
Host smart-19eb566e-0e0b-4e41-9ef9-55bcc616ae65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187989881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_esc
alation.187989881
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.1860967018
Short name T383
Test name
Test status
Simulation time 844950156 ps
CPU time 161 seconds
Started Mar 24 01:18:57 PM PDT 24
Finished Mar 24 01:21:38 PM PDT 24
Peak memory 369932 kb
Host smart-a7fce67a-dcd6-4c17-89a5-9d9ccdc49e94
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860967018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.1860967018
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3596844397
Short name T838
Test name
Test status
Simulation time 148380302 ps
CPU time 4.94 seconds
Started Mar 24 01:19:07 PM PDT 24
Finished Mar 24 01:19:12 PM PDT 24
Peak memory 210204 kb
Host smart-71100f8a-4933-49de-b7be-6bf57c7e2d55
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596844397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.3596844397
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.441552779
Short name T183
Test name
Test status
Simulation time 141522630 ps
CPU time 4.56 seconds
Started Mar 24 01:19:06 PM PDT 24
Finished Mar 24 01:19:11 PM PDT 24
Peak memory 201956 kb
Host smart-f5770ce7-9554-4c60-b4db-48124dfa2527
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441552779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl
_mem_walk.441552779
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.2257134498
Short name T422
Test name
Test status
Simulation time 12253522278 ps
CPU time 765.75 seconds
Started Mar 24 01:18:58 PM PDT 24
Finished Mar 24 01:31:44 PM PDT 24
Peak memory 373496 kb
Host smart-3758c804-8ff1-4870-8373-716388588eb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257134498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.2257134498
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.1756822715
Short name T808
Test name
Test status
Simulation time 185015420 ps
CPU time 3.75 seconds
Started Mar 24 01:18:53 PM PDT 24
Finished Mar 24 01:18:57 PM PDT 24
Peak memory 202024 kb
Host smart-3a2974b4-c050-44c9-87b7-bd19cc41b5d6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756822715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.1756822715
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2852306136
Short name T681
Test name
Test status
Simulation time 19854982393 ps
CPU time 299.9 seconds
Started Mar 24 01:18:59 PM PDT 24
Finished Mar 24 01:23:59 PM PDT 24
Peak memory 201108 kb
Host smart-5f00144f-14c3-45ca-ae49-d35756d444c2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852306136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.2852306136
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.1290223484
Short name T457
Test name
Test status
Simulation time 48608333 ps
CPU time 0.82 seconds
Started Mar 24 01:19:03 PM PDT 24
Finished Mar 24 01:19:04 PM PDT 24
Peak memory 202004 kb
Host smart-1166385f-9160-4f8b-aaf8-36bc0137f3a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290223484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1290223484
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.2071793495
Short name T556
Test name
Test status
Simulation time 114255731224 ps
CPU time 1758.27 seconds
Started Mar 24 01:19:09 PM PDT 24
Finished Mar 24 01:48:28 PM PDT 24
Peak memory 373216 kb
Host smart-7ac6c866-3027-461e-9a54-ad0ac855d7e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071793495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.2071793495
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.3181629702
Short name T419
Test name
Test status
Simulation time 1415506864 ps
CPU time 16.65 seconds
Started Mar 24 01:18:54 PM PDT 24
Finished Mar 24 01:19:11 PM PDT 24
Peak memory 202056 kb
Host smart-602137ab-4ca1-46d5-906a-f71bb1ce8b71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181629702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3181629702
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.3581796985
Short name T132
Test name
Test status
Simulation time 77727261305 ps
CPU time 3470.52 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 02:16:54 PM PDT 24
Peak memory 374540 kb
Host smart-a1f59c8e-5d27-4e31-846f-274ac3fcbb4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581796985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.3581796985
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2613592919
Short name T310
Test name
Test status
Simulation time 2735004078 ps
CPU time 69.13 seconds
Started Mar 24 01:19:03 PM PDT 24
Finished Mar 24 01:20:13 PM PDT 24
Peak memory 273504 kb
Host smart-f7f65967-1cdb-4357-9cf2-353c23e309fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2613592919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2613592919
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.703580215
Short name T846
Test name
Test status
Simulation time 7586933126 ps
CPU time 177.37 seconds
Started Mar 24 01:18:59 PM PDT 24
Finished Mar 24 01:21:56 PM PDT 24
Peak memory 201016 kb
Host smart-128b706e-93cb-42ee-9b70-62556e9fea33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703580215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_stress_pipeline.703580215
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.559026894
Short name T878
Test name
Test status
Simulation time 132760156 ps
CPU time 13.78 seconds
Started Mar 24 01:19:03 PM PDT 24
Finished Mar 24 01:19:17 PM PDT 24
Peak memory 251120 kb
Host smart-b640bce5-f22b-4e47-b6de-563900017fa4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559026894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.559026894
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.658106266
Short name T19
Test name
Test status
Simulation time 3499805031 ps
CPU time 900.99 seconds
Started Mar 24 01:19:03 PM PDT 24
Finished Mar 24 01:34:04 PM PDT 24
Peak memory 350568 kb
Host smart-5eec3001-19e2-4912-be81-247894c3a388
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658106266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.sram_ctrl_access_during_key_req.658106266
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.3129486980
Short name T351
Test name
Test status
Simulation time 14071428 ps
CPU time 0.67 seconds
Started Mar 24 01:19:01 PM PDT 24
Finished Mar 24 01:19:02 PM PDT 24
Peak memory 200988 kb
Host smart-3ba60cd2-037c-40ad-8ffc-6ab7fc065e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129486980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.3129486980
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.2967514732
Short name T664
Test name
Test status
Simulation time 3688835926 ps
CPU time 72.92 seconds
Started Mar 24 01:19:05 PM PDT 24
Finished Mar 24 01:20:18 PM PDT 24
Peak memory 202056 kb
Host smart-8e55a3ed-cd5b-4776-94b6-79e2399325b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967514732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.2967514732
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.1432428795
Short name T370
Test name
Test status
Simulation time 7753239152 ps
CPU time 943.55 seconds
Started Mar 24 01:19:06 PM PDT 24
Finished Mar 24 01:34:50 PM PDT 24
Peak memory 366828 kb
Host smart-670e20e0-312e-47f0-9dd0-2dd488255b92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432428795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.1432428795
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.3971921321
Short name T634
Test name
Test status
Simulation time 827992006 ps
CPU time 4.93 seconds
Started Mar 24 01:19:05 PM PDT 24
Finished Mar 24 01:19:10 PM PDT 24
Peak memory 202056 kb
Host smart-45996860-b80c-4ffe-9953-74c611d6e503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971921321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.3971921321
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.2368463746
Short name T298
Test name
Test status
Simulation time 546405249 ps
CPU time 151.16 seconds
Started Mar 24 01:19:00 PM PDT 24
Finished Mar 24 01:21:32 PM PDT 24
Peak memory 368648 kb
Host smart-7e4ee1f2-860e-4d1b-93a5-49cfcb1fe8f6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368463746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.2368463746
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.149106488
Short name T83
Test name
Test status
Simulation time 798507655 ps
CPU time 2.93 seconds
Started Mar 24 01:19:05 PM PDT 24
Finished Mar 24 01:19:08 PM PDT 24
Peak memory 210188 kb
Host smart-19e36304-ed8c-48c3-b6fc-d83ded2b7630
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149106488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.sram_ctrl_mem_partial_access.149106488
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.1087236410
Short name T673
Test name
Test status
Simulation time 684837125 ps
CPU time 9.95 seconds
Started Mar 24 01:19:03 PM PDT 24
Finished Mar 24 01:19:13 PM PDT 24
Peak memory 201912 kb
Host smart-ed23abe3-1689-44ec-8426-8e5de9cebb41
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087236410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.1087236410
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.1465198
Short name T726
Test name
Test status
Simulation time 88778637989 ps
CPU time 687.63 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 01:30:30 PM PDT 24
Peak memory 373624 kb
Host smart-8e18f14a-59ba-49cb-9725-e2ab3ae3281c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multipl
e_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple
_keys.1465198
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.1569467211
Short name T460
Test name
Test status
Simulation time 271790911 ps
CPU time 9.79 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 01:19:12 PM PDT 24
Peak memory 201972 kb
Host smart-d52146ef-ac69-4f5d-9056-65eed1420771
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569467211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.1569467211
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.280619001
Short name T435
Test name
Test status
Simulation time 5286548538 ps
CPU time 375.29 seconds
Started Mar 24 01:19:04 PM PDT 24
Finished Mar 24 01:25:20 PM PDT 24
Peak memory 202064 kb
Host smart-4afaeea2-f8f9-429d-a4ee-59fdc5da7b56
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280619001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.sram_ctrl_partial_access_b2b.280619001
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.1585821170
Short name T525
Test name
Test status
Simulation time 179378349 ps
CPU time 0.8 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 01:19:03 PM PDT 24
Peak memory 202144 kb
Host smart-aaa8e328-9b12-4b8d-bd1e-7bcf4cd4ddf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585821170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1585821170
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.3766365804
Short name T217
Test name
Test status
Simulation time 451871488 ps
CPU time 8.26 seconds
Started Mar 24 01:19:05 PM PDT 24
Finished Mar 24 01:19:13 PM PDT 24
Peak memory 214384 kb
Host smart-4acb947d-38f9-463d-8da8-72c9a81890ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766365804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3766365804
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.113005002
Short name T940
Test name
Test status
Simulation time 1679700447 ps
CPU time 7.11 seconds
Started Mar 24 01:18:57 PM PDT 24
Finished Mar 24 01:19:05 PM PDT 24
Peak memory 202052 kb
Host smart-c2ea69f2-60bc-41a0-ac1d-d02e1a53fe75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113005002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.113005002
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.3967188059
Short name T620
Test name
Test status
Simulation time 133482812077 ps
CPU time 5911.39 seconds
Started Mar 24 01:19:04 PM PDT 24
Finished Mar 24 02:57:36 PM PDT 24
Peak memory 375728 kb
Host smart-ef8d4384-eb23-41c5-970d-ac5ef8baf6ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967188059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.3967188059
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.568135772
Short name T753
Test name
Test status
Simulation time 4365790754 ps
CPU time 179.89 seconds
Started Mar 24 01:19:09 PM PDT 24
Finished Mar 24 01:22:09 PM PDT 24
Peak memory 342720 kb
Host smart-8dd15816-47a5-4fb1-84d8-c4db6068727a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=568135772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.568135772
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1043323168
Short name T409
Test name
Test status
Simulation time 5407964580 ps
CPU time 266.78 seconds
Started Mar 24 01:19:04 PM PDT 24
Finished Mar 24 01:23:31 PM PDT 24
Peak memory 202048 kb
Host smart-a00453b0-12c9-46a4-9734-27039f0cf96c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043323168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.1043323168
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2114714478
Short name T907
Test name
Test status
Simulation time 566510472 ps
CPU time 78.39 seconds
Started Mar 24 01:18:56 PM PDT 24
Finished Mar 24 01:20:15 PM PDT 24
Peak memory 352020 kb
Host smart-e782f250-9f2a-495c-b66e-838d16443792
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114714478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2114714478
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1298658363
Short name T738
Test name
Test status
Simulation time 11249037513 ps
CPU time 636.09 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 01:29:39 PM PDT 24
Peak memory 370736 kb
Host smart-2e098b6b-8b39-4723-98c6-4df289b34ffd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298658363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.1298658363
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.3609587345
Short name T631
Test name
Test status
Simulation time 35968014 ps
CPU time 0.63 seconds
Started Mar 24 01:19:08 PM PDT 24
Finished Mar 24 01:19:09 PM PDT 24
Peak memory 201792 kb
Host smart-3e7bb3ba-2baa-4fd7-b6f1-c7b66f55eb1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609587345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.3609587345
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.539471512
Short name T239
Test name
Test status
Simulation time 11807554091 ps
CPU time 48.73 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 01:19:51 PM PDT 24
Peak memory 202068 kb
Host smart-0ca3289c-0c2c-4ddc-9f69-48a3cabf1bf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539471512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.
539471512
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.1702498850
Short name T189
Test name
Test status
Simulation time 16568793463 ps
CPU time 1234.76 seconds
Started Mar 24 01:19:08 PM PDT 24
Finished Mar 24 01:39:43 PM PDT 24
Peak memory 368648 kb
Host smart-064cd307-dfbb-4375-b076-939f36af39c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702498850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.1702498850
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.3040740257
Short name T50
Test name
Test status
Simulation time 341617737 ps
CPU time 4.08 seconds
Started Mar 24 01:19:05 PM PDT 24
Finished Mar 24 01:19:09 PM PDT 24
Peak memory 202036 kb
Host smart-edfa4180-cc3a-4bf6-a469-95810f3f18b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040740257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.3040740257
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.1278111735
Short name T909
Test name
Test status
Simulation time 197312260 ps
CPU time 50.88 seconds
Started Mar 24 01:19:05 PM PDT 24
Finished Mar 24 01:19:56 PM PDT 24
Peak memory 304324 kb
Host smart-5751ff0c-6b34-4121-89d7-00289f62917a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278111735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.1278111735
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.973019668
Short name T622
Test name
Test status
Simulation time 149435531 ps
CPU time 2.66 seconds
Started Mar 24 01:19:09 PM PDT 24
Finished Mar 24 01:19:12 PM PDT 24
Peak memory 210196 kb
Host smart-ff1c5357-a908-4e69-a4b4-6f3b4710f784
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973019668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_mem_partial_access.973019668
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.3041501844
Short name T244
Test name
Test status
Simulation time 138486182 ps
CPU time 8.33 seconds
Started Mar 24 01:19:08 PM PDT 24
Finished Mar 24 01:19:16 PM PDT 24
Peak memory 201932 kb
Host smart-cd4561d9-2fb1-4c95-a5a6-8fdfdc23fc25
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041501844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.3041501844
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.3240356077
Short name T434
Test name
Test status
Simulation time 2933583488 ps
CPU time 1270.29 seconds
Started Mar 24 01:19:05 PM PDT 24
Finished Mar 24 01:40:15 PM PDT 24
Peak memory 373828 kb
Host smart-b8bfe388-a147-48d9-9147-8244e42577ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240356077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.3240356077
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.4170303343
Short name T196
Test name
Test status
Simulation time 871368470 ps
CPU time 162.68 seconds
Started Mar 24 01:19:01 PM PDT 24
Finished Mar 24 01:21:44 PM PDT 24
Peak memory 365152 kb
Host smart-5847bb33-8b7e-4c01-92ea-bc8508cda475
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170303343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.4170303343
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.3705227506
Short name T717
Test name
Test status
Simulation time 89808148 ps
CPU time 0.8 seconds
Started Mar 24 01:19:09 PM PDT 24
Finished Mar 24 01:19:09 PM PDT 24
Peak memory 202128 kb
Host smart-5802f1d9-6de5-4323-b18f-7501eda2974d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705227506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3705227506
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.4144484529
Short name T495
Test name
Test status
Simulation time 438595619 ps
CPU time 173.51 seconds
Started Mar 24 01:19:09 PM PDT 24
Finished Mar 24 01:22:03 PM PDT 24
Peak memory 368900 kb
Host smart-3bcb905f-8efe-4484-af69-57d1cca39ff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144484529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.4144484529
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.2614299467
Short name T384
Test name
Test status
Simulation time 38085064 ps
CPU time 2.98 seconds
Started Mar 24 01:19:06 PM PDT 24
Finished Mar 24 01:19:09 PM PDT 24
Peak memory 212608 kb
Host smart-ebadc35b-794f-42e7-9593-ef32084c88a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614299467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2614299467
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2188274793
Short name T366
Test name
Test status
Simulation time 9756359072 ps
CPU time 157.09 seconds
Started Mar 24 01:19:10 PM PDT 24
Finished Mar 24 01:21:47 PM PDT 24
Peak memory 344332 kb
Host smart-d53023cc-8a42-4a05-8465-ec705319786a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2188274793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2188274793
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.647884696
Short name T192
Test name
Test status
Simulation time 8157811360 ps
CPU time 197.37 seconds
Started Mar 24 01:19:03 PM PDT 24
Finished Mar 24 01:22:21 PM PDT 24
Peak memory 201996 kb
Host smart-8ba94e94-31e2-4090-b337-68f4af262220
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647884696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_stress_pipeline.647884696
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.4148065532
Short name T780
Test name
Test status
Simulation time 785324051 ps
CPU time 105.8 seconds
Started Mar 24 01:19:02 PM PDT 24
Finished Mar 24 01:20:48 PM PDT 24
Peak memory 341116 kb
Host smart-7d1b2181-4ce0-4ffd-a57a-8e72eef71119
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148065532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.4148065532
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1573341805
Short name T444
Test name
Test status
Simulation time 7175634457 ps
CPU time 553.56 seconds
Started Mar 24 01:19:08 PM PDT 24
Finished Mar 24 01:28:21 PM PDT 24
Peak memory 340036 kb
Host smart-7fd45a0a-c3f5-4c3c-a66d-6561f6fe14c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573341805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.1573341805
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.915681147
Short name T544
Test name
Test status
Simulation time 49127422 ps
CPU time 0.63 seconds
Started Mar 24 01:19:13 PM PDT 24
Finished Mar 24 01:19:13 PM PDT 24
Peak memory 201800 kb
Host smart-ca74c30e-77f2-4cc2-971f-179554e2d6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915681147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.915681147
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.2057474672
Short name T302
Test name
Test status
Simulation time 9630931356 ps
CPU time 75.49 seconds
Started Mar 24 01:19:10 PM PDT 24
Finished Mar 24 01:20:25 PM PDT 24
Peak memory 202136 kb
Host smart-15187e3f-2cf5-4ad0-b00f-6144a8ab5eac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057474672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.2057474672
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.374225846
Short name T777
Test name
Test status
Simulation time 9154279731 ps
CPU time 1039.45 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 01:36:34 PM PDT 24
Peak memory 373080 kb
Host smart-b18f605a-bba4-48ea-b5f0-38bdc54dd96b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374225846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executabl
e.374225846
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.825728080
Short name T155
Test name
Test status
Simulation time 1891541788 ps
CPU time 5.67 seconds
Started Mar 24 01:19:07 PM PDT 24
Finished Mar 24 01:19:13 PM PDT 24
Peak memory 210260 kb
Host smart-d3b2252a-f21d-4384-8b68-76b833a34078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825728080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_esc
alation.825728080
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.574311712
Short name T642
Test name
Test status
Simulation time 259928407 ps
CPU time 121.64 seconds
Started Mar 24 01:19:07 PM PDT 24
Finished Mar 24 01:21:09 PM PDT 24
Peak memory 360196 kb
Host smart-23f13753-0e88-49e9-b516-245c12abe330
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574311712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.sram_ctrl_max_throughput.574311712
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.1705494877
Short name T532
Test name
Test status
Simulation time 592366539 ps
CPU time 5.42 seconds
Started Mar 24 01:19:12 PM PDT 24
Finished Mar 24 01:19:18 PM PDT 24
Peak memory 210168 kb
Host smart-4f8ff613-e938-4ed3-86f6-7eabcdb12052
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705494877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.1705494877
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.2595876286
Short name T304
Test name
Test status
Simulation time 238006187 ps
CPU time 4.91 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 01:19:19 PM PDT 24
Peak memory 201956 kb
Host smart-73402f59-41a9-4a85-b5a3-aa08dbe60ccc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595876286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.2595876286
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.431802
Short name T372
Test name
Test status
Simulation time 14971953377 ps
CPU time 1255.05 seconds
Started Mar 24 01:19:07 PM PDT 24
Finished Mar 24 01:40:02 PM PDT 24
Peak memory 372904 kb
Host smart-4c2f300d-7390-43f7-9e6d-a77f5f01d06e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple
_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_
keys.431802
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.2548966979
Short name T731
Test name
Test status
Simulation time 2360911603 ps
CPU time 11.9 seconds
Started Mar 24 01:19:08 PM PDT 24
Finished Mar 24 01:19:20 PM PDT 24
Peak memory 202092 kb
Host smart-2e76ba3e-880b-4d89-b455-8a6a575b626b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548966979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.2548966979
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2332179926
Short name T100
Test name
Test status
Simulation time 25650315931 ps
CPU time 317.17 seconds
Started Mar 24 01:19:09 PM PDT 24
Finished Mar 24 01:24:26 PM PDT 24
Peak memory 202240 kb
Host smart-b96f2ff1-11ed-4fc5-bb42-ea259d479794
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332179926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.2332179926
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.1965592885
Short name T843
Test name
Test status
Simulation time 36550441 ps
CPU time 0.74 seconds
Started Mar 24 01:19:12 PM PDT 24
Finished Mar 24 01:19:13 PM PDT 24
Peak memory 202120 kb
Host smart-9f3df836-aa9f-43ef-87cb-40fcfae5cbe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965592885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1965592885
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.2006764866
Short name T281
Test name
Test status
Simulation time 47130000084 ps
CPU time 1266.79 seconds
Started Mar 24 01:19:17 PM PDT 24
Finished Mar 24 01:40:24 PM PDT 24
Peak memory 374888 kb
Host smart-c1b700ad-b350-4af4-8626-892af9907cda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006764866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2006764866
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.1445190393
Short name T156
Test name
Test status
Simulation time 2127906530 ps
CPU time 5.65 seconds
Started Mar 24 01:19:10 PM PDT 24
Finished Mar 24 01:19:16 PM PDT 24
Peak memory 202048 kb
Host smart-58bfef59-87bf-4dcf-a293-adc2cc198803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445190393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1445190393
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.3171542916
Short name T301
Test name
Test status
Simulation time 17777613073 ps
CPU time 1287.2 seconds
Started Mar 24 01:19:15 PM PDT 24
Finished Mar 24 01:40:43 PM PDT 24
Peak memory 372836 kb
Host smart-86b38c83-85c2-4394-a0aa-a435e1a43356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171542916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.3171542916
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2881695653
Short name T466
Test name
Test status
Simulation time 156836290 ps
CPU time 11.56 seconds
Started Mar 24 01:19:15 PM PDT 24
Finished Mar 24 01:19:27 PM PDT 24
Peak memory 211524 kb
Host smart-fdcde76c-e55a-430b-82bd-f3a4b9067e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2881695653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2881695653
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2019069371
Short name T570
Test name
Test status
Simulation time 2262039496 ps
CPU time 98.06 seconds
Started Mar 24 01:19:13 PM PDT 24
Finished Mar 24 01:20:51 PM PDT 24
Peak memory 202016 kb
Host smart-3223addf-5580-44e5-b706-20e89934eedd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019069371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.2019069371
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1074702809
Short name T775
Test name
Test status
Simulation time 100447510 ps
CPU time 35.08 seconds
Started Mar 24 01:19:13 PM PDT 24
Finished Mar 24 01:19:48 PM PDT 24
Peak memory 288924 kb
Host smart-7f3933b6-f2ba-4178-b240-7f090843281e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074702809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.1074702809
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.905519281
Short name T200
Test name
Test status
Simulation time 6827583495 ps
CPU time 502.76 seconds
Started Mar 24 01:17:18 PM PDT 24
Finished Mar 24 01:25:41 PM PDT 24
Peak memory 372104 kb
Host smart-923b04f6-f1d0-4ab5-94ad-ca34c8727f46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905519281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.sram_ctrl_access_during_key_req.905519281
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.1977404612
Short name T474
Test name
Test status
Simulation time 41086200 ps
CPU time 0.64 seconds
Started Mar 24 01:17:20 PM PDT 24
Finished Mar 24 01:17:21 PM PDT 24
Peak memory 201116 kb
Host smart-d840796e-3fbe-45fe-887c-4819d5157c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977404612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.1977404612
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.151637930
Short name T472
Test name
Test status
Simulation time 2038683548 ps
CPU time 31.01 seconds
Started Mar 24 01:17:02 PM PDT 24
Finished Mar 24 01:17:33 PM PDT 24
Peak memory 202252 kb
Host smart-26ac583a-35cf-4a15-9094-fb857b3e7392
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151637930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.151637930
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.2330881935
Short name T763
Test name
Test status
Simulation time 57096701210 ps
CPU time 1537.33 seconds
Started Mar 24 01:17:15 PM PDT 24
Finished Mar 24 01:42:52 PM PDT 24
Peak memory 375128 kb
Host smart-00bef328-6f39-4628-9d30-594cea1186ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330881935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.2330881935
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.3845775991
Short name T396
Test name
Test status
Simulation time 3052064628 ps
CPU time 7.65 seconds
Started Mar 24 01:17:10 PM PDT 24
Finished Mar 24 01:17:18 PM PDT 24
Peak memory 202124 kb
Host smart-8a3c2684-1348-4f2d-a6fe-0689d2eab28d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845775991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.3845775991
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.2552605929
Short name T54
Test name
Test status
Simulation time 102297844 ps
CPU time 45.97 seconds
Started Mar 24 01:16:52 PM PDT 24
Finished Mar 24 01:17:38 PM PDT 24
Peak memory 302288 kb
Host smart-95da3114-4c8a-4373-ac23-b4f81f54b7ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552605929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.2552605929
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.4008256438
Short name T823
Test name
Test status
Simulation time 87118986 ps
CPU time 2.84 seconds
Started Mar 24 01:17:13 PM PDT 24
Finished Mar 24 01:17:16 PM PDT 24
Peak memory 210148 kb
Host smart-ecf68dc7-1658-4f65-99b4-590fc91e6915
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008256438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.4008256438
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.905196318
Short name T356
Test name
Test status
Simulation time 71819524 ps
CPU time 4.37 seconds
Started Mar 24 01:17:15 PM PDT 24
Finished Mar 24 01:17:20 PM PDT 24
Peak memory 201936 kb
Host smart-008e022e-aa31-4d2e-b4d7-67aa110ad002
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905196318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_
mem_walk.905196318
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.1224532103
Short name T283
Test name
Test status
Simulation time 34039999792 ps
CPU time 1028.06 seconds
Started Mar 24 01:16:59 PM PDT 24
Finished Mar 24 01:34:07 PM PDT 24
Peak memory 373668 kb
Host smart-6670c8a6-ae9f-44dd-805d-e455979fc909
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224532103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.1224532103
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.3232909103
Short name T284
Test name
Test status
Simulation time 1091418195 ps
CPU time 13.57 seconds
Started Mar 24 01:16:55 PM PDT 24
Finished Mar 24 01:17:08 PM PDT 24
Peak memory 201960 kb
Host smart-84530834-3e10-47d6-a076-ee8070d81198
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232909103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.3232909103
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1454391175
Short name T935
Test name
Test status
Simulation time 74038652171 ps
CPU time 367.46 seconds
Started Mar 24 01:17:01 PM PDT 24
Finished Mar 24 01:23:09 PM PDT 24
Peak memory 202292 kb
Host smart-b95f8f72-cca8-4d17-8bc2-7b719a3cea99
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454391175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.1454391175
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.1529800218
Short name T299
Test name
Test status
Simulation time 34086192 ps
CPU time 0.8 seconds
Started Mar 24 01:17:16 PM PDT 24
Finished Mar 24 01:17:17 PM PDT 24
Peak memory 202156 kb
Host smart-5c4852cb-7e8e-470a-8995-37ba93156d83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529800218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1529800218
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3728516267
Short name T35
Test name
Test status
Simulation time 162659900 ps
CPU time 2.17 seconds
Started Mar 24 01:17:17 PM PDT 24
Finished Mar 24 01:17:19 PM PDT 24
Peak memory 220968 kb
Host smart-d5f330d4-0e27-4edf-988b-f5aed4d58c9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728516267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3728516267
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.3187765619
Short name T185
Test name
Test status
Simulation time 415160594 ps
CPU time 29.36 seconds
Started Mar 24 01:17:00 PM PDT 24
Finished Mar 24 01:17:29 PM PDT 24
Peak memory 286456 kb
Host smart-63f964f1-bb55-4e85-94ab-65d18966fc79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187765619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3187765619
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.3574412855
Short name T821
Test name
Test status
Simulation time 35102311880 ps
CPU time 2407.06 seconds
Started Mar 24 01:17:10 PM PDT 24
Finished Mar 24 01:57:18 PM PDT 24
Peak memory 381100 kb
Host smart-393a3dd4-38cd-4003-abc2-103f330d2c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574412855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.3574412855
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.220325987
Short name T436
Test name
Test status
Simulation time 685602281 ps
CPU time 18.89 seconds
Started Mar 24 01:17:10 PM PDT 24
Finished Mar 24 01:17:30 PM PDT 24
Peak memory 210244 kb
Host smart-00ba1de3-4e01-48f5-b073-b8b409053e68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=220325987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.220325987
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3801157177
Short name T53
Test name
Test status
Simulation time 2584547987 ps
CPU time 214.17 seconds
Started Mar 24 01:16:53 PM PDT 24
Finished Mar 24 01:20:28 PM PDT 24
Peak memory 202084 kb
Host smart-26dacc5e-d300-47bf-8ab5-e85b2a03286b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801157177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.3801157177
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2797728093
Short name T378
Test name
Test status
Simulation time 138744559 ps
CPU time 76.59 seconds
Started Mar 24 01:17:16 PM PDT 24
Finished Mar 24 01:18:32 PM PDT 24
Peak memory 341076 kb
Host smart-8ab3f824-043c-4153-b7e4-e125cbc2da16
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797728093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.2797728093
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1515333419
Short name T628
Test name
Test status
Simulation time 17808319871 ps
CPU time 1562.16 seconds
Started Mar 24 01:19:11 PM PDT 24
Finished Mar 24 01:45:14 PM PDT 24
Peak memory 371824 kb
Host smart-cef0eb83-4317-4094-8c3e-fc8e28bd9c1f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515333419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.1515333419
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.2200324832
Short name T221
Test name
Test status
Simulation time 43630664 ps
CPU time 0.66 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 01:19:15 PM PDT 24
Peak memory 200856 kb
Host smart-14e8a566-a8c8-4df0-941f-d32fd0bcad65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200324832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.2200324832
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.1778200546
Short name T165
Test name
Test status
Simulation time 5542216854 ps
CPU time 24.54 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 01:19:39 PM PDT 24
Peak memory 202036 kb
Host smart-4b674554-824c-4a57-9e53-f69bec1887d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778200546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.1778200546
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.708341481
Short name T144
Test name
Test status
Simulation time 10691109904 ps
CPU time 515.71 seconds
Started Mar 24 01:19:12 PM PDT 24
Finished Mar 24 01:27:48 PM PDT 24
Peak memory 371320 kb
Host smart-37810def-05fe-4a3f-b1ea-2b0673d41dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708341481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executabl
e.708341481
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.3530327572
Short name T464
Test name
Test status
Simulation time 542821941 ps
CPU time 6.24 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 01:19:20 PM PDT 24
Peak memory 202084 kb
Host smart-6747d632-8e90-4400-8095-eae1e1e339eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530327572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.3530327572
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.837724554
Short name T261
Test name
Test status
Simulation time 121263328 ps
CPU time 71.9 seconds
Started Mar 24 01:19:15 PM PDT 24
Finished Mar 24 01:20:27 PM PDT 24
Peak memory 326232 kb
Host smart-fde14372-1d9d-490d-8895-5b17e601f018
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837724554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_max_throughput.837724554
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1327401655
Short name T668
Test name
Test status
Simulation time 1375478915 ps
CPU time 5.66 seconds
Started Mar 24 01:19:18 PM PDT 24
Finished Mar 24 01:19:24 PM PDT 24
Peak memory 210132 kb
Host smart-9ac5a36a-e507-4836-abcb-9fc1856a409c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327401655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.1327401655
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.2249140780
Short name T323
Test name
Test status
Simulation time 76544709 ps
CPU time 4.41 seconds
Started Mar 24 01:19:12 PM PDT 24
Finished Mar 24 01:19:16 PM PDT 24
Peak memory 201932 kb
Host smart-8bd1b57a-df91-4884-8ced-a043c1ed8c32
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249140780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.2249140780
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.1719467969
Short name T73
Test name
Test status
Simulation time 14103002927 ps
CPU time 1293.01 seconds
Started Mar 24 01:19:13 PM PDT 24
Finished Mar 24 01:40:46 PM PDT 24
Peak memory 373964 kb
Host smart-767cad1e-399f-4b35-a590-cf10ca3d7f7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719467969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.1719467969
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.2082858461
Short name T237
Test name
Test status
Simulation time 416457855 ps
CPU time 134.12 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 01:21:28 PM PDT 24
Peak memory 365412 kb
Host smart-46d58a55-24f4-4b15-8265-5bb31f684c95
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082858461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.2082858461
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2274566162
Short name T697
Test name
Test status
Simulation time 15945223331 ps
CPU time 342.4 seconds
Started Mar 24 01:19:13 PM PDT 24
Finished Mar 24 01:24:56 PM PDT 24
Peak memory 202052 kb
Host smart-c60e1f5f-901e-4f04-805d-cb5aca010fcb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274566162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.2274566162
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.2097615000
Short name T719
Test name
Test status
Simulation time 184285973 ps
CPU time 0.73 seconds
Started Mar 24 01:19:13 PM PDT 24
Finished Mar 24 01:19:15 PM PDT 24
Peak memory 202096 kb
Host smart-4f9f63e8-c86d-480e-9a5d-6f6d85af821d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097615000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2097615000
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3946027224
Short name T646
Test name
Test status
Simulation time 59655242452 ps
CPU time 2130.71 seconds
Started Mar 24 01:19:17 PM PDT 24
Finished Mar 24 01:54:48 PM PDT 24
Peak memory 373728 kb
Host smart-a9bea593-6c14-415f-8eff-fb5a0addc6cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946027224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3946027224
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.715938312
Short name T446
Test name
Test status
Simulation time 8536921956 ps
CPU time 129.38 seconds
Started Mar 24 01:19:11 PM PDT 24
Finished Mar 24 01:21:21 PM PDT 24
Peak memory 355552 kb
Host smart-30956ff5-ac35-4847-9049-268193b93d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715938312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.715938312
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.1114081245
Short name T875
Test name
Test status
Simulation time 193532328372 ps
CPU time 4344.4 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 02:31:39 PM PDT 24
Peak memory 383036 kb
Host smart-8916f9e7-ff22-4d68-9c47-1f9d33d82965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114081245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.1114081245
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1306302642
Short name T112
Test name
Test status
Simulation time 7242339487 ps
CPU time 234.51 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 01:23:09 PM PDT 24
Peak memory 332660 kb
Host smart-752f2676-94e9-4727-a578-32bea3f2d828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1306302642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1306302642
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2933642418
Short name T601
Test name
Test status
Simulation time 1775712402 ps
CPU time 161.54 seconds
Started Mar 24 01:19:15 PM PDT 24
Finished Mar 24 01:21:56 PM PDT 24
Peak memory 202040 kb
Host smart-413dfa88-26db-4e85-9ab4-a1ebb3380961
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933642418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.2933642418
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2633727958
Short name T617
Test name
Test status
Simulation time 83653688 ps
CPU time 24.24 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 01:19:39 PM PDT 24
Peak memory 269484 kb
Host smart-f52f54f4-14fb-4678-9995-57459556ac96
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633727958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.2633727958
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.4215635024
Short name T916
Test name
Test status
Simulation time 20732917623 ps
CPU time 1353.51 seconds
Started Mar 24 01:19:18 PM PDT 24
Finished Mar 24 01:41:52 PM PDT 24
Peak memory 372808 kb
Host smart-749cb000-c3f5-4917-891f-ab1ecfb5a2bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215635024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.4215635024
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.1187843047
Short name T696
Test name
Test status
Simulation time 25790753 ps
CPU time 0.64 seconds
Started Mar 24 01:19:27 PM PDT 24
Finished Mar 24 01:19:27 PM PDT 24
Peak memory 201788 kb
Host smart-705b148c-ce92-4756-b1f3-2d63f57ea203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187843047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.1187843047
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.2870897325
Short name T810
Test name
Test status
Simulation time 1252460025 ps
CPU time 57.89 seconds
Started Mar 24 01:19:21 PM PDT 24
Finished Mar 24 01:20:19 PM PDT 24
Peak memory 201988 kb
Host smart-cee1a903-e493-4cfd-add8-a14efba5e7f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870897325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.2870897325
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.3194692571
Short name T652
Test name
Test status
Simulation time 35184934655 ps
CPU time 879.1 seconds
Started Mar 24 01:19:18 PM PDT 24
Finished Mar 24 01:33:58 PM PDT 24
Peak memory 369984 kb
Host smart-6a94f121-c8a8-4fec-be8d-788ff29db04b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194692571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.3194692571
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.1837690607
Short name T28
Test name
Test status
Simulation time 2740405092 ps
CPU time 5.17 seconds
Started Mar 24 01:19:18 PM PDT 24
Finished Mar 24 01:19:23 PM PDT 24
Peak memory 202000 kb
Host smart-fa9f055a-af50-4b88-a89d-24815de4f0b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837690607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.1837690607
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.546366867
Short name T215
Test name
Test status
Simulation time 364322430 ps
CPU time 29.93 seconds
Started Mar 24 01:19:23 PM PDT 24
Finished Mar 24 01:19:53 PM PDT 24
Peak memory 292688 kb
Host smart-695ded10-3b82-4421-b9f4-d41febf7b6e1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546366867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.sram_ctrl_max_throughput.546366867
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3053935536
Short name T845
Test name
Test status
Simulation time 172451529 ps
CPU time 4.89 seconds
Started Mar 24 01:19:20 PM PDT 24
Finished Mar 24 01:19:25 PM PDT 24
Peak memory 210120 kb
Host smart-391559e9-ab90-4c77-b603-494061a75a89
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053935536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.3053935536
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.2293266477
Short name T485
Test name
Test status
Simulation time 78527637 ps
CPU time 4.68 seconds
Started Mar 24 01:19:19 PM PDT 24
Finished Mar 24 01:19:24 PM PDT 24
Peak memory 201912 kb
Host smart-6b9dcc44-e56a-4735-b9cc-cdfa71a8824b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293266477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.2293266477
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.2409157770
Short name T15
Test name
Test status
Simulation time 50763737466 ps
CPU time 1042.3 seconds
Started Mar 24 01:19:20 PM PDT 24
Finished Mar 24 01:36:42 PM PDT 24
Peak memory 368616 kb
Host smart-829ff5fa-ab5e-40b4-b8b4-2c9f97adfc27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409157770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.2409157770
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.1084163106
Short name T867
Test name
Test status
Simulation time 409850969 ps
CPU time 7 seconds
Started Mar 24 01:19:20 PM PDT 24
Finished Mar 24 01:19:27 PM PDT 24
Peak memory 202024 kb
Host smart-32b0a779-b3fa-44f6-995a-17eb96411ae5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084163106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.1084163106
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2969298794
Short name T684
Test name
Test status
Simulation time 21163549228 ps
CPU time 276.82 seconds
Started Mar 24 01:19:18 PM PDT 24
Finished Mar 24 01:23:55 PM PDT 24
Peak memory 202108 kb
Host smart-04173551-3325-42ba-aed5-ff40b5e6abc2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969298794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.2969298794
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.3877247863
Short name T735
Test name
Test status
Simulation time 233127570 ps
CPU time 0.77 seconds
Started Mar 24 01:19:20 PM PDT 24
Finished Mar 24 01:19:21 PM PDT 24
Peak memory 202172 kb
Host smart-fb2977d1-5545-4805-87e9-a1067b96708c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877247863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3877247863
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.1875329
Short name T904
Test name
Test status
Simulation time 10728743324 ps
CPU time 632.31 seconds
Started Mar 24 01:19:22 PM PDT 24
Finished Mar 24 01:29:55 PM PDT 24
Peak memory 371848 kb
Host smart-70e72d44-a75a-4530-934a-d12ea9339807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1875329
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.1493230727
Short name T506
Test name
Test status
Simulation time 1087134405 ps
CPU time 17.47 seconds
Started Mar 24 01:19:14 PM PDT 24
Finished Mar 24 01:19:32 PM PDT 24
Peak memory 202024 kb
Host smart-2e91fddf-133b-435a-9e59-8bbcbdf103f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493230727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1493230727
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.1662068208
Short name T353
Test name
Test status
Simulation time 49895841211 ps
CPU time 2568.65 seconds
Started Mar 24 01:19:19 PM PDT 24
Finished Mar 24 02:02:08 PM PDT 24
Peak memory 374128 kb
Host smart-e84faff3-c821-4d58-8790-e2a9cf7cbce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662068208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.1662068208
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2476035167
Short name T910
Test name
Test status
Simulation time 1469957453 ps
CPU time 22.56 seconds
Started Mar 24 01:19:18 PM PDT 24
Finished Mar 24 01:19:41 PM PDT 24
Peak memory 211356 kb
Host smart-0350c21a-8640-4587-8135-f61d95807290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2476035167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2476035167
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3042829190
Short name T543
Test name
Test status
Simulation time 2564456417 ps
CPU time 122.64 seconds
Started Mar 24 01:19:18 PM PDT 24
Finished Mar 24 01:21:21 PM PDT 24
Peak memory 202056 kb
Host smart-fc8e448b-28a3-46e0-ae76-cc0b8e0fe8dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042829190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3042829190
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.605092740
Short name T597
Test name
Test status
Simulation time 473944933 ps
CPU time 30.21 seconds
Started Mar 24 01:19:20 PM PDT 24
Finished Mar 24 01:19:51 PM PDT 24
Peak memory 278732 kb
Host smart-3d54cfc2-44a3-4d78-b686-1cd56f9d45d8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605092740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_throughput_w_partial_write.605092740
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1922820972
Short name T885
Test name
Test status
Simulation time 14424171889 ps
CPU time 1392.79 seconds
Started Mar 24 01:19:23 PM PDT 24
Finished Mar 24 01:42:36 PM PDT 24
Peak memory 372076 kb
Host smart-67ff84d6-83c8-41c0-a9a5-eaded0aa4ba1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922820972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.1922820972
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.629484608
Short name T21
Test name
Test status
Simulation time 22211384 ps
CPU time 0.63 seconds
Started Mar 24 01:19:24 PM PDT 24
Finished Mar 24 01:19:24 PM PDT 24
Peak memory 201168 kb
Host smart-71139a8f-31cb-4ea0-805b-d69efbc6970c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629484608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.629484608
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.931833692
Short name T695
Test name
Test status
Simulation time 4439154522 ps
CPU time 67.19 seconds
Started Mar 24 01:19:29 PM PDT 24
Finished Mar 24 01:20:37 PM PDT 24
Peak memory 202088 kb
Host smart-05506aed-e942-443d-b20f-eaab83713ff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931833692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.
931833692
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.3139939065
Short name T62
Test name
Test status
Simulation time 14984010244 ps
CPU time 746.63 seconds
Started Mar 24 01:19:23 PM PDT 24
Finished Mar 24 01:31:49 PM PDT 24
Peak memory 373188 kb
Host smart-67b3da2c-9613-40aa-8cb6-396337bb5881
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139939065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.3139939065
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.3154656793
Short name T690
Test name
Test status
Simulation time 418359638 ps
CPU time 3.79 seconds
Started Mar 24 01:19:24 PM PDT 24
Finished Mar 24 01:19:28 PM PDT 24
Peak memory 202056 kb
Host smart-6b8b794e-0105-43e5-8bc9-1134a86c3eee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154656793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.3154656793
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.2972143175
Short name T345
Test name
Test status
Simulation time 647119341 ps
CPU time 72.78 seconds
Started Mar 24 01:19:22 PM PDT 24
Finished Mar 24 01:20:35 PM PDT 24
Peak memory 324704 kb
Host smart-e10d993c-7d79-403c-af6f-541ee41eb7c3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972143175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.2972143175
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2512872968
Short name T86
Test name
Test status
Simulation time 103804824 ps
CPU time 2.55 seconds
Started Mar 24 01:19:23 PM PDT 24
Finished Mar 24 01:19:25 PM PDT 24
Peak memory 210500 kb
Host smart-41130c41-127b-4190-861d-6b02c56f2c38
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512872968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.2512872968
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.2306301780
Short name T163
Test name
Test status
Simulation time 85660673 ps
CPU time 4.56 seconds
Started Mar 24 01:19:29 PM PDT 24
Finished Mar 24 01:19:34 PM PDT 24
Peak memory 201976 kb
Host smart-d04fadfe-e64b-4843-a509-2f01b153cb3f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306301780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.2306301780
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.3833307027
Short name T496
Test name
Test status
Simulation time 28191879146 ps
CPU time 1449.71 seconds
Started Mar 24 01:19:23 PM PDT 24
Finished Mar 24 01:43:33 PM PDT 24
Peak memory 373880 kb
Host smart-b8eaf589-cc9c-4a93-83aa-05b83cbcaa1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833307027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.3833307027
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.881696531
Short name T39
Test name
Test status
Simulation time 7004866421 ps
CPU time 30.97 seconds
Started Mar 24 01:19:23 PM PDT 24
Finished Mar 24 01:19:54 PM PDT 24
Peak memory 285080 kb
Host smart-1425312d-e021-4593-b231-f32aeced7f8e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881696531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s
ram_ctrl_partial_access.881696531
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2105330958
Short name T99
Test name
Test status
Simulation time 4355742014 ps
CPU time 307.01 seconds
Started Mar 24 01:19:25 PM PDT 24
Finished Mar 24 01:24:32 PM PDT 24
Peak memory 202068 kb
Host smart-b0e3c588-bbd3-48f6-820f-4436d22dfe8e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105330958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.2105330958
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.2809363694
Short name T607
Test name
Test status
Simulation time 77989097 ps
CPU time 0.78 seconds
Started Mar 24 01:19:29 PM PDT 24
Finished Mar 24 01:19:30 PM PDT 24
Peak memory 202148 kb
Host smart-858aba73-c982-443e-adcb-8fbda83b530d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809363694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2809363694
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.576769579
Short name T699
Test name
Test status
Simulation time 3877444500 ps
CPU time 1040.59 seconds
Started Mar 24 01:19:25 PM PDT 24
Finished Mar 24 01:36:45 PM PDT 24
Peak memory 373716 kb
Host smart-c6f4db66-8250-4eca-9b84-5cb9fbbcfe2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576769579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.576769579
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.4205852715
Short name T914
Test name
Test status
Simulation time 7845916066 ps
CPU time 9.23 seconds
Started Mar 24 01:19:24 PM PDT 24
Finished Mar 24 01:19:33 PM PDT 24
Peak memory 202020 kb
Host smart-4f0abe95-b64c-445e-b98a-ed7172b13780
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205852715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.4205852715
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.1675040096
Short name T154
Test name
Test status
Simulation time 22425315004 ps
CPU time 2068.54 seconds
Started Mar 24 01:19:26 PM PDT 24
Finished Mar 24 01:53:55 PM PDT 24
Peak memory 373884 kb
Host smart-204a3db3-c44c-4ca0-8678-044c78610ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675040096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.sram_ctrl_stress_all.1675040096
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2507442643
Short name T562
Test name
Test status
Simulation time 7557651025 ps
CPU time 172.43 seconds
Started Mar 24 01:19:24 PM PDT 24
Finished Mar 24 01:22:16 PM PDT 24
Peak memory 202048 kb
Host smart-d0a39482-4bf1-45b8-a922-81e81d2cbd21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507442643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.2507442643
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4010008196
Short name T271
Test name
Test status
Simulation time 79387109 ps
CPU time 1.81 seconds
Started Mar 24 01:19:23 PM PDT 24
Finished Mar 24 01:19:25 PM PDT 24
Peak memory 210192 kb
Host smart-3f7ee282-706c-4942-b2ab-52be5fda5720
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010008196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.4010008196
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.110252274
Short name T792
Test name
Test status
Simulation time 15547594114 ps
CPU time 969.37 seconds
Started Mar 24 01:19:28 PM PDT 24
Finished Mar 24 01:35:38 PM PDT 24
Peak memory 372836 kb
Host smart-508f9846-fa3f-46eb-bffc-ccd7c05ed6b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110252274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 43.sram_ctrl_access_during_key_req.110252274
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.2292884458
Short name T542
Test name
Test status
Simulation time 104783287 ps
CPU time 0.74 seconds
Started Mar 24 01:19:32 PM PDT 24
Finished Mar 24 01:19:33 PM PDT 24
Peak memory 201168 kb
Host smart-b4850686-0ab9-4cab-a230-b132e28872a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292884458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.2292884458
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.1599470304
Short name T455
Test name
Test status
Simulation time 5683908586 ps
CPU time 62.78 seconds
Started Mar 24 01:19:22 PM PDT 24
Finished Mar 24 01:20:25 PM PDT 24
Peak memory 202112 kb
Host smart-0bef0dd2-1cbd-4987-a2be-ce78f9798c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599470304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.1599470304
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.1318296215
Short name T362
Test name
Test status
Simulation time 1558057935 ps
CPU time 486.75 seconds
Started Mar 24 01:19:27 PM PDT 24
Finished Mar 24 01:27:34 PM PDT 24
Peak memory 353276 kb
Host smart-396517d1-1547-4314-96eb-fbb96463b17a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318296215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.1318296215
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.3565241453
Short name T425
Test name
Test status
Simulation time 421397414 ps
CPU time 3.61 seconds
Started Mar 24 01:19:30 PM PDT 24
Finished Mar 24 01:19:34 PM PDT 24
Peak memory 202032 kb
Host smart-cd2100a8-3298-4c1b-a5e9-99d8a3e2ae56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565241453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.3565241453
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.3134621363
Short name T338
Test name
Test status
Simulation time 1708576420 ps
CPU time 75.38 seconds
Started Mar 24 01:19:29 PM PDT 24
Finished Mar 24 01:20:45 PM PDT 24
Peak memory 321668 kb
Host smart-7f04aa15-c0ff-433f-9a6d-ffa193e93c80
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134621363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.3134621363
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.4284666120
Short name T553
Test name
Test status
Simulation time 240393163 ps
CPU time 4.22 seconds
Started Mar 24 01:19:28 PM PDT 24
Finished Mar 24 01:19:32 PM PDT 24
Peak memory 210268 kb
Host smart-c292f8b7-6437-4d2e-b419-6c81ea69ef6d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284666120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.4284666120
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.3690168024
Short name T725
Test name
Test status
Simulation time 1090272630 ps
CPU time 9.92 seconds
Started Mar 24 01:19:27 PM PDT 24
Finished Mar 24 01:19:37 PM PDT 24
Peak memory 201920 kb
Host smart-dac649a3-6ee3-4529-927f-1ac0919c81ee
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690168024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.3690168024
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.1260361297
Short name T375
Test name
Test status
Simulation time 34960984522 ps
CPU time 655.84 seconds
Started Mar 24 01:19:25 PM PDT 24
Finished Mar 24 01:30:21 PM PDT 24
Peak memory 371700 kb
Host smart-0abc9e76-51f5-4da4-bdd2-00204b1bbd06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260361297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.1260361297
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.969592524
Short name T795
Test name
Test status
Simulation time 38352536 ps
CPU time 0.98 seconds
Started Mar 24 01:19:28 PM PDT 24
Finished Mar 24 01:19:29 PM PDT 24
Peak memory 201708 kb
Host smart-48633337-5758-4de3-8a14-b52ab7269aa7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969592524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s
ram_ctrl_partial_access.969592524
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2688928609
Short name T943
Test name
Test status
Simulation time 74227919398 ps
CPU time 433.72 seconds
Started Mar 24 01:19:27 PM PDT 24
Finished Mar 24 01:26:40 PM PDT 24
Peak memory 202060 kb
Host smart-c55b9a39-827b-4502-a571-a4c3fc2e8041
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688928609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.2688928609
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.205752134
Short name T812
Test name
Test status
Simulation time 88108004 ps
CPU time 0.75 seconds
Started Mar 24 01:19:27 PM PDT 24
Finished Mar 24 01:19:28 PM PDT 24
Peak memory 202188 kb
Host smart-a33f0405-02a7-4aae-8cb6-42907c39ae44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205752134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.205752134
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.660369245
Short name T552
Test name
Test status
Simulation time 9547815315 ps
CPU time 330.78 seconds
Started Mar 24 01:19:28 PM PDT 24
Finished Mar 24 01:24:59 PM PDT 24
Peak memory 365556 kb
Host smart-43069b0a-66b0-410c-aaa6-e65fe7da97ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660369245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.660369245
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.164216207
Short name T541
Test name
Test status
Simulation time 740091316 ps
CPU time 15.59 seconds
Started Mar 24 01:19:22 PM PDT 24
Finished Mar 24 01:19:38 PM PDT 24
Peak memory 202004 kb
Host smart-551c21c2-851c-4976-9d01-afe090d05f6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164216207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.164216207
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.3662260981
Short name T733
Test name
Test status
Simulation time 214031109257 ps
CPU time 4511.02 seconds
Started Mar 24 01:19:32 PM PDT 24
Finished Mar 24 02:34:44 PM PDT 24
Peak memory 374852 kb
Host smart-27c0f7a8-d308-426e-868b-45016faa9f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662260981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.sram_ctrl_stress_all.3662260981
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.313263307
Short name T330
Test name
Test status
Simulation time 672602208 ps
CPU time 34.72 seconds
Started Mar 24 01:19:32 PM PDT 24
Finished Mar 24 01:20:07 PM PDT 24
Peak memory 279988 kb
Host smart-82096ff4-000a-4e50-950b-ab70a4920e30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=313263307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.313263307
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3809488587
Short name T558
Test name
Test status
Simulation time 6762540982 ps
CPU time 156.1 seconds
Started Mar 24 01:19:28 PM PDT 24
Finished Mar 24 01:22:05 PM PDT 24
Peak memory 201992 kb
Host smart-5ab3a090-6ab1-496d-a103-6dffa6367e59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809488587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.3809488587
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4001926162
Short name T539
Test name
Test status
Simulation time 130080110 ps
CPU time 71.32 seconds
Started Mar 24 01:19:28 PM PDT 24
Finished Mar 24 01:20:39 PM PDT 24
Peak memory 317464 kb
Host smart-1141352b-3c46-48b4-a125-2bf03e25613b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001926162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.4001926162
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2658352521
Short name T769
Test name
Test status
Simulation time 3856870510 ps
CPU time 1145.63 seconds
Started Mar 24 01:19:37 PM PDT 24
Finished Mar 24 01:38:43 PM PDT 24
Peak memory 373812 kb
Host smart-cd612983-844a-473e-b509-647e32419853
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658352521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.2658352521
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.2882288344
Short name T167
Test name
Test status
Simulation time 39188669 ps
CPU time 0.64 seconds
Started Mar 24 01:19:37 PM PDT 24
Finished Mar 24 01:19:38 PM PDT 24
Peak memory 201192 kb
Host smart-6471b15c-a21f-4870-8b0c-85c653121798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882288344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.2882288344
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.3469702833
Short name T585
Test name
Test status
Simulation time 28901744864 ps
CPU time 58.01 seconds
Started Mar 24 01:19:32 PM PDT 24
Finished Mar 24 01:20:30 PM PDT 24
Peak memory 202116 kb
Host smart-712ee43d-0602-402d-925c-4e0352bde4a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469702833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.3469702833
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.3099077605
Short name T134
Test name
Test status
Simulation time 2198165030 ps
CPU time 11.95 seconds
Started Mar 24 01:19:39 PM PDT 24
Finished Mar 24 01:19:51 PM PDT 24
Peak memory 202100 kb
Host smart-eca948d7-1e7e-4946-8b74-eee1c15f5c15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099077605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab
le.3099077605
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.1326443460
Short name T276
Test name
Test status
Simulation time 429788958 ps
CPU time 2.65 seconds
Started Mar 24 01:19:36 PM PDT 24
Finished Mar 24 01:19:39 PM PDT 24
Peak memory 202020 kb
Host smart-37aa45e6-e1b3-459a-adc9-ed2a121c997b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326443460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.1326443460
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.1289519585
Short name T430
Test name
Test status
Simulation time 144293097 ps
CPU time 2.57 seconds
Started Mar 24 01:19:35 PM PDT 24
Finished Mar 24 01:19:38 PM PDT 24
Peak memory 218132 kb
Host smart-ac97b6be-d853-41bd-9372-2b13d3639337
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289519585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.1289519585
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1439266173
Short name T319
Test name
Test status
Simulation time 588236197 ps
CPU time 4.92 seconds
Started Mar 24 01:19:37 PM PDT 24
Finished Mar 24 01:19:42 PM PDT 24
Peak memory 210196 kb
Host smart-37416371-3e46-41b6-a81e-45740fbc88d5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439266173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.1439266173
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.3124987101
Short name T5
Test name
Test status
Simulation time 2152871881 ps
CPU time 6.15 seconds
Started Mar 24 01:19:38 PM PDT 24
Finished Mar 24 01:19:44 PM PDT 24
Peak memory 202024 kb
Host smart-be977f0e-8d91-490b-acb8-20c95e455bb0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124987101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.3124987101
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.252398942
Short name T179
Test name
Test status
Simulation time 1819724730 ps
CPU time 761.64 seconds
Started Mar 24 01:19:33 PM PDT 24
Finished Mar 24 01:32:14 PM PDT 24
Peak memory 358428 kb
Host smart-7c97b3e6-05ad-4dca-94dc-3291df2ef7ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252398942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multip
le_keys.252398942
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.774103930
Short name T415
Test name
Test status
Simulation time 279032258 ps
CPU time 14.03 seconds
Started Mar 24 01:19:32 PM PDT 24
Finished Mar 24 01:19:46 PM PDT 24
Peak memory 201932 kb
Host smart-1fc3ce77-6500-45e8-b8b2-fb109a3a5bb6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774103930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s
ram_ctrl_partial_access.774103930
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2228395204
Short name T811
Test name
Test status
Simulation time 4416261696 ps
CPU time 153.55 seconds
Started Mar 24 01:19:37 PM PDT 24
Finished Mar 24 01:22:11 PM PDT 24
Peak memory 202072 kb
Host smart-ed96fa97-c326-4b7e-8c56-0daab975e089
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228395204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.2228395204
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.4217649285
Short name T331
Test name
Test status
Simulation time 81524169 ps
CPU time 0.71 seconds
Started Mar 24 01:19:37 PM PDT 24
Finished Mar 24 01:19:38 PM PDT 24
Peak memory 202140 kb
Host smart-0282a392-881e-43eb-b810-530984603906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217649285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.4217649285
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.1775670871
Short name T264
Test name
Test status
Simulation time 4404834716 ps
CPU time 857.77 seconds
Started Mar 24 01:19:44 PM PDT 24
Finished Mar 24 01:34:02 PM PDT 24
Peak memory 367400 kb
Host smart-2ecba563-1e1c-4a41-b9fe-45387f50a0a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775670871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1775670871
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.978857441
Short name T233
Test name
Test status
Simulation time 171298163 ps
CPU time 9.6 seconds
Started Mar 24 01:19:33 PM PDT 24
Finished Mar 24 01:19:43 PM PDT 24
Peak memory 202016 kb
Host smart-749242c9-75d3-4631-81df-cd8e43f02ca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978857441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.978857441
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.3018169433
Short name T463
Test name
Test status
Simulation time 7676264409 ps
CPU time 1534.7 seconds
Started Mar 24 01:19:43 PM PDT 24
Finished Mar 24 01:45:19 PM PDT 24
Peak memory 379740 kb
Host smart-1cf9d788-566b-43cf-9d9a-20fa49e48ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018169433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.3018169433
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2366149760
Short name T475
Test name
Test status
Simulation time 384139352 ps
CPU time 198.55 seconds
Started Mar 24 01:19:36 PM PDT 24
Finished Mar 24 01:22:55 PM PDT 24
Peak memory 368980 kb
Host smart-76e6652a-0c5c-44ea-9626-7df10825ef27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2366149760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2366149760
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1847827609
Short name T667
Test name
Test status
Simulation time 11060106552 ps
CPU time 273.29 seconds
Started Mar 24 01:19:33 PM PDT 24
Finished Mar 24 01:24:07 PM PDT 24
Peak memory 202076 kb
Host smart-c98ca66d-551a-4ee0-8f91-74f29fd8a851
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847827609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.1847827609
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3283431990
Short name T216
Test name
Test status
Simulation time 621253574 ps
CPU time 152.39 seconds
Started Mar 24 01:19:44 PM PDT 24
Finished Mar 24 01:22:16 PM PDT 24
Peak memory 368312 kb
Host smart-283cd34b-0bb4-42b1-99e3-8a5a9054b6a1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283431990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3283431990
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3246800932
Short name T80
Test name
Test status
Simulation time 3272576448 ps
CPU time 1116.6 seconds
Started Mar 24 01:19:41 PM PDT 24
Finished Mar 24 01:38:18 PM PDT 24
Peak memory 370208 kb
Host smart-857e9c6d-2d9e-460c-b068-5b9527af3c14
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246800932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.3246800932
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.2737983501
Short name T932
Test name
Test status
Simulation time 39267653 ps
CPU time 0.69 seconds
Started Mar 24 01:19:42 PM PDT 24
Finished Mar 24 01:19:43 PM PDT 24
Peak memory 201772 kb
Host smart-2118321b-f8f3-4824-81c4-b17473ef06e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737983501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.2737983501
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.3271230089
Short name T768
Test name
Test status
Simulation time 791452527 ps
CPU time 48.57 seconds
Started Mar 24 01:19:38 PM PDT 24
Finished Mar 24 01:20:27 PM PDT 24
Peak memory 202088 kb
Host smart-d6cf6f38-c5fb-4f24-be01-d390b727af35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271230089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.3271230089
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.1159007930
Short name T394
Test name
Test status
Simulation time 39533331207 ps
CPU time 865.85 seconds
Started Mar 24 01:19:40 PM PDT 24
Finished Mar 24 01:34:06 PM PDT 24
Peak memory 373940 kb
Host smart-4ec9f054-7252-443d-9550-44e4b26bea3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159007930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.1159007930
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.2148648485
Short name T842
Test name
Test status
Simulation time 480489995 ps
CPU time 5.56 seconds
Started Mar 24 01:19:41 PM PDT 24
Finished Mar 24 01:19:47 PM PDT 24
Peak memory 202040 kb
Host smart-04eff8db-c320-4be1-a5f6-731510ee5019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148648485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.2148648485
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.1474047708
Short name T439
Test name
Test status
Simulation time 138169165 ps
CPU time 116.18 seconds
Started Mar 24 01:19:38 PM PDT 24
Finished Mar 24 01:21:34 PM PDT 24
Peak memory 367600 kb
Host smart-67eac299-00c2-4b9d-b0ed-53327d574654
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474047708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.1474047708
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3342723417
Short name T707
Test name
Test status
Simulation time 66874372 ps
CPU time 4.39 seconds
Started Mar 24 01:19:42 PM PDT 24
Finished Mar 24 01:19:46 PM PDT 24
Peak memory 210108 kb
Host smart-48d4365f-46ed-4056-996c-4711dec3fbf4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342723417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.3342723417
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.4278068685
Short name T623
Test name
Test status
Simulation time 267492244 ps
CPU time 7.98 seconds
Started Mar 24 01:19:41 PM PDT 24
Finished Mar 24 01:19:50 PM PDT 24
Peak memory 201996 kb
Host smart-e0bc5e2a-5535-415d-8a44-05c25c51bf78
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278068685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.4278068685
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.1863656857
Short name T493
Test name
Test status
Simulation time 221931792 ps
CPU time 2.5 seconds
Started Mar 24 01:19:38 PM PDT 24
Finished Mar 24 01:19:40 PM PDT 24
Peak memory 201980 kb
Host smart-1eb45354-8cb0-49da-ac20-470fd7969ec8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863656857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.1863656857
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2712614771
Short name T471
Test name
Test status
Simulation time 45278066400 ps
CPU time 292.27 seconds
Started Mar 24 01:19:39 PM PDT 24
Finished Mar 24 01:24:31 PM PDT 24
Peak memory 202096 kb
Host smart-82764f58-ad3b-4ab2-a66f-a719afe38dda
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712614771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.2712614771
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.3717514385
Short name T398
Test name
Test status
Simulation time 76678514 ps
CPU time 0.77 seconds
Started Mar 24 01:19:41 PM PDT 24
Finished Mar 24 01:19:42 PM PDT 24
Peak memory 202092 kb
Host smart-e876c25a-d92d-48cb-a05b-6d63b55268e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717514385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3717514385
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.3522099858
Short name T390
Test name
Test status
Simulation time 53654334887 ps
CPU time 881.97 seconds
Started Mar 24 01:19:40 PM PDT 24
Finished Mar 24 01:34:23 PM PDT 24
Peak memory 371664 kb
Host smart-20c2a963-f519-4a8f-af41-eb58a4d1c4eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522099858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3522099858
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.582998177
Short name T614
Test name
Test status
Simulation time 397179606 ps
CPU time 38.86 seconds
Started Mar 24 01:19:39 PM PDT 24
Finished Mar 24 01:20:18 PM PDT 24
Peak memory 295708 kb
Host smart-48052b5a-c15d-44b8-8231-e11cc063701c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582998177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.582998177
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.1445568084
Short name T129
Test name
Test status
Simulation time 20948344728 ps
CPU time 1402.56 seconds
Started Mar 24 01:19:42 PM PDT 24
Finished Mar 24 01:43:05 PM PDT 24
Peak memory 373848 kb
Host smart-6903275f-b57e-4e93-87b1-1295114645cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445568084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.1445568084
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3634917948
Short name T389
Test name
Test status
Simulation time 6256063277 ps
CPU time 289.21 seconds
Started Mar 24 01:19:38 PM PDT 24
Finished Mar 24 01:24:27 PM PDT 24
Peak memory 202064 kb
Host smart-aa89106a-31a9-41fb-899a-a1a42d9cf955
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634917948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.3634917948
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1223015353
Short name T913
Test name
Test status
Simulation time 188358317 ps
CPU time 25.25 seconds
Started Mar 24 01:19:36 PM PDT 24
Finished Mar 24 01:20:01 PM PDT 24
Peak memory 279680 kb
Host smart-5b7c36ec-0080-4df6-a161-d873003828c6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223015353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1223015353
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2815901809
Short name T732
Test name
Test status
Simulation time 14196739982 ps
CPU time 1304.29 seconds
Started Mar 24 01:19:46 PM PDT 24
Finished Mar 24 01:41:31 PM PDT 24
Peak memory 371800 kb
Host smart-dcb62fa3-0b7d-403c-bc59-4168b387640e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815901809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.2815901809
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.507757186
Short name T663
Test name
Test status
Simulation time 18960603 ps
CPU time 0.63 seconds
Started Mar 24 01:19:48 PM PDT 24
Finished Mar 24 01:19:49 PM PDT 24
Peak memory 201144 kb
Host smart-e1f5ae1f-0afd-4e7a-a609-cd044b1298df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507757186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.507757186
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.351963513
Short name T577
Test name
Test status
Simulation time 7261155015 ps
CPU time 29.83 seconds
Started Mar 24 01:19:42 PM PDT 24
Finished Mar 24 01:20:13 PM PDT 24
Peak memory 202156 kb
Host smart-f0c66437-8182-43f3-81a8-c35cc05b1e5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351963513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.
351963513
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.1018966182
Short name T387
Test name
Test status
Simulation time 7909798462 ps
CPU time 782.82 seconds
Started Mar 24 01:19:48 PM PDT 24
Finished Mar 24 01:32:52 PM PDT 24
Peak memory 368528 kb
Host smart-650fdddd-1584-4bd8-9636-0ecfe55b2b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018966182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.1018966182
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.3769507075
Short name T573
Test name
Test status
Simulation time 2196061532 ps
CPU time 6.78 seconds
Started Mar 24 01:19:45 PM PDT 24
Finished Mar 24 01:19:52 PM PDT 24
Peak memory 202128 kb
Host smart-49fb4605-6df4-48ca-910b-887ca1f1c448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769507075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.3769507075
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.3203591728
Short name T191
Test name
Test status
Simulation time 130832585 ps
CPU time 82.94 seconds
Started Mar 24 01:19:48 PM PDT 24
Finished Mar 24 01:21:11 PM PDT 24
Peak memory 357892 kb
Host smart-c85cac30-d331-4330-bc17-f77d8565824c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203591728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.3203591728
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3205169626
Short name T250
Test name
Test status
Simulation time 46737049 ps
CPU time 2.62 seconds
Started Mar 24 01:19:46 PM PDT 24
Finished Mar 24 01:19:49 PM PDT 24
Peak memory 210172 kb
Host smart-da50704a-04a9-4f46-9c3d-248621eeaf65
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205169626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.3205169626
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.461727348
Short name T689
Test name
Test status
Simulation time 74482844 ps
CPU time 4.31 seconds
Started Mar 24 01:19:46 PM PDT 24
Finished Mar 24 01:19:51 PM PDT 24
Peak memory 201952 kb
Host smart-5894c79e-eb75-4eb6-a2ca-0d05fe5bb58f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461727348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl
_mem_walk.461727348
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.395302059
Short name T714
Test name
Test status
Simulation time 21656692112 ps
CPU time 572.46 seconds
Started Mar 24 01:19:42 PM PDT 24
Finished Mar 24 01:29:15 PM PDT 24
Peak memory 353032 kb
Host smart-65efbebf-da4b-4376-8294-6fff1517550b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395302059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip
le_keys.395302059
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.525805835
Short name T314
Test name
Test status
Simulation time 803635755 ps
CPU time 26.62 seconds
Started Mar 24 01:19:47 PM PDT 24
Finished Mar 24 01:20:14 PM PDT 24
Peak memory 284196 kb
Host smart-d9263769-1162-492b-9883-b6f58bd9d109
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525805835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s
ram_ctrl_partial_access.525805835
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3690951244
Short name T827
Test name
Test status
Simulation time 46637653093 ps
CPU time 392.8 seconds
Started Mar 24 01:19:49 PM PDT 24
Finished Mar 24 01:26:23 PM PDT 24
Peak memory 202076 kb
Host smart-7b03f78e-2ed0-49b8-be8d-7e8b5758a1a5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690951244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.3690951244
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.1062206578
Short name T32
Test name
Test status
Simulation time 46869638 ps
CPU time 0.75 seconds
Started Mar 24 01:19:45 PM PDT 24
Finished Mar 24 01:19:46 PM PDT 24
Peak memory 202128 kb
Host smart-4300412a-f4fd-48bc-96d1-1d6886aa1d8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062206578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1062206578
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.625292326
Short name T42
Test name
Test status
Simulation time 55137032648 ps
CPU time 831.42 seconds
Started Mar 24 01:19:46 PM PDT 24
Finished Mar 24 01:33:38 PM PDT 24
Peak memory 372048 kb
Host smart-2f3f4cf3-a2a3-4201-adb2-b125bcf5d8f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625292326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.625292326
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.1953626643
Short name T490
Test name
Test status
Simulation time 230473358 ps
CPU time 12.65 seconds
Started Mar 24 01:19:42 PM PDT 24
Finished Mar 24 01:19:56 PM PDT 24
Peak memory 202052 kb
Host smart-e4ba4a2c-fd39-4bb6-953b-700a36c6e421
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953626643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1953626643
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.1441943188
Short name T694
Test name
Test status
Simulation time 139746665010 ps
CPU time 604.01 seconds
Started Mar 24 01:19:47 PM PDT 24
Finished Mar 24 01:29:51 PM PDT 24
Peak memory 371028 kb
Host smart-a3c82d45-2a23-491c-b6b3-ce669ad39b8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441943188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.1441943188
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3989916274
Short name T554
Test name
Test status
Simulation time 1476805041 ps
CPU time 342.71 seconds
Started Mar 24 01:19:46 PM PDT 24
Finished Mar 24 01:25:30 PM PDT 24
Peak memory 375088 kb
Host smart-a5fce30a-c19f-4c1e-a1aa-39c771b64c97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3989916274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3989916274
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1495803492
Short name T898
Test name
Test status
Simulation time 10994729519 ps
CPU time 150.11 seconds
Started Mar 24 01:19:49 PM PDT 24
Finished Mar 24 01:22:19 PM PDT 24
Peak memory 202060 kb
Host smart-bdfbe709-46a8-4901-a008-6eceeb9a8947
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495803492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.1495803492
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2909447813
Short name T730
Test name
Test status
Simulation time 309051372 ps
CPU time 136.91 seconds
Started Mar 24 01:19:47 PM PDT 24
Finished Mar 24 01:22:04 PM PDT 24
Peak memory 366400 kb
Host smart-a15e28f8-f917-4529-9fc1-90613dff55fb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909447813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2909447813
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3795404646
Short name T37
Test name
Test status
Simulation time 4361084214 ps
CPU time 1078.93 seconds
Started Mar 24 01:19:52 PM PDT 24
Finished Mar 24 01:37:52 PM PDT 24
Peak memory 373052 kb
Host smart-f6b1e99b-c67c-4e37-92b4-25cbf6e86773
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795404646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.3795404646
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.2886535940
Short name T884
Test name
Test status
Simulation time 41691848 ps
CPU time 0.65 seconds
Started Mar 24 01:19:56 PM PDT 24
Finished Mar 24 01:19:57 PM PDT 24
Peak memory 200952 kb
Host smart-ee1d4fe6-8976-4d7e-8272-682a373fca47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886535940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.2886535940
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.1370492822
Short name T245
Test name
Test status
Simulation time 6157371924 ps
CPU time 36.01 seconds
Started Mar 24 01:19:46 PM PDT 24
Finished Mar 24 01:20:22 PM PDT 24
Peak memory 202068 kb
Host smart-ca097b36-3173-472a-8521-f029d779af75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370492822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.1370492822
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.3163276768
Short name T786
Test name
Test status
Simulation time 16916116874 ps
CPU time 712.35 seconds
Started Mar 24 01:19:52 PM PDT 24
Finished Mar 24 01:31:45 PM PDT 24
Peak memory 373208 kb
Host smart-bd77d485-0cbe-4519-8da0-8ccacdd25891
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163276768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.3163276768
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.2231193558
Short name T589
Test name
Test status
Simulation time 750025024 ps
CPU time 7.69 seconds
Started Mar 24 01:19:51 PM PDT 24
Finished Mar 24 01:19:59 PM PDT 24
Peak memory 210216 kb
Host smart-0863d9f0-0a85-4d61-80f3-71a09037afe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231193558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.2231193558
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.3488265480
Short name T600
Test name
Test status
Simulation time 294599930 ps
CPU time 47.4 seconds
Started Mar 24 01:19:53 PM PDT 24
Finished Mar 24 01:20:40 PM PDT 24
Peak memory 313312 kb
Host smart-e6ccc8ac-54d4-415e-87e6-cbe2df8e7333
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488265480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.3488265480
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1684188668
Short name T234
Test name
Test status
Simulation time 179206833 ps
CPU time 2.98 seconds
Started Mar 24 01:19:51 PM PDT 24
Finished Mar 24 01:19:54 PM PDT 24
Peak memory 210244 kb
Host smart-1d38ad26-854b-43f4-b52b-a00ddf8487f4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684188668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.1684188668
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.1222424121
Short name T639
Test name
Test status
Simulation time 145338153 ps
CPU time 4.2 seconds
Started Mar 24 01:19:51 PM PDT 24
Finished Mar 24 01:19:56 PM PDT 24
Peak memory 201912 kb
Host smart-45f15d35-24b6-402e-b31e-4cc4ac6ef41f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222424121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.1222424121
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.1979380284
Short name T765
Test name
Test status
Simulation time 1218760520 ps
CPU time 99.11 seconds
Started Mar 24 01:19:46 PM PDT 24
Finished Mar 24 01:21:25 PM PDT 24
Peak memory 335400 kb
Host smart-14917c7b-ac94-4238-9d45-e67b3331d153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979380284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.1979380284
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.810757384
Short name T177
Test name
Test status
Simulation time 56041873 ps
CPU time 1.75 seconds
Started Mar 24 01:19:47 PM PDT 24
Finished Mar 24 01:19:49 PM PDT 24
Peak memory 201988 kb
Host smart-db8cb0dd-d504-4321-9f86-f319a44e209a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810757384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s
ram_ctrl_partial_access.810757384
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2221333877
Short name T901
Test name
Test status
Simulation time 24504472912 ps
CPU time 156.5 seconds
Started Mar 24 01:19:46 PM PDT 24
Finished Mar 24 01:22:24 PM PDT 24
Peak memory 202080 kb
Host smart-35a62910-85ce-4ba3-97ce-26d17b48d306
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221333877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.2221333877
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.711351614
Short name T538
Test name
Test status
Simulation time 31865460 ps
CPU time 0.75 seconds
Started Mar 24 01:19:52 PM PDT 24
Finished Mar 24 01:19:53 PM PDT 24
Peak memory 202192 kb
Host smart-3bdea2d0-5cc3-4820-8b90-3593148f41cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711351614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.711351614
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.1308139773
Short name T919
Test name
Test status
Simulation time 3234258663 ps
CPU time 781.77 seconds
Started Mar 24 01:19:51 PM PDT 24
Finished Mar 24 01:32:53 PM PDT 24
Peak memory 373588 kb
Host smart-dafc4006-4628-42cc-9ada-562c63a36d24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308139773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.1308139773
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.4149325553
Short name T592
Test name
Test status
Simulation time 162877577 ps
CPU time 4.05 seconds
Started Mar 24 01:19:45 PM PDT 24
Finished Mar 24 01:19:49 PM PDT 24
Peak memory 201988 kb
Host smart-0851375f-94c5-4bc5-bbbe-e3b7b987a485
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149325553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.4149325553
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.476479081
Short name T379
Test name
Test status
Simulation time 3725356060 ps
CPU time 12.65 seconds
Started Mar 24 01:19:51 PM PDT 24
Finished Mar 24 01:20:04 PM PDT 24
Peak memory 211464 kb
Host smart-4ef00608-6521-4c1d-ba9a-b78e6b56de5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=476479081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.476479081
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1067780094
Short name T453
Test name
Test status
Simulation time 6247504467 ps
CPU time 294.27 seconds
Started Mar 24 01:19:47 PM PDT 24
Finished Mar 24 01:24:41 PM PDT 24
Peak memory 202080 kb
Host smart-d5f9bed0-bf0a-4116-94ed-8275f80d2187
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067780094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.1067780094
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3664260821
Short name T512
Test name
Test status
Simulation time 179647063 ps
CPU time 119.37 seconds
Started Mar 24 01:19:50 PM PDT 24
Finished Mar 24 01:21:50 PM PDT 24
Peak memory 365464 kb
Host smart-61777c92-8674-4dac-b061-8222a591edb7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664260821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.3664260821
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4144524507
Short name T807
Test name
Test status
Simulation time 7683706179 ps
CPU time 894.63 seconds
Started Mar 24 01:20:06 PM PDT 24
Finished Mar 24 01:35:01 PM PDT 24
Peak memory 371840 kb
Host smart-58a685db-27f5-4b31-89eb-95824fbd61fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144524507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.4144524507
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.3010015291
Short name T280
Test name
Test status
Simulation time 84216557 ps
CPU time 0.64 seconds
Started Mar 24 01:19:54 PM PDT 24
Finished Mar 24 01:19:55 PM PDT 24
Peak memory 201120 kb
Host smart-6a5bc926-eba5-446f-8def-0558b65638df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010015291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.3010015291
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.3250242876
Short name T856
Test name
Test status
Simulation time 17114516204 ps
CPU time 64.05 seconds
Started Mar 24 01:19:51 PM PDT 24
Finished Mar 24 01:20:55 PM PDT 24
Peak memory 202068 kb
Host smart-faf01991-36bc-4104-811c-2f3afe70e52a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250242876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.3250242876
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.766150962
Short name T839
Test name
Test status
Simulation time 18032194781 ps
CPU time 2241.11 seconds
Started Mar 24 01:19:55 PM PDT 24
Finished Mar 24 01:57:16 PM PDT 24
Peak memory 373888 kb
Host smart-453580b7-e434-4d9a-809e-67ab208d915f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766150962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl
e.766150962
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.3549524057
Short name T832
Test name
Test status
Simulation time 517448316 ps
CPU time 6.35 seconds
Started Mar 24 01:19:58 PM PDT 24
Finished Mar 24 01:20:04 PM PDT 24
Peak memory 202080 kb
Host smart-a894ace1-7677-466c-bf63-0bfe80a02b9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549524057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.3549524057
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.2766207482
Short name T251
Test name
Test status
Simulation time 41156756 ps
CPU time 1.54 seconds
Started Mar 24 01:19:54 PM PDT 24
Finished Mar 24 01:19:56 PM PDT 24
Peak memory 210268 kb
Host smart-0b098402-d007-4359-a02b-30254af68b78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766207482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.2766207482
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3088072488
Short name T886
Test name
Test status
Simulation time 670605512 ps
CPU time 5.25 seconds
Started Mar 24 01:19:58 PM PDT 24
Finished Mar 24 01:20:04 PM PDT 24
Peak memory 210160 kb
Host smart-1f388ba1-4659-4e57-bc27-58b47c19c2c4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088072488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.3088072488
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.1927310438
Short name T837
Test name
Test status
Simulation time 230953271 ps
CPU time 5.17 seconds
Started Mar 24 01:19:55 PM PDT 24
Finished Mar 24 01:20:00 PM PDT 24
Peak memory 201960 kb
Host smart-39f46f6e-4107-4453-a4a7-267f708f2c1e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927310438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.1927310438
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.2051693070
Short name T829
Test name
Test status
Simulation time 3781331694 ps
CPU time 22.5 seconds
Started Mar 24 01:19:52 PM PDT 24
Finished Mar 24 01:20:15 PM PDT 24
Peak memory 202124 kb
Host smart-6cf8f680-2550-4a56-a281-41bc95adf3c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051693070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.2051693070
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.3027937629
Short name T682
Test name
Test status
Simulation time 2539936373 ps
CPU time 44.18 seconds
Started Mar 24 01:19:57 PM PDT 24
Finished Mar 24 01:20:41 PM PDT 24
Peak memory 289580 kb
Host smart-99e56364-a0f5-4a4e-b9ee-98dfd10622d0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027937629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.3027937629
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2140387760
Short name T386
Test name
Test status
Simulation time 4178773681 ps
CPU time 143.79 seconds
Started Mar 24 01:20:06 PM PDT 24
Finished Mar 24 01:22:31 PM PDT 24
Peak memory 202064 kb
Host smart-adb43d18-f7eb-4931-9c91-fc485e022261
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140387760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.2140387760
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.2705998781
Short name T591
Test name
Test status
Simulation time 140410047 ps
CPU time 0.8 seconds
Started Mar 24 01:19:56 PM PDT 24
Finished Mar 24 01:19:57 PM PDT 24
Peak memory 202076 kb
Host smart-aa3b486b-5759-46b1-b384-4f426c6684e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705998781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2705998781
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.2406444721
Short name T31
Test name
Test status
Simulation time 25939654894 ps
CPU time 797.63 seconds
Started Mar 24 01:19:58 PM PDT 24
Finished Mar 24 01:33:16 PM PDT 24
Peak memory 372832 kb
Host smart-53bd50a1-8a90-43f4-9a61-0936ae7347b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406444721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2406444721
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.1222657716
Short name T306
Test name
Test status
Simulation time 545269522 ps
CPU time 69.45 seconds
Started Mar 24 01:19:55 PM PDT 24
Finished Mar 24 01:21:05 PM PDT 24
Peak memory 322648 kb
Host smart-86fb9145-48e6-463d-9c2f-3dc780df1cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222657716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1222657716
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3845644960
Short name T860
Test name
Test status
Simulation time 1713533131 ps
CPU time 165.7 seconds
Started Mar 24 01:19:51 PM PDT 24
Finished Mar 24 01:22:37 PM PDT 24
Peak memory 201856 kb
Host smart-41ac469a-f73b-4516-91fe-b55390a578b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845644960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.3845644960
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2861193936
Short name T424
Test name
Test status
Simulation time 195281512 ps
CPU time 34.32 seconds
Started Mar 24 01:19:54 PM PDT 24
Finished Mar 24 01:20:29 PM PDT 24
Peak memory 289688 kb
Host smart-975c14b7-aa99-48ef-a22c-1825305a5172
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861193936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.2861193936
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4168095300
Short name T918
Test name
Test status
Simulation time 5732544993 ps
CPU time 811.24 seconds
Started Mar 24 01:20:01 PM PDT 24
Finished Mar 24 01:33:32 PM PDT 24
Peak memory 368744 kb
Host smart-40ee2bc2-0e43-4d3f-a04a-f6dabb16b523
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168095300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.4168095300
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.3727561647
Short name T388
Test name
Test status
Simulation time 36446497 ps
CPU time 0.61 seconds
Started Mar 24 01:20:00 PM PDT 24
Finished Mar 24 01:20:01 PM PDT 24
Peak memory 200860 kb
Host smart-6b22d155-bc8d-4098-a71d-3f09b816a153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727561647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.3727561647
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.2332463195
Short name T778
Test name
Test status
Simulation time 2707755942 ps
CPU time 45.65 seconds
Started Mar 24 01:20:00 PM PDT 24
Finished Mar 24 01:20:46 PM PDT 24
Peak memory 202108 kb
Host smart-15b5221d-a29f-4b0d-82c4-08d101fa74ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332463195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.2332463195
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.2986084527
Short name T745
Test name
Test status
Simulation time 30608026723 ps
CPU time 462.44 seconds
Started Mar 24 01:20:01 PM PDT 24
Finished Mar 24 01:27:44 PM PDT 24
Peak memory 339040 kb
Host smart-11db533c-154b-47b1-acb8-0205f5318bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986084527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.2986084527
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.2551373975
Short name T410
Test name
Test status
Simulation time 556565883 ps
CPU time 6.28 seconds
Started Mar 24 01:20:08 PM PDT 24
Finished Mar 24 01:20:14 PM PDT 24
Peak memory 202068 kb
Host smart-13c8b31b-2b8a-4225-a7f0-d8be49a49df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551373975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.2551373975
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.2440954418
Short name T820
Test name
Test status
Simulation time 81519725 ps
CPU time 18.54 seconds
Started Mar 24 01:20:08 PM PDT 24
Finished Mar 24 01:20:27 PM PDT 24
Peak memory 276204 kb
Host smart-227acf07-4044-4d82-8093-3e943e6a2695
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440954418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.2440954418
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1796143603
Short name T567
Test name
Test status
Simulation time 385812722 ps
CPU time 2.99 seconds
Started Mar 24 01:20:08 PM PDT 24
Finished Mar 24 01:20:11 PM PDT 24
Peak memory 210176 kb
Host smart-b2931b33-b8b8-461a-826b-5a1ce91275b5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796143603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.1796143603
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.3120823870
Short name T364
Test name
Test status
Simulation time 84549388 ps
CPU time 4.68 seconds
Started Mar 24 01:20:00 PM PDT 24
Finished Mar 24 01:20:05 PM PDT 24
Peak memory 201936 kb
Host smart-b66a9872-da3c-4c04-a68b-dc5417b5df5a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120823870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.3120823870
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.3041119312
Short name T421
Test name
Test status
Simulation time 78152489220 ps
CPU time 869.07 seconds
Started Mar 24 01:19:57 PM PDT 24
Finished Mar 24 01:34:26 PM PDT 24
Peak memory 374860 kb
Host smart-374b8313-34c3-49b6-baef-a2e02a2dd0d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041119312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.3041119312
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.41748624
Short name T655
Test name
Test status
Simulation time 1489573856 ps
CPU time 117.2 seconds
Started Mar 24 01:20:00 PM PDT 24
Finished Mar 24 01:21:57 PM PDT 24
Peak memory 364496 kb
Host smart-0ca23a3c-6319-4b35-910b-dbc03ce73f56
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sr
am_ctrl_partial_access.41748624
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1744135871
Short name T692
Test name
Test status
Simulation time 55107093810 ps
CPU time 306.53 seconds
Started Mar 24 01:20:01 PM PDT 24
Finished Mar 24 01:25:08 PM PDT 24
Peak memory 202120 kb
Host smart-90b909e6-8f32-43f7-9e2e-b750fbeb68a2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744135871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.1744135871
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.187178725
Short name T190
Test name
Test status
Simulation time 78342332 ps
CPU time 0.78 seconds
Started Mar 24 01:20:01 PM PDT 24
Finished Mar 24 01:20:02 PM PDT 24
Peak memory 202148 kb
Host smart-8e2c139f-f448-4741-824f-9deafdb3f9f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187178725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.187178725
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.4095180339
Short name T427
Test name
Test status
Simulation time 70352556035 ps
CPU time 1360.93 seconds
Started Mar 24 01:20:08 PM PDT 24
Finished Mar 24 01:42:49 PM PDT 24
Peak memory 369872 kb
Host smart-03d9a793-3f0b-4645-821c-4830e0706a54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095180339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.4095180339
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.1532516589
Short name T275
Test name
Test status
Simulation time 963104228 ps
CPU time 17.86 seconds
Started Mar 24 01:19:56 PM PDT 24
Finished Mar 24 01:20:14 PM PDT 24
Peak memory 255344 kb
Host smart-2ae68a05-1d63-4734-bec4-8b5ca3f7ddb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532516589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1532516589
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.3890997333
Short name T879
Test name
Test status
Simulation time 267246505280 ps
CPU time 3472.51 seconds
Started Mar 24 01:20:00 PM PDT 24
Finished Mar 24 02:17:53 PM PDT 24
Peak memory 373748 kb
Host smart-601dc44a-a890-4983-b72a-bd50212eff6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890997333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.3890997333
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3289942621
Short name T43
Test name
Test status
Simulation time 1025218215 ps
CPU time 49.73 seconds
Started Mar 24 01:20:07 PM PDT 24
Finished Mar 24 01:20:57 PM PDT 24
Peak memory 298152 kb
Host smart-8b1fd530-8611-410d-b266-173f54b864eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3289942621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3289942621
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1272537702
Short name T230
Test name
Test status
Simulation time 2495223042 ps
CPU time 230.92 seconds
Started Mar 24 01:20:01 PM PDT 24
Finished Mar 24 01:23:53 PM PDT 24
Peak memory 202064 kb
Host smart-6b321772-b696-4ede-a56e-f94e4cc60420
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272537702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.1272537702
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1176612286
Short name T669
Test name
Test status
Simulation time 185067488 ps
CPU time 108.04 seconds
Started Mar 24 01:20:00 PM PDT 24
Finished Mar 24 01:21:49 PM PDT 24
Peak memory 365508 kb
Host smart-632a7b44-59fe-4efa-843f-dfae65a280bd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176612286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1176612286
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2235888127
Short name T627
Test name
Test status
Simulation time 24977210513 ps
CPU time 943.05 seconds
Started Mar 24 01:17:14 PM PDT 24
Finished Mar 24 01:32:57 PM PDT 24
Peak memory 369680 kb
Host smart-4bc0c2ee-2910-48f2-b181-c80221177dc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235888127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.2235888127
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.3262336145
Short name T612
Test name
Test status
Simulation time 22115011 ps
CPU time 0.65 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:27 PM PDT 24
Peak memory 200972 kb
Host smart-c4a398bb-8d72-4978-9d22-71cf19448660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262336145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.3262336145
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.3524745269
Short name T593
Test name
Test status
Simulation time 11861709105 ps
CPU time 57 seconds
Started Mar 24 01:17:21 PM PDT 24
Finished Mar 24 01:18:19 PM PDT 24
Peak memory 202012 kb
Host smart-52a52513-5858-42a2-9eff-f6f0fe7ab164
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524745269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
3524745269
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.2751680867
Short name T724
Test name
Test status
Simulation time 7840194372 ps
CPU time 1151.46 seconds
Started Mar 24 01:17:17 PM PDT 24
Finished Mar 24 01:36:29 PM PDT 24
Peak memory 370896 kb
Host smart-0449d21a-1f21-4594-ac67-04be5d2278b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751680867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.2751680867
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.3358611622
Short name T344
Test name
Test status
Simulation time 723187492 ps
CPU time 5.39 seconds
Started Mar 24 01:17:21 PM PDT 24
Finished Mar 24 01:17:27 PM PDT 24
Peak memory 202120 kb
Host smart-e302f67a-4e91-4f75-a718-4d93c73322b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358611622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.3358611622
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.2454285820
Short name T164
Test name
Test status
Simulation time 242696254 ps
CPU time 10.64 seconds
Started Mar 24 01:17:21 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 251004 kb
Host smart-a8d89da3-a286-4e31-bcac-9ffd6d48dbb1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454285820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.2454285820
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1315878924
Short name T638
Test name
Test status
Simulation time 97233280 ps
CPU time 3 seconds
Started Mar 24 01:17:20 PM PDT 24
Finished Mar 24 01:17:24 PM PDT 24
Peak memory 210148 kb
Host smart-854fa56b-d445-4851-a50d-4e8c55246a92
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315878924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.1315878924
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.362011139
Short name T317
Test name
Test status
Simulation time 356045519 ps
CPU time 5.27 seconds
Started Mar 24 01:17:15 PM PDT 24
Finished Mar 24 01:17:20 PM PDT 24
Peak memory 201936 kb
Host smart-b5bcc054-27b9-49c8-8845-ea1395ceecbe
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362011139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_
mem_walk.362011139
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.1012028157
Short name T513
Test name
Test status
Simulation time 977831270 ps
CPU time 82.88 seconds
Started Mar 24 01:17:19 PM PDT 24
Finished Mar 24 01:18:42 PM PDT 24
Peak memory 358160 kb
Host smart-502399d5-85bb-46b8-9831-c41137cd66bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012028157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.1012028157
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.1198960950
Short name T145
Test name
Test status
Simulation time 2071948639 ps
CPU time 54.89 seconds
Started Mar 24 01:17:12 PM PDT 24
Finished Mar 24 01:18:07 PM PDT 24
Peak memory 314220 kb
Host smart-a8e32975-3074-4024-982d-6f19f9c25508
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198960950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.1198960950
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4237332024
Short name T38
Test name
Test status
Simulation time 15819229017 ps
CPU time 319.8 seconds
Started Mar 24 01:17:22 PM PDT 24
Finished Mar 24 01:22:42 PM PDT 24
Peak memory 202056 kb
Host smart-bbd4ab78-a617-43c9-bd49-2d6d3ba7574d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237332024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.4237332024
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.3179314795
Short name T922
Test name
Test status
Simulation time 53524298 ps
CPU time 0.89 seconds
Started Mar 24 01:17:08 PM PDT 24
Finished Mar 24 01:17:09 PM PDT 24
Peak memory 202084 kb
Host smart-dd9c910e-afd1-4d10-9235-1aabef93159e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179314795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3179314795
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.945324736
Short name T147
Test name
Test status
Simulation time 12919187566 ps
CPU time 962.01 seconds
Started Mar 24 01:17:17 PM PDT 24
Finished Mar 24 01:33:19 PM PDT 24
Peak memory 373320 kb
Host smart-170d030f-983b-4aac-90d6-1c74b41ac76b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945324736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.945324736
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.484766576
Short name T336
Test name
Test status
Simulation time 1451086949 ps
CPU time 12.59 seconds
Started Mar 24 01:17:13 PM PDT 24
Finished Mar 24 01:17:26 PM PDT 24
Peak memory 202000 kb
Host smart-d1927fc9-ff73-43fa-957d-7c4945f7a6aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484766576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.484766576
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.3513746968
Short name T934
Test name
Test status
Simulation time 111571276893 ps
CPU time 3209.46 seconds
Started Mar 24 01:17:13 PM PDT 24
Finished Mar 24 02:10:43 PM PDT 24
Peak memory 377912 kb
Host smart-e230887c-741b-4381-9f04-fe601e9946fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513746968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.3513746968
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4242010977
Short name T550
Test name
Test status
Simulation time 903250439 ps
CPU time 61.18 seconds
Started Mar 24 01:17:18 PM PDT 24
Finished Mar 24 01:18:20 PM PDT 24
Peak memory 308008 kb
Host smart-9df952eb-3583-4fa2-82ea-b90b66768b0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4242010977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.4242010977
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2823989394
Short name T377
Test name
Test status
Simulation time 2681554962 ps
CPU time 258.37 seconds
Started Mar 24 01:17:15 PM PDT 24
Finished Mar 24 01:21:33 PM PDT 24
Peak memory 202044 kb
Host smart-1e4ce0d6-ab7b-4001-a89a-4fa8cbae0567
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823989394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.2823989394
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3342580104
Short name T560
Test name
Test status
Simulation time 615281314 ps
CPU time 104.05 seconds
Started Mar 24 01:17:22 PM PDT 24
Finished Mar 24 01:19:07 PM PDT 24
Peak memory 365568 kb
Host smart-0bdc8bee-09ff-4ebb-a515-e88c5d5cbc3a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342580104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.3342580104
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2280457730
Short name T293
Test name
Test status
Simulation time 1019721580 ps
CPU time 196.06 seconds
Started Mar 24 01:17:16 PM PDT 24
Finished Mar 24 01:20:32 PM PDT 24
Peak memory 366984 kb
Host smart-f2ed1f30-26fd-4f9a-b20a-5b4f83d5e455
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280457730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.2280457730
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.1502905752
Short name T580
Test name
Test status
Simulation time 18780797 ps
CPU time 0.63 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:26 PM PDT 24
Peak memory 201172 kb
Host smart-28daaaa2-5599-4934-9c64-c543f3e18551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502905752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.1502905752
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.2540512098
Short name T659
Test name
Test status
Simulation time 3342300195 ps
CPU time 67.61 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:18:31 PM PDT 24
Peak memory 202092 kb
Host smart-c6f443e3-37c2-4235-ba8c-db47ab1b383a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540512098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
2540512098
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.3177151540
Short name T637
Test name
Test status
Simulation time 72051400027 ps
CPU time 709.58 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:29:15 PM PDT 24
Peak memory 340144 kb
Host smart-a29b3000-e5ee-4c7e-bad9-b15f7d88f69b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177151540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.3177151540
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.3625040175
Short name T505
Test name
Test status
Simulation time 600928741 ps
CPU time 7.39 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:17:30 PM PDT 24
Peak memory 202060 kb
Host smart-41643356-d5ec-4c1c-907d-0dbb73481d68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625040175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.3625040175
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.1384588708
Short name T407
Test name
Test status
Simulation time 133353832 ps
CPU time 104.34 seconds
Started Mar 24 01:17:19 PM PDT 24
Finished Mar 24 01:19:04 PM PDT 24
Peak memory 362528 kb
Host smart-13e1b3b7-315e-4f53-82c5-73767d59cb76
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384588708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.1384588708
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2792430249
Short name T594
Test name
Test status
Simulation time 604827740 ps
CPU time 4.98 seconds
Started Mar 24 01:17:20 PM PDT 24
Finished Mar 24 01:17:26 PM PDT 24
Peak memory 210160 kb
Host smart-1fac1e8b-ba8e-489a-b808-83484bf46920
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792430249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.2792430249
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3914099316
Short name T863
Test name
Test status
Simulation time 1855917224 ps
CPU time 5.12 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:17:28 PM PDT 24
Peak memory 201912 kb
Host smart-e600587b-9f65-4b6e-8fff-d8131b5fdb4d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914099316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3914099316
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.815612857
Short name T214
Test name
Test status
Simulation time 11495618042 ps
CPU time 468.39 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:25:13 PM PDT 24
Peak memory 371148 kb
Host smart-dde88ace-65b9-4df8-bbf7-e779e1ef2f8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815612857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multipl
e_keys.815612857
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.1932604357
Short name T225
Test name
Test status
Simulation time 219257915 ps
CPU time 10.92 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 201980 kb
Host smart-d97066cd-3630-486d-928d-7cdaaa4d2d12
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932604357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.1932604357
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.942944159
Short name T328
Test name
Test status
Simulation time 22527566695 ps
CPU time 485.85 seconds
Started Mar 24 01:17:22 PM PDT 24
Finished Mar 24 01:25:29 PM PDT 24
Peak memory 202076 kb
Host smart-a5191bab-8cf1-4eb4-b27d-f989c36390b3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942944159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.sram_ctrl_partial_access_b2b.942944159
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.2621756557
Short name T680
Test name
Test status
Simulation time 36026936 ps
CPU time 0.77 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:17:24 PM PDT 24
Peak memory 202172 kb
Host smart-6a46b0a1-9af1-489a-b81f-3b5bf3d6f1a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621756557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2621756557
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.3204677600
Short name T501
Test name
Test status
Simulation time 14248149689 ps
CPU time 815.2 seconds
Started Mar 24 01:17:22 PM PDT 24
Finished Mar 24 01:30:57 PM PDT 24
Peak memory 373764 kb
Host smart-961b1e0c-93ef-4928-a002-d7cf06f1296c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204677600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3204677600
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.3159466262
Short name T587
Test name
Test status
Simulation time 130255348 ps
CPU time 1.01 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:17:24 PM PDT 24
Peak memory 201852 kb
Host smart-e5a05ca7-bc06-448c-b3ea-f0e3630a3536
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159466262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3159466262
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.4279978364
Short name T606
Test name
Test status
Simulation time 100452139999 ps
CPU time 3173.28 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 02:10:19 PM PDT 24
Peak memory 372580 kb
Host smart-67f1fc02-b859-4340-b368-ca8c97ba25fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279978364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.4279978364
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.675663442
Short name T113
Test name
Test status
Simulation time 4571154838 ps
CPU time 105.25 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:19:08 PM PDT 24
Peak memory 345304 kb
Host smart-cfd5d84a-114b-4b0d-a94a-8ae46b2b7212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=675663442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.675663442
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.1010894690
Short name T16
Test name
Test status
Simulation time 11634956074 ps
CPU time 147.9 seconds
Started Mar 24 01:17:21 PM PDT 24
Finished Mar 24 01:19:49 PM PDT 24
Peak memory 202048 kb
Host smart-7549b540-714a-4cf5-b7f5-f9e2fc1244a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010894690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.1010894690
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1495810507
Short name T484
Test name
Test status
Simulation time 277116204 ps
CPU time 92.04 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:18:56 PM PDT 24
Peak memory 342100 kb
Host smart-ac541b24-1c72-433d-8179-03bd2a4ed4ec
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495810507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.1495810507
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3264033101
Short name T467
Test name
Test status
Simulation time 12674782304 ps
CPU time 617.14 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:27:42 PM PDT 24
Peak memory 371716 kb
Host smart-5f1f7bcc-710a-4be6-a396-fa4413ce7b7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264033101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.3264033101
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.509750738
Short name T374
Test name
Test status
Simulation time 36057213 ps
CPU time 0.65 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:26 PM PDT 24
Peak memory 200992 kb
Host smart-38e7820b-f4ff-4519-a199-66c18ea0130f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509750738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.509750738
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.4042557046
Short name T754
Test name
Test status
Simulation time 2946264076 ps
CPU time 48.58 seconds
Started Mar 24 01:17:20 PM PDT 24
Finished Mar 24 01:18:09 PM PDT 24
Peak memory 202116 kb
Host smart-d357f8f3-1b18-4b68-aec9-d83c03455bef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042557046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
4042557046
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.788757992
Short name T411
Test name
Test status
Simulation time 2064031123 ps
CPU time 560.13 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:26:46 PM PDT 24
Peak memory 368336 kb
Host smart-2f0695d0-22de-4184-9b18-f3678878375a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788757992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable
.788757992
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.2774731220
Short name T801
Test name
Test status
Simulation time 1536145772 ps
CPU time 3.68 seconds
Started Mar 24 01:17:20 PM PDT 24
Finished Mar 24 01:17:24 PM PDT 24
Peak memory 202016 kb
Host smart-a9844da0-1588-4bef-9042-fb136a67f915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774731220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.2774731220
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.1564188907
Short name T236
Test name
Test status
Simulation time 43563494 ps
CPU time 1.87 seconds
Started Mar 24 01:17:21 PM PDT 24
Finished Mar 24 01:17:23 PM PDT 24
Peak memory 210232 kb
Host smart-095e413d-2747-466d-8319-55a004e6f5c3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564188907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.1564188907
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3711879876
Short name T877
Test name
Test status
Simulation time 941281594 ps
CPU time 5.51 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 210232 kb
Host smart-b7c912cb-b6c7-4378-ab9c-ce5a6b8ddbe2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711879876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.3711879876
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.53727965
Short name T588
Test name
Test status
Simulation time 488690725 ps
CPU time 8.99 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:17:33 PM PDT 24
Peak memory 201876 kb
Host smart-ead8950a-a8de-40dc-a38f-9259687257eb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53727965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_m
em_walk.53727965
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.443707442
Short name T381
Test name
Test status
Simulation time 34893683007 ps
CPU time 557.09 seconds
Started Mar 24 01:17:22 PM PDT 24
Finished Mar 24 01:26:40 PM PDT 24
Peak memory 348596 kb
Host smart-e04cd57e-f033-431c-90c7-dd787a433317
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443707442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multipl
e_keys.443707442
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.4209379786
Short name T880
Test name
Test status
Simulation time 444373701 ps
CPU time 19.48 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:17:43 PM PDT 24
Peak memory 271096 kb
Host smart-3059c772-988a-46b1-9e57-bdeecf5704e8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209379786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.4209379786
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.179068518
Short name T939
Test name
Test status
Simulation time 16608871875 ps
CPU time 320.3 seconds
Started Mar 24 01:17:21 PM PDT 24
Finished Mar 24 01:22:42 PM PDT 24
Peak memory 202000 kb
Host smart-200a79b8-7ea2-4c67-8e48-c131295bdc43
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179068518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.sram_ctrl_partial_access_b2b.179068518
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.1342776606
Short name T937
Test name
Test status
Simulation time 42704692 ps
CPU time 0.74 seconds
Started Mar 24 01:17:22 PM PDT 24
Finished Mar 24 01:17:23 PM PDT 24
Peak memory 202100 kb
Host smart-e3ccad5c-b424-4b6c-a91c-a06168764fac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342776606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1342776606
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.1975378396
Short name T751
Test name
Test status
Simulation time 20205963103 ps
CPU time 402.5 seconds
Started Mar 24 01:17:22 PM PDT 24
Finished Mar 24 01:24:05 PM PDT 24
Peak memory 356520 kb
Host smart-88138406-06da-422a-b305-c5c7e33796ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975378396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1975378396
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.911004747
Short name T779
Test name
Test status
Simulation time 235193347 ps
CPU time 11.91 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:17:35 PM PDT 24
Peak memory 202072 kb
Host smart-3829ffc9-6953-4b03-9662-8f62cf6f2d26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911004747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.911004747
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.2470059406
Short name T392
Test name
Test status
Simulation time 43922747003 ps
CPU time 3161.54 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 02:10:05 PM PDT 24
Peak memory 375524 kb
Host smart-728ef9ee-55b1-4259-9f16-7731608e7d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470059406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.2470059406
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1624124549
Short name T337
Test name
Test status
Simulation time 8290742864 ps
CPU time 201.82 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:20:47 PM PDT 24
Peak memory 202028 kb
Host smart-c38a9ded-f968-4d6d-9f70-8580edb99d11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624124549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.1624124549
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4231717369
Short name T418
Test name
Test status
Simulation time 155471559 ps
CPU time 66.66 seconds
Started Mar 24 01:17:20 PM PDT 24
Finished Mar 24 01:18:27 PM PDT 24
Peak memory 343112 kb
Host smart-d8ee13df-cc6b-4ef0-9153-11a5bbb02920
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231717369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.4231717369
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2495915275
Short name T624
Test name
Test status
Simulation time 16049196947 ps
CPU time 501.73 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:25:48 PM PDT 24
Peak memory 368484 kb
Host smart-5b14007f-30d2-43c1-9de9-dff3b0f67e5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495915275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.2495915275
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.1495222835
Short name T193
Test name
Test status
Simulation time 64161108 ps
CPU time 0.69 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:26 PM PDT 24
Peak memory 200956 kb
Host smart-241437bd-ca9d-4cb8-a1e1-93a258b95fbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495222835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.1495222835
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.821631611
Short name T253
Test name
Test status
Simulation time 2501997766 ps
CPU time 60.39 seconds
Started Mar 24 01:17:20 PM PDT 24
Finished Mar 24 01:18:21 PM PDT 24
Peak memory 202016 kb
Host smart-289ec2a5-900a-443a-b1d2-6e78039752d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821631611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.821631611
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.2864918254
Short name T736
Test name
Test status
Simulation time 55903207987 ps
CPU time 170.82 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:20:16 PM PDT 24
Peak memory 338924 kb
Host smart-8d19feb3-23a0-49ae-8f6a-a33178c18384
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864918254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.2864918254
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.2672291710
Short name T928
Test name
Test status
Simulation time 2802582239 ps
CPU time 10.54 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:17:33 PM PDT 24
Peak memory 202180 kb
Host smart-21458e6a-6799-4358-9a17-6e98a2aa6985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672291710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.2672291710
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.2396897803
Short name T870
Test name
Test status
Simulation time 210226484 ps
CPU time 2.31 seconds
Started Mar 24 01:17:21 PM PDT 24
Finished Mar 24 01:17:24 PM PDT 24
Peak memory 216964 kb
Host smart-84c940b9-1f00-4e65-9075-8a2bdfc3b91f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396897803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.2396897803
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2766127951
Short name T309
Test name
Test status
Simulation time 65389236 ps
CPU time 4.39 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:30 PM PDT 24
Peak memory 210188 kb
Host smart-966f40e1-c9e8-46e7-9364-c81884f9e821
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766127951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.2766127951
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.1686887665
Short name T897
Test name
Test status
Simulation time 1055683641 ps
CPU time 9.46 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:35 PM PDT 24
Peak memory 201972 kb
Host smart-9a97e1f7-662b-4eb1-9d2d-6b65ff0c78a6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686887665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.1686887665
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.24708385
Short name T676
Test name
Test status
Simulation time 15547796705 ps
CPU time 1418.48 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:41:02 PM PDT 24
Peak memory 368768 kb
Host smart-5a98d85d-cb8a-4695-bae5-462387979739
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24708385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple
_keys.24708385
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.3654075590
Short name T865
Test name
Test status
Simulation time 124512244 ps
CPU time 22.86 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:48 PM PDT 24
Peak memory 275960 kb
Host smart-23d7a22f-45c3-414c-a1b4-204b2e8255ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654075590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.3654075590
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3477354628
Short name T393
Test name
Test status
Simulation time 11172195062 ps
CPU time 292.15 seconds
Started Mar 24 01:17:22 PM PDT 24
Finished Mar 24 01:22:15 PM PDT 24
Peak memory 201988 kb
Host smart-beba0d33-f41a-452d-a326-9edc1935b3ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477354628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.3477354628
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.3405368181
Short name T33
Test name
Test status
Simulation time 76119478 ps
CPU time 0.75 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:17:28 PM PDT 24
Peak memory 202144 kb
Host smart-8a46b741-d1c2-41f2-9b18-1be977614757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405368181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3405368181
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.1622762700
Short name T851
Test name
Test status
Simulation time 10651059415 ps
CPU time 879.58 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:32:05 PM PDT 24
Peak memory 368704 kb
Host smart-94927d20-bc22-4cb3-9dcd-9360d5425de4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622762700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1622762700
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.3998884773
Short name T670
Test name
Test status
Simulation time 285658342 ps
CPU time 96.9 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:19:04 PM PDT 24
Peak memory 357384 kb
Host smart-5af7649f-3444-4158-bebf-f4b2ea775480
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998884773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3998884773
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.765609545
Short name T535
Test name
Test status
Simulation time 29547123801 ps
CPU time 2749.93 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 02:03:17 PM PDT 24
Peak memory 372948 kb
Host smart-9b340915-d752-4739-b0ff-f07426a72381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765609545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_stress_all.765609545
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2973528918
Short name T44
Test name
Test status
Simulation time 1235675256 ps
CPU time 19.72 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:47 PM PDT 24
Peak memory 210392 kb
Host smart-0f907e04-ea37-4a53-a708-73802d88b0f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2973528918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2973528918
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1202677515
Short name T397
Test name
Test status
Simulation time 6538535365 ps
CPU time 148.47 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:19:54 PM PDT 24
Peak memory 202104 kb
Host smart-605db8c2-52a5-4d43-bc80-77cba2e185f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202677515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.1202677515
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3409211253
Short name T195
Test name
Test status
Simulation time 385997787 ps
CPU time 29.6 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:17:53 PM PDT 24
Peak memory 284676 kb
Host smart-ed654d67-98bb-435c-af16-90bad7680128
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409211253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.3409211253
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3357539186
Short name T202
Test name
Test status
Simulation time 488951214 ps
CPU time 42.66 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:18:08 PM PDT 24
Peak memory 265072 kb
Host smart-0b0d67db-f580-419a-9deb-6967c5ff9a07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357539186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.3357539186
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.4023988649
Short name T199
Test name
Test status
Simulation time 13908688 ps
CPU time 0.65 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:26 PM PDT 24
Peak memory 201040 kb
Host smart-b79f562e-be0d-454a-8e07-0ef8ecbf3579
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023988649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.4023988649
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.111749912
Short name T521
Test name
Test status
Simulation time 19881124841 ps
CPU time 72.76 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:18:39 PM PDT 24
Peak memory 202088 kb
Host smart-3a739cd2-25d7-4ca6-bf4e-8ecf49ef5f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111749912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.111749912
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.1794033527
Short name T906
Test name
Test status
Simulation time 524670168 ps
CPU time 272.6 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:21:58 PM PDT 24
Peak memory 372156 kb
Host smart-1bcba50d-f67c-4af1-94fc-6aafe043ea99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794033527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.1794033527
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.1497624121
Short name T741
Test name
Test status
Simulation time 2041154883 ps
CPU time 6.29 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 202036 kb
Host smart-02a65de2-ef73-478a-9352-0f811636c978
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497624121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.1497624121
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.2139986122
Short name T917
Test name
Test status
Simulation time 134713986 ps
CPU time 153.89 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:20:00 PM PDT 24
Peak memory 368488 kb
Host smart-3a1e70fb-3164-4b88-b49c-f103b5699026
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139986122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.2139986122
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.329536893
Short name T480
Test name
Test status
Simulation time 132465118 ps
CPU time 4.37 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:30 PM PDT 24
Peak memory 210232 kb
Host smart-7004dd73-ed01-4673-b6eb-6ff78899d742
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329536893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_mem_partial_access.329536893
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.3104008199
Short name T55
Test name
Test status
Simulation time 530368996 ps
CPU time 8.83 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:34 PM PDT 24
Peak memory 201944 kb
Host smart-7ce1f553-921f-4a54-828f-3ba1b90a5ae2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104008199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.3104008199
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.2758099367
Short name T902
Test name
Test status
Simulation time 5959339936 ps
CPU time 639.7 seconds
Started Mar 24 01:17:24 PM PDT 24
Finished Mar 24 01:28:04 PM PDT 24
Peak memory 355864 kb
Host smart-99229c51-615d-4dcc-8c11-96b40ddb77e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758099367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.2758099367
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.3240164061
Short name T3
Test name
Test status
Simulation time 700553427 ps
CPU time 28.57 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:55 PM PDT 24
Peak memory 270804 kb
Host smart-548d3203-ba50-4a10-83a5-df0dd973f31b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240164061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.3240164061
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3048439458
Short name T852
Test name
Test status
Simulation time 1576475879 ps
CPU time 110.21 seconds
Started Mar 24 01:17:23 PM PDT 24
Finished Mar 24 01:19:14 PM PDT 24
Peak memory 201984 kb
Host smart-f9506861-fe13-4a9e-8184-a198aa97146f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048439458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.3048439458
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.96569249
Short name T518
Test name
Test status
Simulation time 135764713 ps
CPU time 0.76 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:17:26 PM PDT 24
Peak memory 202136 kb
Host smart-76751dda-edcf-4c62-b2d8-e829461ed12e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96569249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.96569249
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.2590933211
Short name T335
Test name
Test status
Simulation time 47810458982 ps
CPU time 802.24 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 01:30:49 PM PDT 24
Peak memory 372880 kb
Host smart-487b81b7-47a8-493b-86b1-ea041b4dc741
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590933211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2590933211
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.1009547349
Short name T182
Test name
Test status
Simulation time 155603948 ps
CPU time 3.06 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:29 PM PDT 24
Peak memory 210108 kb
Host smart-6f16317b-1495-4dc4-9c2d-5f111b2ba5d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009547349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1009547349
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.1667691486
Short name T148
Test name
Test status
Simulation time 37989267838 ps
CPU time 3246.4 seconds
Started Mar 24 01:17:27 PM PDT 24
Finished Mar 24 02:11:34 PM PDT 24
Peak memory 381956 kb
Host smart-19f6948c-83df-4899-94f6-e9edc18f9531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667691486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.1667691486
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.477161690
Short name T903
Test name
Test status
Simulation time 1057094739 ps
CPU time 9.62 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 213112 kb
Host smart-1c850855-ad67-4137-9b1f-17f125420a68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=477161690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.477161690
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.681983055
Short name T98
Test name
Test status
Simulation time 11899205421 ps
CPU time 279.53 seconds
Started Mar 24 01:17:26 PM PDT 24
Finished Mar 24 01:22:06 PM PDT 24
Peak memory 202108 kb
Host smart-e97aff86-62ae-407d-a015-754c07e662f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681983055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_stress_pipeline.681983055
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2108912174
Short name T864
Test name
Test status
Simulation time 1027665843 ps
CPU time 145.99 seconds
Started Mar 24 01:17:25 PM PDT 24
Finished Mar 24 01:19:52 PM PDT 24
Peak memory 365412 kb
Host smart-d791d9a8-b12b-4739-b157-c9a0539e9645
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108912174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2108912174
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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