| T795 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1186799366 |
|
|
Mar 28 03:09:01 PM PDT 24 |
Mar 28 03:21:36 PM PDT 24 |
8058879969 ps |
| T796 |
/workspace/coverage/default/47.sram_ctrl_stress_all.2486938225 |
|
|
Mar 28 03:13:45 PM PDT 24 |
Mar 28 04:33:29 PM PDT 24 |
13939649963 ps |
| T797 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1938938110 |
|
|
Mar 28 03:08:05 PM PDT 24 |
Mar 28 03:10:40 PM PDT 24 |
3288794682 ps |
| T798 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3718556932 |
|
|
Mar 28 03:13:20 PM PDT 24 |
Mar 28 03:13:33 PM PDT 24 |
620277772 ps |
| T799 |
/workspace/coverage/default/1.sram_ctrl_stress_all.3440980435 |
|
|
Mar 28 03:07:46 PM PDT 24 |
Mar 28 03:38:49 PM PDT 24 |
39192410460 ps |
| T800 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.986121626 |
|
|
Mar 28 03:11:23 PM PDT 24 |
Mar 28 03:14:41 PM PDT 24 |
2885999816 ps |
| T801 |
/workspace/coverage/default/36.sram_ctrl_regwen.2875282922 |
|
|
Mar 28 03:11:59 PM PDT 24 |
Mar 28 03:29:50 PM PDT 24 |
46209266947 ps |
| T802 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.3278970949 |
|
|
Mar 28 03:11:59 PM PDT 24 |
Mar 28 03:20:04 PM PDT 24 |
37153488351 ps |
| T803 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.226496339 |
|
|
Mar 28 03:09:03 PM PDT 24 |
Mar 28 03:11:38 PM PDT 24 |
272992384 ps |
| T804 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3019536449 |
|
|
Mar 28 03:09:34 PM PDT 24 |
Mar 28 03:13:33 PM PDT 24 |
58636413289 ps |
| T805 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3538050292 |
|
|
Mar 28 03:08:14 PM PDT 24 |
Mar 28 03:08:15 PM PDT 24 |
128734920 ps |
| T806 |
/workspace/coverage/default/48.sram_ctrl_executable.2500118315 |
|
|
Mar 28 03:13:45 PM PDT 24 |
Mar 28 03:29:52 PM PDT 24 |
5246439449 ps |
| T807 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2020650271 |
|
|
Mar 28 03:13:43 PM PDT 24 |
Mar 28 03:31:42 PM PDT 24 |
24630078361 ps |
| T808 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3921980526 |
|
|
Mar 28 03:11:18 PM PDT 24 |
Mar 28 04:44:47 PM PDT 24 |
77117883275 ps |
| T809 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.628124857 |
|
|
Mar 28 03:08:05 PM PDT 24 |
Mar 28 03:10:00 PM PDT 24 |
290991214 ps |
| T810 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1666673016 |
|
|
Mar 28 03:12:38 PM PDT 24 |
Mar 28 03:12:46 PM PDT 24 |
170623964 ps |
| T34 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.3107550458 |
|
|
Mar 28 03:07:52 PM PDT 24 |
Mar 28 03:07:56 PM PDT 24 |
383182916 ps |
| T811 |
/workspace/coverage/default/36.sram_ctrl_alert_test.277841419 |
|
|
Mar 28 03:12:02 PM PDT 24 |
Mar 28 03:12:03 PM PDT 24 |
45980136 ps |
| T812 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2433481630 |
|
|
Mar 28 03:09:33 PM PDT 24 |
Mar 28 03:09:38 PM PDT 24 |
66858832 ps |
| T813 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3773049760 |
|
|
Mar 28 03:08:16 PM PDT 24 |
Mar 28 03:09:10 PM PDT 24 |
119821729 ps |
| T814 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1848667537 |
|
|
Mar 28 03:12:02 PM PDT 24 |
Mar 28 03:14:19 PM PDT 24 |
796401606 ps |
| T815 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1326998543 |
|
|
Mar 28 03:08:11 PM PDT 24 |
Mar 28 03:08:18 PM PDT 24 |
1566083747 ps |
| T816 |
/workspace/coverage/default/8.sram_ctrl_smoke.2972902759 |
|
|
Mar 28 03:08:05 PM PDT 24 |
Mar 28 03:10:26 PM PDT 24 |
2943196468 ps |
| T817 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2791730161 |
|
|
Mar 28 03:13:23 PM PDT 24 |
Mar 28 03:16:19 PM PDT 24 |
7300682051 ps |
| T818 |
/workspace/coverage/default/42.sram_ctrl_regwen.4155891384 |
|
|
Mar 28 03:12:56 PM PDT 24 |
Mar 28 03:29:31 PM PDT 24 |
18285530975 ps |
| T819 |
/workspace/coverage/default/5.sram_ctrl_executable.2092131012 |
|
|
Mar 28 03:08:06 PM PDT 24 |
Mar 28 03:10:40 PM PDT 24 |
4467793707 ps |
| T820 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.965249945 |
|
|
Mar 28 03:10:47 PM PDT 24 |
Mar 28 03:10:49 PM PDT 24 |
65874795 ps |
| T821 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2215926523 |
|
|
Mar 28 03:11:03 PM PDT 24 |
Mar 28 03:11:15 PM PDT 24 |
245510798 ps |
| T822 |
/workspace/coverage/default/38.sram_ctrl_bijection.663143508 |
|
|
Mar 28 03:12:21 PM PDT 24 |
Mar 28 03:13:03 PM PDT 24 |
1347572617 ps |
| T823 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3903270490 |
|
|
Mar 28 03:07:50 PM PDT 24 |
Mar 28 03:12:35 PM PDT 24 |
10237663943 ps |
| T824 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2698705968 |
|
|
Mar 28 03:11:19 PM PDT 24 |
Mar 28 03:17:19 PM PDT 24 |
4948401470 ps |
| T825 |
/workspace/coverage/default/35.sram_ctrl_smoke.172505837 |
|
|
Mar 28 03:11:39 PM PDT 24 |
Mar 28 03:11:41 PM PDT 24 |
52918191 ps |
| T826 |
/workspace/coverage/default/40.sram_ctrl_stress_all.817923776 |
|
|
Mar 28 03:12:37 PM PDT 24 |
Mar 28 03:49:35 PM PDT 24 |
101920334023 ps |
| T827 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1718891596 |
|
|
Mar 28 03:12:20 PM PDT 24 |
Mar 28 03:18:59 PM PDT 24 |
16747646457 ps |
| T828 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2103785492 |
|
|
Mar 28 03:09:57 PM PDT 24 |
Mar 28 03:13:58 PM PDT 24 |
3220037471 ps |
| T829 |
/workspace/coverage/default/27.sram_ctrl_smoke.117008403 |
|
|
Mar 28 03:10:31 PM PDT 24 |
Mar 28 03:10:43 PM PDT 24 |
2357504875 ps |
| T830 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3683438127 |
|
|
Mar 28 03:10:05 PM PDT 24 |
Mar 28 03:13:54 PM PDT 24 |
1644223934 ps |
| T831 |
/workspace/coverage/default/17.sram_ctrl_stress_all.2443183096 |
|
|
Mar 28 03:09:18 PM PDT 24 |
Mar 28 03:53:02 PM PDT 24 |
52717764595 ps |
| T832 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2709883995 |
|
|
Mar 28 03:09:35 PM PDT 24 |
Mar 28 03:09:46 PM PDT 24 |
343127568 ps |
| T833 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2720964333 |
|
|
Mar 28 03:07:08 PM PDT 24 |
Mar 28 03:07:09 PM PDT 24 |
92824534 ps |
| T834 |
/workspace/coverage/default/10.sram_ctrl_partial_access.3208407432 |
|
|
Mar 28 03:08:13 PM PDT 24 |
Mar 28 03:10:12 PM PDT 24 |
227919055 ps |
| T835 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1706311752 |
|
|
Mar 28 03:10:48 PM PDT 24 |
Mar 28 03:15:39 PM PDT 24 |
10162533545 ps |
| T836 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.1022897423 |
|
|
Mar 28 03:09:20 PM PDT 24 |
Mar 28 03:09:22 PM PDT 24 |
65805539 ps |
| T837 |
/workspace/coverage/default/34.sram_ctrl_bijection.3516244781 |
|
|
Mar 28 03:11:39 PM PDT 24 |
Mar 28 03:11:54 PM PDT 24 |
681342613 ps |
| T838 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2631649250 |
|
|
Mar 28 03:13:21 PM PDT 24 |
Mar 28 03:32:45 PM PDT 24 |
3657385334 ps |
| T839 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1580015148 |
|
|
Mar 28 03:09:04 PM PDT 24 |
Mar 28 03:09:11 PM PDT 24 |
1630218619 ps |
| T840 |
/workspace/coverage/default/13.sram_ctrl_bijection.2855179026 |
|
|
Mar 28 03:09:04 PM PDT 24 |
Mar 28 03:10:03 PM PDT 24 |
3842675601 ps |
| T841 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3597005220 |
|
|
Mar 28 03:10:24 PM PDT 24 |
Mar 28 03:10:27 PM PDT 24 |
160008781 ps |
| T842 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.4047475623 |
|
|
Mar 28 03:09:05 PM PDT 24 |
Mar 28 03:09:10 PM PDT 24 |
234944130 ps |
| T843 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2940382250 |
|
|
Mar 28 03:13:21 PM PDT 24 |
Mar 28 03:16:11 PM PDT 24 |
2390382320 ps |
| T844 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1554316223 |
|
|
Mar 28 03:12:54 PM PDT 24 |
Mar 28 03:20:15 PM PDT 24 |
2333545861 ps |
| T845 |
/workspace/coverage/default/25.sram_ctrl_regwen.2493788687 |
|
|
Mar 28 03:10:25 PM PDT 24 |
Mar 28 03:29:01 PM PDT 24 |
3555716840 ps |
| T846 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2258964204 |
|
|
Mar 28 03:11:24 PM PDT 24 |
Mar 28 03:11:30 PM PDT 24 |
169983808 ps |
| T847 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.4078269704 |
|
|
Mar 28 03:13:46 PM PDT 24 |
Mar 28 03:17:15 PM PDT 24 |
2417855846 ps |
| T848 |
/workspace/coverage/default/30.sram_ctrl_executable.4037098036 |
|
|
Mar 28 03:11:09 PM PDT 24 |
Mar 28 03:25:04 PM PDT 24 |
3152929711 ps |
| T849 |
/workspace/coverage/default/33.sram_ctrl_alert_test.4218644192 |
|
|
Mar 28 03:11:38 PM PDT 24 |
Mar 28 03:11:38 PM PDT 24 |
37178028 ps |
| T850 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.3516220213 |
|
|
Mar 28 03:09:23 PM PDT 24 |
Mar 28 03:30:37 PM PDT 24 |
6131637240 ps |
| T851 |
/workspace/coverage/default/39.sram_ctrl_smoke.2269400551 |
|
|
Mar 28 03:12:20 PM PDT 24 |
Mar 28 03:12:36 PM PDT 24 |
2153477827 ps |
| T852 |
/workspace/coverage/default/37.sram_ctrl_smoke.3074830755 |
|
|
Mar 28 03:12:01 PM PDT 24 |
Mar 28 03:12:13 PM PDT 24 |
401723785 ps |
| T853 |
/workspace/coverage/default/18.sram_ctrl_alert_test.364716463 |
|
|
Mar 28 03:09:33 PM PDT 24 |
Mar 28 03:09:34 PM PDT 24 |
21352016 ps |
| T854 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1923716387 |
|
|
Mar 28 03:08:42 PM PDT 24 |
Mar 28 03:08:42 PM PDT 24 |
29782596 ps |
| T855 |
/workspace/coverage/default/7.sram_ctrl_partial_access.3424869891 |
|
|
Mar 28 03:08:07 PM PDT 24 |
Mar 28 03:08:44 PM PDT 24 |
282461802 ps |
| T856 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3869083185 |
|
|
Mar 28 03:08:06 PM PDT 24 |
Mar 28 03:09:59 PM PDT 24 |
2953090757 ps |
| T857 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3711482862 |
|
|
Mar 28 03:08:09 PM PDT 24 |
Mar 28 03:08:10 PM PDT 24 |
27453529 ps |
| T858 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1008227076 |
|
|
Mar 28 03:08:15 PM PDT 24 |
Mar 28 03:50:37 PM PDT 24 |
44993316551 ps |
| T859 |
/workspace/coverage/default/12.sram_ctrl_executable.2688231600 |
|
|
Mar 28 03:08:43 PM PDT 24 |
Mar 28 03:16:25 PM PDT 24 |
8756748340 ps |
| T860 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3987671253 |
|
|
Mar 28 03:07:48 PM PDT 24 |
Mar 28 03:13:17 PM PDT 24 |
4488611024 ps |
| T861 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2514184751 |
|
|
Mar 28 03:12:56 PM PDT 24 |
Mar 28 03:29:12 PM PDT 24 |
7833692149 ps |
| T862 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.4184852393 |
|
|
Mar 28 03:10:28 PM PDT 24 |
Mar 28 03:10:33 PM PDT 24 |
1197108474 ps |
| T863 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.58053740 |
|
|
Mar 28 03:09:21 PM PDT 24 |
Mar 28 03:09:24 PM PDT 24 |
688326791 ps |
| T864 |
/workspace/coverage/default/40.sram_ctrl_bijection.4082891632 |
|
|
Mar 28 03:12:17 PM PDT 24 |
Mar 28 03:12:47 PM PDT 24 |
1791918585 ps |
| T865 |
/workspace/coverage/default/28.sram_ctrl_regwen.981908872 |
|
|
Mar 28 03:10:46 PM PDT 24 |
Mar 28 03:32:51 PM PDT 24 |
29124924131 ps |
| T866 |
/workspace/coverage/default/5.sram_ctrl_bijection.1328381947 |
|
|
Mar 28 03:08:08 PM PDT 24 |
Mar 28 03:09:01 PM PDT 24 |
1760919453 ps |
| T867 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1514294145 |
|
|
Mar 28 03:11:09 PM PDT 24 |
Mar 28 03:16:10 PM PDT 24 |
9721646702 ps |
| T868 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1736412783 |
|
|
Mar 28 03:11:07 PM PDT 24 |
Mar 28 03:21:44 PM PDT 24 |
1553179126 ps |
| T869 |
/workspace/coverage/default/15.sram_ctrl_smoke.1690813316 |
|
|
Mar 28 03:09:02 PM PDT 24 |
Mar 28 03:09:35 PM PDT 24 |
177674055 ps |
| T870 |
/workspace/coverage/default/32.sram_ctrl_partial_access.4070194854 |
|
|
Mar 28 03:11:23 PM PDT 24 |
Mar 28 03:11:31 PM PDT 24 |
179436377 ps |
| T871 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4290162747 |
|
|
Mar 28 03:11:59 PM PDT 24 |
Mar 28 03:23:21 PM PDT 24 |
15230673281 ps |
| T872 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.1716699881 |
|
|
Mar 28 03:11:14 PM PDT 24 |
Mar 28 03:23:13 PM PDT 24 |
9063492082 ps |
| T873 |
/workspace/coverage/default/6.sram_ctrl_regwen.2413463721 |
|
|
Mar 28 03:08:04 PM PDT 24 |
Mar 28 03:28:46 PM PDT 24 |
2962036639 ps |
| T874 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2893924181 |
|
|
Mar 28 03:08:19 PM PDT 24 |
Mar 28 03:08:20 PM PDT 24 |
124679932 ps |
| T875 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3496241066 |
|
|
Mar 28 03:11:04 PM PDT 24 |
Mar 28 03:11:05 PM PDT 24 |
48024809 ps |
| T876 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3289142365 |
|
|
Mar 28 03:07:49 PM PDT 24 |
Mar 28 03:25:44 PM PDT 24 |
4103728081 ps |
| T877 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.2040081777 |
|
|
Mar 28 03:10:06 PM PDT 24 |
Mar 28 03:11:06 PM PDT 24 |
982257333 ps |
| T878 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3137637464 |
|
|
Mar 28 03:08:16 PM PDT 24 |
Mar 28 03:08:48 PM PDT 24 |
1599517604 ps |
| T879 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1141162386 |
|
|
Mar 28 03:07:08 PM PDT 24 |
Mar 28 03:07:20 PM PDT 24 |
132775756 ps |
| T880 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.4265211022 |
|
|
Mar 28 03:09:22 PM PDT 24 |
Mar 28 03:11:23 PM PDT 24 |
554343926 ps |
| T881 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3725556380 |
|
|
Mar 28 03:08:07 PM PDT 24 |
Mar 28 03:11:24 PM PDT 24 |
8398655420 ps |
| T882 |
/workspace/coverage/default/44.sram_ctrl_alert_test.2815914880 |
|
|
Mar 28 03:13:20 PM PDT 24 |
Mar 28 03:13:21 PM PDT 24 |
10448049 ps |
| T883 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.371652608 |
|
|
Mar 28 03:08:05 PM PDT 24 |
Mar 28 03:08:18 PM PDT 24 |
9318616434 ps |
| T884 |
/workspace/coverage/default/1.sram_ctrl_partial_access.862557830 |
|
|
Mar 28 03:07:07 PM PDT 24 |
Mar 28 03:07:25 PM PDT 24 |
326488739 ps |
| T885 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.2851964330 |
|
|
Mar 28 03:09:53 PM PDT 24 |
Mar 28 03:10:23 PM PDT 24 |
332424419 ps |
| T886 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1902475640 |
|
|
Mar 28 03:10:06 PM PDT 24 |
Mar 28 03:12:25 PM PDT 24 |
1457603538 ps |
| T887 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1018694007 |
|
|
Mar 28 03:09:04 PM PDT 24 |
Mar 28 03:09:10 PM PDT 24 |
2344254512 ps |
| T888 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.350148065 |
|
|
Mar 28 03:08:46 PM PDT 24 |
Mar 28 03:08:49 PM PDT 24 |
67536876 ps |
| T889 |
/workspace/coverage/default/8.sram_ctrl_executable.623217759 |
|
|
Mar 28 03:08:15 PM PDT 24 |
Mar 28 03:16:51 PM PDT 24 |
13555281890 ps |
| T890 |
/workspace/coverage/default/41.sram_ctrl_bijection.2598435039 |
|
|
Mar 28 03:12:35 PM PDT 24 |
Mar 28 03:13:28 PM PDT 24 |
6423438999 ps |
| T891 |
/workspace/coverage/default/43.sram_ctrl_smoke.488249013 |
|
|
Mar 28 03:13:01 PM PDT 24 |
Mar 28 03:14:16 PM PDT 24 |
129843906 ps |
| T892 |
/workspace/coverage/default/30.sram_ctrl_bijection.2337500397 |
|
|
Mar 28 03:11:06 PM PDT 24 |
Mar 28 03:11:27 PM PDT 24 |
1172858786 ps |
| T893 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1515096637 |
|
|
Mar 28 03:08:19 PM PDT 24 |
Mar 28 03:08:20 PM PDT 24 |
151114208 ps |
| T894 |
/workspace/coverage/default/40.sram_ctrl_executable.3934349025 |
|
|
Mar 28 03:12:37 PM PDT 24 |
Mar 28 03:34:58 PM PDT 24 |
47235380236 ps |
| T895 |
/workspace/coverage/default/7.sram_ctrl_smoke.3854905839 |
|
|
Mar 28 03:08:11 PM PDT 24 |
Mar 28 03:08:21 PM PDT 24 |
958442293 ps |
| T896 |
/workspace/coverage/default/37.sram_ctrl_alert_test.3001322858 |
|
|
Mar 28 03:12:00 PM PDT 24 |
Mar 28 03:12:00 PM PDT 24 |
11214934 ps |
| T897 |
/workspace/coverage/default/37.sram_ctrl_bijection.4228601971 |
|
|
Mar 28 03:11:59 PM PDT 24 |
Mar 28 03:12:54 PM PDT 24 |
848597371 ps |
| T898 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2174983165 |
|
|
Mar 28 03:12:57 PM PDT 24 |
Mar 28 03:13:01 PM PDT 24 |
58558922 ps |
| T899 |
/workspace/coverage/default/9.sram_ctrl_stress_all.103075201 |
|
|
Mar 28 03:08:28 PM PDT 24 |
Mar 28 03:26:07 PM PDT 24 |
95488199592 ps |
| T900 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.564620658 |
|
|
Mar 28 03:09:54 PM PDT 24 |
Mar 28 03:10:49 PM PDT 24 |
385335035 ps |
| T901 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.527012503 |
|
|
Mar 28 03:07:08 PM PDT 24 |
Mar 28 03:07:13 PM PDT 24 |
1084766301 ps |
| T902 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.545858266 |
|
|
Mar 28 03:11:10 PM PDT 24 |
Mar 28 03:14:19 PM PDT 24 |
233656223 ps |
| T903 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1665223281 |
|
|
Mar 28 03:11:04 PM PDT 24 |
Mar 28 03:11:07 PM PDT 24 |
364080689 ps |
| T904 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.261564621 |
|
|
Mar 28 03:12:54 PM PDT 24 |
Mar 28 03:16:47 PM PDT 24 |
6758165745 ps |
| T905 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1597083140 |
|
|
Mar 28 03:08:07 PM PDT 24 |
Mar 28 03:08:08 PM PDT 24 |
78591428 ps |
| T906 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3003302824 |
|
|
Mar 28 03:11:38 PM PDT 24 |
Mar 28 03:23:22 PM PDT 24 |
43953225594 ps |
| T907 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2120182374 |
|
|
Mar 28 03:13:19 PM PDT 24 |
Mar 28 03:29:46 PM PDT 24 |
60204930819 ps |
| T908 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3830460732 |
|
|
Mar 28 03:10:07 PM PDT 24 |
Mar 28 03:10:15 PM PDT 24 |
517391096 ps |
| T909 |
/workspace/coverage/default/47.sram_ctrl_bijection.1097909551 |
|
|
Mar 28 03:13:44 PM PDT 24 |
Mar 28 03:14:38 PM PDT 24 |
808301513 ps |
| T910 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4227516579 |
|
|
Mar 28 03:07:51 PM PDT 24 |
Mar 28 03:08:00 PM PDT 24 |
611386043 ps |
| T911 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.1284703008 |
|
|
Mar 28 03:11:19 PM PDT 24 |
Mar 28 03:11:27 PM PDT 24 |
140008510 ps |
| T912 |
/workspace/coverage/default/20.sram_ctrl_executable.3329796837 |
|
|
Mar 28 03:09:36 PM PDT 24 |
Mar 28 03:28:54 PM PDT 24 |
11338812116 ps |
| T913 |
/workspace/coverage/default/3.sram_ctrl_smoke.186396903 |
|
|
Mar 28 03:07:47 PM PDT 24 |
Mar 28 03:07:58 PM PDT 24 |
194789138 ps |
| T914 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.592905075 |
|
|
Mar 28 03:10:44 PM PDT 24 |
Mar 28 03:15:34 PM PDT 24 |
23796894642 ps |
| T915 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1030135559 |
|
|
Mar 28 03:13:21 PM PDT 24 |
Mar 28 03:17:32 PM PDT 24 |
2612428542 ps |
| T916 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.317657650 |
|
|
Mar 28 03:11:41 PM PDT 24 |
Mar 28 03:11:45 PM PDT 24 |
386564776 ps |
| T917 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2075371193 |
|
|
Mar 28 03:09:21 PM PDT 24 |
Mar 28 03:14:48 PM PDT 24 |
4035555127 ps |
| T918 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.4108412657 |
|
|
Mar 28 03:12:00 PM PDT 24 |
Mar 28 03:16:06 PM PDT 24 |
10000888490 ps |
| T919 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1937100637 |
|
|
Mar 28 03:08:45 PM PDT 24 |
Mar 28 03:13:40 PM PDT 24 |
2995784460 ps |
| T920 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2629247308 |
|
|
Mar 28 03:09:21 PM PDT 24 |
Mar 28 03:09:26 PM PDT 24 |
280080071 ps |
| T921 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3240203580 |
|
|
Mar 28 03:10:49 PM PDT 24 |
Mar 28 03:16:29 PM PDT 24 |
961307863 ps |
| T922 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.2654603980 |
|
|
Mar 28 03:09:12 PM PDT 24 |
Mar 28 03:09:37 PM PDT 24 |
342201139 ps |
| T923 |
/workspace/coverage/default/24.sram_ctrl_stress_all.4082997275 |
|
|
Mar 28 03:10:07 PM PDT 24 |
Mar 28 03:49:49 PM PDT 24 |
8320006297 ps |
| T924 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.210193688 |
|
|
Mar 28 03:10:25 PM PDT 24 |
Mar 28 03:27:53 PM PDT 24 |
2870458346 ps |
| T925 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2486392886 |
|
|
Mar 28 03:07:48 PM PDT 24 |
Mar 28 03:09:42 PM PDT 24 |
186669041 ps |
| T926 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2636979180 |
|
|
Mar 28 03:08:09 PM PDT 24 |
Mar 28 03:43:30 PM PDT 24 |
242568437374 ps |
| T927 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1295594962 |
|
|
Mar 28 03:07:48 PM PDT 24 |
Mar 28 03:11:40 PM PDT 24 |
4639664747 ps |
| T928 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3426223700 |
|
|
Mar 28 03:08:42 PM PDT 24 |
Mar 28 03:27:37 PM PDT 24 |
9611210888 ps |
| T929 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3164463677 |
|
|
Mar 28 03:09:36 PM PDT 24 |
Mar 28 03:10:30 PM PDT 24 |
2122357732 ps |
| T101 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4159052260 |
|
|
Mar 28 12:54:45 PM PDT 24 |
Mar 28 12:54:47 PM PDT 24 |
179579789 ps |
| T102 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1815994119 |
|
|
Mar 28 12:54:50 PM PDT 24 |
Mar 28 12:54:52 PM PDT 24 |
267249921 ps |
| T930 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.480268874 |
|
|
Mar 28 12:54:50 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
38264376 ps |
| T90 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2178541765 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
17551112 ps |
| T931 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4065572437 |
|
|
Mar 28 12:54:46 PM PDT 24 |
Mar 28 12:54:48 PM PDT 24 |
146419824 ps |
| T59 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3438366981 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
17549167 ps |
| T60 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1548578988 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
21876187 ps |
| T103 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1762370850 |
|
|
Mar 28 12:54:42 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
2038666751 ps |
| T91 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1267175157 |
|
|
Mar 28 12:54:32 PM PDT 24 |
Mar 28 12:54:33 PM PDT 24 |
17080552 ps |
| T932 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.587327542 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
70549772 ps |
| T61 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4112833024 |
|
|
Mar 28 12:54:32 PM PDT 24 |
Mar 28 12:54:33 PM PDT 24 |
13825694 ps |
| T100 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2526536569 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
67070493 ps |
| T933 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1924388077 |
|
|
Mar 28 12:54:32 PM PDT 24 |
Mar 28 12:54:33 PM PDT 24 |
36552770 ps |
| T62 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3006876397 |
|
|
Mar 28 12:54:51 PM PDT 24 |
Mar 28 12:54:55 PM PDT 24 |
760761394 ps |
| T92 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.650744205 |
|
|
Mar 28 12:54:46 PM PDT 24 |
Mar 28 12:54:47 PM PDT 24 |
38747337 ps |
| T63 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2971623165 |
|
|
Mar 28 12:54:50 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
63839305 ps |
| T934 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1833766673 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
205164815 ps |
| T122 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3683435099 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:54 PM PDT 24 |
80246143 ps |
| T93 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3513231909 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
14877347 ps |
| T64 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.875869123 |
|
|
Mar 28 12:54:28 PM PDT 24 |
Mar 28 12:54:30 PM PDT 24 |
201675231 ps |
| T935 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3363615416 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
208983195 ps |
| T65 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1559081635 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:50 PM PDT 24 |
244174267 ps |
| T66 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2301246331 |
|
|
Mar 28 12:54:47 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
215596639 ps |
| T936 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.432385088 |
|
|
Mar 28 12:54:47 PM PDT 24 |
Mar 28 12:54:48 PM PDT 24 |
79897891 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2166937780 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:44 PM PDT 24 |
20879934 ps |
| T937 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3784067560 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:54 PM PDT 24 |
198632167 ps |
| T118 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2477577949 |
|
|
Mar 28 12:54:54 PM PDT 24 |
Mar 28 12:54:56 PM PDT 24 |
361285320 ps |
| T938 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1296136255 |
|
|
Mar 28 12:54:46 PM PDT 24 |
Mar 28 12:54:47 PM PDT 24 |
99646996 ps |
| T939 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2228494052 |
|
|
Mar 28 12:55:04 PM PDT 24 |
Mar 28 12:55:08 PM PDT 24 |
119226877 ps |
| T68 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.228404255 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:52 PM PDT 24 |
780022656 ps |
| T71 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.611760972 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
30303340 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3852264070 |
|
|
Mar 28 12:54:29 PM PDT 24 |
Mar 28 12:54:30 PM PDT 24 |
23041946 ps |
| T940 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2769203785 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
38515757 ps |
| T941 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2489150083 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
376489134 ps |
| T73 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2694011502 |
|
|
Mar 28 12:54:57 PM PDT 24 |
Mar 28 12:55:01 PM PDT 24 |
818034367 ps |
| T74 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.542739730 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
1062175024 ps |
| T942 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3832809580 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
28270537 ps |
| T117 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4046226390 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:46 PM PDT 24 |
590426534 ps |
| T943 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2304622688 |
|
|
Mar 28 12:54:50 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
2838070212 ps |
| T944 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.848235415 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
21845874 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3037991037 |
|
|
Mar 28 12:54:27 PM PDT 24 |
Mar 28 12:54:27 PM PDT 24 |
98911371 ps |
| T81 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.83054420 |
|
|
Mar 28 12:54:50 PM PDT 24 |
Mar 28 12:54:52 PM PDT 24 |
787452728 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3843380755 |
|
|
Mar 28 12:54:46 PM PDT 24 |
Mar 28 12:54:48 PM PDT 24 |
383127084 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1727837953 |
|
|
Mar 28 12:54:42 PM PDT 24 |
Mar 28 12:54:43 PM PDT 24 |
42183570 ps |
| T947 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.121644730 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:46 PM PDT 24 |
30592591 ps |
| T948 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.454146381 |
|
|
Mar 28 12:54:44 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
22628157 ps |
| T949 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3778686208 |
|
|
Mar 28 12:54:32 PM PDT 24 |
Mar 28 12:54:35 PM PDT 24 |
79090586 ps |
| T119 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4038927851 |
|
|
Mar 28 12:54:44 PM PDT 24 |
Mar 28 12:54:47 PM PDT 24 |
519224056 ps |
| T950 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.126643963 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
77598683 ps |
| T951 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1680985534 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:48 PM PDT 24 |
19811678 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.224837107 |
|
|
Mar 28 12:54:47 PM PDT 24 |
Mar 28 12:54:50 PM PDT 24 |
108364411 ps |
| T121 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1991556751 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
173661007 ps |
| T120 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.488366018 |
|
|
Mar 28 12:54:54 PM PDT 24 |
Mar 28 12:54:57 PM PDT 24 |
204650544 ps |
| T953 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2925733136 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
23843976 ps |
| T82 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3310366056 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:50 PM PDT 24 |
19118673 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1019936322 |
|
|
Mar 28 12:54:50 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
18299345 ps |
| T955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2717320011 |
|
|
Mar 28 12:54:28 PM PDT 24 |
Mar 28 12:54:32 PM PDT 24 |
417479505 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3053182129 |
|
|
Mar 28 12:54:44 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
26436305 ps |
| T83 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2590774136 |
|
|
Mar 28 12:54:54 PM PDT 24 |
Mar 28 12:54:55 PM PDT 24 |
16365816 ps |
| T957 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1927695911 |
|
|
Mar 28 12:54:51 PM PDT 24 |
Mar 28 12:54:52 PM PDT 24 |
12086221 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3144531083 |
|
|
Mar 28 12:54:40 PM PDT 24 |
Mar 28 12:54:41 PM PDT 24 |
115017358 ps |
| T89 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3580727968 |
|
|
Mar 28 12:54:28 PM PDT 24 |
Mar 28 12:54:29 PM PDT 24 |
21198803 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.245819645 |
|
|
Mar 28 12:54:47 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
67451831 ps |
| T960 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.750128968 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
13712255 ps |
| T961 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1428431420 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:50 PM PDT 24 |
50517164 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2844535338 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
56518465 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4020031504 |
|
|
Mar 28 12:54:42 PM PDT 24 |
Mar 28 12:54:44 PM PDT 24 |
111290533 ps |
| T964 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3723777590 |
|
|
Mar 28 12:54:53 PM PDT 24 |
Mar 28 12:54:56 PM PDT 24 |
32203775 ps |
| T123 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1787328739 |
|
|
Mar 28 12:54:44 PM PDT 24 |
Mar 28 12:54:46 PM PDT 24 |
282047598 ps |
| T965 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.296380378 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:54 PM PDT 24 |
90396034 ps |
| T966 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3603844346 |
|
|
Mar 28 12:54:45 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
22671490 ps |
| T967 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1155171261 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:52 PM PDT 24 |
377403326 ps |
| T968 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4231140177 |
|
|
Mar 28 12:54:46 PM PDT 24 |
Mar 28 12:54:47 PM PDT 24 |
44077832 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3905727023 |
|
|
Mar 28 12:54:44 PM PDT 24 |
Mar 28 12:54:44 PM PDT 24 |
48282945 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.29309333 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:44 PM PDT 24 |
13788321 ps |
| T971 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1828632844 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
44933492 ps |
| T972 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4235489803 |
|
|
Mar 28 12:54:45 PM PDT 24 |
Mar 28 12:54:46 PM PDT 24 |
18081727 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3947890127 |
|
|
Mar 28 12:54:45 PM PDT 24 |
Mar 28 12:54:48 PM PDT 24 |
137403220 ps |
| T84 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.568030358 |
|
|
Mar 28 12:54:46 PM PDT 24 |
Mar 28 12:54:48 PM PDT 24 |
1928964643 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2811526593 |
|
|
Mar 28 12:54:50 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
26920207 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1000027236 |
|
|
Mar 28 12:54:28 PM PDT 24 |
Mar 28 12:54:30 PM PDT 24 |
147015463 ps |
| T976 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.614316483 |
|
|
Mar 28 12:54:53 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
11635146 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1214519684 |
|
|
Mar 28 12:54:32 PM PDT 24 |
Mar 28 12:54:34 PM PDT 24 |
151523747 ps |
| T124 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1983623118 |
|
|
Mar 28 12:54:44 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
104601397 ps |
| T978 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.973587167 |
|
|
Mar 28 12:54:46 PM PDT 24 |
Mar 28 12:54:50 PM PDT 24 |
719585244 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1211352953 |
|
|
Mar 28 12:54:26 PM PDT 24 |
Mar 28 12:54:31 PM PDT 24 |
113897745 ps |
| T127 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2871322736 |
|
|
Mar 28 12:54:47 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
290705542 ps |
| T980 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.302345224 |
|
|
Mar 28 12:54:47 PM PDT 24 |
Mar 28 12:54:47 PM PDT 24 |
33763012 ps |
| T981 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.339660012 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
10275163 ps |
| T126 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1786537963 |
|
|
Mar 28 12:54:27 PM PDT 24 |
Mar 28 12:54:30 PM PDT 24 |
181701262 ps |
| T982 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3664712497 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
52539937 ps |
| T983 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1381575435 |
|
|
Mar 28 12:54:42 PM PDT 24 |
Mar 28 12:54:43 PM PDT 24 |
16747328 ps |
| T125 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3379608877 |
|
|
Mar 28 12:54:33 PM PDT 24 |
Mar 28 12:54:35 PM PDT 24 |
976391682 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3292323868 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:50 PM PDT 24 |
68980073 ps |
| T985 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2239225705 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:49 PM PDT 24 |
98143566 ps |
| T85 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2046091021 |
|
|
Mar 28 12:54:54 PM PDT 24 |
Mar 28 12:54:56 PM PDT 24 |
253702137 ps |
| T986 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3528800146 |
|
|
Mar 28 12:54:50 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
309181876 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2940780682 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:46 PM PDT 24 |
137163667 ps |
| T988 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2101818228 |
|
|
Mar 28 12:54:44 PM PDT 24 |
Mar 28 12:54:47 PM PDT 24 |
798957581 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3825400796 |
|
|
Mar 28 12:54:45 PM PDT 24 |
Mar 28 12:54:46 PM PDT 24 |
91658838 ps |
| T86 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2197719980 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:52 PM PDT 24 |
1617863796 ps |
| T87 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.26997793 |
|
|
Mar 28 12:54:45 PM PDT 24 |
Mar 28 12:54:45 PM PDT 24 |
15142211 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.842780286 |
|
|
Mar 28 12:54:31 PM PDT 24 |
Mar 28 12:54:33 PM PDT 24 |
132741054 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2373506491 |
|
|
Mar 28 12:54:26 PM PDT 24 |
Mar 28 12:54:27 PM PDT 24 |
77675866 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.183745628 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:54 PM PDT 24 |
441975077 ps |
| T993 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3489628936 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:53 PM PDT 24 |
28714339 ps |
| T994 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1933710519 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:52 PM PDT 24 |
44075194 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.281920072 |
|
|
Mar 28 12:54:41 PM PDT 24 |
Mar 28 12:54:43 PM PDT 24 |
39251701 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1583665833 |
|
|
Mar 28 12:54:44 PM PDT 24 |
Mar 28 12:54:47 PM PDT 24 |
820266771 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1941001029 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
192844313 ps |
| T998 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3689173389 |
|
|
Mar 28 12:54:45 PM PDT 24 |
Mar 28 12:54:46 PM PDT 24 |
47927426 ps |
| T999 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1393165395 |
|
|
Mar 28 12:54:48 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
85489849 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.635114708 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:55 PM PDT 24 |
294086301 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.4151086041 |
|
|
Mar 28 12:54:44 PM PDT 24 |
Mar 28 12:54:46 PM PDT 24 |
164999495 ps |