| T297 |
/workspace/coverage/default/17.sram_ctrl_regwen.1776228255 |
|
|
Apr 28 03:40:25 PM PDT 24 |
Apr 28 03:52:06 PM PDT 24 |
9080714247 ps |
| T298 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.264489666 |
|
|
Apr 28 03:39:31 PM PDT 24 |
Apr 28 03:39:37 PM PDT 24 |
3144704336 ps |
| T47 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3133627983 |
|
|
Apr 28 03:40:33 PM PDT 24 |
Apr 28 03:41:17 PM PDT 24 |
1830802194 ps |
| T299 |
/workspace/coverage/default/35.sram_ctrl_bijection.1625746025 |
|
|
Apr 28 03:41:33 PM PDT 24 |
Apr 28 03:42:53 PM PDT 24 |
6803369968 ps |
| T20 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3659151286 |
|
|
Apr 28 03:39:22 PM PDT 24 |
Apr 28 03:39:26 PM PDT 24 |
229044817 ps |
| T300 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.540566543 |
|
|
Apr 28 03:41:49 PM PDT 24 |
Apr 28 03:41:54 PM PDT 24 |
260006974 ps |
| T301 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.2744949839 |
|
|
Apr 28 03:42:15 PM PDT 24 |
Apr 28 03:42:16 PM PDT 24 |
25970538 ps |
| T302 |
/workspace/coverage/default/9.sram_ctrl_bijection.3630537506 |
|
|
Apr 28 03:39:48 PM PDT 24 |
Apr 28 03:40:14 PM PDT 24 |
1466633209 ps |
| T303 |
/workspace/coverage/default/28.sram_ctrl_executable.4123515031 |
|
|
Apr 28 03:40:56 PM PDT 24 |
Apr 28 04:02:12 PM PDT 24 |
13476980436 ps |
| T304 |
/workspace/coverage/default/48.sram_ctrl_executable.2805382799 |
|
|
Apr 28 03:42:56 PM PDT 24 |
Apr 28 04:11:41 PM PDT 24 |
4865799137 ps |
| T305 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3128899956 |
|
|
Apr 28 03:40:02 PM PDT 24 |
Apr 28 03:40:17 PM PDT 24 |
1624911282 ps |
| T306 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.3763654007 |
|
|
Apr 28 03:41:19 PM PDT 24 |
Apr 28 03:41:24 PM PDT 24 |
235067357 ps |
| T307 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2704733519 |
|
|
Apr 28 03:41:05 PM PDT 24 |
Apr 28 03:42:06 PM PDT 24 |
680481701 ps |
| T308 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.910273119 |
|
|
Apr 28 03:41:55 PM PDT 24 |
Apr 28 03:42:02 PM PDT 24 |
458924977 ps |
| T309 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2848355003 |
|
|
Apr 28 03:40:39 PM PDT 24 |
Apr 28 03:48:22 PM PDT 24 |
1723234443 ps |
| T310 |
/workspace/coverage/default/44.sram_ctrl_stress_all.1209544449 |
|
|
Apr 28 03:42:31 PM PDT 24 |
Apr 28 04:37:42 PM PDT 24 |
21999258463 ps |
| T311 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1283990591 |
|
|
Apr 28 03:40:12 PM PDT 24 |
Apr 28 03:40:17 PM PDT 24 |
230888577 ps |
| T312 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.1314044884 |
|
|
Apr 28 03:39:52 PM PDT 24 |
Apr 28 03:40:42 PM PDT 24 |
203734035 ps |
| T313 |
/workspace/coverage/default/24.sram_ctrl_executable.1124360031 |
|
|
Apr 28 03:40:38 PM PDT 24 |
Apr 28 03:41:49 PM PDT 24 |
8732199157 ps |
| T314 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3813739138 |
|
|
Apr 28 03:41:28 PM PDT 24 |
Apr 28 03:44:22 PM PDT 24 |
3535526023 ps |
| T315 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.191219088 |
|
|
Apr 28 03:39:42 PM PDT 24 |
Apr 28 03:39:47 PM PDT 24 |
1229806326 ps |
| T90 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.717169272 |
|
|
Apr 28 03:42:30 PM PDT 24 |
Apr 28 03:44:33 PM PDT 24 |
4565074386 ps |
| T316 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.296199711 |
|
|
Apr 28 03:40:41 PM PDT 24 |
Apr 28 03:40:51 PM PDT 24 |
140391319 ps |
| T317 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3282813893 |
|
|
Apr 28 03:39:20 PM PDT 24 |
Apr 28 04:05:52 PM PDT 24 |
37574229194 ps |
| T318 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2392216573 |
|
|
Apr 28 03:39:50 PM PDT 24 |
Apr 28 03:41:29 PM PDT 24 |
4101935058 ps |
| T319 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2804263000 |
|
|
Apr 28 03:41:39 PM PDT 24 |
Apr 28 03:42:32 PM PDT 24 |
360362550 ps |
| T320 |
/workspace/coverage/default/0.sram_ctrl_executable.759039783 |
|
|
Apr 28 03:39:20 PM PDT 24 |
Apr 28 03:41:26 PM PDT 24 |
2935427611 ps |
| T321 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2840553267 |
|
|
Apr 28 03:42:51 PM PDT 24 |
Apr 28 03:46:40 PM PDT 24 |
12693044795 ps |
| T322 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1040702192 |
|
|
Apr 28 03:40:56 PM PDT 24 |
Apr 28 03:44:55 PM PDT 24 |
5007323150 ps |
| T323 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.981890789 |
|
|
Apr 28 03:41:14 PM PDT 24 |
Apr 28 03:48:48 PM PDT 24 |
226152600968 ps |
| T324 |
/workspace/coverage/default/32.sram_ctrl_smoke.3346395484 |
|
|
Apr 28 03:41:20 PM PDT 24 |
Apr 28 03:41:22 PM PDT 24 |
110555749 ps |
| T325 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.1376496625 |
|
|
Apr 28 03:41:32 PM PDT 24 |
Apr 28 03:41:34 PM PDT 24 |
121566225 ps |
| T326 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3818174313 |
|
|
Apr 28 03:40:03 PM PDT 24 |
Apr 28 03:40:04 PM PDT 24 |
184300726 ps |
| T327 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2294036466 |
|
|
Apr 28 03:40:30 PM PDT 24 |
Apr 28 03:42:43 PM PDT 24 |
267656579 ps |
| T328 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.307119651 |
|
|
Apr 28 03:39:47 PM PDT 24 |
Apr 28 03:39:48 PM PDT 24 |
79394836 ps |
| T329 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4152247929 |
|
|
Apr 28 03:42:37 PM PDT 24 |
Apr 28 03:58:11 PM PDT 24 |
50186782095 ps |
| T330 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2966443776 |
|
|
Apr 28 03:41:16 PM PDT 24 |
Apr 28 03:42:08 PM PDT 24 |
131892406 ps |
| T331 |
/workspace/coverage/default/27.sram_ctrl_alert_test.3523582536 |
|
|
Apr 28 03:40:52 PM PDT 24 |
Apr 28 03:40:54 PM PDT 24 |
13696869 ps |
| T332 |
/workspace/coverage/default/6.sram_ctrl_smoke.776774529 |
|
|
Apr 28 03:39:41 PM PDT 24 |
Apr 28 03:40:39 PM PDT 24 |
876732326 ps |
| T333 |
/workspace/coverage/default/2.sram_ctrl_bijection.2107702248 |
|
|
Apr 28 03:39:29 PM PDT 24 |
Apr 28 03:40:13 PM PDT 24 |
674992295 ps |
| T334 |
/workspace/coverage/default/19.sram_ctrl_partial_access.1891252879 |
|
|
Apr 28 03:40:31 PM PDT 24 |
Apr 28 03:40:35 PM PDT 24 |
1439117218 ps |
| T335 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2086178699 |
|
|
Apr 28 03:39:48 PM PDT 24 |
Apr 28 04:16:23 PM PDT 24 |
21250858396 ps |
| T336 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2559786777 |
|
|
Apr 28 03:39:54 PM PDT 24 |
Apr 28 03:47:15 PM PDT 24 |
10857302814 ps |
| T337 |
/workspace/coverage/default/13.sram_ctrl_executable.3938755816 |
|
|
Apr 28 03:40:06 PM PDT 24 |
Apr 28 03:45:39 PM PDT 24 |
21817405388 ps |
| T338 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1780914918 |
|
|
Apr 28 03:41:46 PM PDT 24 |
Apr 28 03:43:29 PM PDT 24 |
435833314 ps |
| T339 |
/workspace/coverage/default/39.sram_ctrl_stress_all.1985749481 |
|
|
Apr 28 03:41:58 PM PDT 24 |
Apr 28 04:19:06 PM PDT 24 |
16821652768 ps |
| T340 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2962912114 |
|
|
Apr 28 03:40:25 PM PDT 24 |
Apr 28 03:41:01 PM PDT 24 |
574726725 ps |
| T341 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3765921912 |
|
|
Apr 28 03:40:46 PM PDT 24 |
Apr 28 03:40:47 PM PDT 24 |
33425411 ps |
| T342 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3685894038 |
|
|
Apr 28 03:41:17 PM PDT 24 |
Apr 28 03:43:27 PM PDT 24 |
8228435871 ps |
| T343 |
/workspace/coverage/default/38.sram_ctrl_executable.922782661 |
|
|
Apr 28 03:41:54 PM PDT 24 |
Apr 28 03:58:44 PM PDT 24 |
4144276419 ps |
| T344 |
/workspace/coverage/default/26.sram_ctrl_partial_access.3601585311 |
|
|
Apr 28 03:40:47 PM PDT 24 |
Apr 28 03:40:51 PM PDT 24 |
89816701 ps |
| T345 |
/workspace/coverage/default/12.sram_ctrl_executable.2772919191 |
|
|
Apr 28 03:40:01 PM PDT 24 |
Apr 28 04:12:56 PM PDT 24 |
12501802680 ps |
| T346 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2835549566 |
|
|
Apr 28 03:39:46 PM PDT 24 |
Apr 28 03:39:52 PM PDT 24 |
311115388 ps |
| T347 |
/workspace/coverage/default/35.sram_ctrl_stress_all.2368337610 |
|
|
Apr 28 03:41:36 PM PDT 24 |
Apr 28 05:23:55 PM PDT 24 |
169389138786 ps |
| T348 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3989196065 |
|
|
Apr 28 03:40:37 PM PDT 24 |
Apr 28 03:44:23 PM PDT 24 |
4267448725 ps |
| T349 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2842059951 |
|
|
Apr 28 03:40:00 PM PDT 24 |
Apr 28 03:40:10 PM PDT 24 |
441527126 ps |
| T350 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2268887183 |
|
|
Apr 28 03:39:34 PM PDT 24 |
Apr 28 03:39:45 PM PDT 24 |
896290828 ps |
| T351 |
/workspace/coverage/default/5.sram_ctrl_regwen.1447881612 |
|
|
Apr 28 03:39:41 PM PDT 24 |
Apr 28 03:49:01 PM PDT 24 |
12849987243 ps |
| T352 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2540488189 |
|
|
Apr 28 03:40:23 PM PDT 24 |
Apr 28 03:44:00 PM PDT 24 |
5411311630 ps |
| T353 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.270383933 |
|
|
Apr 28 03:39:21 PM PDT 24 |
Apr 28 03:40:59 PM PDT 24 |
629207307 ps |
| T354 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.912080856 |
|
|
Apr 28 03:40:00 PM PDT 24 |
Apr 28 03:40:03 PM PDT 24 |
89039113 ps |
| T355 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1780774941 |
|
|
Apr 28 03:41:19 PM PDT 24 |
Apr 28 03:41:21 PM PDT 24 |
154712896 ps |
| T356 |
/workspace/coverage/default/39.sram_ctrl_alert_test.276219633 |
|
|
Apr 28 03:41:59 PM PDT 24 |
Apr 28 03:42:00 PM PDT 24 |
16626326 ps |
| T357 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.3012349147 |
|
|
Apr 28 03:40:40 PM PDT 24 |
Apr 28 03:42:46 PM PDT 24 |
515900053 ps |
| T358 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.636252443 |
|
|
Apr 28 03:39:33 PM PDT 24 |
Apr 28 03:45:25 PM PDT 24 |
7095395376 ps |
| T359 |
/workspace/coverage/default/18.sram_ctrl_regwen.3131098078 |
|
|
Apr 28 03:40:20 PM PDT 24 |
Apr 28 03:46:19 PM PDT 24 |
83917223921 ps |
| T360 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3030149954 |
|
|
Apr 28 03:41:11 PM PDT 24 |
Apr 28 03:49:00 PM PDT 24 |
1081283907 ps |
| T361 |
/workspace/coverage/default/39.sram_ctrl_executable.2167027157 |
|
|
Apr 28 03:42:00 PM PDT 24 |
Apr 28 03:57:55 PM PDT 24 |
30768540658 ps |
| T362 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.549332542 |
|
|
Apr 28 03:42:18 PM PDT 24 |
Apr 28 03:42:24 PM PDT 24 |
764679710 ps |
| T363 |
/workspace/coverage/default/11.sram_ctrl_regwen.445332848 |
|
|
Apr 28 03:39:54 PM PDT 24 |
Apr 28 03:48:03 PM PDT 24 |
15593493720 ps |
| T364 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.35007245 |
|
|
Apr 28 03:39:50 PM PDT 24 |
Apr 28 03:39:51 PM PDT 24 |
33950220 ps |
| T365 |
/workspace/coverage/default/21.sram_ctrl_executable.3466681234 |
|
|
Apr 28 03:40:30 PM PDT 24 |
Apr 28 03:52:02 PM PDT 24 |
4711101494 ps |
| T366 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2765029633 |
|
|
Apr 28 03:40:50 PM PDT 24 |
Apr 28 03:47:58 PM PDT 24 |
19621204796 ps |
| T367 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.2398031719 |
|
|
Apr 28 03:41:54 PM PDT 24 |
Apr 28 03:42:21 PM PDT 24 |
352095275 ps |
| T368 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.21829264 |
|
|
Apr 28 03:40:19 PM PDT 24 |
Apr 28 03:40:25 PM PDT 24 |
460658957 ps |
| T369 |
/workspace/coverage/default/4.sram_ctrl_smoke.428137741 |
|
|
Apr 28 03:39:35 PM PDT 24 |
Apr 28 03:39:49 PM PDT 24 |
1381638442 ps |
| T370 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2836147128 |
|
|
Apr 28 03:41:24 PM PDT 24 |
Apr 28 04:02:35 PM PDT 24 |
33715836089 ps |
| T371 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.4270261559 |
|
|
Apr 28 03:41:16 PM PDT 24 |
Apr 28 03:44:06 PM PDT 24 |
7592893174 ps |
| T372 |
/workspace/coverage/default/24.sram_ctrl_smoke.1743957034 |
|
|
Apr 28 03:40:42 PM PDT 24 |
Apr 28 03:40:57 PM PDT 24 |
1939488332 ps |
| T373 |
/workspace/coverage/default/15.sram_ctrl_stress_all.4201459346 |
|
|
Apr 28 03:40:06 PM PDT 24 |
Apr 28 04:50:13 PM PDT 24 |
74226649953 ps |
| T374 |
/workspace/coverage/default/34.sram_ctrl_executable.2310428432 |
|
|
Apr 28 03:41:28 PM PDT 24 |
Apr 28 03:49:28 PM PDT 24 |
4238172945 ps |
| T375 |
/workspace/coverage/default/2.sram_ctrl_smoke.3955452762 |
|
|
Apr 28 03:39:26 PM PDT 24 |
Apr 28 03:39:38 PM PDT 24 |
1312785717 ps |
| T30 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.779510826 |
|
|
Apr 28 03:39:21 PM PDT 24 |
Apr 28 03:39:24 PM PDT 24 |
401984797 ps |
| T376 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.575949105 |
|
|
Apr 28 03:41:22 PM PDT 24 |
Apr 28 03:41:28 PM PDT 24 |
414715438 ps |
| T377 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.1431688204 |
|
|
Apr 28 03:40:30 PM PDT 24 |
Apr 28 03:40:37 PM PDT 24 |
2579996276 ps |
| T378 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1136346298 |
|
|
Apr 28 03:40:04 PM PDT 24 |
Apr 28 03:43:41 PM PDT 24 |
2283613486 ps |
| T379 |
/workspace/coverage/default/49.sram_ctrl_alert_test.1040180949 |
|
|
Apr 28 03:43:07 PM PDT 24 |
Apr 28 03:43:08 PM PDT 24 |
66245549 ps |
| T380 |
/workspace/coverage/default/11.sram_ctrl_bijection.2177475458 |
|
|
Apr 28 03:39:59 PM PDT 24 |
Apr 28 03:40:59 PM PDT 24 |
4111230441 ps |
| T381 |
/workspace/coverage/default/42.sram_ctrl_alert_test.825791802 |
|
|
Apr 28 03:42:15 PM PDT 24 |
Apr 28 03:42:16 PM PDT 24 |
14851516 ps |
| T382 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2084163544 |
|
|
Apr 28 03:41:00 PM PDT 24 |
Apr 28 03:45:02 PM PDT 24 |
13128602305 ps |
| T383 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1221055597 |
|
|
Apr 28 03:42:49 PM PDT 24 |
Apr 28 03:44:03 PM PDT 24 |
117809567 ps |
| T384 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.4101058635 |
|
|
Apr 28 03:40:43 PM PDT 24 |
Apr 28 03:40:44 PM PDT 24 |
44833255 ps |
| T385 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1922775029 |
|
|
Apr 28 03:39:36 PM PDT 24 |
Apr 28 03:39:41 PM PDT 24 |
85367474 ps |
| T386 |
/workspace/coverage/default/30.sram_ctrl_stress_all.2857679452 |
|
|
Apr 28 03:41:17 PM PDT 24 |
Apr 28 03:45:10 PM PDT 24 |
24557365350 ps |
| T387 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2935474824 |
|
|
Apr 28 03:41:17 PM PDT 24 |
Apr 28 04:18:04 PM PDT 24 |
139524510097 ps |
| T388 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3180838929 |
|
|
Apr 28 03:40:36 PM PDT 24 |
Apr 28 03:40:46 PM PDT 24 |
141414401 ps |
| T389 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2671562270 |
|
|
Apr 28 03:41:18 PM PDT 24 |
Apr 28 03:41:19 PM PDT 24 |
15520306 ps |
| T390 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2311451659 |
|
|
Apr 28 03:40:42 PM PDT 24 |
Apr 28 03:40:51 PM PDT 24 |
773472529 ps |
| T391 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3135081455 |
|
|
Apr 28 03:40:40 PM PDT 24 |
Apr 28 03:40:44 PM PDT 24 |
101603729 ps |
| T392 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.549928499 |
|
|
Apr 28 03:40:36 PM PDT 24 |
Apr 28 03:40:42 PM PDT 24 |
353792116 ps |
| T393 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.2631668468 |
|
|
Apr 28 03:40:53 PM PDT 24 |
Apr 28 03:41:01 PM PDT 24 |
635740940 ps |
| T394 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.593464867 |
|
|
Apr 28 03:40:05 PM PDT 24 |
Apr 28 03:43:45 PM PDT 24 |
10388739236 ps |
| T395 |
/workspace/coverage/default/8.sram_ctrl_regwen.2375581052 |
|
|
Apr 28 03:39:48 PM PDT 24 |
Apr 28 04:04:26 PM PDT 24 |
15123909767 ps |
| T396 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3231442823 |
|
|
Apr 28 03:42:32 PM PDT 24 |
Apr 28 03:44:56 PM PDT 24 |
294571563 ps |
| T91 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3109201905 |
|
|
Apr 28 03:39:53 PM PDT 24 |
Apr 28 03:41:46 PM PDT 24 |
6074283552 ps |
| T397 |
/workspace/coverage/default/25.sram_ctrl_partial_access.198403406 |
|
|
Apr 28 03:40:42 PM PDT 24 |
Apr 28 03:40:56 PM PDT 24 |
1287217216 ps |
| T398 |
/workspace/coverage/default/26.sram_ctrl_regwen.171397356 |
|
|
Apr 28 03:40:53 PM PDT 24 |
Apr 28 04:01:47 PM PDT 24 |
52439224931 ps |
| T399 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2746484359 |
|
|
Apr 28 03:41:16 PM PDT 24 |
Apr 28 03:41:20 PM PDT 24 |
171510555 ps |
| T400 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2548584451 |
|
|
Apr 28 03:39:43 PM PDT 24 |
Apr 28 03:42:10 PM PDT 24 |
1658964593 ps |
| T401 |
/workspace/coverage/default/20.sram_ctrl_partial_access.1787584808 |
|
|
Apr 28 03:40:28 PM PDT 24 |
Apr 28 03:42:37 PM PDT 24 |
3548933923 ps |
| T402 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.1170654287 |
|
|
Apr 28 03:40:47 PM PDT 24 |
Apr 28 03:59:46 PM PDT 24 |
11297093305 ps |
| T403 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.1698811041 |
|
|
Apr 28 03:40:31 PM PDT 24 |
Apr 28 03:40:33 PM PDT 24 |
118441629 ps |
| T404 |
/workspace/coverage/default/19.sram_ctrl_executable.2972443694 |
|
|
Apr 28 03:40:26 PM PDT 24 |
Apr 28 04:05:57 PM PDT 24 |
3789714977 ps |
| T405 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.946891626 |
|
|
Apr 28 03:42:51 PM PDT 24 |
Apr 28 03:50:26 PM PDT 24 |
10844160938 ps |
| T92 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3252985686 |
|
|
Apr 28 03:39:39 PM PDT 24 |
Apr 28 03:45:37 PM PDT 24 |
2381987921 ps |
| T406 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1715211623 |
|
|
Apr 28 03:42:17 PM PDT 24 |
Apr 28 03:46:12 PM PDT 24 |
5137092292 ps |
| T407 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.1018718678 |
|
|
Apr 28 03:40:09 PM PDT 24 |
Apr 28 03:40:14 PM PDT 24 |
79810945 ps |
| T408 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1334745545 |
|
|
Apr 28 03:40:00 PM PDT 24 |
Apr 28 04:10:08 PM PDT 24 |
66635508910 ps |
| T409 |
/workspace/coverage/default/8.sram_ctrl_alert_test.167247205 |
|
|
Apr 28 03:39:49 PM PDT 24 |
Apr 28 03:39:50 PM PDT 24 |
12808795 ps |
| T410 |
/workspace/coverage/default/5.sram_ctrl_smoke.360580468 |
|
|
Apr 28 03:39:35 PM PDT 24 |
Apr 28 03:40:52 PM PDT 24 |
505091722 ps |
| T411 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2233270619 |
|
|
Apr 28 03:39:25 PM PDT 24 |
Apr 28 03:48:07 PM PDT 24 |
1923294774 ps |
| T412 |
/workspace/coverage/default/1.sram_ctrl_executable.2789803194 |
|
|
Apr 28 03:39:25 PM PDT 24 |
Apr 28 03:40:39 PM PDT 24 |
2907522143 ps |
| T413 |
/workspace/coverage/default/23.sram_ctrl_bijection.3860679796 |
|
|
Apr 28 03:40:38 PM PDT 24 |
Apr 28 03:41:48 PM PDT 24 |
14314811103 ps |
| T414 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.564743831 |
|
|
Apr 28 03:41:23 PM PDT 24 |
Apr 28 03:43:18 PM PDT 24 |
497980810 ps |
| T415 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1941796099 |
|
|
Apr 28 03:40:46 PM PDT 24 |
Apr 28 03:44:01 PM PDT 24 |
4197231191 ps |
| T416 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.215511168 |
|
|
Apr 28 03:41:17 PM PDT 24 |
Apr 28 03:41:22 PM PDT 24 |
282615792 ps |
| T417 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.4245754990 |
|
|
Apr 28 03:41:10 PM PDT 24 |
Apr 28 03:41:21 PM PDT 24 |
2482946727 ps |
| T418 |
/workspace/coverage/default/31.sram_ctrl_smoke.844806461 |
|
|
Apr 28 03:41:16 PM PDT 24 |
Apr 28 03:41:27 PM PDT 24 |
656807464 ps |
| T419 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.789683546 |
|
|
Apr 28 03:39:57 PM PDT 24 |
Apr 28 03:41:59 PM PDT 24 |
4222387854 ps |
| T420 |
/workspace/coverage/default/45.sram_ctrl_executable.1584550980 |
|
|
Apr 28 03:42:32 PM PDT 24 |
Apr 28 04:03:15 PM PDT 24 |
61885045471 ps |
| T421 |
/workspace/coverage/default/3.sram_ctrl_regwen.820141874 |
|
|
Apr 28 03:39:29 PM PDT 24 |
Apr 28 03:55:53 PM PDT 24 |
10326974899 ps |
| T422 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.271212825 |
|
|
Apr 28 03:41:56 PM PDT 24 |
Apr 28 03:42:02 PM PDT 24 |
3126218027 ps |
| T423 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2943353886 |
|
|
Apr 28 03:40:14 PM PDT 24 |
Apr 28 03:40:18 PM PDT 24 |
190614202 ps |
| T424 |
/workspace/coverage/default/2.sram_ctrl_alert_test.3305524820 |
|
|
Apr 28 03:39:40 PM PDT 24 |
Apr 28 03:39:41 PM PDT 24 |
26754576 ps |
| T425 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1751200975 |
|
|
Apr 28 03:40:00 PM PDT 24 |
Apr 28 03:40:02 PM PDT 24 |
39302317 ps |
| T426 |
/workspace/coverage/default/10.sram_ctrl_stress_all.399729744 |
|
|
Apr 28 03:39:53 PM PDT 24 |
Apr 28 04:15:24 PM PDT 24 |
190172095055 ps |
| T427 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2232003059 |
|
|
Apr 28 03:39:55 PM PDT 24 |
Apr 28 03:40:00 PM PDT 24 |
1353119792 ps |
| T428 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1792699563 |
|
|
Apr 28 03:40:14 PM PDT 24 |
Apr 28 03:55:59 PM PDT 24 |
2645111148 ps |
| T429 |
/workspace/coverage/default/34.sram_ctrl_regwen.4253691509 |
|
|
Apr 28 03:41:33 PM PDT 24 |
Apr 28 04:19:33 PM PDT 24 |
17629152610 ps |
| T430 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2187170608 |
|
|
Apr 28 03:41:28 PM PDT 24 |
Apr 28 03:47:05 PM PDT 24 |
73296452323 ps |
| T431 |
/workspace/coverage/default/29.sram_ctrl_stress_all.631905982 |
|
|
Apr 28 03:41:04 PM PDT 24 |
Apr 28 05:04:21 PM PDT 24 |
50089061368 ps |
| T432 |
/workspace/coverage/default/8.sram_ctrl_smoke.211651750 |
|
|
Apr 28 03:39:43 PM PDT 24 |
Apr 28 03:39:44 PM PDT 24 |
140485555 ps |
| T433 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.1046889030 |
|
|
Apr 28 03:39:46 PM PDT 24 |
Apr 28 03:39:58 PM PDT 24 |
2749102312 ps |
| T434 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1570619504 |
|
|
Apr 28 03:41:36 PM PDT 24 |
Apr 28 03:41:39 PM PDT 24 |
160357610 ps |
| T435 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3228612797 |
|
|
Apr 28 03:42:50 PM PDT 24 |
Apr 28 03:43:02 PM PDT 24 |
79605190 ps |
| T436 |
/workspace/coverage/default/43.sram_ctrl_bijection.333827590 |
|
|
Apr 28 03:42:18 PM PDT 24 |
Apr 28 03:43:30 PM PDT 24 |
2270635219 ps |
| T437 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3042287677 |
|
|
Apr 28 03:40:12 PM PDT 24 |
Apr 28 03:55:54 PM PDT 24 |
2257422710 ps |
| T438 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3036614760 |
|
|
Apr 28 03:42:41 PM PDT 24 |
Apr 28 03:42:49 PM PDT 24 |
628677026 ps |
| T439 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3611879546 |
|
|
Apr 28 03:41:56 PM PDT 24 |
Apr 28 03:41:57 PM PDT 24 |
76444428 ps |
| T440 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.3480102835 |
|
|
Apr 28 03:41:22 PM PDT 24 |
Apr 28 03:41:23 PM PDT 24 |
43425443 ps |
| T441 |
/workspace/coverage/default/9.sram_ctrl_alert_test.3548598832 |
|
|
Apr 28 03:39:49 PM PDT 24 |
Apr 28 03:39:50 PM PDT 24 |
44860182 ps |
| T442 |
/workspace/coverage/default/26.sram_ctrl_executable.822862769 |
|
|
Apr 28 03:40:47 PM PDT 24 |
Apr 28 03:53:42 PM PDT 24 |
1960437338 ps |
| T443 |
/workspace/coverage/default/1.sram_ctrl_stress_all.3606861949 |
|
|
Apr 28 03:39:22 PM PDT 24 |
Apr 28 05:19:52 PM PDT 24 |
95036979290 ps |
| T444 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2605442541 |
|
|
Apr 28 03:41:00 PM PDT 24 |
Apr 28 03:42:46 PM PDT 24 |
156812698 ps |
| T445 |
/workspace/coverage/default/44.sram_ctrl_regwen.1590315370 |
|
|
Apr 28 03:42:28 PM PDT 24 |
Apr 28 03:56:57 PM PDT 24 |
24659167138 ps |
| T446 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.2708246244 |
|
|
Apr 28 03:40:03 PM PDT 24 |
Apr 28 03:40:18 PM PDT 24 |
137297259 ps |
| T447 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.707098145 |
|
|
Apr 28 03:41:23 PM PDT 24 |
Apr 28 03:47:17 PM PDT 24 |
14926013646 ps |
| T448 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2158748118 |
|
|
Apr 28 03:39:35 PM PDT 24 |
Apr 28 03:42:15 PM PDT 24 |
314131802 ps |
| T449 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2670085962 |
|
|
Apr 28 03:39:57 PM PDT 24 |
Apr 28 03:42:20 PM PDT 24 |
151373186 ps |
| T450 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3168512244 |
|
|
Apr 28 03:40:15 PM PDT 24 |
Apr 28 03:46:03 PM PDT 24 |
3610580342 ps |
| T451 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1772617918 |
|
|
Apr 28 03:42:19 PM PDT 24 |
Apr 28 03:42:29 PM PDT 24 |
8428460492 ps |
| T452 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.950233413 |
|
|
Apr 28 03:40:01 PM PDT 24 |
Apr 28 03:47:12 PM PDT 24 |
20974060345 ps |
| T453 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.804467568 |
|
|
Apr 28 03:41:40 PM PDT 24 |
Apr 28 03:46:23 PM PDT 24 |
11807017218 ps |
| T454 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.667114008 |
|
|
Apr 28 03:39:45 PM PDT 24 |
Apr 28 03:39:48 PM PDT 24 |
69287246 ps |
| T455 |
/workspace/coverage/default/0.sram_ctrl_regwen.223777170 |
|
|
Apr 28 03:39:19 PM PDT 24 |
Apr 28 03:59:28 PM PDT 24 |
5870312379 ps |
| T456 |
/workspace/coverage/default/15.sram_ctrl_smoke.1450373292 |
|
|
Apr 28 03:40:15 PM PDT 24 |
Apr 28 03:40:25 PM PDT 24 |
57261948 ps |
| T457 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3628675801 |
|
|
Apr 28 03:42:20 PM PDT 24 |
Apr 28 03:42:33 PM PDT 24 |
147022706 ps |
| T458 |
/workspace/coverage/default/32.sram_ctrl_regwen.1473754043 |
|
|
Apr 28 03:41:19 PM PDT 24 |
Apr 28 04:04:39 PM PDT 24 |
24280295216 ps |
| T459 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.4049452380 |
|
|
Apr 28 03:42:09 PM PDT 24 |
Apr 28 03:45:36 PM PDT 24 |
2352947453 ps |
| T460 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.102219919 |
|
|
Apr 28 03:40:26 PM PDT 24 |
Apr 28 03:40:27 PM PDT 24 |
84591838 ps |
| T461 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3872505128 |
|
|
Apr 28 03:41:22 PM PDT 24 |
Apr 28 03:41:23 PM PDT 24 |
13072576 ps |
| T462 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2784613309 |
|
|
Apr 28 03:41:59 PM PDT 24 |
Apr 28 03:42:20 PM PDT 24 |
3024203607 ps |
| T93 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3436735422 |
|
|
Apr 28 03:40:53 PM PDT 24 |
Apr 28 03:41:16 PM PDT 24 |
2297160422 ps |
| T463 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2725907341 |
|
|
Apr 28 03:39:46 PM PDT 24 |
Apr 28 03:39:52 PM PDT 24 |
752831353 ps |
| T464 |
/workspace/coverage/default/6.sram_ctrl_bijection.1026357387 |
|
|
Apr 28 03:39:43 PM PDT 24 |
Apr 28 03:40:50 PM PDT 24 |
6091474087 ps |
| T465 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.489836541 |
|
|
Apr 28 03:41:14 PM PDT 24 |
Apr 28 03:41:15 PM PDT 24 |
27328964 ps |
| T466 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2129832813 |
|
|
Apr 28 03:41:32 PM PDT 24 |
Apr 28 04:57:11 PM PDT 24 |
78043479235 ps |
| T467 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3875530968 |
|
|
Apr 28 03:39:56 PM PDT 24 |
Apr 28 03:40:01 PM PDT 24 |
253855333 ps |
| T468 |
/workspace/coverage/default/48.sram_ctrl_alert_test.283551228 |
|
|
Apr 28 03:42:57 PM PDT 24 |
Apr 28 03:42:58 PM PDT 24 |
56458584 ps |
| T469 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.354290436 |
|
|
Apr 28 03:40:05 PM PDT 24 |
Apr 28 03:48:08 PM PDT 24 |
40685355513 ps |
| T470 |
/workspace/coverage/default/25.sram_ctrl_executable.2446524736 |
|
|
Apr 28 03:40:44 PM PDT 24 |
Apr 28 04:06:06 PM PDT 24 |
6691295714 ps |
| T471 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4252993600 |
|
|
Apr 28 03:40:54 PM PDT 24 |
Apr 28 03:42:01 PM PDT 24 |
134928338 ps |
| T472 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2843296887 |
|
|
Apr 28 03:40:08 PM PDT 24 |
Apr 28 03:46:59 PM PDT 24 |
3468256836 ps |
| T473 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3544512330 |
|
|
Apr 28 03:40:02 PM PDT 24 |
Apr 28 03:40:08 PM PDT 24 |
305652312 ps |
| T474 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.4089561776 |
|
|
Apr 28 03:40:20 PM PDT 24 |
Apr 28 03:40:38 PM PDT 24 |
318949141 ps |
| T475 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1828898495 |
|
|
Apr 28 03:42:20 PM PDT 24 |
Apr 28 03:42:26 PM PDT 24 |
609629994 ps |
| T476 |
/workspace/coverage/default/5.sram_ctrl_executable.269730548 |
|
|
Apr 28 03:39:43 PM PDT 24 |
Apr 28 03:48:23 PM PDT 24 |
31807521885 ps |
| T477 |
/workspace/coverage/default/35.sram_ctrl_regwen.2006311148 |
|
|
Apr 28 03:41:33 PM PDT 24 |
Apr 28 03:48:23 PM PDT 24 |
5824768663 ps |
| T478 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.441498828 |
|
|
Apr 28 03:40:36 PM PDT 24 |
Apr 28 03:40:39 PM PDT 24 |
300497338 ps |
| T479 |
/workspace/coverage/default/6.sram_ctrl_regwen.3489512579 |
|
|
Apr 28 03:39:39 PM PDT 24 |
Apr 28 03:58:21 PM PDT 24 |
8920953586 ps |
| T480 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.2153710636 |
|
|
Apr 28 03:40:57 PM PDT 24 |
Apr 28 03:41:01 PM PDT 24 |
93932357 ps |
| T481 |
/workspace/coverage/default/35.sram_ctrl_executable.3252966369 |
|
|
Apr 28 03:41:31 PM PDT 24 |
Apr 28 03:54:44 PM PDT 24 |
2909512353 ps |
| T482 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1882187423 |
|
|
Apr 28 03:42:37 PM PDT 24 |
Apr 28 03:42:38 PM PDT 24 |
83297746 ps |
| T483 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2081411618 |
|
|
Apr 28 03:41:50 PM PDT 24 |
Apr 28 03:44:49 PM PDT 24 |
611747692 ps |
| T484 |
/workspace/coverage/default/18.sram_ctrl_stress_all.3930175267 |
|
|
Apr 28 03:40:20 PM PDT 24 |
Apr 28 05:23:10 PM PDT 24 |
80868593616 ps |
| T485 |
/workspace/coverage/default/36.sram_ctrl_regwen.2221541389 |
|
|
Apr 28 03:41:36 PM PDT 24 |
Apr 28 03:42:15 PM PDT 24 |
1431906744 ps |
| T486 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3327830759 |
|
|
Apr 28 03:42:41 PM PDT 24 |
Apr 28 03:42:42 PM PDT 24 |
29464569 ps |
| T487 |
/workspace/coverage/default/26.sram_ctrl_stress_all.3227445708 |
|
|
Apr 28 03:40:55 PM PDT 24 |
Apr 28 05:05:22 PM PDT 24 |
22769085042 ps |
| T488 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1712417684 |
|
|
Apr 28 03:40:14 PM PDT 24 |
Apr 28 03:40:15 PM PDT 24 |
36572975 ps |
| T489 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1484714039 |
|
|
Apr 28 03:40:12 PM PDT 24 |
Apr 28 03:40:14 PM PDT 24 |
30226757 ps |
| T490 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1827025874 |
|
|
Apr 28 03:40:56 PM PDT 24 |
Apr 28 03:45:45 PM PDT 24 |
503332752 ps |
| T491 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3947392453 |
|
|
Apr 28 03:42:04 PM PDT 24 |
Apr 28 03:51:43 PM PDT 24 |
1392936930 ps |
| T492 |
/workspace/coverage/default/3.sram_ctrl_partial_access.618812827 |
|
|
Apr 28 03:39:33 PM PDT 24 |
Apr 28 03:40:07 PM PDT 24 |
510996291 ps |
| T493 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3599894132 |
|
|
Apr 28 03:39:59 PM PDT 24 |
Apr 28 03:40:20 PM PDT 24 |
692583097 ps |
| T494 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2975540034 |
|
|
Apr 28 03:41:56 PM PDT 24 |
Apr 28 03:41:59 PM PDT 24 |
123262967 ps |
| T495 |
/workspace/coverage/default/1.sram_ctrl_partial_access.3471378639 |
|
|
Apr 28 03:39:27 PM PDT 24 |
Apr 28 03:39:36 PM PDT 24 |
896248532 ps |
| T496 |
/workspace/coverage/default/27.sram_ctrl_smoke.2784618597 |
|
|
Apr 28 03:40:52 PM PDT 24 |
Apr 28 03:41:01 PM PDT 24 |
323281222 ps |
| T497 |
/workspace/coverage/default/15.sram_ctrl_alert_test.3525612671 |
|
|
Apr 28 03:40:10 PM PDT 24 |
Apr 28 03:40:11 PM PDT 24 |
176832310 ps |
| T94 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3642632534 |
|
|
Apr 28 03:42:12 PM PDT 24 |
Apr 28 03:42:29 PM PDT 24 |
671510722 ps |
| T498 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2284310076 |
|
|
Apr 28 03:39:58 PM PDT 24 |
Apr 28 03:42:35 PM PDT 24 |
2167125459 ps |
| T499 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2341753568 |
|
|
Apr 28 03:41:17 PM PDT 24 |
Apr 28 03:41:20 PM PDT 24 |
178007846 ps |
| T500 |
/workspace/coverage/default/12.sram_ctrl_regwen.1818319042 |
|
|
Apr 28 03:39:56 PM PDT 24 |
Apr 28 03:47:55 PM PDT 24 |
6929325750 ps |
| T501 |
/workspace/coverage/default/43.sram_ctrl_partial_access.4246459289 |
|
|
Apr 28 03:42:15 PM PDT 24 |
Apr 28 03:42:24 PM PDT 24 |
1488098223 ps |
| T502 |
/workspace/coverage/default/30.sram_ctrl_executable.981494656 |
|
|
Apr 28 03:41:09 PM PDT 24 |
Apr 28 03:45:34 PM PDT 24 |
17451409933 ps |
| T503 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.970796703 |
|
|
Apr 28 03:39:33 PM PDT 24 |
Apr 28 03:39:34 PM PDT 24 |
174183503 ps |
| T504 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.416119650 |
|
|
Apr 28 03:39:36 PM PDT 24 |
Apr 28 03:39:42 PM PDT 24 |
875958573 ps |
| T505 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2638020329 |
|
|
Apr 28 03:39:49 PM PDT 24 |
Apr 28 03:39:55 PM PDT 24 |
663116883 ps |
| T506 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3796089138 |
|
|
Apr 28 03:39:21 PM PDT 24 |
Apr 28 03:41:02 PM PDT 24 |
1175168686 ps |
| T507 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.431276136 |
|
|
Apr 28 03:40:58 PM PDT 24 |
Apr 28 03:41:04 PM PDT 24 |
147341090 ps |
| T508 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.2669389707 |
|
|
Apr 28 03:42:37 PM PDT 24 |
Apr 28 03:42:42 PM PDT 24 |
278765841 ps |
| T509 |
/workspace/coverage/default/32.sram_ctrl_partial_access.402017718 |
|
|
Apr 28 03:41:17 PM PDT 24 |
Apr 28 03:41:19 PM PDT 24 |
303011154 ps |
| T510 |
/workspace/coverage/default/37.sram_ctrl_partial_access.1363908931 |
|
|
Apr 28 03:41:44 PM PDT 24 |
Apr 28 03:42:00 PM PDT 24 |
326416395 ps |
| T511 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2284034597 |
|
|
Apr 28 03:41:17 PM PDT 24 |
Apr 28 03:41:19 PM PDT 24 |
54928017 ps |
| T512 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.2554341122 |
|
|
Apr 28 03:41:04 PM PDT 24 |
Apr 28 03:41:05 PM PDT 24 |
29473066 ps |
| T513 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1897011115 |
|
|
Apr 28 03:41:48 PM PDT 24 |
Apr 28 04:37:09 PM PDT 24 |
163979523249 ps |
| T514 |
/workspace/coverage/default/23.sram_ctrl_regwen.243003588 |
|
|
Apr 28 03:40:36 PM PDT 24 |
Apr 28 04:01:14 PM PDT 24 |
24920197701 ps |
| T515 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.3611377838 |
|
|
Apr 28 03:40:14 PM PDT 24 |
Apr 28 03:40:17 PM PDT 24 |
326334508 ps |
| T516 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.4060662018 |
|
|
Apr 28 03:40:56 PM PDT 24 |
Apr 28 03:55:24 PM PDT 24 |
7107699727 ps |
| T517 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3548320779 |
|
|
Apr 28 03:41:23 PM PDT 24 |
Apr 28 03:42:35 PM PDT 24 |
464859793 ps |
| T518 |
/workspace/coverage/default/25.sram_ctrl_alert_test.1600438329 |
|
|
Apr 28 03:40:45 PM PDT 24 |
Apr 28 03:40:46 PM PDT 24 |
17492264 ps |
| T519 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1418317440 |
|
|
Apr 28 03:39:22 PM PDT 24 |
Apr 28 03:39:27 PM PDT 24 |
237812705 ps |
| T520 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1714169166 |
|
|
Apr 28 03:39:56 PM PDT 24 |
Apr 28 03:47:29 PM PDT 24 |
8619624181 ps |
| T521 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1769475300 |
|
|
Apr 28 03:41:57 PM PDT 24 |
Apr 28 04:08:58 PM PDT 24 |
3849564712 ps |
| T522 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.2784288926 |
|
|
Apr 28 03:41:50 PM PDT 24 |
Apr 28 03:41:51 PM PDT 24 |
180144398 ps |
| T523 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.17401866 |
|
|
Apr 28 03:39:26 PM PDT 24 |
Apr 28 03:39:54 PM PDT 24 |
385649955 ps |
| T524 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2551740016 |
|
|
Apr 28 03:39:58 PM PDT 24 |
Apr 28 03:40:04 PM PDT 24 |
1681357998 ps |
| T525 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2805034709 |
|
|
Apr 28 03:40:27 PM PDT 24 |
Apr 28 03:40:49 PM PDT 24 |
321061389 ps |
| T526 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3160860518 |
|
|
Apr 28 03:39:41 PM PDT 24 |
Apr 28 03:43:28 PM PDT 24 |
6775438181 ps |
| T527 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1655854914 |
|
|
Apr 28 03:40:57 PM PDT 24 |
Apr 28 03:43:35 PM PDT 24 |
7555257654 ps |
| T528 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.595411240 |
|
|
Apr 28 03:40:45 PM PDT 24 |
Apr 28 03:40:53 PM PDT 24 |
551200403 ps |
| T529 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1801382343 |
|
|
Apr 28 03:41:36 PM PDT 24 |
Apr 28 03:48:02 PM PDT 24 |
17612528405 ps |
| T530 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3119001139 |
|
|
Apr 28 03:40:42 PM PDT 24 |
Apr 28 03:46:18 PM PDT 24 |
14253895537 ps |
| T531 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3656171910 |
|
|
Apr 28 03:40:14 PM PDT 24 |
Apr 28 03:41:00 PM PDT 24 |
1469198405 ps |
| T532 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.196472789 |
|
|
Apr 28 03:39:20 PM PDT 24 |
Apr 28 03:42:03 PM PDT 24 |
1703539211 ps |
| T533 |
/workspace/coverage/default/44.sram_ctrl_executable.1111072877 |
|
|
Apr 28 03:42:28 PM PDT 24 |
Apr 28 04:05:00 PM PDT 24 |
22990138548 ps |
| T534 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3948245171 |
|
|
Apr 28 03:39:20 PM PDT 24 |
Apr 28 03:39:25 PM PDT 24 |
1548978574 ps |
| T535 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3682916240 |
|
|
Apr 28 03:39:48 PM PDT 24 |
Apr 28 03:39:54 PM PDT 24 |
863500066 ps |
| T536 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.3887579360 |
|
|
Apr 28 03:42:02 PM PDT 24 |
Apr 28 03:42:11 PM PDT 24 |
943661765 ps |
| T537 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.4235382040 |
|
|
Apr 28 03:40:26 PM PDT 24 |
Apr 28 03:40:46 PM PDT 24 |
168862879 ps |
| T538 |
/workspace/coverage/default/6.sram_ctrl_partial_access.3728237139 |
|
|
Apr 28 03:39:46 PM PDT 24 |
Apr 28 03:40:00 PM PDT 24 |
2749538524 ps |