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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total test records in report: 1023
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T786 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2691489845 Apr 28 03:39:59 PM PDT 24 Apr 28 03:47:46 PM PDT 24 11597517964 ps
T787 /workspace/coverage/default/34.sram_ctrl_lc_escalation.3392110709 Apr 28 03:41:28 PM PDT 24 Apr 28 03:41:35 PM PDT 24 487433285 ps
T788 /workspace/coverage/default/21.sram_ctrl_partial_access.2001703125 Apr 28 03:40:35 PM PDT 24 Apr 28 03:41:28 PM PDT 24 444658452 ps
T789 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.4271525861 Apr 28 03:40:06 PM PDT 24 Apr 28 03:40:12 PM PDT 24 2982608316 ps
T790 /workspace/coverage/default/5.sram_ctrl_ram_cfg.1098639520 Apr 28 03:39:39 PM PDT 24 Apr 28 03:39:41 PM PDT 24 47453150 ps
T791 /workspace/coverage/default/34.sram_ctrl_smoke.507855314 Apr 28 03:41:22 PM PDT 24 Apr 28 03:41:33 PM PDT 24 521856073 ps
T792 /workspace/coverage/default/38.sram_ctrl_multiple_keys.3809001988 Apr 28 03:41:47 PM PDT 24 Apr 28 04:12:54 PM PDT 24 3386522093 ps
T793 /workspace/coverage/default/12.sram_ctrl_smoke.313119102 Apr 28 03:39:57 PM PDT 24 Apr 28 03:40:12 PM PDT 24 268647865 ps
T794 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1261455641 Apr 28 03:42:47 PM PDT 24 Apr 28 03:49:24 PM PDT 24 3228357668 ps
T795 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3719813486 Apr 28 03:41:18 PM PDT 24 Apr 28 03:59:12 PM PDT 24 3528891678 ps
T796 /workspace/coverage/default/7.sram_ctrl_partial_access.3658517255 Apr 28 03:40:08 PM PDT 24 Apr 28 03:40:20 PM PDT 24 940972392 ps
T797 /workspace/coverage/default/12.sram_ctrl_alert_test.517878954 Apr 28 03:40:00 PM PDT 24 Apr 28 03:40:02 PM PDT 24 17258195 ps
T798 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.4096360808 Apr 28 03:41:05 PM PDT 24 Apr 28 03:46:09 PM PDT 24 1008201730 ps
T799 /workspace/coverage/default/7.sram_ctrl_multiple_keys.520180895 Apr 28 03:40:03 PM PDT 24 Apr 28 03:42:46 PM PDT 24 3431326125 ps
T800 /workspace/coverage/default/48.sram_ctrl_ram_cfg.868838312 Apr 28 03:42:56 PM PDT 24 Apr 28 03:42:57 PM PDT 24 94563452 ps
T801 /workspace/coverage/default/17.sram_ctrl_mem_walk.4042209102 Apr 28 03:40:18 PM PDT 24 Apr 28 03:40:29 PM PDT 24 1134501116 ps
T802 /workspace/coverage/default/0.sram_ctrl_partial_access.637786626 Apr 28 03:39:21 PM PDT 24 Apr 28 03:39:25 PM PDT 24 219392002 ps
T803 /workspace/coverage/default/34.sram_ctrl_partial_access.4186241214 Apr 28 03:41:26 PM PDT 24 Apr 28 03:41:42 PM PDT 24 624686951 ps
T804 /workspace/coverage/default/28.sram_ctrl_lc_escalation.526402872 Apr 28 03:40:56 PM PDT 24 Apr 28 03:41:03 PM PDT 24 2042551331 ps
T805 /workspace/coverage/default/30.sram_ctrl_bijection.3685098785 Apr 28 03:41:03 PM PDT 24 Apr 28 03:42:13 PM PDT 24 4756455020 ps
T806 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1091705894 Apr 28 03:39:35 PM PDT 24 Apr 28 03:41:33 PM PDT 24 5008224907 ps
T807 /workspace/coverage/default/4.sram_ctrl_executable.3894997200 Apr 28 03:39:33 PM PDT 24 Apr 28 03:54:11 PM PDT 24 17058480788 ps
T808 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.3214622721 Apr 28 03:41:29 PM PDT 24 Apr 28 03:46:48 PM PDT 24 15705257046 ps
T809 /workspace/coverage/default/49.sram_ctrl_smoke.3721356025 Apr 28 03:42:59 PM PDT 24 Apr 28 03:44:24 PM PDT 24 558470161 ps
T810 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.50501308 Apr 28 03:41:58 PM PDT 24 Apr 28 03:43:13 PM PDT 24 427887090 ps
T811 /workspace/coverage/default/46.sram_ctrl_max_throughput.328022049 Apr 28 03:42:42 PM PDT 24 Apr 28 03:44:06 PM PDT 24 393884033 ps
T812 /workspace/coverage/default/43.sram_ctrl_ram_cfg.2171608549 Apr 28 03:42:21 PM PDT 24 Apr 28 03:42:22 PM PDT 24 35375043 ps
T813 /workspace/coverage/default/46.sram_ctrl_executable.693428038 Apr 28 03:42:47 PM PDT 24 Apr 28 04:07:01 PM PDT 24 107791937523 ps
T814 /workspace/coverage/default/20.sram_ctrl_alert_test.3473671330 Apr 28 03:40:35 PM PDT 24 Apr 28 03:40:36 PM PDT 24 22314995 ps
T31 /workspace/coverage/default/3.sram_ctrl_sec_cm.3932341275 Apr 28 03:39:30 PM PDT 24 Apr 28 03:39:34 PM PDT 24 474123031 ps
T815 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3803276793 Apr 28 03:41:26 PM PDT 24 Apr 28 03:42:26 PM PDT 24 162157888 ps
T816 /workspace/coverage/default/40.sram_ctrl_stress_all.897553497 Apr 28 03:42:02 PM PDT 24 Apr 28 04:31:47 PM PDT 24 36786357467 ps
T817 /workspace/coverage/default/24.sram_ctrl_regwen.141253996 Apr 28 03:40:39 PM PDT 24 Apr 28 03:48:11 PM PDT 24 22794533822 ps
T818 /workspace/coverage/default/32.sram_ctrl_executable.2900839503 Apr 28 03:41:18 PM PDT 24 Apr 28 04:13:27 PM PDT 24 30097739718 ps
T819 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2152561852 Apr 28 03:40:55 PM PDT 24 Apr 28 03:46:44 PM PDT 24 15440395067 ps
T820 /workspace/coverage/default/13.sram_ctrl_smoke.2005071829 Apr 28 03:39:56 PM PDT 24 Apr 28 03:40:10 PM PDT 24 2666407294 ps
T821 /workspace/coverage/default/45.sram_ctrl_stress_all.3729047515 Apr 28 03:42:39 PM PDT 24 Apr 28 04:36:49 PM PDT 24 15234051882 ps
T822 /workspace/coverage/default/18.sram_ctrl_alert_test.3522884412 Apr 28 03:40:21 PM PDT 24 Apr 28 03:40:23 PM PDT 24 12736469 ps
T823 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1823499918 Apr 28 03:40:06 PM PDT 24 Apr 28 03:45:44 PM PDT 24 13718473362 ps
T824 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1078115290 Apr 28 03:40:30 PM PDT 24 Apr 28 04:01:22 PM PDT 24 4508317097 ps
T825 /workspace/coverage/default/43.sram_ctrl_regwen.3835263891 Apr 28 03:42:19 PM PDT 24 Apr 28 04:02:25 PM PDT 24 69328536286 ps
T826 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2623721351 Apr 28 03:40:20 PM PDT 24 Apr 28 03:54:51 PM PDT 24 3408104743 ps
T827 /workspace/coverage/default/47.sram_ctrl_multiple_keys.2177185578 Apr 28 03:42:47 PM PDT 24 Apr 28 04:14:51 PM PDT 24 13233751244 ps
T828 /workspace/coverage/default/23.sram_ctrl_multiple_keys.2236433594 Apr 28 03:40:40 PM PDT 24 Apr 28 03:45:58 PM PDT 24 6626664004 ps
T829 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1355470034 Apr 28 03:40:30 PM PDT 24 Apr 28 03:50:01 PM PDT 24 22422033683 ps
T830 /workspace/coverage/default/38.sram_ctrl_bijection.2145544846 Apr 28 03:41:49 PM PDT 24 Apr 28 03:42:43 PM PDT 24 6148342360 ps
T831 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.604690927 Apr 28 03:43:01 PM PDT 24 Apr 28 03:43:06 PM PDT 24 95251086 ps
T832 /workspace/coverage/default/22.sram_ctrl_lc_escalation.2664898180 Apr 28 03:40:38 PM PDT 24 Apr 28 03:40:47 PM PDT 24 2848417272 ps
T833 /workspace/coverage/default/41.sram_ctrl_multiple_keys.325404999 Apr 28 03:42:02 PM PDT 24 Apr 28 03:58:56 PM PDT 24 1779992550 ps
T834 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2753404460 Apr 28 03:40:34 PM PDT 24 Apr 28 03:47:32 PM PDT 24 21755596431 ps
T835 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3112511396 Apr 28 03:40:44 PM PDT 24 Apr 28 03:41:24 PM PDT 24 502668873 ps
T836 /workspace/coverage/default/32.sram_ctrl_ram_cfg.942256746 Apr 28 03:41:20 PM PDT 24 Apr 28 03:41:21 PM PDT 24 106166628 ps
T837 /workspace/coverage/default/37.sram_ctrl_regwen.1890585431 Apr 28 03:41:49 PM PDT 24 Apr 28 03:59:33 PM PDT 24 6745894532 ps
T838 /workspace/coverage/default/33.sram_ctrl_ram_cfg.1561482397 Apr 28 03:41:22 PM PDT 24 Apr 28 03:41:23 PM PDT 24 92168898 ps
T839 /workspace/coverage/default/25.sram_ctrl_stress_all.441073299 Apr 28 03:40:43 PM PDT 24 Apr 28 04:57:40 PM PDT 24 168663893938 ps
T840 /workspace/coverage/default/45.sram_ctrl_smoke.2160361598 Apr 28 03:42:34 PM PDT 24 Apr 28 03:42:43 PM PDT 24 421422197 ps
T841 /workspace/coverage/default/8.sram_ctrl_stress_all.3776234332 Apr 28 03:39:50 PM PDT 24 Apr 28 05:08:49 PM PDT 24 25586033763 ps
T842 /workspace/coverage/default/19.sram_ctrl_alert_test.164270170 Apr 28 03:40:30 PM PDT 24 Apr 28 03:40:32 PM PDT 24 49025327 ps
T843 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3030710520 Apr 28 03:39:24 PM PDT 24 Apr 28 03:39:30 PM PDT 24 171508909 ps
T844 /workspace/coverage/default/24.sram_ctrl_bijection.2939251150 Apr 28 03:40:44 PM PDT 24 Apr 28 03:41:51 PM PDT 24 17709071702 ps
T845 /workspace/coverage/default/23.sram_ctrl_mem_walk.1151970988 Apr 28 03:40:38 PM PDT 24 Apr 28 03:40:44 PM PDT 24 72342586 ps
T846 /workspace/coverage/default/0.sram_ctrl_lc_escalation.1879421895 Apr 28 03:39:19 PM PDT 24 Apr 28 03:39:28 PM PDT 24 10097399468 ps
T847 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.699479363 Apr 28 03:42:23 PM PDT 24 Apr 28 03:46:19 PM PDT 24 14476554618 ps
T848 /workspace/coverage/default/36.sram_ctrl_smoke.559173714 Apr 28 03:41:35 PM PDT 24 Apr 28 03:41:52 PM PDT 24 3917969139 ps
T849 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1985254222 Apr 28 03:40:14 PM PDT 24 Apr 28 04:14:00 PM PDT 24 7455509061 ps
T850 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.4251725594 Apr 28 03:40:01 PM PDT 24 Apr 28 03:40:21 PM PDT 24 236303075 ps
T851 /workspace/coverage/default/46.sram_ctrl_alert_test.2082070730 Apr 28 03:42:47 PM PDT 24 Apr 28 03:42:48 PM PDT 24 12821204 ps
T852 /workspace/coverage/default/33.sram_ctrl_bijection.3223917484 Apr 28 03:41:21 PM PDT 24 Apr 28 03:42:23 PM PDT 24 3012204907 ps
T853 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3462412691 Apr 28 03:42:25 PM PDT 24 Apr 28 03:49:23 PM PDT 24 17644991385 ps
T854 /workspace/coverage/default/3.sram_ctrl_executable.2938540160 Apr 28 03:39:31 PM PDT 24 Apr 28 03:56:37 PM PDT 24 9192863561 ps
T855 /workspace/coverage/default/27.sram_ctrl_max_throughput.990965585 Apr 28 03:40:54 PM PDT 24 Apr 28 03:41:26 PM PDT 24 87266289 ps
T856 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3709205848 Apr 28 03:41:54 PM PDT 24 Apr 28 03:50:35 PM PDT 24 22544056904 ps
T857 /workspace/coverage/default/44.sram_ctrl_multiple_keys.3581379618 Apr 28 03:42:27 PM PDT 24 Apr 28 04:03:03 PM PDT 24 7662789812 ps
T858 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3259770394 Apr 28 03:39:30 PM PDT 24 Apr 28 03:45:24 PM PDT 24 5174045522 ps
T859 /workspace/coverage/default/35.sram_ctrl_multiple_keys.363641719 Apr 28 03:41:31 PM PDT 24 Apr 28 04:05:12 PM PDT 24 12523335188 ps
T860 /workspace/coverage/default/18.sram_ctrl_ram_cfg.70001353 Apr 28 03:40:19 PM PDT 24 Apr 28 03:40:20 PM PDT 24 85371488 ps
T861 /workspace/coverage/default/13.sram_ctrl_alert_test.1364436825 Apr 28 03:40:04 PM PDT 24 Apr 28 03:40:05 PM PDT 24 21457472 ps
T862 /workspace/coverage/default/46.sram_ctrl_lc_escalation.3121446854 Apr 28 03:42:47 PM PDT 24 Apr 28 03:42:51 PM PDT 24 279241158 ps
T863 /workspace/coverage/default/0.sram_ctrl_ram_cfg.649021641 Apr 28 03:39:16 PM PDT 24 Apr 28 03:39:17 PM PDT 24 103991745 ps
T864 /workspace/coverage/default/10.sram_ctrl_executable.2127850000 Apr 28 03:39:51 PM PDT 24 Apr 28 03:45:50 PM PDT 24 11371258111 ps
T865 /workspace/coverage/default/22.sram_ctrl_smoke.402802935 Apr 28 03:40:35 PM PDT 24 Apr 28 03:41:46 PM PDT 24 1560069214 ps
T866 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1742516388 Apr 28 03:40:54 PM PDT 24 Apr 28 03:45:18 PM PDT 24 2798827822 ps
T867 /workspace/coverage/default/33.sram_ctrl_mem_walk.1010648761 Apr 28 03:41:23 PM PDT 24 Apr 28 03:41:28 PM PDT 24 236350905 ps
T868 /workspace/coverage/default/17.sram_ctrl_ram_cfg.3494748777 Apr 28 03:40:16 PM PDT 24 Apr 28 03:40:17 PM PDT 24 62735704 ps
T869 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.748314446 Apr 28 03:42:33 PM PDT 24 Apr 28 03:46:37 PM PDT 24 34492155858 ps
T870 /workspace/coverage/default/43.sram_ctrl_stress_all.2840411790 Apr 28 03:42:23 PM PDT 24 Apr 28 04:53:29 PM PDT 24 30222047839 ps
T871 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1023817829 Apr 28 03:40:08 PM PDT 24 Apr 28 03:44:00 PM PDT 24 2508055494 ps
T872 /workspace/coverage/default/41.sram_ctrl_ram_cfg.3107294177 Apr 28 03:42:07 PM PDT 24 Apr 28 03:42:08 PM PDT 24 28118512 ps
T873 /workspace/coverage/default/11.sram_ctrl_executable.1222384486 Apr 28 03:39:58 PM PDT 24 Apr 28 03:53:17 PM PDT 24 7561255372 ps
T874 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2165334038 Apr 28 03:42:29 PM PDT 24 Apr 28 03:44:48 PM PDT 24 195195049 ps
T875 /workspace/coverage/default/17.sram_ctrl_stress_all.876212828 Apr 28 03:40:14 PM PDT 24 Apr 28 04:28:43 PM PDT 24 25710229126 ps
T876 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.124666391 Apr 28 03:39:34 PM PDT 24 Apr 28 03:45:48 PM PDT 24 43129623734 ps
T877 /workspace/coverage/default/14.sram_ctrl_ram_cfg.884399018 Apr 28 03:40:15 PM PDT 24 Apr 28 03:40:16 PM PDT 24 97797801 ps
T878 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1405971491 Apr 28 03:40:40 PM PDT 24 Apr 28 03:44:23 PM PDT 24 3614820780 ps
T879 /workspace/coverage/default/47.sram_ctrl_executable.3748442981 Apr 28 03:42:45 PM PDT 24 Apr 28 04:04:50 PM PDT 24 8322322044 ps
T880 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3079220494 Apr 28 03:40:30 PM PDT 24 Apr 28 03:44:46 PM PDT 24 23173352916 ps
T881 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.694534300 Apr 28 03:39:57 PM PDT 24 Apr 28 03:41:11 PM PDT 24 125464448 ps
T882 /workspace/coverage/default/13.sram_ctrl_lc_escalation.3521263326 Apr 28 03:40:02 PM PDT 24 Apr 28 03:40:09 PM PDT 24 1152037596 ps
T883 /workspace/coverage/default/41.sram_ctrl_partial_access.499599249 Apr 28 03:42:07 PM PDT 24 Apr 28 03:43:18 PM PDT 24 907873040 ps
T884 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1969056464 Apr 28 03:40:40 PM PDT 24 Apr 28 03:44:12 PM PDT 24 30149976106 ps
T885 /workspace/coverage/default/34.sram_ctrl_bijection.2100530986 Apr 28 03:41:28 PM PDT 24 Apr 28 03:41:50 PM PDT 24 3810107196 ps
T886 /workspace/coverage/default/39.sram_ctrl_regwen.1937786779 Apr 28 03:41:58 PM PDT 24 Apr 28 03:49:28 PM PDT 24 11272710177 ps
T887 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2978566187 Apr 28 03:41:34 PM PDT 24 Apr 28 03:43:46 PM PDT 24 1721394228 ps
T888 /workspace/coverage/default/32.sram_ctrl_multiple_keys.2389133696 Apr 28 03:41:16 PM PDT 24 Apr 28 03:54:51 PM PDT 24 13314819169 ps
T889 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3631275473 Apr 28 03:39:44 PM PDT 24 Apr 28 03:39:47 PM PDT 24 340415554 ps
T890 /workspace/coverage/default/42.sram_ctrl_multiple_keys.4162087567 Apr 28 03:42:11 PM PDT 24 Apr 28 03:56:40 PM PDT 24 11854836758 ps
T891 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2533375155 Apr 28 03:40:30 PM PDT 24 Apr 28 03:45:17 PM PDT 24 6859557876 ps
T892 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4099366836 Apr 28 03:41:14 PM PDT 24 Apr 28 03:50:08 PM PDT 24 5387104626 ps
T893 /workspace/coverage/default/48.sram_ctrl_smoke.2498503353 Apr 28 03:42:50 PM PDT 24 Apr 28 03:43:01 PM PDT 24 1586284511 ps
T894 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3203912468 Apr 28 03:41:33 PM PDT 24 Apr 28 03:48:58 PM PDT 24 88592307789 ps
T895 /workspace/coverage/default/18.sram_ctrl_lc_escalation.1693123860 Apr 28 03:40:19 PM PDT 24 Apr 28 03:40:23 PM PDT 24 1178607788 ps
T896 /workspace/coverage/default/18.sram_ctrl_max_throughput.1414257192 Apr 28 03:40:20 PM PDT 24 Apr 28 03:40:27 PM PDT 24 99525509 ps
T897 /workspace/coverage/default/28.sram_ctrl_partial_access.2300532496 Apr 28 03:40:55 PM PDT 24 Apr 28 03:41:04 PM PDT 24 1380317471 ps
T898 /workspace/coverage/default/7.sram_ctrl_ram_cfg.3238990356 Apr 28 03:40:02 PM PDT 24 Apr 28 03:40:04 PM PDT 24 94441927 ps
T899 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2883847746 Apr 28 03:41:39 PM PDT 24 Apr 28 03:48:47 PM PDT 24 7283846409 ps
T900 /workspace/coverage/default/49.sram_ctrl_max_throughput.3791654025 Apr 28 03:42:59 PM PDT 24 Apr 28 03:43:04 PM PDT 24 65655595 ps
T901 /workspace/coverage/default/23.sram_ctrl_smoke.1644026745 Apr 28 03:40:39 PM PDT 24 Apr 28 03:40:41 PM PDT 24 38543564 ps
T902 /workspace/coverage/default/25.sram_ctrl_multiple_keys.887289636 Apr 28 03:40:47 PM PDT 24 Apr 28 03:47:20 PM PDT 24 18739775873 ps
T903 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2920487907 Apr 28 03:39:39 PM PDT 24 Apr 28 03:41:16 PM PDT 24 604130235 ps
T904 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1702854629 Apr 28 03:40:16 PM PDT 24 Apr 28 03:58:12 PM PDT 24 1206587170 ps
T905 /workspace/coverage/default/44.sram_ctrl_alert_test.1425500390 Apr 28 03:42:33 PM PDT 24 Apr 28 03:42:34 PM PDT 24 28517060 ps
T906 /workspace/coverage/default/27.sram_ctrl_partial_access.763556272 Apr 28 03:40:54 PM PDT 24 Apr 28 03:41:05 PM PDT 24 2058414549 ps
T907 /workspace/coverage/default/39.sram_ctrl_bijection.2694551037 Apr 28 03:41:55 PM PDT 24 Apr 28 03:42:38 PM PDT 24 1276732492 ps
T908 /workspace/coverage/default/40.sram_ctrl_executable.3961335029 Apr 28 03:42:04 PM PDT 24 Apr 28 03:49:03 PM PDT 24 51035176190 ps
T909 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.1986377466 Apr 28 03:41:59 PM PDT 24 Apr 28 03:42:04 PM PDT 24 623596087 ps
T910 /workspace/coverage/default/44.sram_ctrl_partial_access.1287847384 Apr 28 03:42:23 PM PDT 24 Apr 28 03:42:41 PM PDT 24 1047682531 ps
T911 /workspace/coverage/default/26.sram_ctrl_mem_walk.1324233061 Apr 28 03:40:47 PM PDT 24 Apr 28 03:40:52 PM PDT 24 145592023 ps
T912 /workspace/coverage/default/15.sram_ctrl_regwen.1058778973 Apr 28 03:40:10 PM PDT 24 Apr 28 04:06:54 PM PDT 24 3829268513 ps
T913 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1856756030 Apr 28 03:39:43 PM PDT 24 Apr 28 03:47:48 PM PDT 24 6764510086 ps
T914 /workspace/coverage/default/9.sram_ctrl_smoke.850696964 Apr 28 03:39:48 PM PDT 24 Apr 28 03:39:51 PM PDT 24 643088665 ps
T915 /workspace/coverage/default/29.sram_ctrl_bijection.3177030444 Apr 28 03:40:56 PM PDT 24 Apr 28 03:41:27 PM PDT 24 5218557021 ps
T916 /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2814146175 Apr 28 03:41:05 PM PDT 24 Apr 28 03:45:42 PM PDT 24 2988475945 ps
T917 /workspace/coverage/default/38.sram_ctrl_max_throughput.3590300114 Apr 28 03:41:54 PM PDT 24 Apr 28 03:42:22 PM PDT 24 97896305 ps
T918 /workspace/coverage/default/1.sram_ctrl_alert_test.3326171430 Apr 28 03:39:31 PM PDT 24 Apr 28 03:39:32 PM PDT 24 19792983 ps
T919 /workspace/coverage/default/1.sram_ctrl_mem_walk.1410353990 Apr 28 03:39:23 PM PDT 24 Apr 28 03:39:33 PM PDT 24 1355420564 ps
T920 /workspace/coverage/default/23.sram_ctrl_executable.3290291525 Apr 28 03:40:42 PM PDT 24 Apr 28 03:58:05 PM PDT 24 7762782297 ps
T921 /workspace/coverage/default/42.sram_ctrl_executable.1294876912 Apr 28 03:42:16 PM PDT 24 Apr 28 03:54:49 PM PDT 24 18222988164 ps
T922 /workspace/coverage/default/14.sram_ctrl_multiple_keys.2956141651 Apr 28 03:40:03 PM PDT 24 Apr 28 04:20:31 PM PDT 24 70342279366 ps
T923 /workspace/coverage/default/32.sram_ctrl_bijection.527724053 Apr 28 03:41:14 PM PDT 24 Apr 28 03:42:20 PM PDT 24 12030735342 ps
T924 /workspace/coverage/default/3.sram_ctrl_lc_escalation.2638938798 Apr 28 03:39:30 PM PDT 24 Apr 28 03:39:32 PM PDT 24 257384248 ps
T52 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3517641343 Apr 28 03:24:19 PM PDT 24 Apr 28 03:24:21 PM PDT 24 14761663 ps
T925 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1178414877 Apr 28 03:24:14 PM PDT 24 Apr 28 03:24:15 PM PDT 24 35947745 ps
T86 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2028483173 Apr 28 03:24:01 PM PDT 24 Apr 28 03:24:02 PM PDT 24 16335509 ps
T53 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1170000813 Apr 28 03:23:40 PM PDT 24 Apr 28 03:23:41 PM PDT 24 17608618 ps
T926 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.17694246 Apr 28 03:23:52 PM PDT 24 Apr 28 03:23:57 PM PDT 24 164703800 ps
T76 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3004607921 Apr 28 03:24:24 PM PDT 24 Apr 28 03:24:25 PM PDT 24 19170671 ps
T54 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3555070239 Apr 28 03:24:15 PM PDT 24 Apr 28 03:24:19 PM PDT 24 486240653 ps
T87 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3716435219 Apr 28 03:24:15 PM PDT 24 Apr 28 03:24:18 PM PDT 24 742332889 ps
T55 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1601222183 Apr 28 03:23:32 PM PDT 24 Apr 28 03:23:34 PM PDT 24 215383047 ps
T56 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1691592765 Apr 28 03:24:03 PM PDT 24 Apr 28 03:24:06 PM PDT 24 1534738176 ps
T88 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.96562856 Apr 28 03:24:28 PM PDT 24 Apr 28 03:24:31 PM PDT 24 280646345 ps
T77 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3757113145 Apr 28 03:23:56 PM PDT 24 Apr 28 03:23:58 PM PDT 24 819869791 ps
T78 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3641036978 Apr 28 03:24:00 PM PDT 24 Apr 28 03:24:02 PM PDT 24 22827256 ps
T927 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.988047074 Apr 28 03:24:22 PM PDT 24 Apr 28 03:24:25 PM PDT 24 222594666 ps
T89 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.915397838 Apr 28 03:24:22 PM PDT 24 Apr 28 03:24:26 PM PDT 24 205367631 ps
T928 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2813921976 Apr 28 03:23:30 PM PDT 24 Apr 28 03:23:32 PM PDT 24 30566089 ps
T929 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1264395732 Apr 28 03:23:21 PM PDT 24 Apr 28 03:23:22 PM PDT 24 44477737 ps
T930 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4059812612 Apr 28 03:24:23 PM PDT 24 Apr 28 03:24:24 PM PDT 24 38392528 ps
T931 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1440522906 Apr 28 03:24:01 PM PDT 24 Apr 28 03:24:02 PM PDT 24 31529214 ps
T57 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.135679257 Apr 28 03:23:40 PM PDT 24 Apr 28 03:23:41 PM PDT 24 21351305 ps
T932 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2851178926 Apr 28 03:23:59 PM PDT 24 Apr 28 03:24:02 PM PDT 24 87079950 ps
T933 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2940507055 Apr 28 03:24:21 PM PDT 24 Apr 28 03:24:25 PM PDT 24 264181648 ps
T934 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3175787879 Apr 28 03:23:52 PM PDT 24 Apr 28 03:23:53 PM PDT 24 158689236 ps
T58 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2265375945 Apr 28 03:23:45 PM PDT 24 Apr 28 03:23:49 PM PDT 24 427654660 ps
T935 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3626531224 Apr 28 03:23:45 PM PDT 24 Apr 28 03:23:49 PM PDT 24 502801110 ps
T936 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.64765873 Apr 28 03:24:27 PM PDT 24 Apr 28 03:24:28 PM PDT 24 13689227 ps
T937 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.925081257 Apr 28 03:23:25 PM PDT 24 Apr 28 03:23:26 PM PDT 24 13819872 ps
T59 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1339936560 Apr 28 03:24:17 PM PDT 24 Apr 28 03:24:19 PM PDT 24 34222646 ps
T60 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.281269744 Apr 28 03:24:19 PM PDT 24 Apr 28 03:24:23 PM PDT 24 1545619371 ps
T938 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3526809251 Apr 28 03:23:16 PM PDT 24 Apr 28 03:23:19 PM PDT 24 86028469 ps
T939 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1806916471 Apr 28 03:24:04 PM PDT 24 Apr 28 03:24:07 PM PDT 24 80659952 ps
T940 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2527341097 Apr 28 03:24:29 PM PDT 24 Apr 28 03:24:30 PM PDT 24 93681902 ps
T61 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4050733577 Apr 28 03:23:56 PM PDT 24 Apr 28 03:24:00 PM PDT 24 448603090 ps
T62 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3265071724 Apr 28 03:24:09 PM PDT 24 Apr 28 03:24:10 PM PDT 24 13057835 ps
T941 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3884706216 Apr 28 03:24:14 PM PDT 24 Apr 28 03:24:15 PM PDT 24 14661795 ps
T108 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.99963490 Apr 28 03:23:32 PM PDT 24 Apr 28 03:23:34 PM PDT 24 204199201 ps
T63 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3457093366 Apr 28 03:24:04 PM PDT 24 Apr 28 03:24:07 PM PDT 24 783156132 ps
T72 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3651156113 Apr 28 03:23:37 PM PDT 24 Apr 28 03:23:39 PM PDT 24 360826041 ps
T109 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.602639372 Apr 28 03:24:05 PM PDT 24 Apr 28 03:24:08 PM PDT 24 188256412 ps
T942 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1349576370 Apr 28 03:23:50 PM PDT 24 Apr 28 03:23:51 PM PDT 24 85984357 ps
T110 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1649691847 Apr 28 03:23:59 PM PDT 24 Apr 28 03:24:01 PM PDT 24 178317565 ps
T943 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3227180062 Apr 28 03:23:26 PM PDT 24 Apr 28 03:23:28 PM PDT 24 348228706 ps
T944 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2637918446 Apr 28 03:23:59 PM PDT 24 Apr 28 03:24:01 PM PDT 24 40980042 ps
T945 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1613997586 Apr 28 03:24:02 PM PDT 24 Apr 28 03:24:05 PM PDT 24 474627893 ps
T946 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3045149232 Apr 28 03:24:09 PM PDT 24 Apr 28 03:24:10 PM PDT 24 14931372 ps
T73 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.62287325 Apr 28 03:24:00 PM PDT 24 Apr 28 03:24:03 PM PDT 24 1456286449 ps
T75 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3452533955 Apr 28 03:23:50 PM PDT 24 Apr 28 03:23:51 PM PDT 24 12374216 ps
T947 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3476891688 Apr 28 03:23:45 PM PDT 24 Apr 28 03:23:46 PM PDT 24 45074163 ps
T948 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3751638264 Apr 28 03:24:22 PM PDT 24 Apr 28 03:24:24 PM PDT 24 20136131 ps
T111 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1277613689 Apr 28 03:23:59 PM PDT 24 Apr 28 03:24:02 PM PDT 24 172218566 ps
T949 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3988144562 Apr 28 03:24:17 PM PDT 24 Apr 28 03:24:18 PM PDT 24 41730252 ps
T950 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2929346584 Apr 28 03:23:35 PM PDT 24 Apr 28 03:23:38 PM PDT 24 337251070 ps
T951 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3117128416 Apr 28 03:23:54 PM PDT 24 Apr 28 03:23:55 PM PDT 24 98596443 ps
T952 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1668714302 Apr 28 03:23:17 PM PDT 24 Apr 28 03:23:19 PM PDT 24 933023682 ps
T74 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2457613624 Apr 28 03:24:18 PM PDT 24 Apr 28 03:24:22 PM PDT 24 3396303343 ps
T953 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1705585186 Apr 28 03:24:15 PM PDT 24 Apr 28 03:24:18 PM PDT 24 309954971 ps
T954 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4060598496 Apr 28 03:23:21 PM PDT 24 Apr 28 03:23:22 PM PDT 24 47200257 ps
T955 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1593260989 Apr 28 03:23:59 PM PDT 24 Apr 28 03:24:00 PM PDT 24 41719664 ps
T116 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3030140596 Apr 28 03:23:40 PM PDT 24 Apr 28 03:23:43 PM PDT 24 423049100 ps
T115 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1455292342 Apr 28 03:24:08 PM PDT 24 Apr 28 03:24:11 PM PDT 24 697439053 ps
T956 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1720202581 Apr 28 03:24:20 PM PDT 24 Apr 28 03:24:22 PM PDT 24 44413646 ps
T957 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.647872743 Apr 28 03:24:22 PM PDT 24 Apr 28 03:24:25 PM PDT 24 132934059 ps
T958 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4246995499 Apr 28 03:23:45 PM PDT 24 Apr 28 03:23:47 PM PDT 24 62183940 ps
T959 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1743316822 Apr 28 03:24:24 PM PDT 24 Apr 28 03:24:26 PM PDT 24 73752666 ps
T960 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3689680852 Apr 28 03:23:49 PM PDT 24 Apr 28 03:23:53 PM PDT 24 442149419 ps
T961 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.947963272 Apr 28 03:23:37 PM PDT 24 Apr 28 03:23:38 PM PDT 24 22206336 ps
T962 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2320260132 Apr 28 03:24:20 PM PDT 24 Apr 28 03:24:23 PM PDT 24 198596802 ps
T963 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.232867324 Apr 28 03:23:21 PM PDT 24 Apr 28 03:23:24 PM PDT 24 2587991265 ps
T964 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2719231430 Apr 28 03:23:25 PM PDT 24 Apr 28 03:23:27 PM PDT 24 19964699 ps
T112 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.167449217 Apr 28 03:23:50 PM PDT 24 Apr 28 03:23:52 PM PDT 24 334577150 ps
T965 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2434815348 Apr 28 03:23:54 PM PDT 24 Apr 28 03:23:57 PM PDT 24 106545610 ps
T966 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.825728386 Apr 28 03:23:25 PM PDT 24 Apr 28 03:23:26 PM PDT 24 96357802 ps
T967 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.379881932 Apr 28 03:23:21 PM PDT 24 Apr 28 03:23:23 PM PDT 24 62139166 ps
T968 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3965470844 Apr 28 03:24:14 PM PDT 24 Apr 28 03:24:16 PM PDT 24 474714268 ps
T969 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.453175753 Apr 28 03:23:22 PM PDT 24 Apr 28 03:23:26 PM PDT 24 284526611 ps
T113 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2906816794 Apr 28 03:24:13 PM PDT 24 Apr 28 03:24:15 PM PDT 24 219719601 ps
T970 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1766289971 Apr 28 03:24:17 PM PDT 24 Apr 28 03:24:19 PM PDT 24 278808459 ps
T971 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3216593408 Apr 28 03:23:54 PM PDT 24 Apr 28 03:23:57 PM PDT 24 264681374 ps
T972 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2270431072 Apr 28 03:23:35 PM PDT 24 Apr 28 03:23:38 PM PDT 24 84522833 ps
T973 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4257774547 Apr 28 03:24:12 PM PDT 24 Apr 28 03:24:13 PM PDT 24 96277182 ps
T974 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3711482347 Apr 28 03:24:11 PM PDT 24 Apr 28 03:24:16 PM PDT 24 559637009 ps
T975 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1991118634 Apr 28 03:24:01 PM PDT 24 Apr 28 03:24:05 PM PDT 24 790105193 ps
T976 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3318691057 Apr 28 03:24:22 PM PDT 24 Apr 28 03:24:23 PM PDT 24 14329859 ps
T977 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.734582547 Apr 28 03:24:04 PM PDT 24 Apr 28 03:24:05 PM PDT 24 15560861 ps
T978 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.204982230 Apr 28 03:23:41 PM PDT 24 Apr 28 03:23:42 PM PDT 24 46113081 ps
T979 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3295821382 Apr 28 03:24:19 PM PDT 24 Apr 28 03:24:21 PM PDT 24 15305764 ps
T980 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3330235747 Apr 28 03:23:21 PM PDT 24 Apr 28 03:23:22 PM PDT 24 33412382 ps
T981 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.363560466 Apr 28 03:24:12 PM PDT 24 Apr 28 03:24:13 PM PDT 24 23041623 ps
T982 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1402647309 Apr 28 03:24:15 PM PDT 24 Apr 28 03:24:21 PM PDT 24 126733664 ps
T983 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1300642627 Apr 28 03:24:04 PM PDT 24 Apr 28 03:24:08 PM PDT 24 97814869 ps
T984 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1377576102 Apr 28 03:23:36 PM PDT 24 Apr 28 03:23:37 PM PDT 24 54117665 ps
T985 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2194826979 Apr 28 03:24:14 PM PDT 24 Apr 28 03:24:17 PM PDT 24 74275843 ps
T986 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3382949278 Apr 28 03:24:23 PM PDT 24 Apr 28 03:24:26 PM PDT 24 969680495 ps
T987 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.668084777 Apr 28 03:23:42 PM PDT 24 Apr 28 03:23:45 PM PDT 24 185601204 ps
T114 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.862946709 Apr 28 03:24:17 PM PDT 24 Apr 28 03:24:20 PM PDT 24 541362503 ps
T988 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1424465122 Apr 28 03:23:45 PM PDT 24 Apr 28 03:23:47 PM PDT 24 20018684 ps
T989 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.71822787 Apr 28 03:24:00 PM PDT 24 Apr 28 03:24:02 PM PDT 24 520144784 ps
T990 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3544525491 Apr 28 03:23:21 PM PDT 24 Apr 28 03:23:22 PM PDT 24 42247470 ps
T991 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2700394505 Apr 28 03:23:21 PM PDT 24 Apr 28 03:23:24 PM PDT 24 51342325 ps
T992 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2351304983 Apr 28 03:24:14 PM PDT 24 Apr 28 03:24:19 PM PDT 24 156686215 ps
T993 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2371433884 Apr 28 03:24:13 PM PDT 24 Apr 28 03:24:16 PM PDT 24 1215594772 ps
T994 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1332616385 Apr 28 03:23:54 PM PDT 24 Apr 28 03:23:57 PM PDT 24 129556290 ps
T995 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3798090217 Apr 28 03:23:31 PM PDT 24 Apr 28 03:23:33 PM PDT 24 41706748 ps
T996 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1409298129 Apr 28 03:23:46 PM PDT 24 Apr 28 03:23:48 PM PDT 24 31202512 ps
T997 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1415228924 Apr 28 03:23:59 PM PDT 24 Apr 28 03:24:01 PM PDT 24 41502038 ps
T998 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1817727995 Apr 28 03:24:04 PM PDT 24 Apr 28 03:24:06 PM PDT 24 32022543 ps
T999 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1008235254 Apr 28 03:24:23 PM PDT 24 Apr 28 03:24:25 PM PDT 24 242826990 ps
T1000 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3739399518 Apr 28 03:24:11 PM PDT 24 Apr 28 03:24:12 PM PDT 24 75324944 ps
T118 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4196045971 Apr 28 03:23:45 PM PDT 24 Apr 28 03:23:48 PM PDT 24 317105700 ps
T1001 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1395226636 Apr 28 03:24:09 PM PDT 24 Apr 28 03:24:12 PM PDT 24 429539780 ps
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