| T793 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.3400007744 |
|
|
Apr 30 01:42:30 PM PDT 24 |
Apr 30 01:42:31 PM PDT 24 |
71757438 ps |
| T794 |
/workspace/coverage/default/36.sram_ctrl_regwen.1511994353 |
|
|
Apr 30 01:44:13 PM PDT 24 |
Apr 30 01:56:41 PM PDT 24 |
37656906408 ps |
| T795 |
/workspace/coverage/default/17.sram_ctrl_partial_access.178174687 |
|
|
Apr 30 01:42:27 PM PDT 24 |
Apr 30 01:43:39 PM PDT 24 |
346029125 ps |
| T796 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1143369579 |
|
|
Apr 30 01:43:59 PM PDT 24 |
Apr 30 01:44:24 PM PDT 24 |
1284042806 ps |
| T797 |
/workspace/coverage/default/39.sram_ctrl_smoke.365555902 |
|
|
Apr 30 01:44:35 PM PDT 24 |
Apr 30 01:47:09 PM PDT 24 |
674021046 ps |
| T798 |
/workspace/coverage/default/7.sram_ctrl_partial_access.3672276736 |
|
|
Apr 30 01:42:00 PM PDT 24 |
Apr 30 01:42:15 PM PDT 24 |
1421059395 ps |
| T799 |
/workspace/coverage/default/24.sram_ctrl_executable.4029949421 |
|
|
Apr 30 01:42:57 PM PDT 24 |
Apr 30 02:01:27 PM PDT 24 |
78987510373 ps |
| T800 |
/workspace/coverage/default/18.sram_ctrl_regwen.1860545655 |
|
|
Apr 30 01:42:25 PM PDT 24 |
Apr 30 01:49:20 PM PDT 24 |
15767648450 ps |
| T801 |
/workspace/coverage/default/26.sram_ctrl_regwen.1069992880 |
|
|
Apr 30 01:43:07 PM PDT 24 |
Apr 30 01:54:10 PM PDT 24 |
3777093448 ps |
| T802 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1572348525 |
|
|
Apr 30 01:42:08 PM PDT 24 |
Apr 30 01:45:27 PM PDT 24 |
2237436909 ps |
| T803 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.824176896 |
|
|
Apr 30 01:44:02 PM PDT 24 |
Apr 30 01:44:03 PM PDT 24 |
49505168 ps |
| T804 |
/workspace/coverage/default/38.sram_ctrl_bijection.2576201808 |
|
|
Apr 30 01:44:30 PM PDT 24 |
Apr 30 01:44:59 PM PDT 24 |
1772778216 ps |
| T805 |
/workspace/coverage/default/28.sram_ctrl_regwen.1169466426 |
|
|
Apr 30 01:43:21 PM PDT 24 |
Apr 30 02:05:57 PM PDT 24 |
86794327862 ps |
| T806 |
/workspace/coverage/default/46.sram_ctrl_executable.1664449253 |
|
|
Apr 30 01:45:38 PM PDT 24 |
Apr 30 02:11:00 PM PDT 24 |
13477405441 ps |
| T807 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.640005069 |
|
|
Apr 30 01:42:03 PM PDT 24 |
Apr 30 01:42:07 PM PDT 24 |
150748096 ps |
| T808 |
/workspace/coverage/default/30.sram_ctrl_alert_test.1040889153 |
|
|
Apr 30 01:43:34 PM PDT 24 |
Apr 30 01:43:35 PM PDT 24 |
13867365 ps |
| T809 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.517385874 |
|
|
Apr 30 01:42:30 PM PDT 24 |
Apr 30 01:42:37 PM PDT 24 |
1207063242 ps |
| T810 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2936064481 |
|
|
Apr 30 01:43:41 PM PDT 24 |
Apr 30 02:03:01 PM PDT 24 |
14595292508 ps |
| T811 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.486783550 |
|
|
Apr 30 01:44:20 PM PDT 24 |
Apr 30 01:44:21 PM PDT 24 |
122712470 ps |
| T812 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1254911448 |
|
|
Apr 30 01:43:15 PM PDT 24 |
Apr 30 01:47:12 PM PDT 24 |
4899324418 ps |
| T813 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.2265192827 |
|
|
Apr 30 01:42:25 PM PDT 24 |
Apr 30 01:58:53 PM PDT 24 |
52268925223 ps |
| T814 |
/workspace/coverage/default/0.sram_ctrl_executable.1232219559 |
|
|
Apr 30 01:41:38 PM PDT 24 |
Apr 30 02:02:57 PM PDT 24 |
12413907564 ps |
| T815 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2325641417 |
|
|
Apr 30 01:43:06 PM PDT 24 |
Apr 30 01:47:34 PM PDT 24 |
4024672352 ps |
| T816 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1432769365 |
|
|
Apr 30 01:43:41 PM PDT 24 |
Apr 30 01:46:38 PM PDT 24 |
7641809468 ps |
| T817 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.2254678912 |
|
|
Apr 30 01:42:56 PM PDT 24 |
Apr 30 01:43:02 PM PDT 24 |
313982807 ps |
| T818 |
/workspace/coverage/default/39.sram_ctrl_bijection.3497396381 |
|
|
Apr 30 01:44:37 PM PDT 24 |
Apr 30 01:45:44 PM PDT 24 |
4830995669 ps |
| T819 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2948737348 |
|
|
Apr 30 01:42:14 PM PDT 24 |
Apr 30 01:42:23 PM PDT 24 |
869232525 ps |
| T820 |
/workspace/coverage/default/20.sram_ctrl_smoke.926892939 |
|
|
Apr 30 01:42:30 PM PDT 24 |
Apr 30 01:44:52 PM PDT 24 |
740992551 ps |
| T821 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3786947607 |
|
|
Apr 30 01:43:41 PM PDT 24 |
Apr 30 01:55:23 PM PDT 24 |
9565995337 ps |
| T822 |
/workspace/coverage/default/9.sram_ctrl_bijection.721057614 |
|
|
Apr 30 01:42:00 PM PDT 24 |
Apr 30 01:43:13 PM PDT 24 |
3822645248 ps |
| T823 |
/workspace/coverage/default/4.sram_ctrl_stress_all.3147120448 |
|
|
Apr 30 01:41:50 PM PDT 24 |
Apr 30 02:12:42 PM PDT 24 |
121474802056 ps |
| T824 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2222002681 |
|
|
Apr 30 01:41:59 PM PDT 24 |
Apr 30 01:42:32 PM PDT 24 |
1122127108 ps |
| T825 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.265049566 |
|
|
Apr 30 01:41:41 PM PDT 24 |
Apr 30 01:42:35 PM PDT 24 |
116172762 ps |
| T826 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3448373641 |
|
|
Apr 30 01:42:57 PM PDT 24 |
Apr 30 01:43:03 PM PDT 24 |
698645285 ps |
| T827 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1927395038 |
|
|
Apr 30 01:41:39 PM PDT 24 |
Apr 30 01:42:15 PM PDT 24 |
1257658227 ps |
| T828 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.2667416125 |
|
|
Apr 30 01:45:04 PM PDT 24 |
Apr 30 01:45:05 PM PDT 24 |
85270935 ps |
| T829 |
/workspace/coverage/default/16.sram_ctrl_bijection.1129159478 |
|
|
Apr 30 01:42:27 PM PDT 24 |
Apr 30 01:43:03 PM PDT 24 |
1144738659 ps |
| T830 |
/workspace/coverage/default/3.sram_ctrl_partial_access.1823139790 |
|
|
Apr 30 01:41:42 PM PDT 24 |
Apr 30 01:41:50 PM PDT 24 |
331530078 ps |
| T831 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.3690819741 |
|
|
Apr 30 01:44:59 PM PDT 24 |
Apr 30 01:45:07 PM PDT 24 |
285718894 ps |
| T832 |
/workspace/coverage/default/30.sram_ctrl_smoke.4245494617 |
|
|
Apr 30 01:43:25 PM PDT 24 |
Apr 30 01:45:35 PM PDT 24 |
1504157491 ps |
| T833 |
/workspace/coverage/default/28.sram_ctrl_executable.4021123841 |
|
|
Apr 30 01:43:21 PM PDT 24 |
Apr 30 01:45:32 PM PDT 24 |
2098921459 ps |
| T834 |
/workspace/coverage/default/40.sram_ctrl_stress_all.2138627623 |
|
|
Apr 30 01:44:55 PM PDT 24 |
Apr 30 02:23:25 PM PDT 24 |
179305248171 ps |
| T835 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.1554207354 |
|
|
Apr 30 01:42:06 PM PDT 24 |
Apr 30 01:42:11 PM PDT 24 |
74748275 ps |
| T836 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.1088223089 |
|
|
Apr 30 01:44:12 PM PDT 24 |
Apr 30 01:44:13 PM PDT 24 |
146762151 ps |
| T837 |
/workspace/coverage/default/49.sram_ctrl_bijection.1610967254 |
|
|
Apr 30 01:46:06 PM PDT 24 |
Apr 30 01:46:28 PM PDT 24 |
1665992953 ps |
| T838 |
/workspace/coverage/default/5.sram_ctrl_stress_all.3528971290 |
|
|
Apr 30 01:41:51 PM PDT 24 |
Apr 30 01:46:21 PM PDT 24 |
64317535556 ps |
| T839 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2135535735 |
|
|
Apr 30 01:42:15 PM PDT 24 |
Apr 30 01:42:20 PM PDT 24 |
219186849 ps |
| T840 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2863702916 |
|
|
Apr 30 01:42:05 PM PDT 24 |
Apr 30 01:42:26 PM PDT 24 |
135955386 ps |
| T841 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1823104502 |
|
|
Apr 30 01:42:12 PM PDT 24 |
Apr 30 01:42:18 PM PDT 24 |
516601815 ps |
| T842 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.43743167 |
|
|
Apr 30 01:45:05 PM PDT 24 |
Apr 30 01:45:10 PM PDT 24 |
610386325 ps |
| T843 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2528146649 |
|
|
Apr 30 01:45:58 PM PDT 24 |
Apr 30 01:46:05 PM PDT 24 |
1628420473 ps |
| T844 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.4166325645 |
|
|
Apr 30 01:44:14 PM PDT 24 |
Apr 30 01:46:02 PM PDT 24 |
144562499 ps |
| T845 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2383500003 |
|
|
Apr 30 01:45:04 PM PDT 24 |
Apr 30 01:47:42 PM PDT 24 |
157161309 ps |
| T846 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.3975530472 |
|
|
Apr 30 01:43:03 PM PDT 24 |
Apr 30 01:43:05 PM PDT 24 |
155477056 ps |
| T847 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.824555996 |
|
|
Apr 30 01:41:44 PM PDT 24 |
Apr 30 01:45:27 PM PDT 24 |
10293007516 ps |
| T848 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1761653480 |
|
|
Apr 30 01:43:24 PM PDT 24 |
Apr 30 01:47:21 PM PDT 24 |
6706462348 ps |
| T849 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3673667124 |
|
|
Apr 30 01:42:34 PM PDT 24 |
Apr 30 01:42:42 PM PDT 24 |
281069891 ps |
| T35 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2108559337 |
|
|
Apr 30 01:41:54 PM PDT 24 |
Apr 30 01:41:57 PM PDT 24 |
749724361 ps |
| T850 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.4277067262 |
|
|
Apr 30 01:43:47 PM PDT 24 |
Apr 30 02:14:20 PM PDT 24 |
13694773949 ps |
| T851 |
/workspace/coverage/default/34.sram_ctrl_smoke.2992734376 |
|
|
Apr 30 01:43:56 PM PDT 24 |
Apr 30 01:44:35 PM PDT 24 |
385665014 ps |
| T852 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3509789999 |
|
|
Apr 30 01:45:24 PM PDT 24 |
Apr 30 01:45:45 PM PDT 24 |
993491987 ps |
| T853 |
/workspace/coverage/default/41.sram_ctrl_regwen.798817953 |
|
|
Apr 30 01:44:57 PM PDT 24 |
Apr 30 01:50:58 PM PDT 24 |
25648714916 ps |
| T854 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3302405318 |
|
|
Apr 30 01:42:29 PM PDT 24 |
Apr 30 02:07:05 PM PDT 24 |
4293667782 ps |
| T855 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2049788005 |
|
|
Apr 30 01:42:13 PM PDT 24 |
Apr 30 01:42:15 PM PDT 24 |
75786913 ps |
| T856 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1672858504 |
|
|
Apr 30 01:41:57 PM PDT 24 |
Apr 30 01:41:58 PM PDT 24 |
44437352 ps |
| T857 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3058539698 |
|
|
Apr 30 01:44:01 PM PDT 24 |
Apr 30 01:54:52 PM PDT 24 |
3336873031 ps |
| T858 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1223899790 |
|
|
Apr 30 01:42:21 PM PDT 24 |
Apr 30 01:42:22 PM PDT 24 |
28571136 ps |
| T859 |
/workspace/coverage/default/25.sram_ctrl_partial_access.278238424 |
|
|
Apr 30 01:43:04 PM PDT 24 |
Apr 30 01:44:43 PM PDT 24 |
691595454 ps |
| T860 |
/workspace/coverage/default/32.sram_ctrl_partial_access.48984701 |
|
|
Apr 30 01:43:42 PM PDT 24 |
Apr 30 01:44:27 PM PDT 24 |
495950594 ps |
| T861 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.277381297 |
|
|
Apr 30 01:41:38 PM PDT 24 |
Apr 30 01:42:14 PM PDT 24 |
2292734378 ps |
| T862 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3347241200 |
|
|
Apr 30 01:42:00 PM PDT 24 |
Apr 30 01:53:36 PM PDT 24 |
30989252171 ps |
| T863 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.211033165 |
|
|
Apr 30 01:43:52 PM PDT 24 |
Apr 30 01:44:01 PM PDT 24 |
155194570 ps |
| T864 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.1254969956 |
|
|
Apr 30 01:42:08 PM PDT 24 |
Apr 30 01:42:11 PM PDT 24 |
162798924 ps |
| T865 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1399473150 |
|
|
Apr 30 01:44:14 PM PDT 24 |
Apr 30 01:48:10 PM PDT 24 |
459652874 ps |
| T866 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1215946570 |
|
|
Apr 30 01:45:18 PM PDT 24 |
Apr 30 01:54:29 PM PDT 24 |
189180409447 ps |
| T867 |
/workspace/coverage/default/6.sram_ctrl_regwen.2630638598 |
|
|
Apr 30 01:41:52 PM PDT 24 |
Apr 30 02:02:53 PM PDT 24 |
14863966094 ps |
| T868 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.799952734 |
|
|
Apr 30 01:45:43 PM PDT 24 |
Apr 30 01:45:53 PM PDT 24 |
271039648 ps |
| T869 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2132462404 |
|
|
Apr 30 01:41:40 PM PDT 24 |
Apr 30 02:39:36 PM PDT 24 |
11777517039 ps |
| T870 |
/workspace/coverage/default/28.sram_ctrl_smoke.1765401746 |
|
|
Apr 30 01:43:13 PM PDT 24 |
Apr 30 01:43:39 PM PDT 24 |
263008893 ps |
| T871 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.1868066053 |
|
|
Apr 30 01:42:22 PM PDT 24 |
Apr 30 01:42:27 PM PDT 24 |
306883140 ps |
| T872 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3371542850 |
|
|
Apr 30 01:41:47 PM PDT 24 |
Apr 30 01:42:16 PM PDT 24 |
355366721 ps |
| T873 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2016670393 |
|
|
Apr 30 01:42:10 PM PDT 24 |
Apr 30 01:42:16 PM PDT 24 |
1887623764 ps |
| T874 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.421006635 |
|
|
Apr 30 01:41:59 PM PDT 24 |
Apr 30 01:49:11 PM PDT 24 |
97207323446 ps |
| T875 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.3483318775 |
|
|
Apr 30 01:44:29 PM PDT 24 |
Apr 30 01:44:34 PM PDT 24 |
886760496 ps |
| T876 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2533903644 |
|
|
Apr 30 01:42:31 PM PDT 24 |
Apr 30 01:42:57 PM PDT 24 |
2300240507 ps |
| T877 |
/workspace/coverage/default/14.sram_ctrl_smoke.1471606844 |
|
|
Apr 30 01:42:14 PM PDT 24 |
Apr 30 01:42:29 PM PDT 24 |
3502356793 ps |
| T878 |
/workspace/coverage/default/6.sram_ctrl_smoke.4004399007 |
|
|
Apr 30 01:41:50 PM PDT 24 |
Apr 30 01:42:03 PM PDT 24 |
262668929 ps |
| T879 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2592261526 |
|
|
Apr 30 01:46:09 PM PDT 24 |
Apr 30 02:00:24 PM PDT 24 |
2239686156 ps |
| T880 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3052754281 |
|
|
Apr 30 01:43:40 PM PDT 24 |
Apr 30 01:44:05 PM PDT 24 |
195107308 ps |
| T881 |
/workspace/coverage/default/23.sram_ctrl_smoke.1310110656 |
|
|
Apr 30 01:42:52 PM PDT 24 |
Apr 30 01:43:18 PM PDT 24 |
362097635 ps |
| T882 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.913016898 |
|
|
Apr 30 01:46:02 PM PDT 24 |
Apr 30 01:48:18 PM PDT 24 |
1552760705 ps |
| T883 |
/workspace/coverage/default/4.sram_ctrl_bijection.3211152515 |
|
|
Apr 30 01:41:50 PM PDT 24 |
Apr 30 01:42:24 PM PDT 24 |
2851537857 ps |
| T884 |
/workspace/coverage/default/3.sram_ctrl_regwen.2384042993 |
|
|
Apr 30 01:41:44 PM PDT 24 |
Apr 30 01:50:07 PM PDT 24 |
7469400991 ps |
| T885 |
/workspace/coverage/default/15.sram_ctrl_partial_access.4275819443 |
|
|
Apr 30 01:42:12 PM PDT 24 |
Apr 30 01:43:37 PM PDT 24 |
324736423 ps |
| T886 |
/workspace/coverage/default/27.sram_ctrl_alert_test.4111826855 |
|
|
Apr 30 01:43:11 PM PDT 24 |
Apr 30 01:43:12 PM PDT 24 |
14310333 ps |
| T887 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3902664805 |
|
|
Apr 30 01:43:49 PM PDT 24 |
Apr 30 01:43:53 PM PDT 24 |
984218886 ps |
| T888 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3754043454 |
|
|
Apr 30 01:42:37 PM PDT 24 |
Apr 30 01:56:20 PM PDT 24 |
4833672950 ps |
| T889 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1997861425 |
|
|
Apr 30 01:42:19 PM PDT 24 |
Apr 30 01:42:24 PM PDT 24 |
344760136 ps |
| T890 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1663868335 |
|
|
Apr 30 01:41:39 PM PDT 24 |
Apr 30 01:57:25 PM PDT 24 |
14031639894 ps |
| T891 |
/workspace/coverage/default/2.sram_ctrl_alert_test.1820956135 |
|
|
Apr 30 01:41:40 PM PDT 24 |
Apr 30 01:41:42 PM PDT 24 |
20227648 ps |
| T892 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.4180946813 |
|
|
Apr 30 01:42:23 PM PDT 24 |
Apr 30 01:46:33 PM PDT 24 |
2608913701 ps |
| T893 |
/workspace/coverage/default/37.sram_ctrl_executable.3343904704 |
|
|
Apr 30 01:44:20 PM PDT 24 |
Apr 30 01:51:30 PM PDT 24 |
4524555714 ps |
| T894 |
/workspace/coverage/default/26.sram_ctrl_alert_test.614864384 |
|
|
Apr 30 01:43:14 PM PDT 24 |
Apr 30 01:43:15 PM PDT 24 |
14619886 ps |
| T895 |
/workspace/coverage/default/7.sram_ctrl_smoke.1698935443 |
|
|
Apr 30 01:42:00 PM PDT 24 |
Apr 30 01:42:22 PM PDT 24 |
2915470691 ps |
| T896 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3273031929 |
|
|
Apr 30 01:42:19 PM PDT 24 |
Apr 30 02:13:22 PM PDT 24 |
29965813158 ps |
| T897 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1334545209 |
|
|
Apr 30 01:42:09 PM PDT 24 |
Apr 30 01:43:25 PM PDT 24 |
189511754 ps |
| T898 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2768088641 |
|
|
Apr 30 01:45:33 PM PDT 24 |
Apr 30 01:46:11 PM PDT 24 |
189614914 ps |
| T899 |
/workspace/coverage/default/19.sram_ctrl_smoke.705018346 |
|
|
Apr 30 01:42:31 PM PDT 24 |
Apr 30 01:42:46 PM PDT 24 |
11638527184 ps |
| T900 |
/workspace/coverage/default/4.sram_ctrl_regwen.66744310 |
|
|
Apr 30 01:41:50 PM PDT 24 |
Apr 30 01:50:33 PM PDT 24 |
10095893406 ps |
| T901 |
/workspace/coverage/default/44.sram_ctrl_regwen.3541229099 |
|
|
Apr 30 01:45:22 PM PDT 24 |
Apr 30 02:00:00 PM PDT 24 |
134247875109 ps |
| T902 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3090467663 |
|
|
Apr 30 01:41:51 PM PDT 24 |
Apr 30 01:41:54 PM PDT 24 |
182828684 ps |
| T903 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2984995538 |
|
|
Apr 30 01:44:22 PM PDT 24 |
Apr 30 02:12:43 PM PDT 24 |
13893715437 ps |
| T904 |
/workspace/coverage/default/23.sram_ctrl_stress_all.72484881 |
|
|
Apr 30 01:42:57 PM PDT 24 |
Apr 30 02:06:02 PM PDT 24 |
58292205594 ps |
| T905 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.4102041557 |
|
|
Apr 30 01:42:23 PM PDT 24 |
Apr 30 01:42:26 PM PDT 24 |
172402875 ps |
| T906 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3932935596 |
|
|
Apr 30 01:42:58 PM PDT 24 |
Apr 30 01:43:06 PM PDT 24 |
124103648 ps |
| T907 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.2181985380 |
|
|
Apr 30 01:41:48 PM PDT 24 |
Apr 30 01:56:37 PM PDT 24 |
8116026983 ps |
| T908 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1505693241 |
|
|
Apr 30 01:43:52 PM PDT 24 |
Apr 30 01:45:26 PM PDT 24 |
2058533089 ps |
| T909 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3203272649 |
|
|
Apr 30 01:41:33 PM PDT 24 |
Apr 30 01:52:15 PM PDT 24 |
50361848522 ps |
| T910 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.2411993449 |
|
|
Apr 30 01:45:42 PM PDT 24 |
Apr 30 01:45:51 PM PDT 24 |
632272328 ps |
| T911 |
/workspace/coverage/default/41.sram_ctrl_bijection.1132392431 |
|
|
Apr 30 01:44:51 PM PDT 24 |
Apr 30 01:45:14 PM PDT 24 |
14520276177 ps |
| T912 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2796492912 |
|
|
Apr 30 01:42:16 PM PDT 24 |
Apr 30 01:42:17 PM PDT 24 |
14728885 ps |
| T913 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3054738329 |
|
|
Apr 30 01:44:15 PM PDT 24 |
Apr 30 01:44:20 PM PDT 24 |
303769425 ps |
| T914 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2726352163 |
|
|
Apr 30 01:46:03 PM PDT 24 |
Apr 30 02:38:50 PM PDT 24 |
200510903461 ps |
| T915 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.4150391620 |
|
|
Apr 30 01:42:25 PM PDT 24 |
Apr 30 01:42:26 PM PDT 24 |
26585743 ps |
| T916 |
/workspace/coverage/default/34.sram_ctrl_regwen.853099678 |
|
|
Apr 30 01:44:00 PM PDT 24 |
Apr 30 01:49:24 PM PDT 24 |
22774801721 ps |
| T917 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.198383211 |
|
|
Apr 30 01:42:53 PM PDT 24 |
Apr 30 01:57:10 PM PDT 24 |
11465092559 ps |
| T918 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.471989882 |
|
|
Apr 30 01:44:45 PM PDT 24 |
Apr 30 01:44:46 PM PDT 24 |
87431489 ps |
| T919 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1061702549 |
|
|
Apr 30 01:45:07 PM PDT 24 |
Apr 30 01:51:53 PM PDT 24 |
6721816770 ps |
| T920 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3368539781 |
|
|
Apr 30 01:42:14 PM PDT 24 |
Apr 30 01:48:36 PM PDT 24 |
3915993353 ps |
| T921 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3862266749 |
|
|
Apr 30 01:42:21 PM PDT 24 |
Apr 30 01:51:54 PM PDT 24 |
972677802 ps |
| T922 |
/workspace/coverage/default/5.sram_ctrl_regwen.3468771378 |
|
|
Apr 30 01:41:52 PM PDT 24 |
Apr 30 01:56:17 PM PDT 24 |
46254156414 ps |
| T923 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2508097582 |
|
|
Apr 30 01:41:57 PM PDT 24 |
Apr 30 01:42:54 PM PDT 24 |
1756107764 ps |
| T924 |
/workspace/coverage/default/3.sram_ctrl_smoke.1967950618 |
|
|
Apr 30 01:41:40 PM PDT 24 |
Apr 30 01:41:43 PM PDT 24 |
84198786 ps |
| T925 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2097588658 |
|
|
Apr 30 01:42:16 PM PDT 24 |
Apr 30 01:47:29 PM PDT 24 |
1254501947 ps |
| T926 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.994594889 |
|
|
Apr 30 01:42:14 PM PDT 24 |
Apr 30 01:48:32 PM PDT 24 |
29464227113 ps |
| T927 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1892530672 |
|
|
Apr 30 01:42:33 PM PDT 24 |
Apr 30 01:47:17 PM PDT 24 |
11627172147 ps |
| T928 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.498092036 |
|
|
Apr 30 01:43:46 PM PDT 24 |
Apr 30 01:59:40 PM PDT 24 |
4008716181 ps |
| T929 |
/workspace/coverage/default/30.sram_ctrl_partial_access.3551231490 |
|
|
Apr 30 01:43:26 PM PDT 24 |
Apr 30 01:43:28 PM PDT 24 |
168163215 ps |
| T930 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.231596182 |
|
|
Apr 30 01:41:43 PM PDT 24 |
Apr 30 01:42:32 PM PDT 24 |
119382073 ps |
| T931 |
/workspace/coverage/default/35.sram_ctrl_smoke.3176689873 |
|
|
Apr 30 01:44:04 PM PDT 24 |
Apr 30 01:44:10 PM PDT 24 |
993723218 ps |
| T100 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.735725652 |
|
|
Apr 30 01:40:59 PM PDT 24 |
Apr 30 01:41:01 PM PDT 24 |
88065777 ps |
| T932 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.293890609 |
|
|
Apr 30 01:40:59 PM PDT 24 |
Apr 30 01:41:01 PM PDT 24 |
116039602 ps |
| T61 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1353403087 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:51 PM PDT 24 |
101669736 ps |
| T98 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1137127232 |
|
|
Apr 30 01:40:49 PM PDT 24 |
Apr 30 01:40:50 PM PDT 24 |
90371415 ps |
| T62 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2732681331 |
|
|
Apr 30 01:40:59 PM PDT 24 |
Apr 30 01:41:03 PM PDT 24 |
793505084 ps |
| T933 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1387724270 |
|
|
Apr 30 01:41:05 PM PDT 24 |
Apr 30 01:41:09 PM PDT 24 |
143624156 ps |
| T101 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3939412630 |
|
|
Apr 30 01:40:48 PM PDT 24 |
Apr 30 01:40:51 PM PDT 24 |
785073695 ps |
| T934 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1146529565 |
|
|
Apr 30 01:41:07 PM PDT 24 |
Apr 30 01:41:08 PM PDT 24 |
167594093 ps |
| T935 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3433290763 |
|
|
Apr 30 01:41:01 PM PDT 24 |
Apr 30 01:41:05 PM PDT 24 |
113815469 ps |
| T63 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3092227722 |
|
|
Apr 30 01:40:59 PM PDT 24 |
Apr 30 01:41:02 PM PDT 24 |
1008649346 ps |
| T936 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1050299417 |
|
|
Apr 30 01:41:06 PM PDT 24 |
Apr 30 01:41:07 PM PDT 24 |
11710187 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1035574059 |
|
|
Apr 30 01:40:59 PM PDT 24 |
Apr 30 01:41:02 PM PDT 24 |
348352822 ps |
| T99 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3359183451 |
|
|
Apr 30 01:40:57 PM PDT 24 |
Apr 30 01:40:58 PM PDT 24 |
27972532 ps |
| T110 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3499752540 |
|
|
Apr 30 01:41:06 PM PDT 24 |
Apr 30 01:41:09 PM PDT 24 |
419221965 ps |
| T937 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3009285331 |
|
|
Apr 30 01:40:52 PM PDT 24 |
Apr 30 01:40:54 PM PDT 24 |
548905191 ps |
| T938 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.877870298 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:41:00 PM PDT 24 |
45028221 ps |
| T113 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4266538621 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:10 PM PDT 24 |
168048281 ps |
| T939 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1021468139 |
|
|
Apr 30 01:41:10 PM PDT 24 |
Apr 30 01:41:12 PM PDT 24 |
34349081 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4260586369 |
|
|
Apr 30 01:40:59 PM PDT 24 |
Apr 30 01:41:01 PM PDT 24 |
20981389 ps |
| T65 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3823144475 |
|
|
Apr 30 01:41:03 PM PDT 24 |
Apr 30 01:41:05 PM PDT 24 |
38678618 ps |
| T66 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1337118174 |
|
|
Apr 30 01:40:56 PM PDT 24 |
Apr 30 01:41:00 PM PDT 24 |
1617494148 ps |
| T940 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.879725240 |
|
|
Apr 30 01:41:01 PM PDT 24 |
Apr 30 01:41:06 PM PDT 24 |
564408909 ps |
| T111 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3594305760 |
|
|
Apr 30 01:41:02 PM PDT 24 |
Apr 30 01:41:04 PM PDT 24 |
127961967 ps |
| T67 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.922328828 |
|
|
Apr 30 01:41:09 PM PDT 24 |
Apr 30 01:41:10 PM PDT 24 |
35255194 ps |
| T941 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1967825609 |
|
|
Apr 30 01:40:43 PM PDT 24 |
Apr 30 01:40:47 PM PDT 24 |
45536313 ps |
| T68 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2913097747 |
|
|
Apr 30 01:41:04 PM PDT 24 |
Apr 30 01:41:08 PM PDT 24 |
1658142740 ps |
| T69 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4002612816 |
|
|
Apr 30 01:41:03 PM PDT 24 |
Apr 30 01:41:04 PM PDT 24 |
41743415 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2503568731 |
|
|
Apr 30 01:40:52 PM PDT 24 |
Apr 30 01:40:53 PM PDT 24 |
17743844 ps |
| T92 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3749785605 |
|
|
Apr 30 01:41:09 PM PDT 24 |
Apr 30 01:41:13 PM PDT 24 |
803980207 ps |
| T76 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3904988295 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:52 PM PDT 24 |
12395208 ps |
| T114 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1323916642 |
|
|
Apr 30 01:40:40 PM PDT 24 |
Apr 30 01:40:43 PM PDT 24 |
504975912 ps |
| T77 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1985135765 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:40:59 PM PDT 24 |
35051278 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3953920718 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:52 PM PDT 24 |
111943900 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3475771621 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:41:01 PM PDT 24 |
66984383 ps |
| T943 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2509154175 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:52 PM PDT 24 |
94954964 ps |
| T944 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2933010001 |
|
|
Apr 30 01:41:04 PM PDT 24 |
Apr 30 01:41:06 PM PDT 24 |
139137603 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.901480777 |
|
|
Apr 30 01:40:51 PM PDT 24 |
Apr 30 01:40:53 PM PDT 24 |
25278495 ps |
| T94 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.837472662 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:40:59 PM PDT 24 |
51661401 ps |
| T945 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1662004620 |
|
|
Apr 30 01:41:01 PM PDT 24 |
Apr 30 01:41:05 PM PDT 24 |
73067327 ps |
| T95 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1571666761 |
|
|
Apr 30 01:40:48 PM PDT 24 |
Apr 30 01:40:49 PM PDT 24 |
29688523 ps |
| T946 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.281843247 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:40:59 PM PDT 24 |
13571218 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1777474917 |
|
|
Apr 30 01:40:52 PM PDT 24 |
Apr 30 01:40:53 PM PDT 24 |
70903991 ps |
| T115 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.439603366 |
|
|
Apr 30 01:40:49 PM PDT 24 |
Apr 30 01:40:51 PM PDT 24 |
578348964 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1230254854 |
|
|
Apr 30 01:40:51 PM PDT 24 |
Apr 30 01:40:54 PM PDT 24 |
118363583 ps |
| T949 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1248581389 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:51 PM PDT 24 |
43904673 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1390506402 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:54 PM PDT 24 |
147384239 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2919034426 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:51 PM PDT 24 |
80740675 ps |
| T951 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3832774657 |
|
|
Apr 30 01:41:04 PM PDT 24 |
Apr 30 01:41:05 PM PDT 24 |
12832347 ps |
| T952 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3641170025 |
|
|
Apr 30 01:41:07 PM PDT 24 |
Apr 30 01:41:09 PM PDT 24 |
117594051 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.153348346 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:51 PM PDT 24 |
11606489 ps |
| T954 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3423022762 |
|
|
Apr 30 01:41:09 PM PDT 24 |
Apr 30 01:41:11 PM PDT 24 |
91333323 ps |
| T955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1814568638 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:52 PM PDT 24 |
315892917 ps |
| T79 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3739875198 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:52 PM PDT 24 |
98604843 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3114118714 |
|
|
Apr 30 01:41:05 PM PDT 24 |
Apr 30 01:41:06 PM PDT 24 |
25876565 ps |
| T957 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.137149487 |
|
|
Apr 30 01:40:57 PM PDT 24 |
Apr 30 01:40:58 PM PDT 24 |
41485360 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1772763727 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:41:00 PM PDT 24 |
76895352 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.594125480 |
|
|
Apr 30 01:40:49 PM PDT 24 |
Apr 30 01:40:50 PM PDT 24 |
30079734 ps |
| T960 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3089563280 |
|
|
Apr 30 01:41:09 PM PDT 24 |
Apr 30 01:41:11 PM PDT 24 |
58067402 ps |
| T116 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4154684129 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:11 PM PDT 24 |
226693024 ps |
| T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2979142561 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:41:00 PM PDT 24 |
449075857 ps |
| T117 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.686389773 |
|
|
Apr 30 01:41:11 PM PDT 24 |
Apr 30 01:41:14 PM PDT 24 |
192266918 ps |
| T962 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.457448430 |
|
|
Apr 30 01:41:05 PM PDT 24 |
Apr 30 01:41:06 PM PDT 24 |
20704961 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1488625409 |
|
|
Apr 30 01:41:00 PM PDT 24 |
Apr 30 01:41:01 PM PDT 24 |
16375006 ps |
| T87 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.177771118 |
|
|
Apr 30 01:40:57 PM PDT 24 |
Apr 30 01:40:58 PM PDT 24 |
22021123 ps |
| T89 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.169986625 |
|
|
Apr 30 01:41:07 PM PDT 24 |
Apr 30 01:41:11 PM PDT 24 |
1118771608 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1109836882 |
|
|
Apr 30 01:41:12 PM PDT 24 |
Apr 30 01:41:16 PM PDT 24 |
367272949 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.699131604 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:10 PM PDT 24 |
249102210 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3478427574 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:52 PM PDT 24 |
193790553 ps |
| T966 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2157287122 |
|
|
Apr 30 01:41:04 PM PDT 24 |
Apr 30 01:41:05 PM PDT 24 |
34019126 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4197246223 |
|
|
Apr 30 01:40:52 PM PDT 24 |
Apr 30 01:40:53 PM PDT 24 |
22969311 ps |
| T968 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2012601827 |
|
|
Apr 30 01:40:48 PM PDT 24 |
Apr 30 01:40:50 PM PDT 24 |
46629751 ps |
| T112 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.663661337 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:11 PM PDT 24 |
999693658 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1022787023 |
|
|
Apr 30 01:40:41 PM PDT 24 |
Apr 30 01:40:45 PM PDT 24 |
3827595651 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3131606832 |
|
|
Apr 30 01:40:56 PM PDT 24 |
Apr 30 01:40:57 PM PDT 24 |
20898952 ps |
| T90 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1250015536 |
|
|
Apr 30 01:40:57 PM PDT 24 |
Apr 30 01:41:01 PM PDT 24 |
392503527 ps |
| T971 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.110154793 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:41:02 PM PDT 24 |
336663752 ps |
| T972 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1808483921 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:09 PM PDT 24 |
20814486 ps |
| T119 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3126039993 |
|
|
Apr 30 01:40:59 PM PDT 24 |
Apr 30 01:41:01 PM PDT 24 |
159267665 ps |
| T973 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4003153749 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:10 PM PDT 24 |
57068900 ps |
| T974 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1460521314 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:41:02 PM PDT 24 |
42273132 ps |
| T975 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1003469721 |
|
|
Apr 30 01:41:06 PM PDT 24 |
Apr 30 01:41:09 PM PDT 24 |
82649867 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3790671056 |
|
|
Apr 30 01:40:51 PM PDT 24 |
Apr 30 01:40:56 PM PDT 24 |
224240307 ps |
| T977 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.683706061 |
|
|
Apr 30 01:41:11 PM PDT 24 |
Apr 30 01:41:13 PM PDT 24 |
97703464 ps |
| T978 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1851270273 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:11 PM PDT 24 |
27944383 ps |
| T979 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1048519521 |
|
|
Apr 30 01:41:09 PM PDT 24 |
Apr 30 01:41:10 PM PDT 24 |
13020694 ps |
| T121 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3918457405 |
|
|
Apr 30 01:40:58 PM PDT 24 |
Apr 30 01:41:00 PM PDT 24 |
280409673 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.440782576 |
|
|
Apr 30 01:41:04 PM PDT 24 |
Apr 30 01:41:06 PM PDT 24 |
142046501 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4265583317 |
|
|
Apr 30 01:41:05 PM PDT 24 |
Apr 30 01:41:07 PM PDT 24 |
18643074 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3644212176 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:52 PM PDT 24 |
24988553 ps |
| T982 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.366073349 |
|
|
Apr 30 01:41:04 PM PDT 24 |
Apr 30 01:41:05 PM PDT 24 |
77025100 ps |
| T983 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3348450569 |
|
|
Apr 30 01:41:10 PM PDT 24 |
Apr 30 01:41:13 PM PDT 24 |
138278899 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3109970465 |
|
|
Apr 30 01:40:51 PM PDT 24 |
Apr 30 01:40:54 PM PDT 24 |
967731280 ps |
| T985 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.615299012 |
|
|
Apr 30 01:41:06 PM PDT 24 |
Apr 30 01:41:08 PM PDT 24 |
104461933 ps |
| T986 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3661189142 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:10 PM PDT 24 |
831130907 ps |
| T987 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1368212475 |
|
|
Apr 30 01:41:07 PM PDT 24 |
Apr 30 01:41:09 PM PDT 24 |
77879568 ps |
| T988 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2301587679 |
|
|
Apr 30 01:41:06 PM PDT 24 |
Apr 30 01:41:09 PM PDT 24 |
259220698 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1399161393 |
|
|
Apr 30 01:41:05 PM PDT 24 |
Apr 30 01:41:08 PM PDT 24 |
784775210 ps |
| T990 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3927183275 |
|
|
Apr 30 01:40:59 PM PDT 24 |
Apr 30 01:41:02 PM PDT 24 |
89567734 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4151536496 |
|
|
Apr 30 01:41:11 PM PDT 24 |
Apr 30 01:41:13 PM PDT 24 |
49809369 ps |
| T120 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1113997343 |
|
|
Apr 30 01:40:57 PM PDT 24 |
Apr 30 01:40:59 PM PDT 24 |
88845025 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2548901054 |
|
|
Apr 30 01:40:59 PM PDT 24 |
Apr 30 01:41:01 PM PDT 24 |
127331896 ps |
| T993 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.865744297 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:12 PM PDT 24 |
89292968 ps |
| T994 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2079384327 |
|
|
Apr 30 01:41:12 PM PDT 24 |
Apr 30 01:41:14 PM PDT 24 |
117924850 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.100039591 |
|
|
Apr 30 01:41:00 PM PDT 24 |
Apr 30 01:41:02 PM PDT 24 |
52070168 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3219913972 |
|
|
Apr 30 01:41:10 PM PDT 24 |
Apr 30 01:41:13 PM PDT 24 |
288704902 ps |
| T997 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1853536242 |
|
|
Apr 30 01:40:49 PM PDT 24 |
Apr 30 01:40:54 PM PDT 24 |
2573540779 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3485897176 |
|
|
Apr 30 01:40:50 PM PDT 24 |
Apr 30 01:40:51 PM PDT 24 |
59087419 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2868943168 |
|
|
Apr 30 01:41:08 PM PDT 24 |
Apr 30 01:41:14 PM PDT 24 |
1213690420 ps |
| T1000 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3703202721 |
|
|
Apr 30 01:41:04 PM PDT 24 |
Apr 30 01:41:05 PM PDT 24 |
113504334 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3154600656 |
|
|
Apr 30 01:40:52 PM PDT 24 |
Apr 30 01:40:55 PM PDT 24 |
1138586413 ps |