SRAM_CTRL/RET Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.273m	734.852us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	13.942us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	42.025us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.350s	185.481us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	34.641us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.170s	258.745us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	42.025us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	34.641us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.660s	448.002us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.360s	724.299us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	27.091m	66.824ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.002m	44.726ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.641m	21.665ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.002m	11.143ms	1	50	2.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.730s	924.082us	50	50	100.00
V2	executable	sram_ctrl_executable	31.110m	21.936ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.721m	3.553ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.307m	327.971ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.821m	154.010us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.916m	613.975us	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.694m	18.028ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.900s	89.254us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.039h	19.512ms	0	50	0.00
V2	alert_test	sram_ctrl_alert_test	0.740s	85.765us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.190s	173.394us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.190s	173.394us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	13.942us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	42.025us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	34.641us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	23.466us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	13.942us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	42.025us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	34.641us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	23.466us	20	20	100.00
V2		TOTAL			639	740	86.35
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.000s	3.911ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.110s	211.210us	5	5	100.00
		sram_ctrl_tl_intg_err	4.090s	792.979us	14	20	70.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.110s	211.210us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.090s	792.979us	14	20	70.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.694m	18.028ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	42.025us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.110m	21.936ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.110m	21.936ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.110m	21.936ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.730s	924.082us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.000s	3.911ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.273m	734.852us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.273m	734.852us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.273m	734.852us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.110m	21.936ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.110s	211.210us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.730s	924.082us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.110s	211.210us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.110s	211.210us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.273m	734.852us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.110s	211.210us	5	5	100.00
V2S		TOTAL			38	45	84.44
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	19.853m	3.522ms	4	50	8.00
V3		TOTAL			4	50	8.00
		TOTAL			884	1040	85.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	1	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.27	99.18	95.41	100.00	100.00	96.12	99.56	97.62

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 101 failures:

Test sram_ctrl_stress_all_with_rand_reset has 45 failures.

0.sram_ctrl_stress_all_with_rand_reset.28249389104873511887660149581565237320804683758661910646256341578377073764667
Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 163557607 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 163662867 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 163778653 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 596986709 ps: (sram_ctrl_smoke_vseq.sv:62) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] iteration: 1
  UVM_INFO @ 597007761 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value

1.sram_ctrl_stress_all_with_rand_reset.43648332597329472631179753689971290588295540987005033067233159636551685524894
Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 165885805 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 165925805 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 165945805 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 166762617 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq]
  Reset is issued for run 1/5

... and 43 more failures.

Test sram_ctrl_stress_all has 50 failures.

0.sram_ctrl_stress_all.100405554770400767541920858184481273020765672097007496601321364057552347759788
Line 337, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 731199961 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 731221013 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 731242065 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_lc_escalation_vseq] Update READBACK Value
  UVM_INFO @ 731263117 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 746557395 ps: (sram_ctrl_smoke_vseq.sv:62) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] iteration: 3

1.sram_ctrl_stress_all.7508433169563811841106769109619413261985910471181310012671685967571397538403
Line 289, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 402581725 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 402601725 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 402621725 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Update READBACK Value
  UVM_INFO @ 408051725 ps: (sram_ctrl_stress_all_vseq.sv:47) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] iteration[2]: starting sram_ctrl_smoke_vseq
  UVM_INFO @ 408081725 ps: (sram_ctrl_smoke_vseq.sv:54) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Performing 40 random memory accesses after reset!

... and 48 more failures.

Test sram_ctrl_tl_intg_err has 5 failures.

5.sram_ctrl_tl_intg_err.98212731338487844654714843291632364580894885838272834617854221527284727090645
Line 648, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 240387407 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 240482141 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 240524245 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 241799366 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 242324191 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

6.sram_ctrl_tl_intg_err.27182849469217785426882139481421138992627541778847834413787583740771278313294
Line 512, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 166727843 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 166727843 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 166727843 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 170044552 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 3836377112 val
  UVM_INFO @ 170084956 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds 2136148080 val

... and 3 more failures.

Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.

15.sram_ctrl_passthru_mem_tl_intg_err.21097851946139951084795041920341180145794025829046545494248249159484008644578
Line 471, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_WARNING @ 1889996435 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 1890680651 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 1891049075 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 1910154491 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 1915996643 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

UVM_ERROR (sram_ctrl_scoreboard.sv:422) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 46 failures:
- Test sram_ctrl_access_during_key_req has 46 failures.
  - 0.sram_ctrl_access_during_key_req.5300565965546082382613165075058553457394575309835443645974876998727304675703
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 1443279629 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 1443279629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_access_during_key_req.55966346314417977528096196629211639676196011462963733493860301976035913766582
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 202354733 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 202354733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 44 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:441) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 3 failures:
- Test sram_ctrl_access_during_key_req has 3 failures.
  - 16.sram_ctrl_access_during_key_req.19027684671602969892548599046700772680219096548878739185999719783083140786357
    Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 1343581139 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 1343581139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.sram_ctrl_access_during_key_req.105383893676513760433342474128513379535370723281420412007790505162667360465699
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 146853674 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 146853674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 2.sram_ctrl_tl_intg_err.11731622688107485097278570965673423384134736547858292192040360243063781206559
    Line 576, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 1097224666 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 1097224666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 16.sram_ctrl_csr_mem_rw_with_rand_reset.93325607070731924138309136348941952753239519804020177918463842877346454469454
    Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 454201544 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @ 454201544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 18.sram_ctrl_csr_mem_rw_with_rand_reset.1787279460559473015933644753878631070709920247406528965584697708411649826445
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 186333062 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @ 186333062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 21.sram_ctrl_regwen.66261872812737139439293846560580521107747403322103958079725468418947983293959
    Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 25694768529 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xd3141734
  UVM_INFO @ 25694768529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 41.sram_ctrl_stress_all_with_rand_reset.10622644276210350207051221551113941442448721797248563208419850036144879541710
    Line 296, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2609633061 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2609633061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 46.sram_ctrl_multiple_keys.109412496498278614898223127383650308325633575303479055276136505432170518238480
    Line 311, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 49932079057 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x5172890a
  UVM_INFO @ 49932079057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```