SRAM_CTRL/RET Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.632m	737.339us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	25.467us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	18.370us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.290s	531.394us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	50.582us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.690s	43.905us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	18.370us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	50.582us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.960s	4.877ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.270s	191.612us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	39.115m	10.956ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.244m	28.394ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.498m	5.624ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.624m	3.518ms	3	50	6.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.990s	1.616ms	50	50	100.00
V2	executable	sram_ctrl_executable	34.578m	52.878ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.172m	1.229ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.030m	91.392ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.615m	136.557us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.323m	158.423us	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.181m	69.784ms	47	50	94.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.900s	66.043us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.461h	16.630ms	1	50	2.00
V2	alert_test	sram_ctrl_alert_test	0.730s	29.036us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.420s	547.339us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.420s	547.339us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	25.467us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	18.370us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	50.582us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	106.129us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	25.467us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	18.370us	20	20	100.00
		sram_ctrl_csr_aliasing	0.780s	50.582us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	106.129us	20	20	100.00
V2		TOTAL			639	740	86.35
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.930s	3.901ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.220s	386.220us	5	5	100.00
		sram_ctrl_tl_intg_err	3.450s	580.923us	14	20	70.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.220s	386.220us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.450s	580.923us	14	20	70.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.181m	69.784ms	47	50	94.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	18.370us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.578m	52.878ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.578m	52.878ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.578m	52.878ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.990s	1.616ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.930s	3.901ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.632m	737.339us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.632m	737.339us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.632m	737.339us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.578m	52.878ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.220s	386.220us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.990s	1.616ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.220s	386.220us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.220s	386.220us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.632m	737.339us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.220s	386.220us	5	5	100.00
V2S		TOTAL			39	45	86.67
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	19.509m	17.976ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			888	1040	85.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.24	99.18	95.41	100.00	100.00	96.12	99.56	97.44

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 93 failures:

Test sram_ctrl_stress_all_with_rand_reset has 39 failures.

0.sram_ctrl_stress_all_with_rand_reset.101567424809616768771566519875226544632971135746485538885756325886826213067923
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 1120533612 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 1120804441 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 1120971105 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value
  UVM_INFO @ 1122660277 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq]
  Reset is issued for run 1/5

1.sram_ctrl_stress_all_with_rand_reset.10058290523606789166768259294376357909173408957277478092562278961899759653929
Line 309, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 765660448 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 766486530 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 766616964 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 804529780 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Update READBACK Value
  UVM_INFO @ 813530726 ps: (sram_ctrl_smoke_vseq.sv:101) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Performing 5262 random memory accesses!

... and 37 more failures.

Test sram_ctrl_stress_all has 49 failures.

0.sram_ctrl_stress_all.26438639663041787251637858153141414460678518823158929698993848909700623142246
Line 430, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 15112279910 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 15112397558 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Update READBACK Value
  UVM_WARNING @ 15112397558 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 15112515206 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Update READBACK Value
  UVM_INFO @ 15112632854 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Update READBACK Value

1.sram_ctrl_stress_all.96621044224196977881939212437652954835578800951871706781821415828765336565535
Line 508, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 52395806727 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 52396163872 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 52396306730 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 52563807735 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 52801023444 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value

... and 47 more failures.

Test sram_ctrl_tl_intg_err has 5 failures.

4.sram_ctrl_tl_intg_err.72641722314985707300787063577008327631018060609855039901275346084050265649427
Line 382, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @  73225133 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @  73225133 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @  73225133 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @  74374021 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 3547186143 val
  UVM_INFO @  74445449 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds  192128375 val

6.sram_ctrl_tl_intg_err.55593016377295492115061115158805014025815198991299336175176062317757983279434
Line 478, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 148564748 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 148666788 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 148758624 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 153105528 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Running run_tl_intg_err_vseq 12/20
  UVM_INFO @ 154013684 ps: (cip_tl_seq_item.sv:121) uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below:

... and 3 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:422) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 43 failures:
- Test sram_ctrl_access_during_key_req has 43 failures.
  - 0.sram_ctrl_access_during_key_req.19474223681664763071302233652342825607781073332000973741417342748538324362153
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 440086127 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 440086127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_access_during_key_req.27092116355809697425328342669595643234394858380742447758298573476915015623027
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 211863107 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 211863107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 41 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:441) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 4 failures:
- Test sram_ctrl_access_during_key_req has 4 failures.
  - 11.sram_ctrl_access_during_key_req.35015412845928479985080255971159356617707141126802383083491555428086876336491
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 3323295210 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 3323295210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.sram_ctrl_access_during_key_req.75054052840650498960305242966711306516867954661481963928415160734036592280780
    Line 300, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 3114341768 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 3114341768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_regwen has 3 failures.
  - 4.sram_ctrl_regwen.58777176797100977847251636974149417806930960945608676992295658595924545193019
    Line 296, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 20779254405 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x3024ea29
  UVM_INFO @ 20779254405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.sram_ctrl_regwen.82904389287994471152615905008953539354526046600151830369263639396797999452722
    Line 303, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 30995771264 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x334b4f17
  UVM_INFO @ 30995771264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 3 failures.
  - 13.sram_ctrl_stress_all_with_rand_reset.56776708190280924988459711976423004774042024094866494547506131341254461947076
    Line 295, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1176607112 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1176607112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.sram_ctrl_stress_all_with_rand_reset.93341753754379010253267840987606875587180889768648541219786220472320593035962
    Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1178560508 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1178560508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_executable has 2 failures.
  - 15.sram_ctrl_executable.1716232581085147541322964101675586767733816165758929476646333740339952961026
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 10519989868 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x38de311b
  UVM_INFO @ 10519989868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.sram_ctrl_executable.35130380412590910165612623689126341738132181294509649168898652615118671081178
    Line 293, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 25406853613 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xb0f2de0e
  UVM_INFO @ 25406853613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 37.sram_ctrl_stress_all_with_rand_reset.45573544233405272365197270037095607927949087578263696039753442011974132138998
    Line 297, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13213645951 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x4ec59240
  UVM_INFO @ 13213645951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 18.sram_ctrl_tl_intg_err.92067665593924086407493554229827318646470913371611890403406274629658535320942
    Line 370, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 130976296 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 130976296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 18.sram_ctrl_csr_mem_rw_with_rand_reset.44644702608578179649573609481857833432992982442200675217106485660184007027120
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 123962132 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @ 123962132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 20.sram_ctrl_stress_all_with_rand_reset.80229979065484564581981951746021359085718342561426531234915182063629182525210
    Line 289, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108480672 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 108480672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```