SRAM_CTRL/RET Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.305m 3.015ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 13.123us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 13.600us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.330s 339.083us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.770s 32.931us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 5.750s 10.009ms 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 13.600us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 32.931us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 10.530s 671.141us 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.710s 588.033us 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 32.769m 37.654ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.051m 4.363ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.384m 16.352ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 28.140m 32.029ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 11.360s 1.992ms 50 50 100.00
V2 executable sram_ctrl_executable 25.596m 70.570ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.607m 221.934us 50 50 100.00
sram_ctrl_partial_access_b2b 9.632m 82.142ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.961m 143.810us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.774m 157.239us 50 50 100.00
V2 regwen sram_ctrl_regwen 24.483m 4.374ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.910s 77.845us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.434h 319.826ms 45 50 90.00
V2 alert_test sram_ctrl_alert_test 0.730s 40.638us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.100s 1.520ms 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.100s 1.520ms 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 13.123us 5 5 100.00
sram_ctrl_csr_rw 0.720s 13.600us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 32.931us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.800s 29.395us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 13.123us 5 5 100.00
sram_ctrl_csr_rw 0.720s 13.600us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 32.931us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.800s 29.395us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.550s 1.703ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.500s 413.741us 5 5 100.00
sram_ctrl_tl_intg_err 2.850s 1.820ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.500s 413.741us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.850s 1.820ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 24.483m 4.374ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 13.600us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 25.596m 70.570ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 25.596m 70.570ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 25.596m 70.570ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 11.360s 1.992ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.550s 1.703ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.305m 3.015ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.305m 3.015ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 25.596m 70.570ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.500s 413.741us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 11.360s 1.992ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.500s 413.741us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.500s 413.741us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.305m 3.015ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.500s 413.741us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 21.895m 5.217ms 43 50 86.00
V3 TOTAL 43 50 86.00
TOTAL 1027 1040 98.75

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52

Failure Buckets

Past Results