SRAM_CTRL/RET Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.572m	312.336us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	47.806us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	16.306us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.900s	46.432us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	23.464us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.810s	151.404us	14	20	70.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	16.306us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	23.464us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.330s	1.764ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.210s	1.474ms	50	50	100.00
V1		TOTAL			199	205	97.07
V2	multiple_keys	sram_ctrl_multiple_keys	35.720m	13.098ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	9.353m	9.668ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.575m	20.744ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.003m	2.356ms	1	50	2.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.770s	8.404ms	50	50	100.00
V2	executable	sram_ctrl_executable	36.230m	5.346ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.706m	725.279us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.806m	87.239ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.556m	138.199us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.370m	614.865us	50	50	100.00
V2	regwen	sram_ctrl_regwen	40.761m	42.944ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.840s	197.594us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.573h	433.898ms	0	50	0.00
V2	alert_test	sram_ctrl_alert_test	0.710s	16.494us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.970s	571.446us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.970s	571.446us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	47.806us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	16.306us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	23.464us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.920s	240.663us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	47.806us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	16.306us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	23.464us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.920s	240.663us	20	20	100.00
V2		TOTAL			639	740	86.35
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.120s	5.565ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.440s	1.393ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.860s	345.862us	17	20	85.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.440s	1.393ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.860s	345.862us	17	20	85.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	40.761m	42.944ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	16.306us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	36.230m	5.346ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	36.230m	5.346ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	36.230m	5.346ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.770s	8.404ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.120s	5.565ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.572m	312.336us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.572m	312.336us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.572m	312.336us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	36.230m	5.346ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.440s	1.393ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.770s	8.404ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.440s	1.393ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.440s	1.393ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.572m	312.336us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.440s	1.393ms	5	5	100.00
V2S		TOTAL			42	45	93.33
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	18.117m	35.118ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			887	1040	85.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.38	99.41	95.61	100.00	100.00	96.49	99.56	97.62

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 93 failures:

Test sram_ctrl_stress_all has 50 failures.

0.sram_ctrl_stress_all.107312269952838218672842631829298101120269905219821055267820188850507166527024
Line 594, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 14762043980 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 14762248523 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Update READBACK Value
  UVM_INFO @ 14762453066 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Update READBACK Value
  UVM_INFO @ 14786589140 ps: (sram_ctrl_smoke_vseq.sv:101) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Performing 8729 random memory accesses!
  UVM_INFO @ 16175845196 ps: (sram_ctrl_smoke_vseq.sv:62) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] iteration: 4

1.sram_ctrl_stress_all.48552175506867658181681226132422562831780812771123053364834645942729107145373
Line 681, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

  UVM_WARNING @ 26961085366 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 26961205366 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @ 26961245366 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 28159185366 ps: (sram_ctrl_smoke_vseq.sv:62) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] iteration: 3
  UVM_INFO @ 28159345366 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value

... and 48 more failures.

Test sram_ctrl_stress_all_with_rand_reset has 40 failures.

1.sram_ctrl_stress_all_with_rand_reset.36672289776458369261004972971783537589316096429733096293348665384924864708340
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @  80463732 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @  80503732 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_stress_all_vseq] Update READBACK Value
  UVM_INFO @  80523732 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @  81335480 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq]
  Reset is issued for run 1/5

2.sram_ctrl_stress_all_with_rand_reset.50882330577509177625712083752374243354518982826760285708680184686329996411203
Line 352, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 1054087497 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 1054170831 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 1054254165 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Update READBACK Value
  UVM_INFO @ 1071962640 ps: (sram_ctrl_smoke_vseq.sv:62) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] iteration: 2
  UVM_INFO @ 1071962640 ps: (sram_ctrl_smoke_vseq.sv:101) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Performing 10000 random memory accesses!

... and 38 more failures.

Test sram_ctrl_tl_intg_err has 3 failures.

1.sram_ctrl_tl_intg_err.41351163256632671031888973443920399122909226230258542661146635666637410287268
Line 508, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 114580789 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 114680789 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 114780789 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 114820789 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 116655054 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value

8.sram_ctrl_tl_intg_err.1437476506554883267442115249612529243192442748557996966876133483555559213079
Line 631, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest/run.log

  UVM_WARNING @ 825076098 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 825076098 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 825076098 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 827703503 ps: (sram_ctrl_base_vseq.sv:65) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Update READBACK Value
  UVM_INFO @ 830387735 ps: (dv_base_reg.sv:325) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds 3447740918 val

... and 1 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:422) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 45 failures:
- Test sram_ctrl_access_during_key_req has 45 failures.
  - 0.sram_ctrl_access_during_key_req.109793870305372610311427399837303574789635140228814336182217811226170868820082
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @  71884383 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @  71884383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_access_during_key_req.43565955829567435062945859193897024944561422791171007547095128373553177102096
    Line 283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 558511735 ps: (sram_ctrl_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 558511735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 43 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:441) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 4 failures:
- Test sram_ctrl_access_during_key_req has 4 failures.
  - 8.sram_ctrl_access_during_key_req.71533495804793851252014509894540847329679676037205388412259534473556152496118
    Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 985202912 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 985202912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.sram_ctrl_access_during_key_req.71147898531378895336302589448752912513537738540749754317505454410302695672040
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest/run.log
```
  UVM_ERROR @ 1898174753 ps: (sram_ctrl_scoreboard.sv:441) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
  UVM_INFO @ 1898174753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 3 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 3 failures.
  - 5.sram_ctrl_csr_mem_rw_with_rand_reset.38134226754246359772122920028363660699030684511081681098948115100212873256431
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 278869081 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @ 278869081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.sram_ctrl_csr_mem_rw_with_rand_reset.25313543939714964331943616874795527435891183634158405297957518857233756063344
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106686779 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @ 106686779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 3 failures.
  - 22.sram_ctrl_stress_all_with_rand_reset.37643663670861603787052922670315607012435962053605914792787836786629556975076
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 610738261 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 610738261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.sram_ctrl_stress_all_with_rand_reset.6325242307938870618623705988390424702631189017355336016469661257351867730256
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3898458840 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3898458840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.12281793392201831894045820046557528504165643577205518991015897640151348842291
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  46431623 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  46431623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.sram_ctrl_csr_mem_rw_with_rand_reset.6222875640769870385703611577565443057893770336790634366256595571887289668811
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  24087080 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  24087080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 11.sram_ctrl_regwen.2017100250660833337337115524791482648368532207906889575244952953024628952454
    Line 304, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 38271794597 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xc7636844
  UVM_INFO @ 38271794597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 12.sram_ctrl_csr_mem_rw_with_rand_reset.2532876057841514164185182369364355291307143629890668256991011176491617102155
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  30982504 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  30982504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 47.sram_ctrl_multiple_keys.10174493611003817171233163968315064107162443851644158099200210308602469090904
    Line 331, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 78825457075 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xacf5e871
  UVM_INFO @ 78825457075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```