SRAM_CTRL/RET Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.677m	2.697ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	26.373us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	52.878us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.120s	242.535us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	43.907us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.040s	228.760us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	52.878us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	43.907us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.020s	664.058us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.120s	670.112us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	35.891m	25.239ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.263m	41.703ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.465m	5.650ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.151m	5.107ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.440s	12.578ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.065m	6.990ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.133m	6.418ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.416m	21.133ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.635m	139.128us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.515m	314.217us	50	50	100.00
V2	regwen	sram_ctrl_regwen	41.444m	22.439ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.940s	387.560us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.223h	1.291s	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.740s	19.203us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.300s	547.210us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.300s	547.210us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	26.373us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	52.878us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	43.907us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	16.386us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	26.373us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	52.878us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	43.907us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	16.386us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.600s	1.537ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.820s	12.500us	0	5	0.00
		sram_ctrl_tl_intg_err	2.590s	641.570us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.820s	12.500us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.590s	641.570us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	41.444m	22.439ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	52.878us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.065m	6.990ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.065m	6.990ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.065m	6.990ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.440s	12.578ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.600s	1.537ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.677m	2.697ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.677m	2.697ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.677m	2.697ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.065m	6.990ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.820s	12.500us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.440s	12.578ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.820s	12.500us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.820s	12.500us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.677m	2.697ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.820s	12.500us	0	5	0.00
V2S		TOTAL			40	45	88.89
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.012m	36.392ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			1027	1040	98.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	2	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	98.99	92.48	99.31	100.00	95.26	98.38	97.26

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 4 failures.
  - 5.sram_ctrl_stress_all_with_rand_reset.83398607774623823942787960518375827475108576583364989902569020499849189632783
    Line 314, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1688586678 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1688586678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.sram_ctrl_stress_all_with_rand_reset.86447604034616968498777002699911651305001039607057985476551629235091428683561
    Line 405, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1926130753 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1926130753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Offending '(!$isunknown(tl_o.d_valid))' has 2 failures:
- Test sram_ctrl_sec_cm has 2 failures.
  - 0.sram_ctrl_sec_cm.98682464075322600572893615114301077147125972793296728048063027731025434893001
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(tl_o.d_valid))'
  UVM_ERROR @   1623784 ps: (tlul_adapter_sram.sv:623) [ASSERT FAILED] TlOutValidKnown_A
  UVM_INFO @   1623784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.sram_ctrl_sec_cm.56609551489348510459180812680063277259783245802646353310733318529066774665067
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(tl_o.d_valid))'
  UVM_ERROR @  21498698 ps: (tlul_adapter_sram.sv:623) [ASSERT FAILED] TlOutValidKnown_A
  UVM_INFO @  21498698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:
- Test sram_ctrl_sec_cm has 2 failures.
  - 3.sram_ctrl_sec_cm.85123879510400610828872063803220515114448299788754570938691688244271027930533
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  10083277 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  10083277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.sram_ctrl_sec_cm.114336765277218205046281834081954344857522531663275730348336835069580479865968
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  12500321 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  12500321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

21.sram_ctrl_stress_all.86086805224405388432498368417478465136694901984794341900825445179275650682591
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 352387807 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 352387807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.sram_ctrl_stress_all.52232846014240358224971300443392224445677863467123272024490682322508478774030
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 260137848 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 260137848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 1.sram_ctrl_sec_cm.26918730798190044535909751118376488140158831814599513700116605516789192159732
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  10558792 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  10558792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 2.sram_ctrl_regwen.46917996055059679090812824535910610710345834200136168281556744016818300142140
    Line 285, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 57304693403 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xd918f1b0
  UVM_INFO @ 57304693403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 37.sram_ctrl_stress_all.72414304623825576046900413584338039219465237842414242932234632895518265409291
    Line 287, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 170441418793 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xa3daa668
  UVM_INFO @ 170441418793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```