| T299 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3210950840 |
|
|
Aug 23 06:42:36 AM UTC 24 |
Aug 23 06:42:57 AM UTC 24 |
2237489416 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3285171084 |
|
|
Aug 23 06:42:46 AM UTC 24 |
Aug 23 06:43:00 AM UTC 24 |
87972244 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.3492192093 |
|
|
Aug 23 06:43:01 AM UTC 24 |
Aug 23 06:43:03 AM UTC 24 |
78155791 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1286383380 |
|
|
Aug 23 06:37:24 AM UTC 24 |
Aug 23 06:43:11 AM UTC 24 |
3978148586 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2192597396 |
|
|
Aug 23 06:43:03 AM UTC 24 |
Aug 23 06:43:14 AM UTC 24 |
1781320176 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3042877218 |
|
|
Aug 23 06:43:12 AM UTC 24 |
Aug 23 06:43:16 AM UTC 24 |
47726402 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.259837770 |
|
|
Aug 23 06:42:44 AM UTC 24 |
Aug 23 06:43:36 AM UTC 24 |
151391214 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1035203970 |
|
|
Aug 23 06:43:36 AM UTC 24 |
Aug 23 06:43:38 AM UTC 24 |
13851734 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3852776523 |
|
|
Aug 23 06:39:59 AM UTC 24 |
Aug 23 06:43:42 AM UTC 24 |
29753907452 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3768066687 |
|
|
Aug 23 06:43:15 AM UTC 24 |
Aug 23 06:43:51 AM UTC 24 |
2449245346 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3535717724 |
|
|
Aug 23 06:43:38 AM UTC 24 |
Aug 23 06:43:59 AM UTC 24 |
683038989 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.605627183 |
|
|
Aug 23 06:41:49 AM UTC 24 |
Aug 23 06:44:11 AM UTC 24 |
3034774735 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2116667293 |
|
|
Aug 23 06:33:00 AM UTC 24 |
Aug 23 06:44:14 AM UTC 24 |
70133630311 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.774457169 |
|
|
Aug 23 06:18:37 AM UTC 24 |
Aug 23 06:44:26 AM UTC 24 |
121000265314 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1687782830 |
|
|
Aug 23 06:44:12 AM UTC 24 |
Aug 23 06:44:27 AM UTC 24 |
117444359 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.1179758618 |
|
|
Aug 23 06:43:52 AM UTC 24 |
Aug 23 06:44:27 AM UTC 24 |
2265873628 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.4248410055 |
|
|
Aug 23 06:35:48 AM UTC 24 |
Aug 23 06:44:36 AM UTC 24 |
9767523778 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1970308052 |
|
|
Aug 23 06:44:29 AM UTC 24 |
Aug 23 06:44:36 AM UTC 24 |
712623144 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3108653248 |
|
|
Aug 23 06:23:18 AM UTC 24 |
Aug 23 06:44:46 AM UTC 24 |
74704816775 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1660729916 |
|
|
Aug 23 06:39:19 AM UTC 24 |
Aug 23 06:44:58 AM UTC 24 |
2037654818 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.1661075589 |
|
|
Aug 23 06:36:01 AM UTC 24 |
Aug 23 06:44:59 AM UTC 24 |
10014109586 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.2629326233 |
|
|
Aug 23 06:44:59 AM UTC 24 |
Aug 23 06:45:01 AM UTC 24 |
79466264 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3349871665 |
|
|
Aug 23 06:45:00 AM UTC 24 |
Aug 23 06:45:06 AM UTC 24 |
95693015 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2259715518 |
|
|
Aug 23 06:45:02 AM UTC 24 |
Aug 23 06:45:07 AM UTC 24 |
65311133 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.964303608 |
|
|
Aug 23 06:44:47 AM UTC 24 |
Aug 23 06:45:13 AM UTC 24 |
1515611619 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3234337930 |
|
|
Aug 23 06:45:13 AM UTC 24 |
Aug 23 06:45:15 AM UTC 24 |
13228326 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1914342843 |
|
|
Aug 23 06:45:06 AM UTC 24 |
Aug 23 06:45:16 AM UTC 24 |
1108302359 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2661955030 |
|
|
Aug 23 06:44:28 AM UTC 24 |
Aug 23 06:45:23 AM UTC 24 |
307935225 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.316439834 |
|
|
Aug 23 06:18:25 AM UTC 24 |
Aug 23 06:45:27 AM UTC 24 |
36377734052 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2463648204 |
|
|
Aug 23 06:44:27 AM UTC 24 |
Aug 23 06:45:29 AM UTC 24 |
248584480 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.890814285 |
|
|
Aug 23 06:45:16 AM UTC 24 |
Aug 23 06:45:33 AM UTC 24 |
737454063 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3755913108 |
|
|
Aug 23 06:43:42 AM UTC 24 |
Aug 23 06:45:34 AM UTC 24 |
3241043736 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.261173707 |
|
|
Aug 23 06:45:30 AM UTC 24 |
Aug 23 06:45:37 AM UTC 24 |
168206491 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2973299049 |
|
|
Aug 23 06:45:35 AM UTC 24 |
Aug 23 06:45:50 AM UTC 24 |
78417045 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.886714355 |
|
|
Aug 23 06:42:42 AM UTC 24 |
Aug 23 06:45:50 AM UTC 24 |
13045638088 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2817790216 |
|
|
Aug 23 06:45:51 AM UTC 24 |
Aug 23 06:45:57 AM UTC 24 |
1976392165 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.2940758781 |
|
|
Aug 23 06:45:24 AM UTC 24 |
Aug 23 06:45:58 AM UTC 24 |
2755673699 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.2891723259 |
|
|
Aug 23 06:42:58 AM UTC 24 |
Aug 23 06:46:02 AM UTC 24 |
3982415205 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2384451636 |
|
|
Aug 23 06:40:48 AM UTC 24 |
Aug 23 06:46:04 AM UTC 24 |
9818368536 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.481361580 |
|
|
Aug 23 06:46:02 AM UTC 24 |
Aug 23 06:46:04 AM UTC 24 |
33923925 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.897363337 |
|
|
Aug 23 06:46:04 AM UTC 24 |
Aug 23 06:46:09 AM UTC 24 |
255091312 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.932092675 |
|
|
Aug 23 06:46:04 AM UTC 24 |
Aug 23 06:46:09 AM UTC 24 |
281454243 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1579699189 |
|
|
Aug 23 06:45:38 AM UTC 24 |
Aug 23 06:46:17 AM UTC 24 |
130424187 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2585392566 |
|
|
Aug 23 06:46:10 AM UTC 24 |
Aug 23 06:46:19 AM UTC 24 |
878684686 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2612076078 |
|
|
Aug 23 06:46:17 AM UTC 24 |
Aug 23 06:46:19 AM UTC 24 |
20457954 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.2644758556 |
|
|
Aug 23 06:42:53 AM UTC 24 |
Aug 23 06:46:20 AM UTC 24 |
11113121254 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.1975848850 |
|
|
Aug 23 06:45:58 AM UTC 24 |
Aug 23 06:46:21 AM UTC 24 |
1680721245 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3773958308 |
|
|
Aug 23 06:28:50 AM UTC 24 |
Aug 23 06:46:26 AM UTC 24 |
97269489277 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.3335405194 |
|
|
Aug 23 06:44:37 AM UTC 24 |
Aug 23 06:46:35 AM UTC 24 |
4169761948 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.4064965268 |
|
|
Aug 23 06:45:17 AM UTC 24 |
Aug 23 06:46:47 AM UTC 24 |
4577518546 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.3342668997 |
|
|
Aug 23 06:46:20 AM UTC 24 |
Aug 23 06:47:20 AM UTC 24 |
1459499394 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2191957271 |
|
|
Aug 23 06:46:48 AM UTC 24 |
Aug 23 06:47:24 AM UTC 24 |
125909476 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1232756948 |
|
|
Aug 23 06:46:27 AM UTC 24 |
Aug 23 06:47:27 AM UTC 24 |
2668505498 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2349920619 |
|
|
Aug 23 06:47:24 AM UTC 24 |
Aug 23 06:47:31 AM UTC 24 |
3143120177 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3231650537 |
|
|
Aug 23 06:43:59 AM UTC 24 |
Aug 23 06:47:31 AM UTC 24 |
21948145049 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2174474279 |
|
|
Aug 23 06:47:21 AM UTC 24 |
Aug 23 06:47:35 AM UTC 24 |
87536751 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3891753179 |
|
|
Aug 23 06:42:52 AM UTC 24 |
Aug 23 06:47:36 AM UTC 24 |
17206004005 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.910788458 |
|
|
Aug 23 06:47:35 AM UTC 24 |
Aug 23 06:47:37 AM UTC 24 |
27457394 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.2062892604 |
|
|
Aug 23 06:46:21 AM UTC 24 |
Aug 23 06:47:40 AM UTC 24 |
5591795743 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.731927833 |
|
|
Aug 23 06:47:37 AM UTC 24 |
Aug 23 06:47:41 AM UTC 24 |
95958263 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.381884226 |
|
|
Aug 23 06:47:36 AM UTC 24 |
Aug 23 06:47:43 AM UTC 24 |
227070627 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.1241155328 |
|
|
Aug 23 06:47:44 AM UTC 24 |
Aug 23 06:47:45 AM UTC 24 |
48663171 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.670868358 |
|
|
Aug 23 06:41:35 AM UTC 24 |
Aug 23 06:47:45 AM UTC 24 |
2159345199 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.3277379056 |
|
|
Aug 23 06:34:12 AM UTC 24 |
Aug 23 06:48:13 AM UTC 24 |
17080836889 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.3519232167 |
|
|
Aug 23 06:47:46 AM UTC 24 |
Aug 23 06:48:15 AM UTC 24 |
1000629282 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.87919867 |
|
|
Aug 23 06:44:15 AM UTC 24 |
Aug 23 06:48:40 AM UTC 24 |
15048839685 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.743165826 |
|
|
Aug 23 06:48:14 AM UTC 24 |
Aug 23 06:48:44 AM UTC 24 |
2044312548 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1896032746 |
|
|
Aug 23 06:45:28 AM UTC 24 |
Aug 23 06:48:47 AM UTC 24 |
10039373535 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.1134884111 |
|
|
Aug 23 06:48:41 AM UTC 24 |
Aug 23 06:48:52 AM UTC 24 |
197201373 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.324901764 |
|
|
Aug 23 06:48:52 AM UTC 24 |
Aug 23 06:48:54 AM UTC 24 |
117691250 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.6240199 |
|
|
Aug 23 06:48:48 AM UTC 24 |
Aug 23 06:48:56 AM UTC 24 |
310965012 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2820709100 |
|
|
Aug 23 06:28:39 AM UTC 24 |
Aug 23 06:49:04 AM UTC 24 |
32739630035 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1072875913 |
|
|
Aug 23 06:48:46 AM UTC 24 |
Aug 23 06:49:47 AM UTC 24 |
156477861 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.4121697531 |
|
|
Aug 23 06:49:48 AM UTC 24 |
Aug 23 06:49:49 AM UTC 24 |
44283634 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3157351108 |
|
|
Aug 23 06:49:50 AM UTC 24 |
Aug 23 06:50:01 AM UTC 24 |
6276464702 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1989689198 |
|
|
Aug 23 06:50:03 AM UTC 24 |
Aug 23 06:50:06 AM UTC 24 |
92793452 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1197402575 |
|
|
Aug 23 06:32:18 AM UTC 24 |
Aug 23 06:50:11 AM UTC 24 |
3981077010 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3965589949 |
|
|
Aug 23 06:44:37 AM UTC 24 |
Aug 23 06:50:15 AM UTC 24 |
2256224036 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.4000487556 |
|
|
Aug 23 06:36:54 AM UTC 24 |
Aug 23 06:50:17 AM UTC 24 |
17543496028 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1497428371 |
|
|
Aug 23 06:50:16 AM UTC 24 |
Aug 23 06:50:18 AM UTC 24 |
18230044 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.1321719811 |
|
|
Aug 23 06:41:05 AM UTC 24 |
Aug 23 06:50:44 AM UTC 24 |
19720748789 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.2585930092 |
|
|
Aug 23 06:38:55 AM UTC 24 |
Aug 23 06:50:48 AM UTC 24 |
21125830549 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.1711396031 |
|
|
Aug 23 06:47:31 AM UTC 24 |
Aug 23 06:50:54 AM UTC 24 |
17151599467 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.882176824 |
|
|
Aug 23 06:45:34 AM UTC 24 |
Aug 23 06:50:55 AM UTC 24 |
15215337500 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.822184874 |
|
|
Aug 23 06:48:16 AM UTC 24 |
Aug 23 06:51:00 AM UTC 24 |
5215429292 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1201851800 |
|
|
Aug 23 06:51:00 AM UTC 24 |
Aug 23 06:51:02 AM UTC 24 |
75416669 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1440239421 |
|
|
Aug 23 06:51:03 AM UTC 24 |
Aug 23 06:51:05 AM UTC 24 |
233977119 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2662638908 |
|
|
Aug 23 06:50:17 AM UTC 24 |
Aug 23 06:51:06 AM UTC 24 |
1266632740 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.4201193453 |
|
|
Aug 23 06:46:20 AM UTC 24 |
Aug 23 06:51:06 AM UTC 24 |
6879753570 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3483511741 |
|
|
Aug 23 06:50:12 AM UTC 24 |
Aug 23 06:51:12 AM UTC 24 |
5876124985 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1903173104 |
|
|
Aug 23 06:45:58 AM UTC 24 |
Aug 23 06:51:12 AM UTC 24 |
6547649921 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3016372580 |
|
|
Aug 23 06:51:13 AM UTC 24 |
Aug 23 06:51:14 AM UTC 24 |
280590709 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2751863738 |
|
|
Aug 23 06:51:06 AM UTC 24 |
Aug 23 06:51:15 AM UTC 24 |
1262139170 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3857272562 |
|
|
Aug 23 06:51:16 AM UTC 24 |
Aug 23 06:51:22 AM UTC 24 |
193377085 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3925257028 |
|
|
Aug 23 06:51:16 AM UTC 24 |
Aug 23 06:51:26 AM UTC 24 |
1049734785 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2027159138 |
|
|
Aug 23 06:46:22 AM UTC 24 |
Aug 23 06:51:34 AM UTC 24 |
13281580878 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.4037666987 |
|
|
Aug 23 06:51:34 AM UTC 24 |
Aug 23 06:51:36 AM UTC 24 |
41678089 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2220172199 |
|
|
Aug 23 06:50:55 AM UTC 24 |
Aug 23 06:51:39 AM UTC 24 |
2192911598 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1477984549 |
|
|
Aug 23 06:46:36 AM UTC 24 |
Aug 23 06:51:45 AM UTC 24 |
12200334630 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.836368558 |
|
|
Aug 23 06:51:23 AM UTC 24 |
Aug 23 06:51:53 AM UTC 24 |
2671373893 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1071939919 |
|
|
Aug 23 06:48:55 AM UTC 24 |
Aug 23 06:52:08 AM UTC 24 |
2414729939 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3343639077 |
|
|
Aug 23 06:50:45 AM UTC 24 |
Aug 23 06:52:09 AM UTC 24 |
70989700983 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.2118823213 |
|
|
Aug 23 06:51:36 AM UTC 24 |
Aug 23 06:52:31 AM UTC 24 |
134947855 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.2295554092 |
|
|
Aug 23 06:34:12 AM UTC 24 |
Aug 23 06:52:37 AM UTC 24 |
38829806377 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.520899989 |
|
|
Aug 23 06:52:09 AM UTC 24 |
Aug 23 06:52:41 AM UTC 24 |
599374976 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.4039855099 |
|
|
Aug 23 06:51:46 AM UTC 24 |
Aug 23 06:52:41 AM UTC 24 |
13623197512 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3824014665 |
|
|
Aug 23 06:52:42 AM UTC 24 |
Aug 23 06:52:50 AM UTC 24 |
2427566134 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2630972854 |
|
|
Aug 23 06:39:20 AM UTC 24 |
Aug 23 06:52:53 AM UTC 24 |
6573690192 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.816906752 |
|
|
Aug 23 06:52:38 AM UTC 24 |
Aug 23 06:52:53 AM UTC 24 |
448752932 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2336131842 |
|
|
Aug 23 06:52:54 AM UTC 24 |
Aug 23 06:52:56 AM UTC 24 |
58575817 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3038531250 |
|
|
Aug 23 06:52:32 AM UTC 24 |
Aug 23 06:53:00 AM UTC 24 |
635071664 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.4076676461 |
|
|
Aug 23 06:53:01 AM UTC 24 |
Aug 23 06:53:05 AM UTC 24 |
58678778 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.860893034 |
|
|
Aug 23 06:52:56 AM UTC 24 |
Aug 23 06:53:08 AM UTC 24 |
1323441433 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.1902642341 |
|
|
Aug 23 06:50:49 AM UTC 24 |
Aug 23 06:53:36 AM UTC 24 |
19751350518 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1325365861 |
|
|
Aug 23 06:53:36 AM UTC 24 |
Aug 23 06:53:38 AM UTC 24 |
16236748 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3391495644 |
|
|
Aug 23 06:47:28 AM UTC 24 |
Aug 23 06:53:42 AM UTC 24 |
4004107983 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4118477329 |
|
|
Aug 23 06:50:07 AM UTC 24 |
Aug 23 06:53:49 AM UTC 24 |
6494643235 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.495196259 |
|
|
Aug 23 06:53:38 AM UTC 24 |
Aug 23 06:53:50 AM UTC 24 |
1201316558 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.2627327339 |
|
|
Aug 23 06:53:08 AM UTC 24 |
Aug 23 06:54:57 AM UTC 24 |
36852757719 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.1571718323 |
|
|
Aug 23 06:53:50 AM UTC 24 |
Aug 23 06:55:01 AM UTC 24 |
3772111140 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3376832171 |
|
|
Aug 23 06:45:51 AM UTC 24 |
Aug 23 06:55:11 AM UTC 24 |
11678989763 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.4177542089 |
|
|
Aug 23 06:55:01 AM UTC 24 |
Aug 23 06:55:18 AM UTC 24 |
90708700 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1636601849 |
|
|
Aug 23 06:55:18 AM UTC 24 |
Aug 23 06:55:21 AM UTC 24 |
145709133 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2961759860 |
|
|
Aug 23 06:54:25 AM UTC 24 |
Aug 23 06:55:37 AM UTC 24 |
5354752663 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3889284626 |
|
|
Aug 23 06:55:12 AM UTC 24 |
Aug 23 06:55:52 AM UTC 24 |
135231340 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3406688197 |
|
|
Aug 23 06:48:44 AM UTC 24 |
Aug 23 06:55:58 AM UTC 24 |
17800201380 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3530251165 |
|
|
Aug 23 06:56:00 AM UTC 24 |
Aug 23 06:56:02 AM UTC 24 |
53332224 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3745594691 |
|
|
Aug 23 06:56:03 AM UTC 24 |
Aug 23 06:56:13 AM UTC 24 |
342207268 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.142288399 |
|
|
Aug 23 06:56:14 AM UTC 24 |
Aug 23 06:56:17 AM UTC 24 |
423731713 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2751144845 |
|
|
Aug 23 06:53:51 AM UTC 24 |
Aug 23 06:56:40 AM UTC 24 |
1972826736 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.1768349091 |
|
|
Aug 23 06:51:13 AM UTC 24 |
Aug 23 06:56:41 AM UTC 24 |
1312077185 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1236746409 |
|
|
Aug 23 06:56:42 AM UTC 24 |
Aug 23 06:56:43 AM UTC 24 |
22828264 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.1320504106 |
|
|
Aug 23 06:56:44 AM UTC 24 |
Aug 23 06:56:46 AM UTC 24 |
54990270 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2169560893 |
|
|
Aug 23 06:31:29 AM UTC 24 |
Aug 23 06:57:04 AM UTC 24 |
207000426879 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.2282529982 |
|
|
Aug 23 06:47:46 AM UTC 24 |
Aug 23 06:57:24 AM UTC 24 |
18329871825 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2136709467 |
|
|
Aug 23 06:54:58 AM UTC 24 |
Aug 23 06:57:24 AM UTC 24 |
8247215862 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3858324191 |
|
|
Aug 23 06:51:53 AM UTC 24 |
Aug 23 06:57:32 AM UTC 24 |
3598076746 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2227648703 |
|
|
Aug 23 06:57:05 AM UTC 24 |
Aug 23 06:57:32 AM UTC 24 |
2719255733 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.127053393 |
|
|
Aug 23 06:56:18 AM UTC 24 |
Aug 23 06:57:37 AM UTC 24 |
2014078614 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2424676247 |
|
|
Aug 23 06:57:37 AM UTC 24 |
Aug 23 06:57:42 AM UTC 24 |
79992764 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1330750254 |
|
|
Aug 23 06:26:42 AM UTC 24 |
Aug 23 06:57:43 AM UTC 24 |
53097024501 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.416822090 |
|
|
Aug 23 06:57:42 AM UTC 24 |
Aug 23 06:57:45 AM UTC 24 |
120867410 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2802538105 |
|
|
Aug 23 06:57:32 AM UTC 24 |
Aug 23 06:57:46 AM UTC 24 |
292532572 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1219440317 |
|
|
Aug 23 06:52:43 AM UTC 24 |
Aug 23 06:58:35 AM UTC 24 |
9687232710 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3943415737 |
|
|
Aug 23 06:58:36 AM UTC 24 |
Aug 23 06:58:37 AM UTC 24 |
80159821 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1015231117 |
|
|
Aug 23 06:57:25 AM UTC 24 |
Aug 23 06:58:39 AM UTC 24 |
2691044640 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1318854948 |
|
|
Aug 23 06:48:56 AM UTC 24 |
Aug 23 06:58:42 AM UTC 24 |
2478889050 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.1662403587 |
|
|
Aug 23 06:58:38 AM UTC 24 |
Aug 23 06:58:44 AM UTC 24 |
468682486 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.819180105 |
|
|
Aug 23 06:58:40 AM UTC 24 |
Aug 23 06:58:45 AM UTC 24 |
246025492 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2453356131 |
|
|
Aug 23 06:58:46 AM UTC 24 |
Aug 23 06:58:48 AM UTC 24 |
40232280 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.2863185986 |
|
|
Aug 23 06:55:37 AM UTC 24 |
Aug 23 06:58:53 AM UTC 24 |
672505709 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3929129062 |
|
|
Aug 23 06:58:48 AM UTC 24 |
Aug 23 06:58:53 AM UTC 24 |
216256826 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.1059261019 |
|
|
Aug 23 06:56:47 AM UTC 24 |
Aug 23 06:59:01 AM UTC 24 |
6449519065 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2925120329 |
|
|
Aug 23 06:50:56 AM UTC 24 |
Aug 23 06:59:01 AM UTC 24 |
88941103561 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.877625327 |
|
|
Aug 23 06:59:01 AM UTC 24 |
Aug 23 06:59:04 AM UTC 24 |
63124476 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.1309098611 |
|
|
Aug 23 06:49:04 AM UTC 24 |
Aug 23 06:59:10 AM UTC 24 |
10376248004 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2457020512 |
|
|
Aug 23 06:52:51 AM UTC 24 |
Aug 23 06:59:29 AM UTC 24 |
9834248267 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3655615081 |
|
|
Aug 23 06:58:54 AM UTC 24 |
Aug 23 06:59:39 AM UTC 24 |
778382597 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3461170975 |
|
|
Aug 23 06:59:10 AM UTC 24 |
Aug 23 06:59:39 AM UTC 24 |
235736592 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.269351699 |
|
|
Aug 23 06:59:40 AM UTC 24 |
Aug 23 06:59:46 AM UTC 24 |
551178051 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2508642489 |
|
|
Aug 23 06:59:30 AM UTC 24 |
Aug 23 06:59:49 AM UTC 24 |
930210168 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2956681099 |
|
|
Aug 23 06:59:50 AM UTC 24 |
Aug 23 06:59:51 AM UTC 24 |
44285836 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2910381170 |
|
|
Aug 23 06:59:52 AM UTC 24 |
Aug 23 07:00:04 AM UTC 24 |
2607504478 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.898694361 |
|
|
Aug 23 06:41:26 AM UTC 24 |
Aug 23 07:00:07 AM UTC 24 |
22177793845 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.4285227607 |
|
|
Aug 23 07:00:07 AM UTC 24 |
Aug 23 07:00:11 AM UTC 24 |
58408440 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4039562100 |
|
|
Aug 23 07:00:08 AM UTC 24 |
Aug 23 07:00:43 AM UTC 24 |
1148712545 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2091197136 |
|
|
Aug 23 07:00:43 AM UTC 24 |
Aug 23 07:00:45 AM UTC 24 |
12056101 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.420414602 |
|
|
Aug 23 07:00:45 AM UTC 24 |
Aug 23 07:00:49 AM UTC 24 |
401138948 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.4143245765 |
|
|
Aug 23 06:52:54 AM UTC 24 |
Aug 23 07:00:54 AM UTC 24 |
8478761902 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1013668215 |
|
|
Aug 23 06:50:19 AM UTC 24 |
Aug 23 07:01:02 AM UTC 24 |
10033124064 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3264849815 |
|
|
Aug 23 06:52:10 AM UTC 24 |
Aug 23 07:01:05 AM UTC 24 |
23658265458 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3806654291 |
|
|
Aug 23 07:01:06 AM UTC 24 |
Aug 23 07:01:15 AM UTC 24 |
492777276 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2539483054 |
|
|
Aug 23 07:00:54 AM UTC 24 |
Aug 23 07:01:28 AM UTC 24 |
583827234 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.4242727271 |
|
|
Aug 23 06:57:24 AM UTC 24 |
Aug 23 07:01:33 AM UTC 24 |
26643303198 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.1520235085 |
|
|
Aug 23 07:01:34 AM UTC 24 |
Aug 23 07:01:36 AM UTC 24 |
204111769 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.4002325427 |
|
|
Aug 23 07:01:37 AM UTC 24 |
Aug 23 07:01:42 AM UTC 24 |
1690459150 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3563453349 |
|
|
Aug 23 06:57:32 AM UTC 24 |
Aug 23 07:01:54 AM UTC 24 |
3941054817 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2397301064 |
|
|
Aug 23 06:59:01 AM UTC 24 |
Aug 23 07:01:56 AM UTC 24 |
1999527031 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1023201358 |
|
|
Aug 23 06:57:47 AM UTC 24 |
Aug 23 07:02:04 AM UTC 24 |
11163368813 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1097297471 |
|
|
Aug 23 07:02:05 AM UTC 24 |
Aug 23 07:02:07 AM UTC 24 |
28448592 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3132090897 |
|
|
Aug 23 06:55:22 AM UTC 24 |
Aug 23 07:02:11 AM UTC 24 |
4906532202 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3498778268 |
|
|
Aug 23 07:02:12 AM UTC 24 |
Aug 23 07:02:16 AM UTC 24 |
667827237 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1092412549 |
|
|
Aug 23 07:02:07 AM UTC 24 |
Aug 23 07:02:18 AM UTC 24 |
1356112673 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.236571304 |
|
|
Aug 23 06:57:45 AM UTC 24 |
Aug 23 07:02:22 AM UTC 24 |
1887010404 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2034440161 |
|
|
Aug 23 07:02:24 AM UTC 24 |
Aug 23 07:02:25 AM UTC 24 |
25501753 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4090536936 |
|
|
Aug 23 07:01:29 AM UTC 24 |
Aug 23 07:02:26 AM UTC 24 |
473421136 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.4137001914 |
|
|
Aug 23 07:02:26 AM UTC 24 |
Aug 23 07:03:06 AM UTC 24 |
495666276 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.1174462576 |
|
|
Aug 23 06:59:48 AM UTC 24 |
Aug 23 07:03:12 AM UTC 24 |
4108068868 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2411378121 |
|
|
Aug 23 07:02:17 AM UTC 24 |
Aug 23 07:03:13 AM UTC 24 |
859151549 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2492826837 |
|
|
Aug 23 06:59:05 AM UTC 24 |
Aug 23 07:03:31 AM UTC 24 |
7742319161 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3753659253 |
|
|
Aug 23 07:03:14 AM UTC 24 |
Aug 23 07:03:38 AM UTC 24 |
407297767 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.582514368 |
|
|
Aug 23 06:36:38 AM UTC 24 |
Aug 23 07:03:48 AM UTC 24 |
35449732848 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3032159524 |
|
|
Aug 23 07:03:39 AM UTC 24 |
Aug 23 07:03:51 AM UTC 24 |
72640230 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.2090397359 |
|
|
Aug 23 07:03:48 AM UTC 24 |
Aug 23 07:03:54 AM UTC 24 |
153157873 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1154021442 |
|
|
Aug 23 07:03:51 AM UTC 24 |
Aug 23 07:03:56 AM UTC 24 |
709553037 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.3554793884 |
|
|
Aug 23 07:03:07 AM UTC 24 |
Aug 23 07:03:56 AM UTC 24 |
2425909424 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.1576133884 |
|
|
Aug 23 07:01:03 AM UTC 24 |
Aug 23 07:03:57 AM UTC 24 |
8057027631 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3800856335 |
|
|
Aug 23 07:03:58 AM UTC 24 |
Aug 23 07:04:00 AM UTC 24 |
92190810 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.311693002 |
|
|
Aug 23 06:51:40 AM UTC 24 |
Aug 23 07:04:07 AM UTC 24 |
71153113226 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1711739071 |
|
|
Aug 23 07:04:00 AM UTC 24 |
Aug 23 07:04:08 AM UTC 24 |
2637726006 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2763834188 |
|
|
Aug 23 07:04:09 AM UTC 24 |
Aug 23 07:04:14 AM UTC 24 |
338142383 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1244866670 |
|
|
Aug 23 07:04:09 AM UTC 24 |
Aug 23 07:04:35 AM UTC 24 |
268149870 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.1284671575 |
|
|
Aug 23 07:04:36 AM UTC 24 |
Aug 23 07:04:37 AM UTC 24 |
13679184 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.2708497578 |
|
|
Aug 23 06:43:16 AM UTC 24 |
Aug 23 07:04:55 AM UTC 24 |
9374723539 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.2833788276 |
|
|
Aug 23 06:51:07 AM UTC 24 |
Aug 23 07:05:19 AM UTC 24 |
60298929937 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.3710244369 |
|
|
Aug 23 07:05:19 AM UTC 24 |
Aug 23 07:05:36 AM UTC 24 |
280538178 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.1657002561 |
|
|
Aug 23 07:04:38 AM UTC 24 |
Aug 23 07:05:55 AM UTC 24 |
2631600734 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1890198981 |
|
|
Aug 23 07:05:56 AM UTC 24 |
Aug 23 07:06:15 AM UTC 24 |
3765256344 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.1239808901 |
|
|
Aug 23 06:58:53 AM UTC 24 |
Aug 23 07:06:47 AM UTC 24 |
11648466558 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2354502933 |
|
|
Aug 23 06:51:07 AM UTC 24 |
Aug 23 07:06:31 AM UTC 24 |
61903188016 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2864792405 |
|
|
Aug 23 06:59:40 AM UTC 24 |
Aug 23 07:06:40 AM UTC 24 |
11235818567 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.993041531 |
|
|
Aug 23 07:06:48 AM UTC 24 |
Aug 23 07:06:54 AM UTC 24 |
1350274357 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1621527248 |
|
|
Aug 23 07:06:41 AM UTC 24 |
Aug 23 07:06:58 AM UTC 24 |
141425129 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1974429868 |
|
|
Aug 23 07:06:32 AM UTC 24 |
Aug 23 07:07:30 AM UTC 24 |
1406889366 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.365463302 |
|
|
Aug 23 07:03:13 AM UTC 24 |
Aug 23 07:08:05 AM UTC 24 |
28429786715 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3951523958 |
|
|
Aug 23 07:08:05 AM UTC 24 |
Aug 23 07:08:07 AM UTC 24 |
27588793 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.888378774 |
|
|
Aug 23 07:08:07 AM UTC 24 |
Aug 23 07:08:17 AM UTC 24 |
360365599 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1398366207 |
|
|
Aug 23 07:08:17 AM UTC 24 |
Aug 23 07:08:22 AM UTC 24 |
479074019 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1310125324 |
|
|
Aug 23 07:05:37 AM UTC 24 |
Aug 23 07:08:51 AM UTC 24 |
2271333523 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2273223479 |
|
|
Aug 23 07:03:32 AM UTC 24 |
Aug 23 07:08:57 AM UTC 24 |
14547894531 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1879741699 |
|
|
Aug 23 07:08:57 AM UTC 24 |
Aug 23 07:08:59 AM UTC 24 |
14879020 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.1818218889 |
|
|
Aug 23 06:53:42 AM UTC 24 |
Aug 23 07:09:16 AM UTC 24 |
238789832990 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.1842523933 |
|
|
Aug 23 07:08:59 AM UTC 24 |
Aug 23 07:09:58 AM UTC 24 |
2910713242 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.882401251 |
|
|
Aug 23 07:09:59 AM UTC 24 |
Aug 23 07:10:17 AM UTC 24 |
1143626556 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.772790118 |
|
|
Aug 23 07:03:54 AM UTC 24 |
Aug 23 07:10:37 AM UTC 24 |
11510694789 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1116063774 |
|
|
Aug 23 07:10:38 AM UTC 24 |
Aug 23 07:10:40 AM UTC 24 |
54161559 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3467646641 |
|
|
Aug 23 07:02:27 AM UTC 24 |
Aug 23 07:10:59 AM UTC 24 |
3420822438 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.1842465273 |
|
|
Aug 23 07:06:59 AM UTC 24 |
Aug 23 07:11:03 AM UTC 24 |
9311218718 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.1606609115 |
|
|
Aug 23 07:06:15 AM UTC 24 |
Aug 23 07:11:04 AM UTC 24 |
18441329437 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2373053137 |
|
|
Aug 23 07:11:00 AM UTC 24 |
Aug 23 07:11:04 AM UTC 24 |
50587173 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3369898550 |
|
|
Aug 23 07:11:04 AM UTC 24 |
Aug 23 07:11:07 AM UTC 24 |
46267155 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.4124347936 |
|
|
Aug 23 07:11:04 AM UTC 24 |
Aug 23 07:11:15 AM UTC 24 |
1695085865 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2350730674 |
|
|
Aug 23 07:08:23 AM UTC 24 |
Aug 23 07:11:25 AM UTC 24 |
2052466848 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.278709110 |
|
|
Aug 23 07:11:25 AM UTC 24 |
Aug 23 07:11:27 AM UTC 24 |
69503299 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.3511274301 |
|
|
Aug 23 06:55:52 AM UTC 24 |
Aug 23 07:11:30 AM UTC 24 |
13003991268 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1196862832 |
|
|
Aug 23 07:11:27 AM UTC 24 |
Aug 23 07:11:33 AM UTC 24 |
355812316 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.38053941 |
|
|
Aug 23 07:11:31 AM UTC 24 |
Aug 23 07:11:34 AM UTC 24 |
167119100 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.3947667433 |
|
|
Aug 23 07:01:54 AM UTC 24 |
Aug 23 07:11:35 AM UTC 24 |
14440708293 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1862304827 |
|
|
Aug 23 07:11:36 AM UTC 24 |
Aug 23 07:11:37 AM UTC 24 |
10997787 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.3709752375 |
|
|
Aug 23 06:47:32 AM UTC 24 |
Aug 23 07:11:49 AM UTC 24 |
112832107352 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.4041324873 |
|
|
Aug 23 07:01:16 AM UTC 24 |
Aug 23 07:11:53 AM UTC 24 |
111865965981 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.963834466 |
|
|
Aug 23 07:11:38 AM UTC 24 |
Aug 23 07:12:10 AM UTC 24 |
214337774 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.1089153206 |
|
|
Aug 23 07:11:54 AM UTC 24 |
Aug 23 07:12:23 AM UTC 24 |
491541026 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.194032880 |
|
|
Aug 23 07:12:23 AM UTC 24 |
Aug 23 07:12:29 AM UTC 24 |
76424415 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.2142143844 |
|
|
Aug 23 07:00:49 AM UTC 24 |
Aug 23 07:12:29 AM UTC 24 |
34973428656 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.547718240 |
|
|
Aug 23 07:12:55 AM UTC 24 |
Aug 23 07:13:15 AM UTC 24 |
627461192 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.3808088821 |
|
|
Aug 23 07:13:16 AM UTC 24 |
Aug 23 07:13:21 AM UTC 24 |
1269864548 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2137440173 |
|
|
Aug 23 07:12:30 AM UTC 24 |
Aug 23 07:13:26 AM UTC 24 |
151883403 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1227124821 |
|
|
Aug 23 07:10:17 AM UTC 24 |
Aug 23 07:14:05 AM UTC 24 |
2561931918 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1509040274 |
|
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Aug 23 07:12:11 AM UTC 24 |
Aug 23 07:14:37 AM UTC 24 |
2851809173 ps |