| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.95 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.44 |
| T1005 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.349841993 | Aug 23 07:59:27 AM UTC 24 | Aug 23 07:59:29 AM UTC 24 | 45002926 ps | ||
| T1006 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3181112496 | Aug 23 07:59:27 AM UTC 24 | Aug 23 07:59:29 AM UTC 24 | 19262231 ps | ||
| T1007 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1635923909 | Aug 23 07:59:27 AM UTC 24 | Aug 23 07:59:30 AM UTC 24 | 362178660 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4173970399 | Aug 23 07:59:26 AM UTC 24 | Aug 23 07:59:30 AM UTC 24 | 1364527157 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2597803817 | Aug 23 07:59:27 AM UTC 24 | Aug 23 07:59:30 AM UTC 24 | 302782926 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2085909295 | Aug 23 07:59:29 AM UTC 24 | Aug 23 07:59:32 AM UTC 24 | 862041390 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2932680076 | Aug 23 07:59:30 AM UTC 24 | Aug 23 07:59:32 AM UTC 24 | 15692132 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3108859171 | Aug 23 07:59:30 AM UTC 24 | Aug 23 07:59:32 AM UTC 24 | 302603767 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.771391306 | Aug 23 07:59:32 AM UTC 24 | Aug 23 07:59:33 AM UTC 24 | 14669753 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.330586772 | Aug 23 07:59:32 AM UTC 24 | Aug 23 07:59:33 AM UTC 24 | 35460673 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1875239769 | Aug 23 07:59:33 AM UTC 24 | Aug 23 07:59:35 AM UTC 24 | 15428708 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.201812658 | Aug 23 07:59:30 AM UTC 24 | Aug 23 07:59:36 AM UTC 24 | 297395216 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3063732473 | Aug 23 07:59:32 AM UTC 24 | Aug 23 07:59:36 AM UTC 24 | 505030682 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1207308685 | Aug 23 07:59:33 AM UTC 24 | Aug 23 07:59:36 AM UTC 24 | 168927650 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2242488794 | Aug 23 07:59:35 AM UTC 24 | Aug 23 07:59:36 AM UTC 24 | 181886539 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2037546835 | Aug 23 07:59:33 AM UTC 24 | Aug 23 07:59:38 AM UTC 24 | 435606608 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3141232693 | Aug 23 07:59:36 AM UTC 24 | Aug 23 07:59:39 AM UTC 24 | 458386865 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1014752311 | Aug 23 07:59:38 AM UTC 24 | Aug 23 07:59:39 AM UTC 24 | 12702697 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1817373671 | Aug 23 07:59:38 AM UTC 24 | Aug 23 07:59:39 AM UTC 24 | 78660447 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2642609708 | Aug 23 07:59:38 AM UTC 24 | Aug 23 07:59:40 AM UTC 24 | 72673938 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1419728298 | Aug 23 07:59:38 AM UTC 24 | Aug 23 07:59:40 AM UTC 24 | 278958649 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3567247327 | Aug 23 07:59:37 AM UTC 24 | Aug 23 07:59:41 AM UTC 24 | 310306789 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1352989718 | Aug 23 07:59:39 AM UTC 24 | Aug 23 07:59:42 AM UTC 24 | 72572958 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.817524132 | Aug 23 07:59:41 AM UTC 24 | Aug 23 07:59:42 AM UTC 24 | 14082323 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.503474511 | Aug 23 07:59:41 AM UTC 24 | Aug 23 07:59:42 AM UTC 24 | 37578523 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.418379695 | Aug 23 07:59:41 AM UTC 24 | Aug 23 07:59:43 AM UTC 24 | 592611434 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3937341099 | Aug 23 07:59:39 AM UTC 24 | Aug 23 07:59:44 AM UTC 24 | 1603733197 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.877198126 | Aug 23 07:59:41 AM UTC 24 | Aug 23 07:59:44 AM UTC 24 | 41539805 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.460230221 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1765397438 ps |
| CPU time | 8.26 seconds |
| Started | Aug 23 06:18:23 AM UTC 24 |
| Finished | Aug 23 06:18:32 AM UTC 24 |
| Peak memory | 224240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460230221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.460230221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1891284539 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 990774726 ps |
| CPU time | 2.84 seconds |
| Started | Aug 23 06:18:25 AM UTC 24 |
| Finished | Aug 23 06:18:29 AM UTC 24 |
| Peak memory | 257124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891284539 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1891284539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1131693882 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 4112795213 ps |
| CPU time | 328.55 seconds |
| Started | Aug 23 06:23:18 AM UTC 24 |
| Finished | Aug 23 06:28:50 AM UTC 24 |
| Peak memory | 387064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131693882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1131693882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3994413149 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 24113906937 ps |
| CPU time | 280.86 seconds |
| Started | Aug 23 06:21:21 AM UTC 24 |
| Finished | Aug 23 06:26:06 AM UTC 24 |
| Peak memory | 387320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399441314 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.3994413149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1174462701 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 487647098 ps |
| CPU time | 2.17 seconds |
| Started | Aug 23 07:58:18 AM UTC 24 |
| Finished | Aug 23 07:58:21 AM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11744 62701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_in tg_err.1174462701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3861085608 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 300738914 ps |
| CPU time | 4.8 seconds |
| Started | Aug 23 06:18:37 AM UTC 24 |
| Finished | Aug 23 06:18:42 AM UTC 24 |
| Peak memory | 224396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861085608 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.3861085608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.4203442905 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 44751086245 ps |
| CPU time | 211.87 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:21:56 AM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203442905 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acce ss_b2b.4203442905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2359371630 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2310509078 ps |
| CPU time | 105.14 seconds |
| Started | Aug 23 06:18:56 AM UTC 24 |
| Finished | Aug 23 06:20:44 AM UTC 24 |
| Peak memory | 391416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359371630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2359371630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3686905992 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 536451237 ps |
| CPU time | 6.61 seconds |
| Started | Aug 23 06:18:29 AM UTC 24 |
| Finished | Aug 23 06:18:37 AM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686905992 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.3686905992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3236354995 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 84411099820 ps |
| CPU time | 837.85 seconds |
| Started | Aug 23 06:19:34 AM UTC 24 |
| Finished | Aug 23 06:33:41 AM UTC 24 |
| Peak memory | 391300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323635499 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.3236354995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.704155627 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1048965733 ps |
| CPU time | 2.27 seconds |
| Started | Aug 23 07:58:14 AM UTC 24 |
| Finished | Aug 23 07:58:18 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70 4155627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pas sthru_mem_tl_intg_err.704155627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.316439834 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 36377734052 ps |
| CPU time | 1606.2 seconds |
| Started | Aug 23 06:18:25 AM UTC 24 |
| Finished | Aug 23 06:45:27 AM UTC 24 |
| Peak memory | 396988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316439834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.316439834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4294941924 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 47526600 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:18:23 AM UTC 24 |
| Peak memory | 213148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294941924 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.4294941924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3371433626 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 526602176 ps |
| CPU time | 35.39 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:18:58 AM UTC 24 |
| Peak memory | 358252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 371433626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max _throughput.3371433626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1432366525 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 289437311 ps |
| CPU time | 2.04 seconds |
| Started | Aug 23 07:59:20 AM UTC 24 |
| Finished | Aug 23 07:59:23 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14323 66525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_i ntg_err.1432366525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.2754611455 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 40389896 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 06:18:25 AM UTC 24 |
| Finished | Aug 23 06:18:26 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754611455 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.2754611455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.418379695 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 592611434 ps |
| CPU time | 1.72 seconds |
| Started | Aug 23 07:59:41 AM UTC 24 |
| Finished | Aug 23 07:59:43 AM UTC 24 |
| Peak memory | 220476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41837 9695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_in tg_err.418379695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2543018267 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 261507222 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 07:59:00 AM UTC 24 |
| Finished | Aug 23 07:59:03 AM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25430 18267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_in tg_err.2543018267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.1381975035 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2745784594 ps |
| CPU time | 489.94 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:26:37 AM UTC 24 |
| Peak memory | 382516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381975035 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.1381975035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1710386232 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 292138626 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 07:58:12 AM UTC 24 |
| Finished | Aug 23 07:58:14 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17103862 32 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alia sing.1710386232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2423655591 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 124214611 ps |
| CPU time | 2 seconds |
| Started | Aug 23 07:58:10 AM UTC 24 |
| Finished | Aug 23 07:58:13 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24236555 91 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_ bash.2423655591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1631003656 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 44131977 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:58:08 AM UTC 24 |
| Finished | Aug 23 07:58:10 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16310036 56 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_r eset.1631003656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.125236559 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 114492620 ps |
| CPU time | 1.52 seconds |
| Started | Aug 23 07:58:14 AM UTC 24 |
| Finished | Aug 23 07:58:17 AM UTC 24 |
| Peak memory | 220128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=125236559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.125236559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3676292565 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 61086352 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 07:58:10 AM UTC 24 |
| Finished | Aug 23 07:58:12 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676292565 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.3676292565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.554628380 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 851965269 ps |
| CPU time | 1.98 seconds |
| Started | Aug 23 07:57:58 AM UTC 24 |
| Finished | Aug 23 07:58:01 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55 4628380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pas sthru_mem_tl_intg_err.554628380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2347356766 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 20474415 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:58:12 AM UTC 24 |
| Finished | Aug 23 07:58:14 AM UTC 24 |
| Peak memory | 209900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2347356766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_c trl_same_csr_outstanding.2347356766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1707072861 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 716353198 ps |
| CPU time | 4.02 seconds |
| Started | Aug 23 07:58:02 AM UTC 24 |
| Finished | Aug 23 07:58:07 AM UTC 24 |
| Peak memory | 221728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707072861 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.1707072861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.305243577 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 183003878 ps |
| CPU time | 1.58 seconds |
| Started | Aug 23 07:58:07 AM UTC 24 |
| Finished | Aug 23 07:58:10 AM UTC 24 |
| Peak memory | 220408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30524 3577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_int g_err.305243577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2612251350 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 28990838 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 07:58:22 AM UTC 24 |
| Finished | Aug 23 07:58:24 AM UTC 24 |
| Peak memory | 210456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26122513 50 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alia sing.2612251350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2082994015 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 122607819 ps |
| CPU time | 1.85 seconds |
| Started | Aug 23 07:58:22 AM UTC 24 |
| Finished | Aug 23 07:58:25 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20829940 15 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_ bash.2082994015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1758043431 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 26195030 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:58:19 AM UTC 24 |
| Finished | Aug 23 07:58:20 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17580434 31 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_r eset.1758043431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.296669578 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 37114697 ps |
| CPU time | 0.94 seconds |
| Started | Aug 23 07:58:25 AM UTC 24 |
| Finished | Aug 23 07:58:27 AM UTC 24 |
| Peak memory | 209820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=296669578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.296669578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.120790297 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 43161222 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 07:58:21 AM UTC 24 |
| Finished | Aug 23 07:58:22 AM UTC 24 |
| Peak memory | 210788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120790297 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.120790297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3676304888 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 33277587 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 07:58:23 AM UTC 24 |
| Finished | Aug 23 07:58:25 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3676304888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_c trl_same_csr_outstanding.3676304888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.326270968 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 233970131 ps |
| CPU time | 5.2 seconds |
| Started | Aug 23 07:58:14 AM UTC 24 |
| Finished | Aug 23 07:58:21 AM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326270968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.326270968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1577650008 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 142585854 ps |
| CPU time | 1.36 seconds |
| Started | Aug 23 07:59:09 AM UTC 24 |
| Finished | Aug 23 07:59:12 AM UTC 24 |
| Peak memory | 220352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1577650008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1577650008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.580509248 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 13098105 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:59:08 AM UTC 24 |
| Finished | Aug 23 07:59:10 AM UTC 24 |
| Peak memory | 210788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580509248 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.580509248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1379281770 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1624161557 ps |
| CPU time | 3.17 seconds |
| Started | Aug 23 07:59:06 AM UTC 24 |
| Finished | Aug 23 07:59:11 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 79281770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_p assthru_mem_tl_intg_err.1379281770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3806292403 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 13375946 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:59:08 AM UTC 24 |
| Finished | Aug 23 07:59:10 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3806292403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ ctrl_same_csr_outstanding.3806292403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.473372957 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 237579002 ps |
| CPU time | 2.35 seconds |
| Started | Aug 23 07:59:06 AM UTC 24 |
| Finished | Aug 23 07:59:10 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473372957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.473372957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2763297310 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 717245858 ps |
| CPU time | 2.21 seconds |
| Started | Aug 23 07:59:08 AM UTC 24 |
| Finished | Aug 23 07:59:11 AM UTC 24 |
| Peak memory | 221672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27632 97310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_i ntg_err.2763297310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.262183101 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 42987187 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 07:59:13 AM UTC 24 |
| Finished | Aug 23 07:59:15 AM UTC 24 |
| Peak memory | 220600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=262183101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.262183101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1125136653 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 108606554 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 07:59:12 AM UTC 24 |
| Finished | Aug 23 07:59:14 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125136653 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.1125136653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1965880951 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2093135489 ps |
| CPU time | 8.09 seconds |
| Started | Aug 23 07:59:10 AM UTC 24 |
| Finished | Aug 23 07:59:20 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 65880951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_p assthru_mem_tl_intg_err.1965880951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3739677577 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 79842558 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 07:59:12 AM UTC 24 |
| Finished | Aug 23 07:59:14 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3739677577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ ctrl_same_csr_outstanding.3739677577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2631184906 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 163959103 ps |
| CPU time | 5.08 seconds |
| Started | Aug 23 07:59:10 AM UTC 24 |
| Finished | Aug 23 07:59:17 AM UTC 24 |
| Peak memory | 221712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631184906 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.2631184906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3905685626 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 76592537 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 07:59:10 AM UTC 24 |
| Finished | Aug 23 07:59:13 AM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39056 85626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_i ntg_err.3905685626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1660364232 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 46276348 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 07:59:19 AM UTC 24 |
| Finished | Aug 23 07:59:21 AM UTC 24 |
| Peak memory | 220612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1660364232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1660364232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2573048973 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 26430405 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:59:16 AM UTC 24 |
| Finished | Aug 23 07:59:18 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573048973 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.2573048973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3774018054 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 3501731114 ps |
| CPU time | 3.66 seconds |
| Started | Aug 23 07:59:14 AM UTC 24 |
| Finished | Aug 23 07:59:19 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 74018054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_p assthru_mem_tl_intg_err.3774018054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3380131904 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 28613383 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 07:59:18 AM UTC 24 |
| Finished | Aug 23 07:59:19 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3380131904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ ctrl_same_csr_outstanding.3380131904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3285399026 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 130098321 ps |
| CPU time | 4.88 seconds |
| Started | Aug 23 07:59:14 AM UTC 24 |
| Finished | Aug 23 07:59:20 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285399026 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.3285399026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1836309596 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 186688247 ps |
| CPU time | 2.22 seconds |
| Started | Aug 23 07:59:14 AM UTC 24 |
| Finished | Aug 23 07:59:18 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18363 09596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i ntg_err.1836309596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3064852802 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 36265836 ps |
| CPU time | 1.44 seconds |
| Started | Aug 23 07:59:22 AM UTC 24 |
| Finished | Aug 23 07:59:24 AM UTC 24 |
| Peak memory | 220292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3064852802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.3064852802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2198835679 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 13320654 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 07:59:22 AM UTC 24 |
| Finished | Aug 23 07:59:23 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198835679 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.2198835679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2756949383 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 207823139 ps |
| CPU time | 1.84 seconds |
| Started | Aug 23 07:59:19 AM UTC 24 |
| Finished | Aug 23 07:59:22 AM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27 56949383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_p assthru_mem_tl_intg_err.2756949383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2073938765 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 40974573 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 07:59:22 AM UTC 24 |
| Finished | Aug 23 07:59:23 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2073938765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ ctrl_same_csr_outstanding.2073938765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2674828523 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 712225674 ps |
| CPU time | 3.75 seconds |
| Started | Aug 23 07:59:20 AM UTC 24 |
| Finished | Aug 23 07:59:25 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674828523 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.2674828523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.687593685 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 57409562 ps |
| CPU time | 0.93 seconds |
| Started | Aug 23 07:59:25 AM UTC 24 |
| Finished | Aug 23 07:59:26 AM UTC 24 |
| Peak memory | 220284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=687593685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.687593685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3112022659 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 23273150 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:59:24 AM UTC 24 |
| Finished | Aug 23 07:59:26 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112022659 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.3112022659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3370523210 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 1501252392 ps |
| CPU time | 1.92 seconds |
| Started | Aug 23 07:59:23 AM UTC 24 |
| Finished | Aug 23 07:59:26 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 70523210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_p assthru_mem_tl_intg_err.3370523210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1323460101 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 14352125 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 07:59:25 AM UTC 24 |
| Finished | Aug 23 07:59:26 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1323460101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ ctrl_same_csr_outstanding.1323460101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1845678171 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 65630256 ps |
| CPU time | 2.26 seconds |
| Started | Aug 23 07:59:23 AM UTC 24 |
| Finished | Aug 23 07:59:26 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845678171 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.1845678171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1288802654 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 435061789 ps |
| CPU time | 1.46 seconds |
| Started | Aug 23 07:59:24 AM UTC 24 |
| Finished | Aug 23 07:59:27 AM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12888 02654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_i ntg_err.1288802654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.349841993 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 45002926 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 07:59:27 AM UTC 24 |
| Finished | Aug 23 07:59:29 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349841993 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.349841993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4173970399 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 1364527157 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 07:59:26 AM UTC 24 |
| Finished | Aug 23 07:59:30 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41 73970399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_p assthru_mem_tl_intg_err.4173970399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3181112496 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 19262231 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 07:59:27 AM UTC 24 |
| Finished | Aug 23 07:59:29 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3181112496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ ctrl_same_csr_outstanding.3181112496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2597803817 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 302782926 ps |
| CPU time | 2.08 seconds |
| Started | Aug 23 07:59:27 AM UTC 24 |
| Finished | Aug 23 07:59:30 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597803817 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.2597803817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1635923909 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 362178660 ps |
| CPU time | 1.44 seconds |
| Started | Aug 23 07:59:27 AM UTC 24 |
| Finished | Aug 23 07:59:30 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16359 23909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_i ntg_err.1635923909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.330586772 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 35460673 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 07:59:32 AM UTC 24 |
| Finished | Aug 23 07:59:33 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=330586772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.330586772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2932680076 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 15692132 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 07:59:30 AM UTC 24 |
| Finished | Aug 23 07:59:32 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932680076 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.2932680076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2085909295 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 862041390 ps |
| CPU time | 1.96 seconds |
| Started | Aug 23 07:59:29 AM UTC 24 |
| Finished | Aug 23 07:59:32 AM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20 85909295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p assthru_mem_tl_intg_err.2085909295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.771391306 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 14669753 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 07:59:32 AM UTC 24 |
| Finished | Aug 23 07:59:33 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=771391306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_c trl_same_csr_outstanding.771391306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.201812658 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 297395216 ps |
| CPU time | 4.56 seconds |
| Started | Aug 23 07:59:30 AM UTC 24 |
| Finished | Aug 23 07:59:36 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201812658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.201812658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3108859171 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 302603767 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 07:59:30 AM UTC 24 |
| Finished | Aug 23 07:59:32 AM UTC 24 |
| Peak memory | 220400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31088 59171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_i ntg_err.3108859171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1875239769 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 15428708 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:59:33 AM UTC 24 |
| Finished | Aug 23 07:59:35 AM UTC 24 |
| Peak memory | 210844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875239769 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.1875239769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3063732473 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 505030682 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 07:59:32 AM UTC 24 |
| Finished | Aug 23 07:59:36 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 63732473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_p assthru_mem_tl_intg_err.3063732473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2242488794 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 181886539 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 07:59:35 AM UTC 24 |
| Finished | Aug 23 07:59:36 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2242488794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ ctrl_same_csr_outstanding.2242488794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2037546835 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 435606608 ps |
| CPU time | 3.96 seconds |
| Started | Aug 23 07:59:33 AM UTC 24 |
| Finished | Aug 23 07:59:38 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037546835 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.2037546835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1207308685 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 168927650 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 07:59:33 AM UTC 24 |
| Finished | Aug 23 07:59:36 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12073 08685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i ntg_err.1207308685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2642609708 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 72673938 ps |
| CPU time | 1.12 seconds |
| Started | Aug 23 07:59:38 AM UTC 24 |
| Finished | Aug 23 07:59:40 AM UTC 24 |
| Peak memory | 220296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2642609708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2642609708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1014752311 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 12702697 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:59:38 AM UTC 24 |
| Finished | Aug 23 07:59:39 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014752311 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.1014752311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3141232693 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 458386865 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 07:59:36 AM UTC 24 |
| Finished | Aug 23 07:59:39 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 41232693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_p assthru_mem_tl_intg_err.3141232693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1817373671 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 78660447 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 07:59:38 AM UTC 24 |
| Finished | Aug 23 07:59:39 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1817373671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ ctrl_same_csr_outstanding.1817373671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3567247327 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 310306789 ps |
| CPU time | 2.41 seconds |
| Started | Aug 23 07:59:37 AM UTC 24 |
| Finished | Aug 23 07:59:41 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567247327 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.3567247327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1419728298 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 278958649 ps |
| CPU time | 1.79 seconds |
| Started | Aug 23 07:59:38 AM UTC 24 |
| Finished | Aug 23 07:59:40 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14197 28298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_i ntg_err.1419728298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.877198126 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 41539805 ps |
| CPU time | 2.02 seconds |
| Started | Aug 23 07:59:41 AM UTC 24 |
| Finished | Aug 23 07:59:44 AM UTC 24 |
| Peak memory | 223848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=877198126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.877198126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.817524132 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 14082323 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 07:59:41 AM UTC 24 |
| Finished | Aug 23 07:59:42 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817524132 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.817524132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3937341099 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 1603733197 ps |
| CPU time | 3.72 seconds |
| Started | Aug 23 07:59:39 AM UTC 24 |
| Finished | Aug 23 07:59:44 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 37341099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_p assthru_mem_tl_intg_err.3937341099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.503474511 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 37578523 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:59:41 AM UTC 24 |
| Finished | Aug 23 07:59:42 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=503474511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_c trl_same_csr_outstanding.503474511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1352989718 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 72572958 ps |
| CPU time | 2.18 seconds |
| Started | Aug 23 07:59:39 AM UTC 24 |
| Finished | Aug 23 07:59:42 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352989718 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.1352989718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3242692251 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 21438246 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:58:33 AM UTC 24 |
| Finished | Aug 23 07:58:34 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32426922 51 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alia sing.3242692251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2209294631 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 140874589 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 07:58:31 AM UTC 24 |
| Finished | Aug 23 07:58:34 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22092946 31 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_ bash.2209294631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2971224202 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 25445178 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:58:29 AM UTC 24 |
| Finished | Aug 23 07:58:31 AM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29712242 02 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_r eset.2971224202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1920553183 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 29834545 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 07:58:30 AM UTC 24 |
| Finished | Aug 23 07:58:32 AM UTC 24 |
| Peak memory | 209600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920553183 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.1920553183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1831289701 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 237167979 ps |
| CPU time | 2.03 seconds |
| Started | Aug 23 07:58:25 AM UTC 24 |
| Finished | Aug 23 07:58:28 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18 31289701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pa ssthru_mem_tl_intg_err.1831289701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3635515156 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 16052092 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:58:33 AM UTC 24 |
| Finished | Aug 23 07:58:34 AM UTC 24 |
| Peak memory | 209768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3635515156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_c trl_same_csr_outstanding.3635515156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2817475664 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 170062570 ps |
| CPU time | 2.37 seconds |
| Started | Aug 23 07:58:26 AM UTC 24 |
| Finished | Aug 23 07:58:30 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817475664 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.2817475664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2167756 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 257381371 ps |
| CPU time | 2.27 seconds |
| Started | Aug 23 07:58:28 AM UTC 24 |
| Finished | Aug 23 07:58:31 AM UTC 24 |
| Peak memory | 221848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21677 56 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_intg_err.2167756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2309474740 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 46910081 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:58:40 AM UTC 24 |
| Finished | Aug 23 07:58:42 AM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23094747 40 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alia sing.2309474740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2797204904 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 180501593 ps |
| CPU time | 2.01 seconds |
| Started | Aug 23 07:58:39 AM UTC 24 |
| Finished | Aug 23 07:58:42 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27972049 04 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_ bash.2797204904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3973880392 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 18020792 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:58:39 AM UTC 24 |
| Finished | Aug 23 07:58:41 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39738803 92 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_r eset.3973880392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1565572280 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 33052996 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 07:58:41 AM UTC 24 |
| Finished | Aug 23 07:58:43 AM UTC 24 |
| Peak memory | 220348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1565572280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.1565572280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2941310994 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 17191115 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:58:39 AM UTC 24 |
| Finished | Aug 23 07:58:41 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941310994 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.2941310994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1504272991 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 452025836 ps |
| CPU time | 2.55 seconds |
| Started | Aug 23 07:58:35 AM UTC 24 |
| Finished | Aug 23 07:58:38 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 04272991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pa ssthru_mem_tl_intg_err.1504272991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1703509261 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 47160861 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 07:58:41 AM UTC 24 |
| Finished | Aug 23 07:58:43 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1703509261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_c trl_same_csr_outstanding.1703509261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3851072169 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 263022357 ps |
| CPU time | 2.42 seconds |
| Started | Aug 23 07:58:35 AM UTC 24 |
| Finished | Aug 23 07:58:38 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851072169 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.3851072169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2196961692 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 182003725 ps |
| CPU time | 2.22 seconds |
| Started | Aug 23 07:58:38 AM UTC 24 |
| Finished | Aug 23 07:58:41 AM UTC 24 |
| Peak memory | 221848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21969 61692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_in tg_err.2196961692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1569248239 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 59379130 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:58:46 AM UTC 24 |
| Finished | Aug 23 07:58:48 AM UTC 24 |
| Peak memory | 210456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15692482 39 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_alia sing.1569248239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.920224254 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 605920258 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 07:58:46 AM UTC 24 |
| Finished | Aug 23 07:58:48 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92022425 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_b ash.920224254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1655578684 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 22272073 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:58:44 AM UTC 24 |
| Finished | Aug 23 07:58:45 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16555786 84 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_r eset.1655578684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3312670985 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 102038755 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 07:58:47 AM UTC 24 |
| Finished | Aug 23 07:58:49 AM UTC 24 |
| Peak memory | 222396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3312670985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3312670985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2226789808 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 45594137 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 07:58:44 AM UTC 24 |
| Finished | Aug 23 07:58:45 AM UTC 24 |
| Peak memory | 210456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226789808 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.2226789808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2585190338 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1703712297 ps |
| CPU time | 3.37 seconds |
| Started | Aug 23 07:58:43 AM UTC 24 |
| Finished | Aug 23 07:58:47 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25 85190338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pa ssthru_mem_tl_intg_err.2585190338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2599817589 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 161681933 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 07:58:46 AM UTC 24 |
| Finished | Aug 23 07:58:48 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2599817589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_c trl_same_csr_outstanding.2599817589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4191339811 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 681738604 ps |
| CPU time | 2.98 seconds |
| Started | Aug 23 07:58:43 AM UTC 24 |
| Finished | Aug 23 07:58:47 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191339811 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.4191339811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4001455003 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 179022723 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 07:58:43 AM UTC 24 |
| Finished | Aug 23 07:58:46 AM UTC 24 |
| Peak memory | 221608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40014 55003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_in tg_err.4001455003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3228104071 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 33566455 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 07:58:50 AM UTC 24 |
| Finished | Aug 23 07:58:52 AM UTC 24 |
| Peak memory | 220284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3228104071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3228104071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2209334798 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 15835620 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:58:48 AM UTC 24 |
| Finished | Aug 23 07:58:50 AM UTC 24 |
| Peak memory | 210360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209334798 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.2209334798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3669962920 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 1040860651 ps |
| CPU time | 1.97 seconds |
| Started | Aug 23 07:58:47 AM UTC 24 |
| Finished | Aug 23 07:58:50 AM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 69962920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa ssthru_mem_tl_intg_err.3669962920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.414507012 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 20041187 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 07:58:50 AM UTC 24 |
| Finished | Aug 23 07:58:52 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=414507012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ct rl_same_csr_outstanding.414507012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3946960634 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 32002938 ps |
| CPU time | 2.29 seconds |
| Started | Aug 23 07:58:48 AM UTC 24 |
| Finished | Aug 23 07:58:52 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946960634 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.3946960634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.383125536 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 577812748 ps |
| CPU time | 2.02 seconds |
| Started | Aug 23 07:58:48 AM UTC 24 |
| Finished | Aug 23 07:58:51 AM UTC 24 |
| Peak memory | 223792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38312 5536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_int g_err.383125536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2569634126 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 153308935 ps |
| CPU time | 2.54 seconds |
| Started | Aug 23 07:58:53 AM UTC 24 |
| Finished | Aug 23 07:58:57 AM UTC 24 |
| Peak memory | 223884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2569634126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2569634126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.249285968 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 36080832 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:58:52 AM UTC 24 |
| Finished | Aug 23 07:58:54 AM UTC 24 |
| Peak memory | 210372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249285968 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.249285968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3777671053 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 413503803 ps |
| CPU time | 3.13 seconds |
| Started | Aug 23 07:58:51 AM UTC 24 |
| Finished | Aug 23 07:58:55 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37 77671053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pa ssthru_mem_tl_intg_err.3777671053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2927954271 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 30599138 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 07:58:53 AM UTC 24 |
| Finished | Aug 23 07:58:55 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2927954271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c trl_same_csr_outstanding.2927954271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4061228239 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 42215820 ps |
| CPU time | 3.81 seconds |
| Started | Aug 23 07:58:51 AM UTC 24 |
| Finished | Aug 23 07:58:56 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061228239 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.4061228239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1062389898 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 355336936 ps |
| CPU time | 2.35 seconds |
| Started | Aug 23 07:58:52 AM UTC 24 |
| Finished | Aug 23 07:58:55 AM UTC 24 |
| Peak memory | 221512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10623 89898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_in tg_err.1062389898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1017557039 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 70601925 ps |
| CPU time | 2.24 seconds |
| Started | Aug 23 07:58:58 AM UTC 24 |
| Finished | Aug 23 07:59:01 AM UTC 24 |
| Peak memory | 223836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1017557039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1017557039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1908318740 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 14164636 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 07:58:57 AM UTC 24 |
| Finished | Aug 23 07:58:59 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908318740 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.1908318740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.272094162 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 979149654 ps |
| CPU time | 3.14 seconds |
| Started | Aug 23 07:58:54 AM UTC 24 |
| Finished | Aug 23 07:58:59 AM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27 2094162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pas sthru_mem_tl_intg_err.272094162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.972919750 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 32775120 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:58:57 AM UTC 24 |
| Finished | Aug 23 07:58:59 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=972919750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ct rl_same_csr_outstanding.972919750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2271626847 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 35990106 ps |
| CPU time | 2.64 seconds |
| Started | Aug 23 07:58:55 AM UTC 24 |
| Finished | Aug 23 07:59:00 AM UTC 24 |
| Peak memory | 221728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271626847 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.2271626847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3579793615 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 369180813 ps |
| CPU time | 1.55 seconds |
| Started | Aug 23 07:58:55 AM UTC 24 |
| Finished | Aug 23 07:58:59 AM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35797 93615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_in tg_err.3579793615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1578332346 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 145279860 ps |
| CPU time | 1.39 seconds |
| Started | Aug 23 07:59:01 AM UTC 24 |
| Finished | Aug 23 07:59:04 AM UTC 24 |
| Peak memory | 220288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1578332346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1578332346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.642119521 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 17636111 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:59:00 AM UTC 24 |
| Finished | Aug 23 07:59:02 AM UTC 24 |
| Peak memory | 210456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642119521 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.642119521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2512246573 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 433084773 ps |
| CPU time | 2.08 seconds |
| Started | Aug 23 07:58:59 AM UTC 24 |
| Finished | Aug 23 07:59:02 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25 12246573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa ssthru_mem_tl_intg_err.2512246573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3764768481 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 65063455 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:59:00 AM UTC 24 |
| Finished | Aug 23 07:59:02 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3764768481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_c trl_same_csr_outstanding.3764768481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.670399305 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 116881385 ps |
| CPU time | 3.99 seconds |
| Started | Aug 23 07:59:00 AM UTC 24 |
| Finished | Aug 23 07:59:05 AM UTC 24 |
| Peak memory | 221660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670399305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.670399305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4208324118 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 102770568 ps |
| CPU time | 0.93 seconds |
| Started | Aug 23 07:59:06 AM UTC 24 |
| Finished | Aug 23 07:59:08 AM UTC 24 |
| Peak memory | 220288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4208324118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.4208324118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1162998312 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 31887812 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 07:59:04 AM UTC 24 |
| Finished | Aug 23 07:59:06 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162998312 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.1162998312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.553076015 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 195098267 ps |
| CPU time | 1.83 seconds |
| Started | Aug 23 07:59:03 AM UTC 24 |
| Finished | Aug 23 07:59:06 AM UTC 24 |
| Peak memory | 209936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55 3076015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pas sthru_mem_tl_intg_err.553076015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3327832359 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 37444092 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 07:59:05 AM UTC 24 |
| Finished | Aug 23 07:59:07 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000 0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3327832359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_c trl_same_csr_outstanding.3327832359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4023730846 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 151602499 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 07:59:03 AM UTC 24 |
| Finished | Aug 23 07:59:07 AM UTC 24 |
| Peak memory | 211660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023730846 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.4023730846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1190371853 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 222610058 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 07:59:04 AM UTC 24 |
| Finished | Aug 23 07:59:06 AM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11903 71853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_in tg_err.1190371853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.4203702563 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 37593112554 ps |
| CPU time | 416.34 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:25:22 AM UTC 24 |
| Peak memory | 384688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203702563 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_ key_req.4203702563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.4209823495 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3768824620 ps |
| CPU time | 70.4 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:19:33 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209823495 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.4209823495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3648318948 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 709676811 ps |
| CPU time | 7.26 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:18:30 AM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648318948 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.3648318948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1373172961 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 725825016 ps |
| CPU time | 4.83 seconds |
| Started | Aug 23 06:18:23 AM UTC 24 |
| Finished | Aug 23 06:18:29 AM UTC 24 |
| Peak memory | 224332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373172961 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.1373172961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2405507472 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 295110883 ps |
| CPU time | 4.01 seconds |
| Started | Aug 23 06:18:22 AM UTC 24 |
| Finished | Aug 23 06:18:27 AM UTC 24 |
| Peak memory | 224332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405507472 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.2405507472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1012550836 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 452189227 ps |
| CPU time | 26.27 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:18:49 AM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012550836 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.1012550836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.4285560262 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 253374011 ps |
| CPU time | 50.8 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:19:14 AM UTC 24 |
| Peak memory | 378736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285560262 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.4285560262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.110217416 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 15451857917 ps |
| CPU time | 486.41 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:26:33 AM UTC 24 |
| Peak memory | 378968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110217416 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.110217416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.2376508237 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 324795058 ps |
| CPU time | 9.66 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:18:32 AM UTC 24 |
| Peak memory | 213868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376508237 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2376508237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1629190641 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3590363634 ps |
| CPU time | 168.7 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:21:13 AM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629190641 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.1629190641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.723086753 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 105016457 ps |
| CPU time | 2.83 seconds |
| Started | Aug 23 06:18:21 AM UTC 24 |
| Finished | Aug 23 06:18:25 AM UTC 24 |
| Peak memory | 231532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 723086753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_thr oughput_w_partial_write.723086753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2371646625 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4392445797 ps |
| CPU time | 534.01 seconds |
| Started | Aug 23 06:18:30 AM UTC 24 |
| Finished | Aug 23 06:27:30 AM UTC 24 |
| Peak memory | 385196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371646625 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_ key_req.2371646625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1702586960 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 22447254 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 06:18:38 AM UTC 24 |
| Finished | Aug 23 06:18:39 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702586960 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1702586960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.4180401924 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 2668801353 ps |
| CPU time | 37.85 seconds |
| Started | Aug 23 06:18:28 AM UTC 24 |
| Finished | Aug 23 06:19:07 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180401924 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.4180401924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.4031547711 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 10701227402 ps |
| CPU time | 381.94 seconds |
| Started | Aug 23 06:18:33 AM UTC 24 |
| Finished | Aug 23 06:24:59 AM UTC 24 |
| Peak memory | 336060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031547711 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.4031547711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.828820927 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 774621556 ps |
| CPU time | 8.54 seconds |
| Started | Aug 23 06:18:29 AM UTC 24 |
| Finished | Aug 23 06:18:39 AM UTC 24 |
| Peak memory | 266100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 28820927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max_ throughput.828820927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2143605714 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2181304220 ps |
| CPU time | 10.59 seconds |
| Started | Aug 23 06:18:35 AM UTC 24 |
| Finished | Aug 23 06:18:46 AM UTC 24 |
| Peak memory | 224192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143605714 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.2143605714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1745986791 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 16598631730 ps |
| CPU time | 784.84 seconds |
| Started | Aug 23 06:18:28 AM UTC 24 |
| Finished | Aug 23 06:31:40 AM UTC 24 |
| Peak memory | 384684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745986791 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.1745986791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2454346589 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 522406048 ps |
| CPU time | 25.15 seconds |
| Started | Aug 23 06:18:28 AM UTC 24 |
| Finished | Aug 23 06:18:54 AM UTC 24 |
| Peak memory | 317496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454346589 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.2454346589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2852835404 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 43936761260 ps |
| CPU time | 165.01 seconds |
| Started | Aug 23 06:18:28 AM UTC 24 |
| Finished | Aug 23 06:21:16 AM UTC 24 |
| Peak memory | 213996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852835404 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acce ss_b2b.2852835404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.66733943 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 31700748 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 06:18:34 AM UTC 24 |
| Finished | Aug 23 06:18:35 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66733943 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.66733943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.316240613 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 10488820080 ps |
| CPU time | 474.13 seconds |
| Started | Aug 23 06:18:33 AM UTC 24 |
| Finished | Aug 23 06:26:32 AM UTC 24 |
| Peak memory | 376832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316240613 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.316240613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.92870481 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 190257389 ps |
| CPU time | 1.91 seconds |
| Started | Aug 23 06:18:37 AM UTC 24 |
| Finished | Aug 23 06:18:40 AM UTC 24 |
| Peak memory | 246036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92870481 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.92870481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.815281663 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 566655724 ps |
| CPU time | 6.46 seconds |
| Started | Aug 23 06:18:26 AM UTC 24 |
| Finished | Aug 23 06:18:33 AM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815281663 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.815281663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.774457169 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 121000265314 ps |
| CPU time | 1534.62 seconds |
| Started | Aug 23 06:18:37 AM UTC 24 |
| Finished | Aug 23 06:44:26 AM UTC 24 |
| Peak memory | 388712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774457169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.774457169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1908871469 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7708859621 ps |
| CPU time | 59.9 seconds |
| Started | Aug 23 06:18:37 AM UTC 24 |
| Finished | Aug 23 06:19:38 AM UTC 24 |
| Peak memory | 323828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908871469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.1908871469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3305737544 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 15000644574 ps |
| CPU time | 188.66 seconds |
| Started | Aug 23 06:18:28 AM UTC 24 |
| Finished | Aug 23 06:21:39 AM UTC 24 |
| Peak memory | 214260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305737544 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.3305737544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.565452236 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 202716401 ps |
| CPU time | 1.43 seconds |
| Started | Aug 23 06:18:29 AM UTC 24 |
| Finished | Aug 23 06:18:32 AM UTC 24 |
| Peak memory | 222860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 565452236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_thr oughput_w_partial_write.565452236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3317152577 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3217586938 ps |
| CPU time | 39.94 seconds |
| Started | Aug 23 06:32:16 AM UTC 24 |
| Finished | Aug 23 06:32:57 AM UTC 24 |
| Peak memory | 323752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317152577 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during _key_req.3317152577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.433746092 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 39519452 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 06:32:58 AM UTC 24 |
| Finished | Aug 23 06:32:59 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433746092 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.433746092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.2901227919 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3406387137 ps |
| CPU time | 54.09 seconds |
| Started | Aug 23 06:31:42 AM UTC 24 |
| Finished | Aug 23 06:32:37 AM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901227919 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.2901227919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1197402575 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3981077010 ps |
| CPU time | 1062.61 seconds |
| Started | Aug 23 06:32:18 AM UTC 24 |
| Finished | Aug 23 06:50:11 AM UTC 24 |
| Peak memory | 387092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197402575 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.1197402575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.262179339 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2482986043 ps |
| CPU time | 10.16 seconds |
| Started | Aug 23 06:32:07 AM UTC 24 |
| Finished | Aug 23 06:32:18 AM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262179339 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.262179339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.2065907848 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 45704022 ps |
| CPU time | 1.16 seconds |
| Started | Aug 23 06:31:47 AM UTC 24 |
| Finished | Aug 23 06:31:49 AM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 065907848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ma x_throughput.2065907848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.641445986 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1120325226 ps |
| CPU time | 5.01 seconds |
| Started | Aug 23 06:32:48 AM UTC 24 |
| Finished | Aug 23 06:32:55 AM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641445986 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.641445986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2204293986 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 468208250 ps |
| CPU time | 9.75 seconds |
| Started | Aug 23 06:32:41 AM UTC 24 |
| Finished | Aug 23 06:32:52 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204293986 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.2204293986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3149932556 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 20473373303 ps |
| CPU time | 123.24 seconds |
| Started | Aug 23 06:31:38 AM UTC 24 |
| Finished | Aug 23 06:33:43 AM UTC 24 |
| Peak memory | 272180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149932556 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.3149932556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.3840550171 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3824719011 ps |
| CPU time | 33.21 seconds |
| Started | Aug 23 06:31:43 AM UTC 24 |
| Finished | Aug 23 06:32:17 AM UTC 24 |
| Peak memory | 323508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840550171 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.3840550171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2937405767 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 4270771674 ps |
| CPU time | 144.84 seconds |
| Started | Aug 23 06:31:44 AM UTC 24 |
| Finished | Aug 23 06:34:11 AM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937405767 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acc ess_b2b.2937405767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.307899594 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 50836353 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 06:32:38 AM UTC 24 |
| Finished | Aug 23 06:32:40 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307899594 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.307899594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.1655120557 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 2937727629 ps |
| CPU time | 39.86 seconds |
| Started | Aug 23 06:32:19 AM UTC 24 |
| Finished | Aug 23 06:33:00 AM UTC 24 |
| Peak memory | 341868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655120557 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1655120557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.1374449884 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1710159496 ps |
| CPU time | 8.38 seconds |
| Started | Aug 23 06:31:36 AM UTC 24 |
| Finished | Aug 23 06:31:46 AM UTC 24 |
| Peak memory | 260228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374449884 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1374449884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.622990564 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 26410976286 ps |
| CPU time | 3127.39 seconds |
| Started | Aug 23 06:32:55 AM UTC 24 |
| Finished | Aug 23 07:25:31 AM UTC 24 |
| Peak memory | 388984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622990564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.622990564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3437435426 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3122108956 ps |
| CPU time | 280.6 seconds |
| Started | Aug 23 06:31:42 AM UTC 24 |
| Finished | Aug 23 06:36:26 AM UTC 24 |
| Peak memory | 213784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437435426 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.3437435426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.913981389 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 132900159 ps |
| CPU time | 24.12 seconds |
| Started | Aug 23 06:31:50 AM UTC 24 |
| Finished | Aug 23 06:32:15 AM UTC 24 |
| Peak memory | 315224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 913981389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_th roughput_w_partial_write.913981389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2124490127 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 277247869 ps |
| CPU time | 67.72 seconds |
| Started | Aug 23 06:34:01 AM UTC 24 |
| Finished | Aug 23 06:35:11 AM UTC 24 |
| Peak memory | 380720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124490127 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during _key_req.2124490127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3121201340 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 37869526 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 06:35:05 AM UTC 24 |
| Finished | Aug 23 06:35:07 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121201340 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3121201340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.3205439777 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4483861972 ps |
| CPU time | 42.99 seconds |
| Started | Aug 23 06:33:01 AM UTC 24 |
| Finished | Aug 23 06:33:45 AM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205439777 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.3205439777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.2295554092 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 38829806377 ps |
| CPU time | 1094.87 seconds |
| Started | Aug 23 06:34:12 AM UTC 24 |
| Finished | Aug 23 06:52:37 AM UTC 24 |
| Peak memory | 384932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295554092 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.2295554092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.965875916 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 415603838 ps |
| CPU time | 4.37 seconds |
| Started | Aug 23 06:33:55 AM UTC 24 |
| Finished | Aug 23 06:34:01 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965875916 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.965875916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1024994877 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 758013442 ps |
| CPU time | 70.25 seconds |
| Started | Aug 23 06:33:45 AM UTC 24 |
| Finished | Aug 23 06:34:57 AM UTC 24 |
| Peak memory | 380788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 024994877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ma x_throughput.1024994877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2847115351 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 50274505 ps |
| CPU time | 2.52 seconds |
| Started | Aug 23 06:34:58 AM UTC 24 |
| Finished | Aug 23 06:35:01 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847115351 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.2847115351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1859906667 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 131064330 ps |
| CPU time | 4.86 seconds |
| Started | Aug 23 06:34:51 AM UTC 24 |
| Finished | Aug 23 06:34:57 AM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859906667 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.1859906667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2116667293 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 70133630311 ps |
| CPU time | 667.4 seconds |
| Started | Aug 23 06:33:00 AM UTC 24 |
| Finished | Aug 23 06:44:14 AM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116667293 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.2116667293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1191702074 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 68512305 ps |
| CPU time | 2.27 seconds |
| Started | Aug 23 06:33:41 AM UTC 24 |
| Finished | Aug 23 06:33:44 AM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191702074 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.1191702074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1912206264 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 6334082064 ps |
| CPU time | 224.89 seconds |
| Started | Aug 23 06:33:43 AM UTC 24 |
| Finished | Aug 23 06:37:31 AM UTC 24 |
| Peak memory | 213936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912206264 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acc ess_b2b.1912206264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1552461364 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 43359291 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 06:34:49 AM UTC 24 |
| Finished | Aug 23 06:34:50 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552461364 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1552461364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.3277379056 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 17080836889 ps |
| CPU time | 833.47 seconds |
| Started | Aug 23 06:34:12 AM UTC 24 |
| Finished | Aug 23 06:48:13 AM UTC 24 |
| Peak memory | 382904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277379056 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3277379056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.2525960184 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 312546525 ps |
| CPU time | 6.2 seconds |
| Started | Aug 23 06:32:58 AM UTC 24 |
| Finished | Aug 23 06:33:05 AM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525960184 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2525960184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3160978172 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 38483975405 ps |
| CPU time | 119.56 seconds |
| Started | Aug 23 06:35:02 AM UTC 24 |
| Finished | Aug 23 06:37:04 AM UTC 24 |
| Peak memory | 378868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316097817 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.3160978172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1511842191 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2949409228 ps |
| CPU time | 35.37 seconds |
| Started | Aug 23 06:34:58 AM UTC 24 |
| Finished | Aug 23 06:35:35 AM UTC 24 |
| Peak memory | 323824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511842191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1511842191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2902986328 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 6230483577 ps |
| CPU time | 254.16 seconds |
| Started | Aug 23 06:33:06 AM UTC 24 |
| Finished | Aug 23 06:37:23 AM UTC 24 |
| Peak memory | 213936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902986328 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.2902986328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.2504772426 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 488643768 ps |
| CPU time | 23.79 seconds |
| Started | Aug 23 06:33:46 AM UTC 24 |
| Finished | Aug 23 06:34:11 AM UTC 24 |
| Peak memory | 304944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2504772426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_t hroughput_w_partial_write.2504772426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.4248410055 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 9767523778 ps |
| CPU time | 522.82 seconds |
| Started | Aug 23 06:35:48 AM UTC 24 |
| Finished | Aug 23 06:44:36 AM UTC 24 |
| Peak memory | 385088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248410055 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during _key_req.4248410055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1384117718 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 14051352 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 06:36:38 AM UTC 24 |
| Finished | Aug 23 06:36:40 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384117718 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1384117718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.4040367597 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4110228087 ps |
| CPU time | 59.46 seconds |
| Started | Aug 23 06:35:18 AM UTC 24 |
| Finished | Aug 23 06:36:19 AM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040367597 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.4040367597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.1661075589 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 10014109586 ps |
| CPU time | 532.4 seconds |
| Started | Aug 23 06:36:01 AM UTC 24 |
| Finished | Aug 23 06:44:59 AM UTC 24 |
| Peak memory | 387004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661075589 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.1661075589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2455712735 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 218480334 ps |
| CPU time | 2.45 seconds |
| Started | Aug 23 06:35:44 AM UTC 24 |
| Finished | Aug 23 06:35:47 AM UTC 24 |
| Peak memory | 214136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455712735 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.2455712735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3471586092 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 111378080 ps |
| CPU time | 23.18 seconds |
| Started | Aug 23 06:35:36 AM UTC 24 |
| Finished | Aug 23 06:36:00 AM UTC 24 |
| Peak memory | 319348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 471586092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma x_throughput.3471586092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.3560239995 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 248083052 ps |
| CPU time | 4.09 seconds |
| Started | Aug 23 06:36:32 AM UTC 24 |
| Finished | Aug 23 06:36:37 AM UTC 24 |
| Peak memory | 224348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560239995 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.3560239995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.3692718178 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 836060137 ps |
| CPU time | 5.62 seconds |
| Started | Aug 23 06:36:29 AM UTC 24 |
| Finished | Aug 23 06:36:36 AM UTC 24 |
| Peak memory | 224116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692718178 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.3692718178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.1092472914 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 672591007 ps |
| CPU time | 84.16 seconds |
| Started | Aug 23 06:35:11 AM UTC 24 |
| Finished | Aug 23 06:36:37 AM UTC 24 |
| Peak memory | 368424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092472914 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.1092472914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3002360418 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 361902217 ps |
| CPU time | 6.66 seconds |
| Started | Aug 23 06:35:27 AM UTC 24 |
| Finished | Aug 23 06:35:35 AM UTC 24 |
| Peak memory | 214140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002360418 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.3002360418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.3300010983 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 55748424073 ps |
| CPU time | 346.61 seconds |
| Started | Aug 23 06:35:34 AM UTC 24 |
| Finished | Aug 23 06:41:25 AM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300010983 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acc ess_b2b.3300010983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.245187721 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 46538044 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:36:27 AM UTC 24 |
| Finished | Aug 23 06:36:29 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245187721 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.245187721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.237943908 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2604981802 ps |
| CPU time | 163.31 seconds |
| Started | Aug 23 06:36:20 AM UTC 24 |
| Finished | Aug 23 06:39:06 AM UTC 24 |
| Peak memory | 360628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237943908 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.237943908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.228488039 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 131557282 ps |
| CPU time | 9.48 seconds |
| Started | Aug 23 06:35:07 AM UTC 24 |
| Finished | Aug 23 06:35:18 AM UTC 24 |
| Peak memory | 268072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228488039 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.228488039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.582514368 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 35449732848 ps |
| CPU time | 1615.09 seconds |
| Started | Aug 23 06:36:38 AM UTC 24 |
| Finished | Aug 23 07:03:48 AM UTC 24 |
| Peak memory | 389044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582514368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.582514368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.4124096320 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 13741557054 ps |
| CPU time | 307.22 seconds |
| Started | Aug 23 06:35:25 AM UTC 24 |
| Finished | Aug 23 06:40:37 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124096320 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.4124096320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3573189406 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 578593623 ps |
| CPU time | 54.08 seconds |
| Started | Aug 23 06:35:36 AM UTC 24 |
| Finished | Aug 23 06:36:31 AM UTC 24 |
| Peak memory | 376672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3573189406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_t hroughput_w_partial_write.3573189406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.321481101 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2872836159 ps |
| CPU time | 252.62 seconds |
| Started | Aug 23 06:38:27 AM UTC 24 |
| Finished | Aug 23 06:42:43 AM UTC 24 |
| Peak memory | 362340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321481101 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during_ key_req.321481101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2679862123 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 14350961 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 06:39:31 AM UTC 24 |
| Finished | Aug 23 06:39:33 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679862123 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2679862123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.43472616 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 7848710006 ps |
| CPU time | 57.74 seconds |
| Started | Aug 23 06:37:04 AM UTC 24 |
| Finished | Aug 23 06:38:04 AM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43472616 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.43472616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1928680700 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1675463044 ps |
| CPU time | 47.82 seconds |
| Started | Aug 23 06:38:41 AM UTC 24 |
| Finished | Aug 23 06:39:30 AM UTC 24 |
| Peak memory | 337712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928680700 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.1928680700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.3715450583 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2968321227 ps |
| CPU time | 7.8 seconds |
| Started | Aug 23 06:38:18 AM UTC 24 |
| Finished | Aug 23 06:38:27 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715450583 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.3715450583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2779549142 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 267608076 ps |
| CPU time | 65.16 seconds |
| Started | Aug 23 06:37:48 AM UTC 24 |
| Finished | Aug 23 06:38:54 AM UTC 24 |
| Peak memory | 380788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 779549142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ma x_throughput.2779549142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2940077494 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 60218979 ps |
| CPU time | 2.7 seconds |
| Started | Aug 23 06:39:15 AM UTC 24 |
| Finished | Aug 23 06:39:19 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940077494 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.2940077494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.1995256916 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 365608864 ps |
| CPU time | 4.96 seconds |
| Started | Aug 23 06:39:08 AM UTC 24 |
| Finished | Aug 23 06:39:14 AM UTC 24 |
| Peak memory | 224320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995256916 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.1995256916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.4000487556 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 17543496028 ps |
| CPU time | 794.14 seconds |
| Started | Aug 23 06:36:54 AM UTC 24 |
| Finished | Aug 23 06:50:17 AM UTC 24 |
| Peak memory | 386876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000487556 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.4000487556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.4280883627 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 707304981 ps |
| CPU time | 8.1 seconds |
| Started | Aug 23 06:37:32 AM UTC 24 |
| Finished | Aug 23 06:37:41 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280883627 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.4280883627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3784935260 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 42867079535 ps |
| CPU time | 243.1 seconds |
| Started | Aug 23 06:37:42 AM UTC 24 |
| Finished | Aug 23 06:41:48 AM UTC 24 |
| Peak memory | 214004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784935260 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acc ess_b2b.3784935260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.2654417532 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 41800085 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 06:39:06 AM UTC 24 |
| Finished | Aug 23 06:39:08 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654417532 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2654417532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.2585930092 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 21125830549 ps |
| CPU time | 706.3 seconds |
| Started | Aug 23 06:38:55 AM UTC 24 |
| Finished | Aug 23 06:50:48 AM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585930092 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2585930092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.3912625167 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1439012312 ps |
| CPU time | 12.74 seconds |
| Started | Aug 23 06:36:40 AM UTC 24 |
| Finished | Aug 23 06:36:54 AM UTC 24 |
| Peak memory | 214012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912625167 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3912625167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2630972854 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 6573690192 ps |
| CPU time | 805.11 seconds |
| Started | Aug 23 06:39:20 AM UTC 24 |
| Finished | Aug 23 06:52:53 AM UTC 24 |
| Peak memory | 384820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263097285 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.2630972854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1660729916 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2037654818 ps |
| CPU time | 335.79 seconds |
| Started | Aug 23 06:39:19 AM UTC 24 |
| Finished | Aug 23 06:44:58 AM UTC 24 |
| Peak memory | 381048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660729916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1660729916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1286383380 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3978148586 ps |
| CPU time | 342.64 seconds |
| Started | Aug 23 06:37:24 AM UTC 24 |
| Finished | Aug 23 06:43:11 AM UTC 24 |
| Peak memory | 214216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286383380 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.1286383380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3933903217 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 155370256 ps |
| CPU time | 71.35 seconds |
| Started | Aug 23 06:38:05 AM UTC 24 |
| Finished | Aug 23 06:39:18 AM UTC 24 |
| Peak memory | 380772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3933903217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_t hroughput_w_partial_write.3933903217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2384451636 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 9818368536 ps |
| CPU time | 311.71 seconds |
| Started | Aug 23 06:40:48 AM UTC 24 |
| Finished | Aug 23 06:46:04 AM UTC 24 |
| Peak memory | 372552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384451636 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during _key_req.2384451636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2924150835 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 14184090 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 06:41:30 AM UTC 24 |
| Finished | Aug 23 06:41:32 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924150835 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.2924150835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.3507742259 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 277706853 ps |
| CPU time | 15.02 seconds |
| Started | Aug 23 06:40:11 AM UTC 24 |
| Finished | Aug 23 06:40:27 AM UTC 24 |
| Peak memory | 213808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507742259 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.3507742259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.1321719811 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 19720748789 ps |
| CPU time | 572.8 seconds |
| Started | Aug 23 06:41:05 AM UTC 24 |
| Finished | Aug 23 06:50:44 AM UTC 24 |
| Peak memory | 382832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321719811 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.1321719811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3286670340 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 770200189 ps |
| CPU time | 4.26 seconds |
| Started | Aug 23 06:40:42 AM UTC 24 |
| Finished | Aug 23 06:40:47 AM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286670340 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.3286670340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.725736883 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 233053816 ps |
| CPU time | 34.22 seconds |
| Started | Aug 23 06:40:29 AM UTC 24 |
| Finished | Aug 23 06:41:05 AM UTC 24 |
| Peak memory | 352100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 25736883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_max _throughput.725736883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.594391560 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 886641233 ps |
| CPU time | 5.24 seconds |
| Started | Aug 23 06:41:23 AM UTC 24 |
| Finished | Aug 23 06:41:29 AM UTC 24 |
| Peak memory | 224428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594391560 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.594391560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3365667266 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 285808571 ps |
| CPU time | 4.26 seconds |
| Started | Aug 23 06:41:20 AM UTC 24 |
| Finished | Aug 23 06:41:25 AM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365667266 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.3365667266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3852776523 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 29753907452 ps |
| CPU time | 220.35 seconds |
| Started | Aug 23 06:39:59 AM UTC 24 |
| Finished | Aug 23 06:43:42 AM UTC 24 |
| Peak memory | 380772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852776523 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.3852776523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.3960111487 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 37596343 ps |
| CPU time | 1.58 seconds |
| Started | Aug 23 06:40:26 AM UTC 24 |
| Finished | Aug 23 06:40:29 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960111487 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.3960111487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.898013791 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 43041509886 ps |
| CPU time | 130.94 seconds |
| Started | Aug 23 06:40:28 AM UTC 24 |
| Finished | Aug 23 06:42:41 AM UTC 24 |
| Peak memory | 214316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898013791 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acce ss_b2b.898013791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2216233282 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 103069560 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:41:18 AM UTC 24 |
| Finished | Aug 23 06:41:19 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216233282 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2216233282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.4147830168 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 443247852 ps |
| CPU time | 12.16 seconds |
| Started | Aug 23 06:41:09 AM UTC 24 |
| Finished | Aug 23 06:41:22 AM UTC 24 |
| Peak memory | 213820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147830168 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.4147830168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.1447192061 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1999245255 ps |
| CPU time | 35 seconds |
| Started | Aug 23 06:39:34 AM UTC 24 |
| Finished | Aug 23 06:40:10 AM UTC 24 |
| Peak memory | 337860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447192061 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1447192061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.898694361 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 22177793845 ps |
| CPU time | 1109.83 seconds |
| Started | Aug 23 06:41:26 AM UTC 24 |
| Finished | Aug 23 07:00:07 AM UTC 24 |
| Peak memory | 384568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898694361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.898694361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2084378526 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1530547450 ps |
| CPU time | 130.52 seconds |
| Started | Aug 23 06:40:23 AM UTC 24 |
| Finished | Aug 23 06:42:36 AM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084378526 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.2084378526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1670926916 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 58161663 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 06:40:37 AM UTC 24 |
| Finished | Aug 23 06:40:41 AM UTC 24 |
| Peak memory | 231268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1670926916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_t hroughput_w_partial_write.1670926916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3891753179 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 17206004005 ps |
| CPU time | 280.68 seconds |
| Started | Aug 23 06:42:52 AM UTC 24 |
| Finished | Aug 23 06:47:36 AM UTC 24 |
| Peak memory | 376996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891753179 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during _key_req.3891753179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1035203970 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 13851734 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 06:43:36 AM UTC 24 |
| Finished | Aug 23 06:43:38 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035203970 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.1035203970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.50251597 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4575089278 ps |
| CPU time | 64.9 seconds |
| Started | Aug 23 06:41:41 AM UTC 24 |
| Finished | Aug 23 06:42:48 AM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50251597 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.50251597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.2644758556 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 11113121254 ps |
| CPU time | 204.76 seconds |
| Started | Aug 23 06:42:53 AM UTC 24 |
| Finished | Aug 23 06:46:20 AM UTC 24 |
| Peak memory | 379120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644758556 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.2644758556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.709980013 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 784766169 ps |
| CPU time | 2.24 seconds |
| Started | Aug 23 06:42:49 AM UTC 24 |
| Finished | Aug 23 06:42:52 AM UTC 24 |
| Peak memory | 224084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709980013 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.709980013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.259837770 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 151391214 ps |
| CPU time | 50.8 seconds |
| Started | Aug 23 06:42:44 AM UTC 24 |
| Finished | Aug 23 06:43:36 AM UTC 24 |
| Peak memory | 380704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 59837770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_max _throughput.259837770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3042877218 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 47726402 ps |
| CPU time | 2.43 seconds |
| Started | Aug 23 06:43:12 AM UTC 24 |
| Finished | Aug 23 06:43:16 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042877218 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.3042877218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2192597396 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1781320176 ps |
| CPU time | 10.23 seconds |
| Started | Aug 23 06:43:03 AM UTC 24 |
| Finished | Aug 23 06:43:14 AM UTC 24 |
| Peak memory | 224092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192597396 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.2192597396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.670868358 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2159345199 ps |
| CPU time | 366.23 seconds |
| Started | Aug 23 06:41:35 AM UTC 24 |
| Finished | Aug 23 06:47:45 AM UTC 24 |
| Peak memory | 384996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670868358 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.670868358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3210950840 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2237489416 ps |
| CPU time | 19.13 seconds |
| Started | Aug 23 06:42:36 AM UTC 24 |
| Finished | Aug 23 06:42:57 AM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210950840 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.3210950840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.886714355 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 13045638088 ps |
| CPU time | 184.9 seconds |
| Started | Aug 23 06:42:42 AM UTC 24 |
| Finished | Aug 23 06:45:50 AM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886714355 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acce ss_b2b.886714355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.3492192093 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 78155791 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 06:43:01 AM UTC 24 |
| Finished | Aug 23 06:43:03 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492192093 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3492192093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.2891723259 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3982415205 ps |
| CPU time | 181.46 seconds |
| Started | Aug 23 06:42:58 AM UTC 24 |
| Finished | Aug 23 06:46:02 AM UTC 24 |
| Peak memory | 345912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891723259 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2891723259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.2950469841 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 62720330 ps |
| CPU time | 1.14 seconds |
| Started | Aug 23 06:41:32 AM UTC 24 |
| Finished | Aug 23 06:41:34 AM UTC 24 |
| Peak memory | 212572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950469841 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2950469841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.2708497578 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 9374723539 ps |
| CPU time | 1287.16 seconds |
| Started | Aug 23 06:43:16 AM UTC 24 |
| Finished | Aug 23 07:04:55 AM UTC 24 |
| Peak memory | 388716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270849757 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.2708497578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3768066687 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2449245346 ps |
| CPU time | 34.8 seconds |
| Started | Aug 23 06:43:15 AM UTC 24 |
| Finished | Aug 23 06:43:51 AM UTC 24 |
| Peak memory | 226236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768066687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3768066687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.605627183 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3034774735 ps |
| CPU time | 139.46 seconds |
| Started | Aug 23 06:41:49 AM UTC 24 |
| Finished | Aug 23 06:44:11 AM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605627183 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.605627183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3285171084 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 87972244 ps |
| CPU time | 13.47 seconds |
| Started | Aug 23 06:42:46 AM UTC 24 |
| Finished | Aug 23 06:43:00 AM UTC 24 |
| Peak memory | 284448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3285171084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t hroughput_w_partial_write.3285171084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3965589949 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2256224036 ps |
| CPU time | 334.63 seconds |
| Started | Aug 23 06:44:37 AM UTC 24 |
| Finished | Aug 23 06:50:15 AM UTC 24 |
| Peak memory | 380772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965589949 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during _key_req.3965589949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3234337930 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 13228326 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 06:45:13 AM UTC 24 |
| Finished | Aug 23 06:45:15 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234337930 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3234337930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.1179758618 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2265873628 ps |
| CPU time | 33.82 seconds |
| Started | Aug 23 06:43:52 AM UTC 24 |
| Finished | Aug 23 06:44:27 AM UTC 24 |
| Peak memory | 213856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179758618 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.1179758618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.3335405194 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4169761948 ps |
| CPU time | 116.28 seconds |
| Started | Aug 23 06:44:37 AM UTC 24 |
| Finished | Aug 23 06:46:35 AM UTC 24 |
| Peak memory | 356276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335405194 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.3335405194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1970308052 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 712623144 ps |
| CPU time | 6.68 seconds |
| Started | Aug 23 06:44:29 AM UTC 24 |
| Finished | Aug 23 06:44:36 AM UTC 24 |
| Peak memory | 213744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970308052 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.1970308052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2463648204 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 248584480 ps |
| CPU time | 60.82 seconds |
| Started | Aug 23 06:44:27 AM UTC 24 |
| Finished | Aug 23 06:45:29 AM UTC 24 |
| Peak memory | 372596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 463648204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ma x_throughput.2463648204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2259715518 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 65311133 ps |
| CPU time | 4.03 seconds |
| Started | Aug 23 06:45:02 AM UTC 24 |
| Finished | Aug 23 06:45:07 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259715518 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.2259715518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3349871665 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 95693015 ps |
| CPU time | 4.66 seconds |
| Started | Aug 23 06:45:00 AM UTC 24 |
| Finished | Aug 23 06:45:06 AM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349871665 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.3349871665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3755913108 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3241043736 ps |
| CPU time | 109.48 seconds |
| Started | Aug 23 06:43:42 AM UTC 24 |
| Finished | Aug 23 06:45:34 AM UTC 24 |
| Peak memory | 378796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755913108 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3755913108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1687782830 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 117444359 ps |
| CPU time | 14.33 seconds |
| Started | Aug 23 06:44:12 AM UTC 24 |
| Finished | Aug 23 06:44:27 AM UTC 24 |
| Peak memory | 284824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687782830 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.1687782830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.87919867 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 15048839685 ps |
| CPU time | 261.91 seconds |
| Started | Aug 23 06:44:15 AM UTC 24 |
| Finished | Aug 23 06:48:40 AM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87919867 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acces s_b2b.87919867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.2629326233 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 79466264 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 06:44:59 AM UTC 24 |
| Finished | Aug 23 06:45:01 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629326233 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2629326233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.964303608 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1515611619 ps |
| CPU time | 24.57 seconds |
| Started | Aug 23 06:44:47 AM UTC 24 |
| Finished | Aug 23 06:45:13 AM UTC 24 |
| Peak memory | 249668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964303608 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.964303608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.3535717724 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 683038989 ps |
| CPU time | 19.63 seconds |
| Started | Aug 23 06:43:38 AM UTC 24 |
| Finished | Aug 23 06:43:59 AM UTC 24 |
| Peak memory | 315380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535717724 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3535717724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.951928480 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 252891553184 ps |
| CPU time | 2099.47 seconds |
| Started | Aug 23 06:45:08 AM UTC 24 |
| Finished | Aug 23 07:20:27 AM UTC 24 |
| Peak memory | 388712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951928480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.951928480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1914342843 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1108302359 ps |
| CPU time | 8.97 seconds |
| Started | Aug 23 06:45:06 AM UTC 24 |
| Finished | Aug 23 06:45:16 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914342843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1914342843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3231650537 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 21948145049 ps |
| CPU time | 209.01 seconds |
| Started | Aug 23 06:43:59 AM UTC 24 |
| Finished | Aug 23 06:47:31 AM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231650537 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.3231650537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2661955030 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 307935225 ps |
| CPU time | 54.24 seconds |
| Started | Aug 23 06:44:28 AM UTC 24 |
| Finished | Aug 23 06:45:23 AM UTC 24 |
| Peak memory | 382820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2661955030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_t hroughput_w_partial_write.2661955030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3376832171 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 11678989763 ps |
| CPU time | 554.16 seconds |
| Started | Aug 23 06:45:51 AM UTC 24 |
| Finished | Aug 23 06:55:11 AM UTC 24 |
| Peak memory | 384696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376832171 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during _key_req.3376832171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2612076078 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 20457954 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 06:46:17 AM UTC 24 |
| Finished | Aug 23 06:46:19 AM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612076078 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2612076078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.2940758781 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2755673699 ps |
| CPU time | 32.11 seconds |
| Started | Aug 23 06:45:24 AM UTC 24 |
| Finished | Aug 23 06:45:58 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940758781 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.2940758781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1903173104 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 6547649921 ps |
| CPU time | 310.41 seconds |
| Started | Aug 23 06:45:58 AM UTC 24 |
| Finished | Aug 23 06:51:12 AM UTC 24 |
| Peak memory | 364788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903173104 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.1903173104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2817790216 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1976392165 ps |
| CPU time | 5.47 seconds |
| Started | Aug 23 06:45:51 AM UTC 24 |
| Finished | Aug 23 06:45:57 AM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817790216 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2817790216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2973299049 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 78417045 ps |
| CPU time | 14.09 seconds |
| Started | Aug 23 06:45:35 AM UTC 24 |
| Finished | Aug 23 06:45:50 AM UTC 24 |
| Peak memory | 288624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 973299049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ma x_throughput.2973299049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.897363337 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 255091312 ps |
| CPU time | 4.05 seconds |
| Started | Aug 23 06:46:04 AM UTC 24 |
| Finished | Aug 23 06:46:09 AM UTC 24 |
| Peak memory | 224292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897363337 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.897363337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.932092675 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 281454243 ps |
| CPU time | 4.14 seconds |
| Started | Aug 23 06:46:04 AM UTC 24 |
| Finished | Aug 23 06:46:09 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932092675 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.932092675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.4064965268 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4577518546 ps |
| CPU time | 87.62 seconds |
| Started | Aug 23 06:45:17 AM UTC 24 |
| Finished | Aug 23 06:46:47 AM UTC 24 |
| Peak memory | 346260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064965268 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.4064965268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.261173707 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 168206491 ps |
| CPU time | 6.56 seconds |
| Started | Aug 23 06:45:30 AM UTC 24 |
| Finished | Aug 23 06:45:37 AM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261173707 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.261173707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.882176824 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 15215337500 ps |
| CPU time | 317.49 seconds |
| Started | Aug 23 06:45:34 AM UTC 24 |
| Finished | Aug 23 06:50:55 AM UTC 24 |
| Peak memory | 213972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882176824 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acce ss_b2b.882176824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.481361580 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 33923925 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:46:02 AM UTC 24 |
| Finished | Aug 23 06:46:04 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481361580 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.481361580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.1975848850 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1680721245 ps |
| CPU time | 21.28 seconds |
| Started | Aug 23 06:45:58 AM UTC 24 |
| Finished | Aug 23 06:46:21 AM UTC 24 |
| Peak memory | 213788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975848850 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1975848850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.890814285 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 737454063 ps |
| CPU time | 15.51 seconds |
| Started | Aug 23 06:45:16 AM UTC 24 |
| Finished | Aug 23 06:45:33 AM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890814285 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.890814285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2042773590 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 24739252143 ps |
| CPU time | 2502.7 seconds |
| Started | Aug 23 06:46:10 AM UTC 24 |
| Finished | Aug 23 07:28:15 AM UTC 24 |
| Peak memory | 388716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204277359 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.2042773590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2585392566 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 878684686 ps |
| CPU time | 7.61 seconds |
| Started | Aug 23 06:46:10 AM UTC 24 |
| Finished | Aug 23 06:46:19 AM UTC 24 |
| Peak memory | 226240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585392566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2585392566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1896032746 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 10039373535 ps |
| CPU time | 196.58 seconds |
| Started | Aug 23 06:45:28 AM UTC 24 |
| Finished | Aug 23 06:48:47 AM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896032746 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.1896032746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1579699189 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 130424187 ps |
| CPU time | 37.58 seconds |
| Started | Aug 23 06:45:38 AM UTC 24 |
| Finished | Aug 23 06:46:17 AM UTC 24 |
| Peak memory | 354404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1579699189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_t hroughput_w_partial_write.1579699189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3391495644 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4004107983 ps |
| CPU time | 369.5 seconds |
| Started | Aug 23 06:47:28 AM UTC 24 |
| Finished | Aug 23 06:53:42 AM UTC 24 |
| Peak memory | 384932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391495644 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during _key_req.3391495644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.1241155328 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 48663171 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 06:47:44 AM UTC 24 |
| Finished | Aug 23 06:47:45 AM UTC 24 |
| Peak memory | 212816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241155328 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.1241155328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.2062892604 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5591795743 ps |
| CPU time | 77.92 seconds |
| Started | Aug 23 06:46:21 AM UTC 24 |
| Finished | Aug 23 06:47:40 AM UTC 24 |
| Peak memory | 214128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062892604 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.2062892604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.1711396031 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 17151599467 ps |
| CPU time | 200.57 seconds |
| Started | Aug 23 06:47:31 AM UTC 24 |
| Finished | Aug 23 06:50:54 AM UTC 24 |
| Peak memory | 344240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711396031 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.1711396031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2349920619 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3143120177 ps |
| CPU time | 5.77 seconds |
| Started | Aug 23 06:47:24 AM UTC 24 |
| Finished | Aug 23 06:47:31 AM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349920619 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.2349920619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2191957271 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 125909476 ps |
| CPU time | 34.24 seconds |
| Started | Aug 23 06:46:48 AM UTC 24 |
| Finished | Aug 23 06:47:24 AM UTC 24 |
| Peak memory | 364656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 191957271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ma x_throughput.2191957271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.731927833 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 95958263 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 06:47:37 AM UTC 24 |
| Finished | Aug 23 06:47:41 AM UTC 24 |
| Peak memory | 224428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731927833 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.731927833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.381884226 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 227070627 ps |
| CPU time | 5.35 seconds |
| Started | Aug 23 06:47:36 AM UTC 24 |
| Finished | Aug 23 06:47:43 AM UTC 24 |
| Peak memory | 224376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381884226 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.381884226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.4201193453 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 6879753570 ps |
| CPU time | 282.77 seconds |
| Started | Aug 23 06:46:20 AM UTC 24 |
| Finished | Aug 23 06:51:06 AM UTC 24 |
| Peak memory | 352172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201193453 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.4201193453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1232756948 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2668505498 ps |
| CPU time | 59.05 seconds |
| Started | Aug 23 06:46:27 AM UTC 24 |
| Finished | Aug 23 06:47:27 AM UTC 24 |
| Peak memory | 378672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232756948 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.1232756948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.1477984549 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 12200334630 ps |
| CPU time | 305.22 seconds |
| Started | Aug 23 06:46:36 AM UTC 24 |
| Finished | Aug 23 06:51:45 AM UTC 24 |
| Peak memory | 214316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477984549 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acc ess_b2b.1477984549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.910788458 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 27457394 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 06:47:35 AM UTC 24 |
| Finished | Aug 23 06:47:37 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910788458 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.910788458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.3709752375 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 112832107352 ps |
| CPU time | 1443.68 seconds |
| Started | Aug 23 06:47:32 AM UTC 24 |
| Finished | Aug 23 07:11:49 AM UTC 24 |
| Peak memory | 388716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709752375 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3709752375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.3342668997 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1459499394 ps |
| CPU time | 59.46 seconds |
| Started | Aug 23 06:46:20 AM UTC 24 |
| Finished | Aug 23 06:47:20 AM UTC 24 |
| Peak memory | 374504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342668997 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3342668997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.1231979418 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 12661904076 ps |
| CPU time | 3420.04 seconds |
| Started | Aug 23 06:47:42 AM UTC 24 |
| Finished | Aug 23 07:45:12 AM UTC 24 |
| Peak memory | 388692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123197941 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.1231979418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2027159138 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 13281580878 ps |
| CPU time | 307.84 seconds |
| Started | Aug 23 06:46:22 AM UTC 24 |
| Finished | Aug 23 06:51:34 AM UTC 24 |
| Peak memory | 213780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027159138 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.2027159138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2174474279 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 87536751 ps |
| CPU time | 12.81 seconds |
| Started | Aug 23 06:47:21 AM UTC 24 |
| Finished | Aug 23 06:47:35 AM UTC 24 |
| Peak memory | 284516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2174474279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_t hroughput_w_partial_write.2174474279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1071939919 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2414729939 ps |
| CPU time | 190.47 seconds |
| Started | Aug 23 06:48:55 AM UTC 24 |
| Finished | Aug 23 06:52:08 AM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071939919 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during _key_req.1071939919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1497428371 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 18230044 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 06:50:16 AM UTC 24 |
| Finished | Aug 23 06:50:18 AM UTC 24 |
| Peak memory | 212816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497428371 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1497428371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.743165826 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2044312548 ps |
| CPU time | 28.76 seconds |
| Started | Aug 23 06:48:14 AM UTC 24 |
| Finished | Aug 23 06:48:44 AM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743165826 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.743165826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1318854948 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2478889050 ps |
| CPU time | 580.09 seconds |
| Started | Aug 23 06:48:56 AM UTC 24 |
| Finished | Aug 23 06:58:42 AM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318854948 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.1318854948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.324901764 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 117691250 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 06:48:52 AM UTC 24 |
| Finished | Aug 23 06:48:54 AM UTC 24 |
| Peak memory | 225040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324901764 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.324901764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1072875913 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 156477861 ps |
| CPU time | 58.89 seconds |
| Started | Aug 23 06:48:46 AM UTC 24 |
| Finished | Aug 23 06:49:47 AM UTC 24 |
| Peak memory | 380704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 072875913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma x_throughput.1072875913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1989689198 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 92793452 ps |
| CPU time | 2.8 seconds |
| Started | Aug 23 06:50:03 AM UTC 24 |
| Finished | Aug 23 06:50:06 AM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989689198 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.1989689198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3157351108 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 6276464702 ps |
| CPU time | 10.81 seconds |
| Started | Aug 23 06:49:50 AM UTC 24 |
| Finished | Aug 23 06:50:01 AM UTC 24 |
| Peak memory | 224444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157351108 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.3157351108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.2282529982 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 18329871825 ps |
| CPU time | 571.96 seconds |
| Started | Aug 23 06:47:46 AM UTC 24 |
| Finished | Aug 23 06:57:24 AM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282529982 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.2282529982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.1134884111 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 197201373 ps |
| CPU time | 9.24 seconds |
| Started | Aug 23 06:48:41 AM UTC 24 |
| Finished | Aug 23 06:48:52 AM UTC 24 |
| Peak memory | 214052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134884111 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.1134884111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3406688197 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 17800201380 ps |
| CPU time | 428.99 seconds |
| Started | Aug 23 06:48:44 AM UTC 24 |
| Finished | Aug 23 06:55:58 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406688197 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acc ess_b2b.3406688197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.4121697531 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 44283634 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:49:48 AM UTC 24 |
| Finished | Aug 23 06:49:49 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121697531 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.4121697531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.1309098611 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 10376248004 ps |
| CPU time | 599.55 seconds |
| Started | Aug 23 06:49:04 AM UTC 24 |
| Finished | Aug 23 06:59:10 AM UTC 24 |
| Peak memory | 384892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309098611 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.1309098611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.3519232167 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1000629282 ps |
| CPU time | 28.31 seconds |
| Started | Aug 23 06:47:46 AM UTC 24 |
| Finished | Aug 23 06:48:15 AM UTC 24 |
| Peak memory | 317556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519232167 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3519232167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3483511741 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 5876124985 ps |
| CPU time | 58.39 seconds |
| Started | Aug 23 06:50:12 AM UTC 24 |
| Finished | Aug 23 06:51:12 AM UTC 24 |
| Peak memory | 300988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348351174 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.3483511741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4118477329 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 6494643235 ps |
| CPU time | 219.28 seconds |
| Started | Aug 23 06:50:07 AM UTC 24 |
| Finished | Aug 23 06:53:49 AM UTC 24 |
| Peak memory | 391152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118477329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.4118477329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.822184874 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 5215429292 ps |
| CPU time | 161.56 seconds |
| Started | Aug 23 06:48:16 AM UTC 24 |
| Finished | Aug 23 06:51:00 AM UTC 24 |
| Peak memory | 214200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822184874 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.822184874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.6240199 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 310965012 ps |
| CPU time | 6.29 seconds |
| Started | Aug 23 06:48:48 AM UTC 24 |
| Finished | Aug 23 06:48:56 AM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 6240199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_thro ughput_w_partial_write.6240199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2831926742 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 115372594 ps |
| CPU time | 6.35 seconds |
| Started | Aug 23 06:18:50 AM UTC 24 |
| Finished | Aug 23 06:18:57 AM UTC 24 |
| Peak memory | 233328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831926742 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_ key_req.2831926742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2559416951 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 22668011 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 06:18:58 AM UTC 24 |
| Finished | Aug 23 06:18:59 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559416951 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.2559416951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.1310900773 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3157044222 ps |
| CPU time | 13.42 seconds |
| Started | Aug 23 06:18:40 AM UTC 24 |
| Finished | Aug 23 06:18:55 AM UTC 24 |
| Peak memory | 213900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310900773 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.1310900773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.4211972519 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1687908894 ps |
| CPU time | 434.3 seconds |
| Started | Aug 23 06:18:50 AM UTC 24 |
| Finished | Aug 23 06:26:09 AM UTC 24 |
| Peak memory | 378720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211972519 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.4211972519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2168471892 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 417582602 ps |
| CPU time | 5.31 seconds |
| Started | Aug 23 06:18:50 AM UTC 24 |
| Finished | Aug 23 06:18:56 AM UTC 24 |
| Peak memory | 214120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168471892 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.2168471892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2110271760 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 346570161 ps |
| CPU time | 9.09 seconds |
| Started | Aug 23 06:18:47 AM UTC 24 |
| Finished | Aug 23 06:18:57 AM UTC 24 |
| Peak memory | 272240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 110271760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max _throughput.2110271760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.1890576996 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 334288353 ps |
| CPU time | 2.74 seconds |
| Started | Aug 23 06:18:56 AM UTC 24 |
| Finished | Aug 23 06:19:00 AM UTC 24 |
| Peak memory | 224228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890576996 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.1890576996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1211210919 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1766899566 ps |
| CPU time | 9.72 seconds |
| Started | Aug 23 06:18:56 AM UTC 24 |
| Finished | Aug 23 06:19:07 AM UTC 24 |
| Peak memory | 224132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211210919 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.1211210919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1139246528 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 17581826173 ps |
| CPU time | 797.71 seconds |
| Started | Aug 23 06:18:40 AM UTC 24 |
| Finished | Aug 23 06:32:06 AM UTC 24 |
| Peak memory | 386964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139246528 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.1139246528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.575230575 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 222777256 ps |
| CPU time | 10.16 seconds |
| Started | Aug 23 06:18:43 AM UTC 24 |
| Finished | Aug 23 06:18:55 AM UTC 24 |
| Peak memory | 213780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575230575 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.575230575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.658428954 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 7580330704 ps |
| CPU time | 482.71 seconds |
| Started | Aug 23 06:18:45 AM UTC 24 |
| Finished | Aug 23 06:26:53 AM UTC 24 |
| Peak memory | 213836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658428954 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acces s_b2b.658428954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.4277859079 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 124829668 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:18:55 AM UTC 24 |
| Finished | Aug 23 06:18:57 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277859079 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.4277859079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.718052066 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6959675544 ps |
| CPU time | 274.43 seconds |
| Started | Aug 23 06:18:55 AM UTC 24 |
| Finished | Aug 23 06:23:33 AM UTC 24 |
| Peak memory | 335796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718052066 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.718052066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.4280831866 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 645852810 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 06:18:58 AM UTC 24 |
| Finished | Aug 23 06:19:02 AM UTC 24 |
| Peak memory | 250088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280831866 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.4280831866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.2751281068 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 425482200 ps |
| CPU time | 6.86 seconds |
| Started | Aug 23 06:18:40 AM UTC 24 |
| Finished | Aug 23 06:18:48 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751281068 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2751281068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.3935876633 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 22190267653 ps |
| CPU time | 995.21 seconds |
| Started | Aug 23 06:18:57 AM UTC 24 |
| Finished | Aug 23 06:35:42 AM UTC 24 |
| Peak memory | 385036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393587663 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.3935876633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.994357830 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2144218937 ps |
| CPU time | 178.69 seconds |
| Started | Aug 23 06:18:41 AM UTC 24 |
| Finished | Aug 23 06:21:43 AM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994357830 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.994357830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.2808795623 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 429794096 ps |
| CPU time | 16.57 seconds |
| Started | Aug 23 06:18:48 AM UTC 24 |
| Finished | Aug 23 06:19:06 AM UTC 24 |
| Peak memory | 296680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2808795623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_th roughput_w_partial_write.2808795623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2354502933 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 61903188016 ps |
| CPU time | 915.9 seconds |
| Started | Aug 23 06:51:07 AM UTC 24 |
| Finished | Aug 23 07:06:31 AM UTC 24 |
| Peak memory | 387172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354502933 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during _key_req.2354502933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.4037666987 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 41678089 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 06:51:34 AM UTC 24 |
| Finished | Aug 23 06:51:36 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037666987 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.4037666987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.3343639077 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 70989700983 ps |
| CPU time | 82.41 seconds |
| Started | Aug 23 06:50:45 AM UTC 24 |
| Finished | Aug 23 06:52:09 AM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343639077 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.3343639077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.2833788276 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 60298929937 ps |
| CPU time | 843.67 seconds |
| Started | Aug 23 06:51:07 AM UTC 24 |
| Finished | Aug 23 07:05:19 AM UTC 24 |
| Peak memory | 385268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833788276 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.2833788276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2751863738 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1262139170 ps |
| CPU time | 7.33 seconds |
| Started | Aug 23 06:51:06 AM UTC 24 |
| Finished | Aug 23 06:51:15 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751863738 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.2751863738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1201851800 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 75416669 ps |
| CPU time | 0.9 seconds |
| Started | Aug 23 06:51:00 AM UTC 24 |
| Finished | Aug 23 06:51:02 AM UTC 24 |
| Peak memory | 212624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 201851800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ma x_throughput.1201851800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3857272562 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 193377085 ps |
| CPU time | 5.56 seconds |
| Started | Aug 23 06:51:16 AM UTC 24 |
| Finished | Aug 23 06:51:22 AM UTC 24 |
| Peak memory | 224324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857272562 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.3857272562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3925257028 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1049734785 ps |
| CPU time | 9.35 seconds |
| Started | Aug 23 06:51:16 AM UTC 24 |
| Finished | Aug 23 06:51:26 AM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925257028 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.3925257028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1013668215 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 10033124064 ps |
| CPU time | 636.02 seconds |
| Started | Aug 23 06:50:19 AM UTC 24 |
| Finished | Aug 23 07:01:02 AM UTC 24 |
| Peak memory | 382824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013668215 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.1013668215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2220172199 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2192911598 ps |
| CPU time | 42.32 seconds |
| Started | Aug 23 06:50:55 AM UTC 24 |
| Finished | Aug 23 06:51:39 AM UTC 24 |
| Peak memory | 348340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220172199 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.2220172199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2925120329 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 88941103561 ps |
| CPU time | 478.86 seconds |
| Started | Aug 23 06:50:56 AM UTC 24 |
| Finished | Aug 23 06:59:01 AM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925120329 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc ess_b2b.2925120329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3016372580 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 280590709 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 06:51:13 AM UTC 24 |
| Finished | Aug 23 06:51:14 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016372580 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3016372580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.1768349091 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1312077185 ps |
| CPU time | 324.47 seconds |
| Started | Aug 23 06:51:13 AM UTC 24 |
| Finished | Aug 23 06:56:41 AM UTC 24 |
| Peak memory | 378744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768349091 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.1768349091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2662638908 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1266632740 ps |
| CPU time | 46.92 seconds |
| Started | Aug 23 06:50:17 AM UTC 24 |
| Finished | Aug 23 06:51:06 AM UTC 24 |
| Peak memory | 356132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662638908 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2662638908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3134374428 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 74616509202 ps |
| CPU time | 1624.68 seconds |
| Started | Aug 23 06:51:27 AM UTC 24 |
| Finished | Aug 23 07:18:47 AM UTC 24 |
| Peak memory | 396908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313437442 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.3134374428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.836368558 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2671373893 ps |
| CPU time | 28.71 seconds |
| Started | Aug 23 06:51:23 AM UTC 24 |
| Finished | Aug 23 06:51:53 AM UTC 24 |
| Peak memory | 226608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836368558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.836368558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.1902642341 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 19751350518 ps |
| CPU time | 164.03 seconds |
| Started | Aug 23 06:50:49 AM UTC 24 |
| Finished | Aug 23 06:53:36 AM UTC 24 |
| Peak memory | 213980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902642341 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.1902642341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1440239421 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 233977119 ps |
| CPU time | 1.08 seconds |
| Started | Aug 23 06:51:03 AM UTC 24 |
| Finished | Aug 23 06:51:05 AM UTC 24 |
| Peak memory | 212404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1440239421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_t hroughput_w_partial_write.1440239421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1219440317 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 9687232710 ps |
| CPU time | 347.8 seconds |
| Started | Aug 23 06:52:43 AM UTC 24 |
| Finished | Aug 23 06:58:35 AM UTC 24 |
| Peak memory | 384936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219440317 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during _key_req.1219440317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1325365861 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 16236748 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 06:53:36 AM UTC 24 |
| Finished | Aug 23 06:53:38 AM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325365861 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1325365861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.4039855099 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 13623197512 ps |
| CPU time | 53.85 seconds |
| Started | Aug 23 06:51:46 AM UTC 24 |
| Finished | Aug 23 06:52:41 AM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039855099 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.4039855099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.2457020512 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 9834248267 ps |
| CPU time | 393.47 seconds |
| Started | Aug 23 06:52:51 AM UTC 24 |
| Finished | Aug 23 06:59:29 AM UTC 24 |
| Peak memory | 378728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457020512 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.2457020512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3824014665 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2427566134 ps |
| CPU time | 6.99 seconds |
| Started | Aug 23 06:52:42 AM UTC 24 |
| Finished | Aug 23 06:52:50 AM UTC 24 |
| Peak memory | 214312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824014665 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.3824014665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3038531250 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 635071664 ps |
| CPU time | 27.71 seconds |
| Started | Aug 23 06:52:32 AM UTC 24 |
| Finished | Aug 23 06:53:00 AM UTC 24 |
| Peak memory | 321336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 038531250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ma x_throughput.3038531250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.4076676461 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 58678778 ps |
| CPU time | 2.68 seconds |
| Started | Aug 23 06:53:01 AM UTC 24 |
| Finished | Aug 23 06:53:05 AM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076676461 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.4076676461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.860893034 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1323441433 ps |
| CPU time | 10.75 seconds |
| Started | Aug 23 06:52:56 AM UTC 24 |
| Finished | Aug 23 06:53:08 AM UTC 24 |
| Peak memory | 224344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860893034 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.860893034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.311693002 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 71153113226 ps |
| CPU time | 740 seconds |
| Started | Aug 23 06:51:40 AM UTC 24 |
| Finished | Aug 23 07:04:07 AM UTC 24 |
| Peak memory | 385192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311693002 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.311693002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.520899989 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 599374976 ps |
| CPU time | 30.37 seconds |
| Started | Aug 23 06:52:09 AM UTC 24 |
| Finished | Aug 23 06:52:41 AM UTC 24 |
| Peak memory | 333932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520899989 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.520899989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3264849815 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 23658265458 ps |
| CPU time | 528.24 seconds |
| Started | Aug 23 06:52:10 AM UTC 24 |
| Finished | Aug 23 07:01:05 AM UTC 24 |
| Peak memory | 213868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264849815 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acc ess_b2b.3264849815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2336131842 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 58575817 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 06:52:54 AM UTC 24 |
| Finished | Aug 23 06:52:56 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336131842 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2336131842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.4143245765 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 8478761902 ps |
| CPU time | 474.41 seconds |
| Started | Aug 23 06:52:54 AM UTC 24 |
| Finished | Aug 23 07:00:54 AM UTC 24 |
| Peak memory | 380852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143245765 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.4143245765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.2118823213 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 134947855 ps |
| CPU time | 53.56 seconds |
| Started | Aug 23 06:51:36 AM UTC 24 |
| Finished | Aug 23 06:52:31 AM UTC 24 |
| Peak memory | 372852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118823213 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2118823213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.2627327339 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 36852757719 ps |
| CPU time | 106.61 seconds |
| Started | Aug 23 06:53:08 AM UTC 24 |
| Finished | Aug 23 06:54:57 AM UTC 24 |
| Peak memory | 376756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262732733 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.2627327339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3858324191 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3598076746 ps |
| CPU time | 334.05 seconds |
| Started | Aug 23 06:51:53 AM UTC 24 |
| Finished | Aug 23 06:57:32 AM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858324191 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.3858324191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.816906752 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 448752932 ps |
| CPU time | 14.74 seconds |
| Started | Aug 23 06:52:38 AM UTC 24 |
| Finished | Aug 23 06:52:53 AM UTC 24 |
| Peak memory | 290584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 816906752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_th roughput_w_partial_write.816906752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3132090897 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 4906532202 ps |
| CPU time | 404.24 seconds |
| Started | Aug 23 06:55:22 AM UTC 24 |
| Finished | Aug 23 07:02:11 AM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132090897 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during _key_req.3132090897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1236746409 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 22828264 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 06:56:42 AM UTC 24 |
| Finished | Aug 23 06:56:43 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236746409 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1236746409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.1571718323 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3772111140 ps |
| CPU time | 69.38 seconds |
| Started | Aug 23 06:53:50 AM UTC 24 |
| Finished | Aug 23 06:55:01 AM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571718323 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.1571718323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.2863185986 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 672505709 ps |
| CPU time | 192.72 seconds |
| Started | Aug 23 06:55:37 AM UTC 24 |
| Finished | Aug 23 06:58:53 AM UTC 24 |
| Peak memory | 384884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863185986 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.2863185986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1636601849 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 145709133 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 06:55:18 AM UTC 24 |
| Finished | Aug 23 06:55:21 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636601849 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.1636601849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.4177542089 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 90708700 ps |
| CPU time | 15.81 seconds |
| Started | Aug 23 06:55:01 AM UTC 24 |
| Finished | Aug 23 06:55:18 AM UTC 24 |
| Peak memory | 296816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 177542089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ma x_throughput.4177542089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.142288399 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 423731713 ps |
| CPU time | 2.68 seconds |
| Started | Aug 23 06:56:14 AM UTC 24 |
| Finished | Aug 23 06:56:17 AM UTC 24 |
| Peak memory | 224172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142288399 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.142288399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3745594691 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 342207268 ps |
| CPU time | 8.94 seconds |
| Started | Aug 23 06:56:03 AM UTC 24 |
| Finished | Aug 23 06:56:13 AM UTC 24 |
| Peak memory | 224320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745594691 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.3745594691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.1818218889 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 238789832990 ps |
| CPU time | 924.53 seconds |
| Started | Aug 23 06:53:42 AM UTC 24 |
| Finished | Aug 23 07:09:16 AM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818218889 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.1818218889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.2961759860 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 5354752663 ps |
| CPU time | 70.25 seconds |
| Started | Aug 23 06:54:25 AM UTC 24 |
| Finished | Aug 23 06:55:37 AM UTC 24 |
| Peak memory | 378800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961759860 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.2961759860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2136709467 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 8247215862 ps |
| CPU time | 143.77 seconds |
| Started | Aug 23 06:54:58 AM UTC 24 |
| Finished | Aug 23 06:57:24 AM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136709467 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acc ess_b2b.2136709467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3530251165 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 53332224 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:56:00 AM UTC 24 |
| Finished | Aug 23 06:56:02 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530251165 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3530251165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.3511274301 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 13003991268 ps |
| CPU time | 928.07 seconds |
| Started | Aug 23 06:55:52 AM UTC 24 |
| Finished | Aug 23 07:11:30 AM UTC 24 |
| Peak memory | 386928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511274301 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3511274301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.495196259 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1201316558 ps |
| CPU time | 10.6 seconds |
| Started | Aug 23 06:53:38 AM UTC 24 |
| Finished | Aug 23 06:53:50 AM UTC 24 |
| Peak memory | 272156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495196259 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.495196259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2042977369 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 103689319454 ps |
| CPU time | 1439.36 seconds |
| Started | Aug 23 06:56:41 AM UTC 24 |
| Finished | Aug 23 07:20:54 AM UTC 24 |
| Peak memory | 388720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204297736 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.2042977369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.127053393 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2014078614 ps |
| CPU time | 77.59 seconds |
| Started | Aug 23 06:56:18 AM UTC 24 |
| Finished | Aug 23 06:57:37 AM UTC 24 |
| Peak memory | 313192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127053393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.127053393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2751144845 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1972826736 ps |
| CPU time | 167.21 seconds |
| Started | Aug 23 06:53:51 AM UTC 24 |
| Finished | Aug 23 06:56:40 AM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751144845 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.2751144845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3889284626 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 135231340 ps |
| CPU time | 38.54 seconds |
| Started | Aug 23 06:55:12 AM UTC 24 |
| Finished | Aug 23 06:55:52 AM UTC 24 |
| Peak memory | 348004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3889284626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_t hroughput_w_partial_write.3889284626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.236571304 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1887010404 ps |
| CPU time | 274.43 seconds |
| Started | Aug 23 06:57:45 AM UTC 24 |
| Finished | Aug 23 07:02:22 AM UTC 24 |
| Peak memory | 366708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236571304 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during_ key_req.236571304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2453356131 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 40232280 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 06:58:46 AM UTC 24 |
| Finished | Aug 23 06:58:48 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453356131 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2453356131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.2227648703 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2719255733 ps |
| CPU time | 25.61 seconds |
| Started | Aug 23 06:57:05 AM UTC 24 |
| Finished | Aug 23 06:57:32 AM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227648703 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.2227648703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.1023201358 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 11163368813 ps |
| CPU time | 254.33 seconds |
| Started | Aug 23 06:57:47 AM UTC 24 |
| Finished | Aug 23 07:02:04 AM UTC 24 |
| Peak memory | 380780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023201358 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.1023201358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.416822090 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 120867410 ps |
| CPU time | 1.74 seconds |
| Started | Aug 23 06:57:42 AM UTC 24 |
| Finished | Aug 23 06:57:45 AM UTC 24 |
| Peak memory | 222652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416822090 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.416822090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2802538105 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 292532572 ps |
| CPU time | 11.96 seconds |
| Started | Aug 23 06:57:32 AM UTC 24 |
| Finished | Aug 23 06:57:46 AM UTC 24 |
| Peak memory | 282740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 802538105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ma x_throughput.2802538105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.819180105 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 246025492 ps |
| CPU time | 4.16 seconds |
| Started | Aug 23 06:58:40 AM UTC 24 |
| Finished | Aug 23 06:58:45 AM UTC 24 |
| Peak memory | 224344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819180105 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.819180105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.1662403587 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 468682486 ps |
| CPU time | 5.28 seconds |
| Started | Aug 23 06:58:38 AM UTC 24 |
| Finished | Aug 23 06:58:44 AM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662403587 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.1662403587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.1059261019 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 6449519065 ps |
| CPU time | 131.5 seconds |
| Started | Aug 23 06:56:47 AM UTC 24 |
| Finished | Aug 23 06:59:01 AM UTC 24 |
| Peak memory | 307020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059261019 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.1059261019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1015231117 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2691044640 ps |
| CPU time | 72.42 seconds |
| Started | Aug 23 06:57:25 AM UTC 24 |
| Finished | Aug 23 06:58:39 AM UTC 24 |
| Peak memory | 380848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015231117 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.1015231117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3563453349 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3941054817 ps |
| CPU time | 257.46 seconds |
| Started | Aug 23 06:57:32 AM UTC 24 |
| Finished | Aug 23 07:01:54 AM UTC 24 |
| Peak memory | 213884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563453349 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acc ess_b2b.3563453349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3943415737 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 80159821 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:58:36 AM UTC 24 |
| Finished | Aug 23 06:58:37 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943415737 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3943415737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.1194371871 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 20270796897 ps |
| CPU time | 1414.74 seconds |
| Started | Aug 23 06:57:47 AM UTC 24 |
| Finished | Aug 23 07:21:35 AM UTC 24 |
| Peak memory | 386744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194371871 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1194371871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.1320504106 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 54990270 ps |
| CPU time | 1.42 seconds |
| Started | Aug 23 06:56:44 AM UTC 24 |
| Finished | Aug 23 06:56:46 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320504106 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1320504106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1377083688 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 141026288746 ps |
| CPU time | 1596.34 seconds |
| Started | Aug 23 06:58:45 AM UTC 24 |
| Finished | Aug 23 07:25:37 AM UTC 24 |
| Peak memory | 388712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137708368 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.1377083688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.4242727271 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 26643303198 ps |
| CPU time | 245.77 seconds |
| Started | Aug 23 06:57:24 AM UTC 24 |
| Finished | Aug 23 07:01:33 AM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242727271 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.4242727271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2424676247 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 79992764 ps |
| CPU time | 3.17 seconds |
| Started | Aug 23 06:57:37 AM UTC 24 |
| Finished | Aug 23 06:57:42 AM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2424676247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_t hroughput_w_partial_write.2424676247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.2864792405 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 11235818567 ps |
| CPU time | 415.46 seconds |
| Started | Aug 23 06:59:40 AM UTC 24 |
| Finished | Aug 23 07:06:40 AM UTC 24 |
| Peak memory | 382784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864792405 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during _key_req.2864792405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2091197136 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 12056101 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 07:00:43 AM UTC 24 |
| Finished | Aug 23 07:00:45 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091197136 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2091197136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3655615081 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 778382597 ps |
| CPU time | 43.5 seconds |
| Started | Aug 23 06:58:54 AM UTC 24 |
| Finished | Aug 23 06:59:39 AM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655615081 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.3655615081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.1174462576 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4108068868 ps |
| CPU time | 201.25 seconds |
| Started | Aug 23 06:59:48 AM UTC 24 |
| Finished | Aug 23 07:03:12 AM UTC 24 |
| Peak memory | 350024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174462576 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.1174462576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.269351699 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 551178051 ps |
| CPU time | 5.9 seconds |
| Started | Aug 23 06:59:40 AM UTC 24 |
| Finished | Aug 23 06:59:46 AM UTC 24 |
| Peak memory | 213948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269351699 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.269351699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3461170975 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 235736592 ps |
| CPU time | 27.4 seconds |
| Started | Aug 23 06:59:10 AM UTC 24 |
| Finished | Aug 23 06:59:39 AM UTC 24 |
| Peak memory | 329504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 461170975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ma x_throughput.3461170975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.4285227607 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 58408440 ps |
| CPU time | 2.7 seconds |
| Started | Aug 23 07:00:07 AM UTC 24 |
| Finished | Aug 23 07:00:11 AM UTC 24 |
| Peak memory | 224092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285227607 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.4285227607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2910381170 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2607504478 ps |
| CPU time | 11.15 seconds |
| Started | Aug 23 06:59:52 AM UTC 24 |
| Finished | Aug 23 07:00:04 AM UTC 24 |
| Peak memory | 224056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910381170 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.2910381170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.1239808901 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 11648466558 ps |
| CPU time | 468.51 seconds |
| Started | Aug 23 06:58:53 AM UTC 24 |
| Finished | Aug 23 07:06:47 AM UTC 24 |
| Peak memory | 380848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239808901 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.1239808901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.877625327 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 63124476 ps |
| CPU time | 1.93 seconds |
| Started | Aug 23 06:59:01 AM UTC 24 |
| Finished | Aug 23 06:59:04 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877625327 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.877625327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2492826837 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 7742319161 ps |
| CPU time | 262.39 seconds |
| Started | Aug 23 06:59:05 AM UTC 24 |
| Finished | Aug 23 07:03:31 AM UTC 24 |
| Peak memory | 214208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492826837 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acc ess_b2b.2492826837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2956681099 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 44285836 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 06:59:50 AM UTC 24 |
| Finished | Aug 23 06:59:51 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956681099 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2956681099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.974475537 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 77724096361 ps |
| CPU time | 1360.46 seconds |
| Started | Aug 23 06:59:50 AM UTC 24 |
| Finished | Aug 23 07:22:43 AM UTC 24 |
| Peak memory | 387160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974475537 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.974475537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.3929129062 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 216256826 ps |
| CPU time | 4.06 seconds |
| Started | Aug 23 06:58:48 AM UTC 24 |
| Finished | Aug 23 06:58:53 AM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929129062 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3929129062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.4077195680 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 130946860142 ps |
| CPU time | 1655.03 seconds |
| Started | Aug 23 07:00:11 AM UTC 24 |
| Finished | Aug 23 07:28:01 AM UTC 24 |
| Peak memory | 389112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407719568 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.4077195680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4039562100 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1148712545 ps |
| CPU time | 33.13 seconds |
| Started | Aug 23 07:00:08 AM UTC 24 |
| Finished | Aug 23 07:00:43 AM UTC 24 |
| Peak memory | 280756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039562100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.4039562100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2397301064 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1999527031 ps |
| CPU time | 171.83 seconds |
| Started | Aug 23 06:59:01 AM UTC 24 |
| Finished | Aug 23 07:01:56 AM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397301064 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.2397301064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2508642489 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 930210168 ps |
| CPU time | 17.76 seconds |
| Started | Aug 23 06:59:30 AM UTC 24 |
| Finished | Aug 23 06:59:49 AM UTC 24 |
| Peak memory | 300828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2508642489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_t hroughput_w_partial_write.2508642489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.4186374402 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 93521615850 ps |
| CPU time | 1071.66 seconds |
| Started | Aug 23 07:01:43 AM UTC 24 |
| Finished | Aug 23 07:19:45 AM UTC 24 |
| Peak memory | 385188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186374402 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during _key_req.4186374402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2034440161 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 25501753 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:02:24 AM UTC 24 |
| Finished | Aug 23 07:02:25 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034440161 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2034440161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2539483054 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 583827234 ps |
| CPU time | 32.43 seconds |
| Started | Aug 23 07:00:54 AM UTC 24 |
| Finished | Aug 23 07:01:28 AM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539483054 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.2539483054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.3947667433 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 14440708293 ps |
| CPU time | 574.91 seconds |
| Started | Aug 23 07:01:54 AM UTC 24 |
| Finished | Aug 23 07:11:35 AM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947667433 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.3947667433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.4002325427 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1690459150 ps |
| CPU time | 4.18 seconds |
| Started | Aug 23 07:01:37 AM UTC 24 |
| Finished | Aug 23 07:01:42 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002325427 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.4002325427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4090536936 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 473421136 ps |
| CPU time | 55.17 seconds |
| Started | Aug 23 07:01:29 AM UTC 24 |
| Finished | Aug 23 07:02:26 AM UTC 24 |
| Peak memory | 364400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 090536936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma x_throughput.4090536936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3498778268 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 667827237 ps |
| CPU time | 2.9 seconds |
| Started | Aug 23 07:02:12 AM UTC 24 |
| Finished | Aug 23 07:02:16 AM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498778268 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.3498778268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1092412549 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1356112673 ps |
| CPU time | 9.88 seconds |
| Started | Aug 23 07:02:07 AM UTC 24 |
| Finished | Aug 23 07:02:18 AM UTC 24 |
| Peak memory | 224380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092412549 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.1092412549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.2142143844 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 34973428656 ps |
| CPU time | 692.78 seconds |
| Started | Aug 23 07:00:49 AM UTC 24 |
| Finished | Aug 23 07:12:29 AM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142143844 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.2142143844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3806654291 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 492777276 ps |
| CPU time | 8.58 seconds |
| Started | Aug 23 07:01:06 AM UTC 24 |
| Finished | Aug 23 07:01:15 AM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806654291 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.3806654291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.4041324873 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 111865965981 ps |
| CPU time | 630.17 seconds |
| Started | Aug 23 07:01:16 AM UTC 24 |
| Finished | Aug 23 07:11:53 AM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041324873 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acc ess_b2b.4041324873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1097297471 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 28448592 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:02:05 AM UTC 24 |
| Finished | Aug 23 07:02:07 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097297471 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1097297471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.2495157332 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 23660442105 ps |
| CPU time | 993.05 seconds |
| Started | Aug 23 07:01:56 AM UTC 24 |
| Finished | Aug 23 07:18:39 AM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495157332 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2495157332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.420414602 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 401138948 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 07:00:45 AM UTC 24 |
| Finished | Aug 23 07:00:49 AM UTC 24 |
| Peak memory | 213872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420414602 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.420414602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.4067707240 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 57521826041 ps |
| CPU time | 1356.39 seconds |
| Started | Aug 23 07:02:18 AM UTC 24 |
| Finished | Aug 23 07:25:07 AM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406770724 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.4067707240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2411378121 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 859151549 ps |
| CPU time | 54.2 seconds |
| Started | Aug 23 07:02:17 AM UTC 24 |
| Finished | Aug 23 07:03:13 AM UTC 24 |
| Peak memory | 376684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411378121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2411378121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.1576133884 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 8057027631 ps |
| CPU time | 172.31 seconds |
| Started | Aug 23 07:01:03 AM UTC 24 |
| Finished | Aug 23 07:03:57 AM UTC 24 |
| Peak memory | 213960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576133884 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.1576133884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.1520235085 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 204111769 ps |
| CPU time | 1.37 seconds |
| Started | Aug 23 07:01:34 AM UTC 24 |
| Finished | Aug 23 07:01:36 AM UTC 24 |
| Peak memory | 222644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1520235085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_t hroughput_w_partial_write.1520235085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.772790118 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 11510694789 ps |
| CPU time | 398.17 seconds |
| Started | Aug 23 07:03:54 AM UTC 24 |
| Finished | Aug 23 07:10:37 AM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772790118 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during_ key_req.772790118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.1284671575 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 13679184 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 07:04:36 AM UTC 24 |
| Finished | Aug 23 07:04:37 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284671575 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.1284671575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.3554793884 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2425909424 ps |
| CPU time | 47.71 seconds |
| Started | Aug 23 07:03:07 AM UTC 24 |
| Finished | Aug 23 07:03:56 AM UTC 24 |
| Peak memory | 214128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554793884 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.3554793884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.119908651 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 55635755878 ps |
| CPU time | 824.19 seconds |
| Started | Aug 23 07:03:56 AM UTC 24 |
| Finished | Aug 23 07:17:49 AM UTC 24 |
| Peak memory | 384956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119908651 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.119908651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1154021442 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 709553037 ps |
| CPU time | 3.63 seconds |
| Started | Aug 23 07:03:51 AM UTC 24 |
| Finished | Aug 23 07:03:56 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154021442 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.1154021442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3032159524 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 72640230 ps |
| CPU time | 10.62 seconds |
| Started | Aug 23 07:03:39 AM UTC 24 |
| Finished | Aug 23 07:03:51 AM UTC 24 |
| Peak memory | 280432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 032159524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ma x_throughput.3032159524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2763834188 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 338142383 ps |
| CPU time | 4.63 seconds |
| Started | Aug 23 07:04:09 AM UTC 24 |
| Finished | Aug 23 07:04:14 AM UTC 24 |
| Peak memory | 224300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763834188 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.2763834188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1711739071 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2637726006 ps |
| CPU time | 6.58 seconds |
| Started | Aug 23 07:04:00 AM UTC 24 |
| Finished | Aug 23 07:04:08 AM UTC 24 |
| Peak memory | 224468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711739071 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.1711739071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3467646641 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 3420822438 ps |
| CPU time | 507.3 seconds |
| Started | Aug 23 07:02:27 AM UTC 24 |
| Finished | Aug 23 07:10:59 AM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467646641 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3467646641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3753659253 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 407297767 ps |
| CPU time | 23.07 seconds |
| Started | Aug 23 07:03:14 AM UTC 24 |
| Finished | Aug 23 07:03:38 AM UTC 24 |
| Peak memory | 305008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753659253 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.3753659253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2273223479 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 14547894531 ps |
| CPU time | 320.69 seconds |
| Started | Aug 23 07:03:32 AM UTC 24 |
| Finished | Aug 23 07:08:57 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273223479 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acc ess_b2b.2273223479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3800856335 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 92190810 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 07:03:58 AM UTC 24 |
| Finished | Aug 23 07:04:00 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800856335 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3800856335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.1339193858 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 91389745425 ps |
| CPU time | 727.61 seconds |
| Started | Aug 23 07:03:56 AM UTC 24 |
| Finished | Aug 23 07:16:11 AM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339193858 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1339193858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.4137001914 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 495666276 ps |
| CPU time | 39.48 seconds |
| Started | Aug 23 07:02:26 AM UTC 24 |
| Finished | Aug 23 07:03:06 AM UTC 24 |
| Peak memory | 344244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137001914 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.4137001914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2571483455 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 22024208555 ps |
| CPU time | 1566.86 seconds |
| Started | Aug 23 07:04:15 AM UTC 24 |
| Finished | Aug 23 07:30:36 AM UTC 24 |
| Peak memory | 387004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257148345 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.2571483455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1244866670 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 268149870 ps |
| CPU time | 24.75 seconds |
| Started | Aug 23 07:04:09 AM UTC 24 |
| Finished | Aug 23 07:04:35 AM UTC 24 |
| Peak memory | 290996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244866670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1244866670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.365463302 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 28429786715 ps |
| CPU time | 287.76 seconds |
| Started | Aug 23 07:03:13 AM UTC 24 |
| Finished | Aug 23 07:08:05 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365463302 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.365463302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.2090397359 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 153157873 ps |
| CPU time | 4.74 seconds |
| Started | Aug 23 07:03:48 AM UTC 24 |
| Finished | Aug 23 07:03:54 AM UTC 24 |
| Peak memory | 247576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2090397359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_t hroughput_w_partial_write.2090397359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1876596394 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 5472664122 ps |
| CPU time | 975.49 seconds |
| Started | Aug 23 07:06:56 AM UTC 24 |
| Finished | Aug 23 07:23:21 AM UTC 24 |
| Peak memory | 384932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876596394 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during _key_req.1876596394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1879741699 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 14879020 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 07:08:57 AM UTC 24 |
| Finished | Aug 23 07:08:59 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879741699 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1879741699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.3710244369 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 280538178 ps |
| CPU time | 15.64 seconds |
| Started | Aug 23 07:05:19 AM UTC 24 |
| Finished | Aug 23 07:05:36 AM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710244369 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.3710244369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.1842465273 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 9311218718 ps |
| CPU time | 241.34 seconds |
| Started | Aug 23 07:06:59 AM UTC 24 |
| Finished | Aug 23 07:11:03 AM UTC 24 |
| Peak memory | 343912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842465273 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.1842465273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.993041531 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1350274357 ps |
| CPU time | 5.17 seconds |
| Started | Aug 23 07:06:48 AM UTC 24 |
| Finished | Aug 23 07:06:54 AM UTC 24 |
| Peak memory | 214068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993041531 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.993041531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1974429868 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1406889366 ps |
| CPU time | 56.57 seconds |
| Started | Aug 23 07:06:32 AM UTC 24 |
| Finished | Aug 23 07:07:30 AM UTC 24 |
| Peak memory | 378740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 974429868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ma x_throughput.1974429868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1398366207 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 479074019 ps |
| CPU time | 3.92 seconds |
| Started | Aug 23 07:08:17 AM UTC 24 |
| Finished | Aug 23 07:08:22 AM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398366207 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.1398366207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.888378774 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 360365599 ps |
| CPU time | 8.69 seconds |
| Started | Aug 23 07:08:07 AM UTC 24 |
| Finished | Aug 23 07:08:17 AM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888378774 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.888378774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1436851298 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 14700172822 ps |
| CPU time | 847.05 seconds |
| Started | Aug 23 07:04:56 AM UTC 24 |
| Finished | Aug 23 07:19:12 AM UTC 24 |
| Peak memory | 382820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436851298 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.1436851298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1890198981 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 3765256344 ps |
| CPU time | 17.44 seconds |
| Started | Aug 23 07:05:56 AM UTC 24 |
| Finished | Aug 23 07:06:15 AM UTC 24 |
| Peak memory | 213868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890198981 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.1890198981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.1606609115 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 18441329437 ps |
| CPU time | 284.4 seconds |
| Started | Aug 23 07:06:15 AM UTC 24 |
| Finished | Aug 23 07:11:04 AM UTC 24 |
| Peak memory | 213900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606609115 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acc ess_b2b.1606609115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3951523958 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 27588793 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 07:08:05 AM UTC 24 |
| Finished | Aug 23 07:08:07 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951523958 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3951523958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.348976463 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3017251392 ps |
| CPU time | 643.88 seconds |
| Started | Aug 23 07:07:30 AM UTC 24 |
| Finished | Aug 23 07:18:20 AM UTC 24 |
| Peak memory | 385208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348976463 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.348976463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.1657002561 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2631600734 ps |
| CPU time | 75.92 seconds |
| Started | Aug 23 07:04:38 AM UTC 24 |
| Finished | Aug 23 07:05:55 AM UTC 24 |
| Peak memory | 379076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657002561 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1657002561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.115020069 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 82170732702 ps |
| CPU time | 3055.52 seconds |
| Started | Aug 23 07:08:51 AM UTC 24 |
| Finished | Aug 23 08:00:14 AM UTC 24 |
| Peak memory | 388684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115020069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.115020069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2350730674 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2052466848 ps |
| CPU time | 179.4 seconds |
| Started | Aug 23 07:08:23 AM UTC 24 |
| Finished | Aug 23 07:11:25 AM UTC 24 |
| Peak memory | 374968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350730674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2350730674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1310125324 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2271333523 ps |
| CPU time | 190.68 seconds |
| Started | Aug 23 07:05:37 AM UTC 24 |
| Finished | Aug 23 07:08:51 AM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310125324 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.1310125324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1621527248 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 141425129 ps |
| CPU time | 16.11 seconds |
| Started | Aug 23 07:06:41 AM UTC 24 |
| Finished | Aug 23 07:06:58 AM UTC 24 |
| Peak memory | 296808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1621527248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_t hroughput_w_partial_write.1621527248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3541719918 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2139935339 ps |
| CPU time | 315.48 seconds |
| Started | Aug 23 07:11:04 AM UTC 24 |
| Finished | Aug 23 07:16:23 AM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541719918 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during _key_req.3541719918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1862304827 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 10997787 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 07:11:36 AM UTC 24 |
| Finished | Aug 23 07:11:37 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862304827 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1862304827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.882401251 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1143626556 ps |
| CPU time | 16.63 seconds |
| Started | Aug 23 07:09:59 AM UTC 24 |
| Finished | Aug 23 07:10:17 AM UTC 24 |
| Peak memory | 213812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882401251 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.882401251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.2803842859 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 18456169082 ps |
| CPU time | 625.42 seconds |
| Started | Aug 23 07:11:08 AM UTC 24 |
| Finished | Aug 23 07:21:40 AM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803842859 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.2803842859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.4124347936 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1695085865 ps |
| CPU time | 9.82 seconds |
| Started | Aug 23 07:11:04 AM UTC 24 |
| Finished | Aug 23 07:11:15 AM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124347936 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.4124347936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2373053137 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 50587173 ps |
| CPU time | 2.71 seconds |
| Started | Aug 23 07:11:00 AM UTC 24 |
| Finished | Aug 23 07:11:04 AM UTC 24 |
| Peak memory | 231280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 373053137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ma x_throughput.2373053137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.38053941 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 167119100 ps |
| CPU time | 2.54 seconds |
| Started | Aug 23 07:11:31 AM UTC 24 |
| Finished | Aug 23 07:11:34 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38053941 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.38053941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1196862832 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 355812316 ps |
| CPU time | 4.83 seconds |
| Started | Aug 23 07:11:27 AM UTC 24 |
| Finished | Aug 23 07:11:33 AM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196862832 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.1196862832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1950208292 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 6384958161 ps |
| CPU time | 320.18 seconds |
| Started | Aug 23 07:09:16 AM UTC 24 |
| Finished | Aug 23 07:14:40 AM UTC 24 |
| Peak memory | 383096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950208292 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.1950208292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1116063774 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 54161559 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 07:10:38 AM UTC 24 |
| Finished | Aug 23 07:10:40 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116063774 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.1116063774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3614608951 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 72793703582 ps |
| CPU time | 454.28 seconds |
| Started | Aug 23 07:10:41 AM UTC 24 |
| Finished | Aug 23 07:18:20 AM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614608951 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acc ess_b2b.3614608951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.278709110 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 69503299 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 07:11:25 AM UTC 24 |
| Finished | Aug 23 07:11:27 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278709110 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.278709110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.1039208788 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 64550038977 ps |
| CPU time | 845.51 seconds |
| Started | Aug 23 07:11:15 AM UTC 24 |
| Finished | Aug 23 07:25:29 AM UTC 24 |
| Peak memory | 384880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039208788 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1039208788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.1842523933 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2910713242 ps |
| CPU time | 57.27 seconds |
| Started | Aug 23 07:08:59 AM UTC 24 |
| Finished | Aug 23 07:09:58 AM UTC 24 |
| Peak memory | 381036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842523933 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1842523933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2796589504 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 33245373435 ps |
| CPU time | 1920.46 seconds |
| Started | Aug 23 07:11:35 AM UTC 24 |
| Finished | Aug 23 07:43:54 AM UTC 24 |
| Peak memory | 386668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279658950 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.2796589504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1227124821 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2561931918 ps |
| CPU time | 224.71 seconds |
| Started | Aug 23 07:10:17 AM UTC 24 |
| Finished | Aug 23 07:14:05 AM UTC 24 |
| Peak memory | 213968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227124821 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.1227124821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3369898550 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 46267155 ps |
| CPU time | 2.04 seconds |
| Started | Aug 23 07:11:04 AM UTC 24 |
| Finished | Aug 23 07:11:07 AM UTC 24 |
| Peak memory | 230280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3369898550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_t hroughput_w_partial_write.3369898550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2008053809 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 7662751423 ps |
| CPU time | 969.61 seconds |
| Started | Aug 23 07:13:21 AM UTC 24 |
| Finished | Aug 23 07:29:40 AM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008053809 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during _key_req.2008053809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2892416064 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 23806395 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 07:15:09 AM UTC 24 |
| Finished | Aug 23 07:15:11 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892416064 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.2892416064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.1089153206 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 491541026 ps |
| CPU time | 27.64 seconds |
| Started | Aug 23 07:11:54 AM UTC 24 |
| Finished | Aug 23 07:12:23 AM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089153206 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.1089153206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3819467301 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 3169902181 ps |
| CPU time | 498.03 seconds |
| Started | Aug 23 07:13:28 AM UTC 24 |
| Finished | Aug 23 07:21:51 AM UTC 24 |
| Peak memory | 380852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819467301 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.3819467301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.3808088821 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1269864548 ps |
| CPU time | 3.59 seconds |
| Started | Aug 23 07:13:16 AM UTC 24 |
| Finished | Aug 23 07:13:21 AM UTC 24 |
| Peak memory | 213856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808088821 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.3808088821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2137440173 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 151883403 ps |
| CPU time | 54.69 seconds |
| Started | Aug 23 07:12:30 AM UTC 24 |
| Finished | Aug 23 07:13:26 AM UTC 24 |
| Peak memory | 380712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 137440173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma x_throughput.2137440173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2982828976 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 193019866 ps |
| CPU time | 2.89 seconds |
| Started | Aug 23 07:14:41 AM UTC 24 |
| Finished | Aug 23 07:14:45 AM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982828976 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.2982828976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2093667714 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 449911946 ps |
| CPU time | 9.42 seconds |
| Started | Aug 23 07:14:40 AM UTC 24 |
| Finished | Aug 23 07:14:50 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093667714 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.2093667714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1291567930 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 7961656860 ps |
| CPU time | 215.55 seconds |
| Started | Aug 23 07:11:50 AM UTC 24 |
| Finished | Aug 23 07:15:28 AM UTC 24 |
| Peak memory | 385172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291567930 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.1291567930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.194032880 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 76424415 ps |
| CPU time | 4.97 seconds |
| Started | Aug 23 07:12:23 AM UTC 24 |
| Finished | Aug 23 07:12:29 AM UTC 24 |
| Peak memory | 241776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194032880 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.194032880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.3888927419 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 70774178752 ps |
| CPU time | 251.46 seconds |
| Started | Aug 23 07:12:30 AM UTC 24 |
| Finished | Aug 23 07:16:45 AM UTC 24 |
| Peak memory | 213980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888927419 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acc ess_b2b.3888927419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3226279753 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 78332088 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 07:14:38 AM UTC 24 |
| Finished | Aug 23 07:14:40 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226279753 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3226279753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.1333656529 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 5844369787 ps |
| CPU time | 60.89 seconds |
| Started | Aug 23 07:14:06 AM UTC 24 |
| Finished | Aug 23 07:15:08 AM UTC 24 |
| Peak memory | 360380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333656529 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1333656529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.963834466 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 214337774 ps |
| CPU time | 31.13 seconds |
| Started | Aug 23 07:11:38 AM UTC 24 |
| Finished | Aug 23 07:12:10 AM UTC 24 |
| Peak memory | 325356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963834466 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.963834466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1698300438 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 97768451510 ps |
| CPU time | 2663 seconds |
| Started | Aug 23 07:14:51 AM UTC 24 |
| Finished | Aug 23 07:59:38 AM UTC 24 |
| Peak memory | 388928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169830043 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.1698300438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3617717257 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1503626338 ps |
| CPU time | 340.75 seconds |
| Started | Aug 23 07:14:46 AM UTC 24 |
| Finished | Aug 23 07:20:31 AM UTC 24 |
| Peak memory | 389036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617717257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3617717257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1509040274 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2851809173 ps |
| CPU time | 143.63 seconds |
| Started | Aug 23 07:12:11 AM UTC 24 |
| Finished | Aug 23 07:14:37 AM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509040274 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.1509040274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.547718240 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 627461192 ps |
| CPU time | 18.31 seconds |
| Started | Aug 23 07:12:55 AM UTC 24 |
| Finished | Aug 23 07:13:15 AM UTC 24 |
| Peak memory | 292708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 547718240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_th roughput_w_partial_write.547718240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3434717571 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1429642375 ps |
| CPU time | 175.3 seconds |
| Started | Aug 23 06:19:14 AM UTC 24 |
| Finished | Aug 23 06:22:12 AM UTC 24 |
| Peak memory | 385004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434717571 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_ key_req.3434717571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2398070397 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 15794794 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 06:19:39 AM UTC 24 |
| Finished | Aug 23 06:19:41 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398070397 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2398070397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.1924071027 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1843865455 ps |
| CPU time | 27.24 seconds |
| Started | Aug 23 06:19:01 AM UTC 24 |
| Finished | Aug 23 06:19:30 AM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924071027 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.1924071027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.487720358 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2565757171 ps |
| CPU time | 735.61 seconds |
| Started | Aug 23 06:19:18 AM UTC 24 |
| Finished | Aug 23 06:31:41 AM UTC 24 |
| Peak memory | 382816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487720358 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.487720358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1469108361 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 869653546 ps |
| CPU time | 2.58 seconds |
| Started | Aug 23 06:19:13 AM UTC 24 |
| Finished | Aug 23 06:19:17 AM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469108361 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.1469108361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2160039439 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 480135482 ps |
| CPU time | 30.37 seconds |
| Started | Aug 23 06:19:08 AM UTC 24 |
| Finished | Aug 23 06:19:40 AM UTC 24 |
| Peak memory | 343916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 160039439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max _throughput.2160039439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1501561281 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 483496318 ps |
| CPU time | 4.5 seconds |
| Started | Aug 23 06:19:31 AM UTC 24 |
| Finished | Aug 23 06:19:37 AM UTC 24 |
| Peak memory | 224436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501561281 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.1501561281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3628563792 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 463553944 ps |
| CPU time | 9.53 seconds |
| Started | Aug 23 06:19:28 AM UTC 24 |
| Finished | Aug 23 06:19:39 AM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628563792 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.3628563792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2497160768 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 14947140912 ps |
| CPU time | 638.18 seconds |
| Started | Aug 23 06:19:01 AM UTC 24 |
| Finished | Aug 23 06:29:46 AM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497160768 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.2497160768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1033862838 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4526788838 ps |
| CPU time | 17.61 seconds |
| Started | Aug 23 06:19:02 AM UTC 24 |
| Finished | Aug 23 06:19:21 AM UTC 24 |
| Peak memory | 213876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033862838 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.1033862838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3787129630 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 18338773320 ps |
| CPU time | 246.2 seconds |
| Started | Aug 23 06:19:07 AM UTC 24 |
| Finished | Aug 23 06:23:17 AM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787129630 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acce ss_b2b.3787129630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1220924402 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 47668907 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:19:24 AM UTC 24 |
| Finished | Aug 23 06:19:26 AM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220924402 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1220924402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.1762636198 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4086786419 ps |
| CPU time | 17.27 seconds |
| Started | Aug 23 06:19:22 AM UTC 24 |
| Finished | Aug 23 06:19:40 AM UTC 24 |
| Peak memory | 245624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762636198 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1762636198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.4278377776 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 624789267 ps |
| CPU time | 2.71 seconds |
| Started | Aug 23 06:19:37 AM UTC 24 |
| Finished | Aug 23 06:19:41 AM UTC 24 |
| Peak memory | 250100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278377776 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.4278377776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.3991887126 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1007572185 ps |
| CPU time | 10.73 seconds |
| Started | Aug 23 06:18:59 AM UTC 24 |
| Finished | Aug 23 06:19:11 AM UTC 24 |
| Peak memory | 213808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991887126 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3991887126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1652362054 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 980929269 ps |
| CPU time | 109.4 seconds |
| Started | Aug 23 06:19:34 AM UTC 24 |
| Finished | Aug 23 06:21:25 AM UTC 24 |
| Peak memory | 389000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652362054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1652362054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.102278069 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3982378507 ps |
| CPU time | 333.91 seconds |
| Started | Aug 23 06:19:01 AM UTC 24 |
| Finished | Aug 23 06:24:40 AM UTC 24 |
| Peak memory | 213904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102278069 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.102278069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.158941282 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 135285614 ps |
| CPU time | 12.56 seconds |
| Started | Aug 23 06:19:08 AM UTC 24 |
| Finished | Aug 23 06:19:22 AM UTC 24 |
| Peak memory | 272100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 158941282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_thr oughput_w_partial_write.158941282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.833717368 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 29876962084 ps |
| CPU time | 772.72 seconds |
| Started | Aug 23 07:17:39 AM UTC 24 |
| Finished | Aug 23 07:30:40 AM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833717368 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during_ key_req.833717368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.744540097 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 18025392 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:18:40 AM UTC 24 |
| Finished | Aug 23 07:18:41 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744540097 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.744540097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2164304073 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 15314978710 ps |
| CPU time | 54.64 seconds |
| Started | Aug 23 07:15:30 AM UTC 24 |
| Finished | Aug 23 07:16:26 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164304073 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.2164304073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.3084002747 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 4764501797 ps |
| CPU time | 177.52 seconds |
| Started | Aug 23 07:17:40 AM UTC 24 |
| Finished | Aug 23 07:20:40 AM UTC 24 |
| Peak memory | 372984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084002747 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.3084002747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.1292153182 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 133103365 ps |
| CPU time | 1.71 seconds |
| Started | Aug 23 07:17:37 AM UTC 24 |
| Finished | Aug 23 07:17:40 AM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292153182 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.1292153182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2335252472 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 776960237 ps |
| CPU time | 49.48 seconds |
| Started | Aug 23 07:16:46 AM UTC 24 |
| Finished | Aug 23 07:17:37 AM UTC 24 |
| Peak memory | 372596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 335252472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ma x_throughput.2335252472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1636984318 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 351268634 ps |
| CPU time | 5.6 seconds |
| Started | Aug 23 07:18:25 AM UTC 24 |
| Finished | Aug 23 07:18:31 AM UTC 24 |
| Peak memory | 224012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636984318 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.1636984318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.686033917 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 925333937 ps |
| CPU time | 9.66 seconds |
| Started | Aug 23 07:18:21 AM UTC 24 |
| Finished | Aug 23 07:18:32 AM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686033917 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.686033917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1545391684 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 11239991318 ps |
| CPU time | 451.3 seconds |
| Started | Aug 23 07:15:14 AM UTC 24 |
| Finished | Aug 23 07:22:51 AM UTC 24 |
| Peak memory | 386988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545391684 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.1545391684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3772508517 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 839552518 ps |
| CPU time | 52.9 seconds |
| Started | Aug 23 07:16:24 AM UTC 24 |
| Finished | Aug 23 07:17:18 AM UTC 24 |
| Peak memory | 378736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772508517 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.3772508517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.2880169562 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 9517119225 ps |
| CPU time | 310.52 seconds |
| Started | Aug 23 07:16:27 AM UTC 24 |
| Finished | Aug 23 07:21:41 AM UTC 24 |
| Peak memory | 214260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880169562 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acc ess_b2b.2880169562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.362595324 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 109196701 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 07:18:21 AM UTC 24 |
| Finished | Aug 23 07:18:23 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362595324 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.362595324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.1328166002 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2269583984 ps |
| CPU time | 592.42 seconds |
| Started | Aug 23 07:17:49 AM UTC 24 |
| Finished | Aug 23 07:27:48 AM UTC 24 |
| Peak memory | 384808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328166002 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1328166002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3743238810 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 67138252 ps |
| CPU time | 1.78 seconds |
| Started | Aug 23 07:15:11 AM UTC 24 |
| Finished | Aug 23 07:15:14 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743238810 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3743238810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.3374531891 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 12319891421 ps |
| CPU time | 2340.77 seconds |
| Started | Aug 23 07:18:34 AM UTC 24 |
| Finished | Aug 23 07:57:55 AM UTC 24 |
| Peak memory | 388712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337453189 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.3374531891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3399191054 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1651046802 ps |
| CPU time | 216.42 seconds |
| Started | Aug 23 07:18:32 AM UTC 24 |
| Finished | Aug 23 07:22:11 AM UTC 24 |
| Peak memory | 380784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399191054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3399191054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1333415385 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 7437836134 ps |
| CPU time | 335.16 seconds |
| Started | Aug 23 07:16:13 AM UTC 24 |
| Finished | Aug 23 07:21:52 AM UTC 24 |
| Peak memory | 213980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333415385 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.1333415385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.885103604 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 107409744 ps |
| CPU time | 18.06 seconds |
| Started | Aug 23 07:17:19 AM UTC 24 |
| Finished | Aug 23 07:17:38 AM UTC 24 |
| Peak memory | 302876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 885103604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_th roughput_w_partial_write.885103604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.4079975277 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 5029110276 ps |
| CPU time | 258.39 seconds |
| Started | Aug 23 07:20:31 AM UTC 24 |
| Finished | Aug 23 07:24:53 AM UTC 24 |
| Peak memory | 378996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079975277 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during _key_req.4079975277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2197574282 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 29949667 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:21:14 AM UTC 24 |
| Finished | Aug 23 07:21:15 AM UTC 24 |
| Peak memory | 212816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197574282 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2197574282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.790245140 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1027542207 ps |
| CPU time | 57.7 seconds |
| Started | Aug 23 07:19:00 AM UTC 24 |
| Finished | Aug 23 07:19:59 AM UTC 24 |
| Peak memory | 214056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790245140 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.790245140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.67591005 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 8228336947 ps |
| CPU time | 34.28 seconds |
| Started | Aug 23 07:20:37 AM UTC 24 |
| Finished | Aug 23 07:21:13 AM UTC 24 |
| Peak memory | 278692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67591005 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.67591005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.1592163576 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1433366055 ps |
| CPU time | 7.82 seconds |
| Started | Aug 23 07:20:28 AM UTC 24 |
| Finished | Aug 23 07:20:37 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592163576 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.1592163576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.321203323 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 424136368 ps |
| CPU time | 13.92 seconds |
| Started | Aug 23 07:20:00 AM UTC 24 |
| Finished | Aug 23 07:20:15 AM UTC 24 |
| Peak memory | 290792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 21203323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_max _throughput.321203323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.3956816111 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 496094631 ps |
| CPU time | 2.82 seconds |
| Started | Aug 23 07:21:04 AM UTC 24 |
| Finished | Aug 23 07:21:08 AM UTC 24 |
| Peak memory | 224020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956816111 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.3956816111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.398391271 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 378251461 ps |
| CPU time | 5.56 seconds |
| Started | Aug 23 07:20:57 AM UTC 24 |
| Finished | Aug 23 07:21:03 AM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398391271 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.398391271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2191857745 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 33988878927 ps |
| CPU time | 427.34 seconds |
| Started | Aug 23 07:18:48 AM UTC 24 |
| Finished | Aug 23 07:26:00 AM UTC 24 |
| Peak memory | 386988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191857745 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.2191857745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1239669064 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 429947625 ps |
| CPU time | 5.6 seconds |
| Started | Aug 23 07:19:46 AM UTC 24 |
| Finished | Aug 23 07:19:53 AM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239669064 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.1239669064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.2684019190 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 11634794689 ps |
| CPU time | 181.33 seconds |
| Started | Aug 23 07:19:53 AM UTC 24 |
| Finished | Aug 23 07:22:57 AM UTC 24 |
| Peak memory | 213968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684019190 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acc ess_b2b.2684019190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3621493336 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 28049739 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:20:55 AM UTC 24 |
| Finished | Aug 23 07:20:56 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621493336 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3621493336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.699935044 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3045601026 ps |
| CPU time | 151.97 seconds |
| Started | Aug 23 07:20:41 AM UTC 24 |
| Finished | Aug 23 07:23:15 AM UTC 24 |
| Peak memory | 378724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699935044 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.699935044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2849309931 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4080660274 ps |
| CPU time | 15.88 seconds |
| Started | Aug 23 07:18:42 AM UTC 24 |
| Finished | Aug 23 07:18:59 AM UTC 24 |
| Peak memory | 214204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849309931 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2849309931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.2390652281 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 19218417648 ps |
| CPU time | 799.22 seconds |
| Started | Aug 23 07:21:08 AM UTC 24 |
| Finished | Aug 23 07:34:35 AM UTC 24 |
| Peak memory | 380852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239065228 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.2390652281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3565366054 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 257852479 ps |
| CPU time | 10.93 seconds |
| Started | Aug 23 07:21:07 AM UTC 24 |
| Finished | Aug 23 07:21:19 AM UTC 24 |
| Peak memory | 257924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565366054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3565366054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1357906776 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2375197685 ps |
| CPU time | 206.34 seconds |
| Started | Aug 23 07:19:13 AM UTC 24 |
| Finished | Aug 23 07:22:42 AM UTC 24 |
| Peak memory | 213908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357906776 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.1357906776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.890051573 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 139055639 ps |
| CPU time | 47.93 seconds |
| Started | Aug 23 07:20:16 AM UTC 24 |
| Finished | Aug 23 07:21:06 AM UTC 24 |
| Peak memory | 368412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 890051573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_th roughput_w_partial_write.890051573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.4180880569 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 7005953107 ps |
| CPU time | 518.19 seconds |
| Started | Aug 23 07:22:03 AM UTC 24 |
| Finished | Aug 23 07:30:46 AM UTC 24 |
| Peak memory | 384880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180880569 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during _key_req.4180880569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1895826493 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 12129640 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 07:22:51 AM UTC 24 |
| Finished | Aug 23 07:22:53 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895826493 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1895826493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.2246858211 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 54046903993 ps |
| CPU time | 83.18 seconds |
| Started | Aug 23 07:21:22 AM UTC 24 |
| Finished | Aug 23 07:22:47 AM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246858211 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.2246858211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.830380585 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 16688536159 ps |
| CPU time | 497 seconds |
| Started | Aug 23 07:22:12 AM UTC 24 |
| Finished | Aug 23 07:30:34 AM UTC 24 |
| Peak memory | 384824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830380585 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.830380585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.124299612 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 674822619 ps |
| CPU time | 2.28 seconds |
| Started | Aug 23 07:21:59 AM UTC 24 |
| Finished | Aug 23 07:22:02 AM UTC 24 |
| Peak memory | 224404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124299612 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.124299612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2424972666 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 103773094 ps |
| CPU time | 4.81 seconds |
| Started | Aug 23 07:21:51 AM UTC 24 |
| Finished | Aug 23 07:21:57 AM UTC 24 |
| Peak memory | 247664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 424972666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ma x_throughput.2424972666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.875890459 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 172560354 ps |
| CPU time | 5.18 seconds |
| Started | Aug 23 07:22:45 AM UTC 24 |
| Finished | Aug 23 07:22:51 AM UTC 24 |
| Peak memory | 224380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875890459 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.875890459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2541295677 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 920572511 ps |
| CPU time | 5.33 seconds |
| Started | Aug 23 07:22:44 AM UTC 24 |
| Finished | Aug 23 07:22:50 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541295677 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.2541295677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.226845297 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 13121588749 ps |
| CPU time | 254.96 seconds |
| Started | Aug 23 07:21:20 AM UTC 24 |
| Finished | Aug 23 07:25:38 AM UTC 24 |
| Peak memory | 382900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226845297 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.226845297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3581708044 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 775438097 ps |
| CPU time | 44.55 seconds |
| Started | Aug 23 07:21:41 AM UTC 24 |
| Finished | Aug 23 07:22:27 AM UTC 24 |
| Peak memory | 348016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581708044 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.3581708044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.1528604085 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 12630379575 ps |
| CPU time | 302.48 seconds |
| Started | Aug 23 07:21:42 AM UTC 24 |
| Finished | Aug 23 07:26:49 AM UTC 24 |
| Peak memory | 214236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528604085 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acc ess_b2b.1528604085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.534552440 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 89495339 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 07:22:43 AM UTC 24 |
| Finished | Aug 23 07:22:45 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534552440 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.534552440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.3063296731 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 13521116834 ps |
| CPU time | 252.05 seconds |
| Started | Aug 23 07:22:28 AM UTC 24 |
| Finished | Aug 23 07:26:43 AM UTC 24 |
| Peak memory | 384896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063296731 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3063296731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.426977153 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 117596170 ps |
| CPU time | 4.82 seconds |
| Started | Aug 23 07:21:16 AM UTC 24 |
| Finished | Aug 23 07:21:22 AM UTC 24 |
| Peak memory | 213792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426977153 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.426977153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1002028189 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 109000192215 ps |
| CPU time | 3292.51 seconds |
| Started | Aug 23 07:22:50 AM UTC 24 |
| Finished | Aug 23 08:18:15 AM UTC 24 |
| Peak memory | 388792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100202818 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.1002028189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1485101029 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 11438010853 ps |
| CPU time | 95.83 seconds |
| Started | Aug 23 07:22:48 AM UTC 24 |
| Finished | Aug 23 07:24:26 AM UTC 24 |
| Peak memory | 401656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485101029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1485101029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3978395430 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 4329830634 ps |
| CPU time | 175.1 seconds |
| Started | Aug 23 07:21:36 AM UTC 24 |
| Finished | Aug 23 07:24:34 AM UTC 24 |
| Peak memory | 214248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978395430 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.3978395430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.355749015 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 590054620 ps |
| CPU time | 55.16 seconds |
| Started | Aug 23 07:21:52 AM UTC 24 |
| Finished | Aug 23 07:22:49 AM UTC 24 |
| Peak memory | 372592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 355749015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_th roughput_w_partial_write.355749015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1529537295 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3985981463 ps |
| CPU time | 849.28 seconds |
| Started | Aug 23 07:23:29 AM UTC 24 |
| Finished | Aug 23 07:37:46 AM UTC 24 |
| Peak memory | 384860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529537295 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during _key_req.1529537295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1614737448 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 14981862 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 07:24:53 AM UTC 24 |
| Finished | Aug 23 07:24:55 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614737448 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.1614737448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.1673391008 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1051269307 ps |
| CPU time | 58.84 seconds |
| Started | Aug 23 07:22:53 AM UTC 24 |
| Finished | Aug 23 07:23:54 AM UTC 24 |
| Peak memory | 213752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673391008 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.1673391008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.1163729899 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 22136472143 ps |
| CPU time | 442.36 seconds |
| Started | Aug 23 07:23:36 AM UTC 24 |
| Finished | Aug 23 07:31:03 AM UTC 24 |
| Peak memory | 380852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163729899 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.1163729899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3419163934 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 517332374 ps |
| CPU time | 1.84 seconds |
| Started | Aug 23 07:23:25 AM UTC 24 |
| Finished | Aug 23 07:23:28 AM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419163934 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.3419163934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1939280323 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 95148245 ps |
| CPU time | 18.82 seconds |
| Started | Aug 23 07:23:16 AM UTC 24 |
| Finished | Aug 23 07:23:35 AM UTC 24 |
| Peak memory | 309360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 939280323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma x_throughput.1939280323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3633463190 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 92460877 ps |
| CPU time | 4.97 seconds |
| Started | Aug 23 07:24:35 AM UTC 24 |
| Finished | Aug 23 07:24:41 AM UTC 24 |
| Peak memory | 224316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633463190 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.3633463190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3441431033 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 349995854 ps |
| CPU time | 5.6 seconds |
| Started | Aug 23 07:24:28 AM UTC 24 |
| Finished | Aug 23 07:24:35 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441431033 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.3441431033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2158613077 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 6459794722 ps |
| CPU time | 224.93 seconds |
| Started | Aug 23 07:22:52 AM UTC 24 |
| Finished | Aug 23 07:26:40 AM UTC 24 |
| Peak memory | 378776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158613077 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.2158613077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1142297805 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 79168768 ps |
| CPU time | 1.79 seconds |
| Started | Aug 23 07:23:09 AM UTC 24 |
| Finished | Aug 23 07:23:12 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142297805 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.1142297805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.77091006 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 48574732872 ps |
| CPU time | 327.75 seconds |
| Started | Aug 23 07:23:13 AM UTC 24 |
| Finished | Aug 23 07:28:44 AM UTC 24 |
| Peak memory | 213892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77091006 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acces s_b2b.77091006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2883149900 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 91591439 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:24:26 AM UTC 24 |
| Finished | Aug 23 07:24:28 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883149900 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2883149900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.3523672569 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 20000075763 ps |
| CPU time | 625.14 seconds |
| Started | Aug 23 07:23:55 AM UTC 24 |
| Finished | Aug 23 07:34:27 AM UTC 24 |
| Peak memory | 382828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523672569 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3523672569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.272332643 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3156474069 ps |
| CPU time | 16.11 seconds |
| Started | Aug 23 07:22:51 AM UTC 24 |
| Finished | Aug 23 07:23:08 AM UTC 24 |
| Peak memory | 213968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272332643 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.272332643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.47893999 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 19924648803 ps |
| CPU time | 739.96 seconds |
| Started | Aug 23 07:24:42 AM UTC 24 |
| Finished | Aug 23 07:37:11 AM UTC 24 |
| Peak memory | 372528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47893999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.47893999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3683620509 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3601497119 ps |
| CPU time | 281.28 seconds |
| Started | Aug 23 07:24:36 AM UTC 24 |
| Finished | Aug 23 07:29:21 AM UTC 24 |
| Peak memory | 391028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683620509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3683620509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.1091839747 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 5918617193 ps |
| CPU time | 275.53 seconds |
| Started | Aug 23 07:22:58 AM UTC 24 |
| Finished | Aug 23 07:27:37 AM UTC 24 |
| Peak memory | 213980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091839747 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.1091839747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.617912702 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 149948695 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 07:23:22 AM UTC 24 |
| Finished | Aug 23 07:23:24 AM UTC 24 |
| Peak memory | 222924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 617912702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_th roughput_w_partial_write.617912702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.4184602334 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 42196123871 ps |
| CPU time | 735.37 seconds |
| Started | Aug 23 07:25:50 AM UTC 24 |
| Finished | Aug 23 07:38:13 AM UTC 24 |
| Peak memory | 385252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184602334 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during _key_req.4184602334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3847014185 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 12882650 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 07:26:43 AM UTC 24 |
| Finished | Aug 23 07:26:45 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847014185 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3847014185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.2679616598 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2150899133 ps |
| CPU time | 20.25 seconds |
| Started | Aug 23 07:25:07 AM UTC 24 |
| Finished | Aug 23 07:25:29 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679616598 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.2679616598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.207658972 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 5618839868 ps |
| CPU time | 120.13 seconds |
| Started | Aug 23 07:25:51 AM UTC 24 |
| Finished | Aug 23 07:27:53 AM UTC 24 |
| Peak memory | 385276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207658972 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.207658972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.803269759 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 739362225 ps |
| CPU time | 5.61 seconds |
| Started | Aug 23 07:25:43 AM UTC 24 |
| Finished | Aug 23 07:25:49 AM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803269759 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.803269759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2972741609 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 114917254 ps |
| CPU time | 30.18 seconds |
| Started | Aug 23 07:25:38 AM UTC 24 |
| Finished | Aug 23 07:26:09 AM UTC 24 |
| Peak memory | 345884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 972741609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ma x_throughput.2972741609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1769553640 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 291635906 ps |
| CPU time | 4.17 seconds |
| Started | Aug 23 07:26:19 AM UTC 24 |
| Finished | Aug 23 07:26:24 AM UTC 24 |
| Peak memory | 224324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769553640 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.1769553640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1361650122 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 188914832 ps |
| CPU time | 5.11 seconds |
| Started | Aug 23 07:26:12 AM UTC 24 |
| Finished | Aug 23 07:26:18 AM UTC 24 |
| Peak memory | 224064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361650122 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.1361650122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2902151015 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 11894706389 ps |
| CPU time | 132.27 seconds |
| Started | Aug 23 07:25:04 AM UTC 24 |
| Finished | Aug 23 07:27:19 AM UTC 24 |
| Peak memory | 362668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902151015 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.2902151015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.531385378 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 111728961 ps |
| CPU time | 11.19 seconds |
| Started | Aug 23 07:25:30 AM UTC 24 |
| Finished | Aug 23 07:25:42 AM UTC 24 |
| Peak memory | 272240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531385378 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.531385378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3339175394 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 33785374991 ps |
| CPU time | 215.59 seconds |
| Started | Aug 23 07:25:32 AM UTC 24 |
| Finished | Aug 23 07:29:10 AM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339175394 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc ess_b2b.3339175394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.4114085141 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 45377497 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 07:26:10 AM UTC 24 |
| Finished | Aug 23 07:26:12 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114085141 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.4114085141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.276114971 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 6835996794 ps |
| CPU time | 336.25 seconds |
| Started | Aug 23 07:26:01 AM UTC 24 |
| Finished | Aug 23 07:31:41 AM UTC 24 |
| Peak memory | 379128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276114971 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.276114971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.3390297575 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 381112451 ps |
| CPU time | 7.44 seconds |
| Started | Aug 23 07:24:55 AM UTC 24 |
| Finished | Aug 23 07:25:04 AM UTC 24 |
| Peak memory | 213828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390297575 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3390297575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.662005538 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4587753224 ps |
| CPU time | 957.29 seconds |
| Started | Aug 23 07:26:40 AM UTC 24 |
| Finished | Aug 23 07:42:46 AM UTC 24 |
| Peak memory | 387084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662005538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.662005538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3741786200 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2285033387 ps |
| CPU time | 161.28 seconds |
| Started | Aug 23 07:26:25 AM UTC 24 |
| Finished | Aug 23 07:29:09 AM UTC 24 |
| Peak memory | 395192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741786200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3741786200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.4182701109 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2204433558 ps |
| CPU time | 190.41 seconds |
| Started | Aug 23 07:25:30 AM UTC 24 |
| Finished | Aug 23 07:28:43 AM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182701109 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.4182701109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1763452379 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 160065401 ps |
| CPU time | 10.69 seconds |
| Started | Aug 23 07:25:39 AM UTC 24 |
| Finished | Aug 23 07:25:51 AM UTC 24 |
| Peak memory | 280420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1763452379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_t hroughput_w_partial_write.1763452379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.157054944 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2751703693 ps |
| CPU time | 506.18 seconds |
| Started | Aug 23 07:27:51 AM UTC 24 |
| Finished | Aug 23 07:36:22 AM UTC 24 |
| Peak memory | 385196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157054944 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during_ key_req.157054944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.2505035465 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 11300228 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:28:44 AM UTC 24 |
| Finished | Aug 23 07:28:45 AM UTC 24 |
| Peak memory | 212816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505035465 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2505035465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.3608245806 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1361279986 ps |
| CPU time | 20.22 seconds |
| Started | Aug 23 07:27:02 AM UTC 24 |
| Finished | Aug 23 07:27:23 AM UTC 24 |
| Peak memory | 214092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608245806 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.3608245806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.4202937445 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 713216940 ps |
| CPU time | 142.03 seconds |
| Started | Aug 23 07:27:54 AM UTC 24 |
| Finished | Aug 23 07:30:18 AM UTC 24 |
| Peak memory | 378740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202937445 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.4202937445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.314438760 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 309577158 ps |
| CPU time | 4.05 seconds |
| Started | Aug 23 07:27:48 AM UTC 24 |
| Finished | Aug 23 07:27:53 AM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314438760 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.314438760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.124557871 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 391648729 ps |
| CPU time | 1.2 seconds |
| Started | Aug 23 07:27:38 AM UTC 24 |
| Finished | Aug 23 07:27:40 AM UTC 24 |
| Peak memory | 222864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 24557871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_max _throughput.124557871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.937485520 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 101169356 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 07:28:13 AM UTC 24 |
| Finished | Aug 23 07:28:17 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937485520 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.937485520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3823638227 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 656372500 ps |
| CPU time | 7.74 seconds |
| Started | Aug 23 07:28:04 AM UTC 24 |
| Finished | Aug 23 07:28:13 AM UTC 24 |
| Peak memory | 224320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823638227 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.3823638227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1928927113 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 4766762745 ps |
| CPU time | 490.49 seconds |
| Started | Aug 23 07:26:50 AM UTC 24 |
| Finished | Aug 23 07:35:06 AM UTC 24 |
| Peak memory | 381104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928927113 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.1928927113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.234726330 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2462178857 ps |
| CPU time | 8.07 seconds |
| Started | Aug 23 07:27:24 AM UTC 24 |
| Finished | Aug 23 07:27:33 AM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234726330 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.234726330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.4193583167 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 69096909863 ps |
| CPU time | 178.5 seconds |
| Started | Aug 23 07:27:34 AM UTC 24 |
| Finished | Aug 23 07:30:35 AM UTC 24 |
| Peak memory | 213916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193583167 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acc ess_b2b.4193583167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2181670545 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 84407530 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 07:28:02 AM UTC 24 |
| Finished | Aug 23 07:28:04 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181670545 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2181670545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.4201052048 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 61922653076 ps |
| CPU time | 772.82 seconds |
| Started | Aug 23 07:27:54 AM UTC 24 |
| Finished | Aug 23 07:40:55 AM UTC 24 |
| Peak memory | 387272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201052048 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.4201052048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.4136884678 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2650251286 ps |
| CPU time | 14.41 seconds |
| Started | Aug 23 07:26:45 AM UTC 24 |
| Finished | Aug 23 07:27:01 AM UTC 24 |
| Peak memory | 214292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136884678 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.4136884678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1650215540 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 127738896650 ps |
| CPU time | 1688.37 seconds |
| Started | Aug 23 07:28:19 AM UTC 24 |
| Finished | Aug 23 07:56:42 AM UTC 24 |
| Peak memory | 388720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165021554 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.1650215540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3214687460 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 10002499339 ps |
| CPU time | 336.51 seconds |
| Started | Aug 23 07:28:15 AM UTC 24 |
| Finished | Aug 23 07:33:56 AM UTC 24 |
| Peak memory | 376820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214687460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3214687460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1995587355 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 6555173912 ps |
| CPU time | 148.88 seconds |
| Started | Aug 23 07:27:20 AM UTC 24 |
| Finished | Aug 23 07:29:51 AM UTC 24 |
| Peak memory | 213988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995587355 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.1995587355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.2046778235 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 80583758 ps |
| CPU time | 8.73 seconds |
| Started | Aug 23 07:27:41 AM UTC 24 |
| Finished | Aug 23 07:27:51 AM UTC 24 |
| Peak memory | 268132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2046778235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_t hroughput_w_partial_write.2046778235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3286696698 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4517224143 ps |
| CPU time | 769.41 seconds |
| Started | Aug 23 07:29:41 AM UTC 24 |
| Finished | Aug 23 07:42:39 AM UTC 24 |
| Peak memory | 386928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286696698 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during _key_req.3286696698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.3881840945 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 22052868 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 07:30:32 AM UTC 24 |
| Finished | Aug 23 07:30:34 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881840945 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3881840945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.1588344037 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 6016553583 ps |
| CPU time | 27.52 seconds |
| Started | Aug 23 07:28:53 AM UTC 24 |
| Finished | Aug 23 07:29:22 AM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588344037 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.1588344037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.2379347440 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 16002746439 ps |
| CPU time | 221.02 seconds |
| Started | Aug 23 07:29:41 AM UTC 24 |
| Finished | Aug 23 07:33:25 AM UTC 24 |
| Peak memory | 378748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379347440 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.2379347440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2941466743 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1161417362 ps |
| CPU time | 10.18 seconds |
| Started | Aug 23 07:29:29 AM UTC 24 |
| Finished | Aug 23 07:29:40 AM UTC 24 |
| Peak memory | 226216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941466743 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.2941466743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3850834362 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 122994283 ps |
| CPU time | 44.88 seconds |
| Started | Aug 23 07:29:21 AM UTC 24 |
| Finished | Aug 23 07:30:07 AM UTC 24 |
| Peak memory | 352116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 850834362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ma x_throughput.3850834362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2423689902 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 183088778 ps |
| CPU time | 4.94 seconds |
| Started | Aug 23 07:30:19 AM UTC 24 |
| Finished | Aug 23 07:30:25 AM UTC 24 |
| Peak memory | 224340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423689902 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.2423689902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.4291730997 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 786906833 ps |
| CPU time | 9.32 seconds |
| Started | Aug 23 07:30:10 AM UTC 24 |
| Finished | Aug 23 07:30:20 AM UTC 24 |
| Peak memory | 224324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291730997 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.4291730997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.530887984 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 80715476117 ps |
| CPU time | 330.72 seconds |
| Started | Aug 23 07:28:46 AM UTC 24 |
| Finished | Aug 23 07:34:20 AM UTC 24 |
| Peak memory | 380840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530887984 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.530887984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.3472581397 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 149026558 ps |
| CPU time | 6.53 seconds |
| Started | Aug 23 07:29:11 AM UTC 24 |
| Finished | Aug 23 07:29:18 AM UTC 24 |
| Peak memory | 245564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472581397 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.3472581397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.4104381485 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 15992113133 ps |
| CPU time | 376.85 seconds |
| Started | Aug 23 07:29:19 AM UTC 24 |
| Finished | Aug 23 07:35:40 AM UTC 24 |
| Peak memory | 213996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104381485 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acc ess_b2b.4104381485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1526047286 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 48511533 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 07:30:08 AM UTC 24 |
| Finished | Aug 23 07:30:09 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526047286 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1526047286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.4216486292 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 5019828322 ps |
| CPU time | 600.33 seconds |
| Started | Aug 23 07:29:52 AM UTC 24 |
| Finished | Aug 23 07:39:58 AM UTC 24 |
| Peak memory | 382852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216486292 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.4216486292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.2129032663 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 126999946 ps |
| CPU time | 6.63 seconds |
| Started | Aug 23 07:28:45 AM UTC 24 |
| Finished | Aug 23 07:28:52 AM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129032663 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2129032663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.274141292 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 107012345302 ps |
| CPU time | 1401.36 seconds |
| Started | Aug 23 07:30:26 AM UTC 24 |
| Finished | Aug 23 07:54:01 AM UTC 24 |
| Peak memory | 388668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274141292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.274141292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1918491612 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 606543911 ps |
| CPU time | 9.45 seconds |
| Started | Aug 23 07:30:21 AM UTC 24 |
| Finished | Aug 23 07:30:31 AM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918491612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1918491612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.2906631681 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 3525818994 ps |
| CPU time | 282.58 seconds |
| Started | Aug 23 07:29:10 AM UTC 24 |
| Finished | Aug 23 07:33:56 AM UTC 24 |
| Peak memory | 214112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906631681 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.2906631681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.73958366 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 634116837 ps |
| CPU time | 5.3 seconds |
| Started | Aug 23 07:29:22 AM UTC 24 |
| Finished | Aug 23 07:29:28 AM UTC 24 |
| Peak memory | 247912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 73958366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_thr oughput_w_partial_write.73958366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.200187734 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5404894590 ps |
| CPU time | 573.23 seconds |
| Started | Aug 23 07:31:15 AM UTC 24 |
| Finished | Aug 23 07:40:54 AM UTC 24 |
| Peak memory | 385260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200187734 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during_ key_req.200187734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3924970858 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 88078763 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 07:33:27 AM UTC 24 |
| Finished | Aug 23 07:33:28 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924970858 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3924970858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.3916576282 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 6715493793 ps |
| CPU time | 36.71 seconds |
| Started | Aug 23 07:30:36 AM UTC 24 |
| Finished | Aug 23 07:31:14 AM UTC 24 |
| Peak memory | 214004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916576282 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.3916576282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.4025442081 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 7000777876 ps |
| CPU time | 234.48 seconds |
| Started | Aug 23 07:31:20 AM UTC 24 |
| Finished | Aug 23 07:35:17 AM UTC 24 |
| Peak memory | 379012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025442081 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.4025442081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1454204441 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1472478157 ps |
| CPU time | 4.41 seconds |
| Started | Aug 23 07:31:14 AM UTC 24 |
| Finished | Aug 23 07:31:19 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454204441 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.1454204441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1019766553 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 262186885 ps |
| CPU time | 60.07 seconds |
| Started | Aug 23 07:30:58 AM UTC 24 |
| Finished | Aug 23 07:32:00 AM UTC 24 |
| Peak memory | 376688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 019766553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ma x_throughput.1019766553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.759027141 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 97329688 ps |
| CPU time | 5 seconds |
| Started | Aug 23 07:31:56 AM UTC 24 |
| Finished | Aug 23 07:32:02 AM UTC 24 |
| Peak memory | 224324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759027141 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.759027141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.3222580721 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 490357285 ps |
| CPU time | 9.85 seconds |
| Started | Aug 23 07:31:44 AM UTC 24 |
| Finished | Aug 23 07:31:55 AM UTC 24 |
| Peak memory | 224312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222580721 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.3222580721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2597307131 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 11546234541 ps |
| CPU time | 291.48 seconds |
| Started | Aug 23 07:30:35 AM UTC 24 |
| Finished | Aug 23 07:35:30 AM UTC 24 |
| Peak memory | 380792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597307131 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.2597307131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3065023204 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1745788864 ps |
| CPU time | 15.99 seconds |
| Started | Aug 23 07:30:40 AM UTC 24 |
| Finished | Aug 23 07:30:57 AM UTC 24 |
| Peak memory | 284456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065023204 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.3065023204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1737886884 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 18854712653 ps |
| CPU time | 326.03 seconds |
| Started | Aug 23 07:30:47 AM UTC 24 |
| Finished | Aug 23 07:36:18 AM UTC 24 |
| Peak memory | 213944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737886884 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acc ess_b2b.1737886884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1566600991 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 29274256 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:31:42 AM UTC 24 |
| Finished | Aug 23 07:31:44 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566600991 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1566600991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.3261866332 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2557147617 ps |
| CPU time | 270.86 seconds |
| Started | Aug 23 07:31:21 AM UTC 24 |
| Finished | Aug 23 07:35:55 AM UTC 24 |
| Peak memory | 382848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261866332 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3261866332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.1584395622 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 571214372 ps |
| CPU time | 36.21 seconds |
| Started | Aug 23 07:30:35 AM UTC 24 |
| Finished | Aug 23 07:31:12 AM UTC 24 |
| Peak memory | 345988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584395622 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1584395622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.404220282 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 30956587299 ps |
| CPU time | 778.18 seconds |
| Started | Aug 23 07:32:03 AM UTC 24 |
| Finished | Aug 23 07:45:10 AM UTC 24 |
| Peak memory | 384896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404220282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.404220282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1499507467 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 8382487104 ps |
| CPU time | 565.82 seconds |
| Started | Aug 23 07:32:01 AM UTC 24 |
| Finished | Aug 23 07:41:33 AM UTC 24 |
| Peak memory | 397224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499507467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1499507467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.3720733335 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 14294817107 ps |
| CPU time | 208.17 seconds |
| Started | Aug 23 07:30:37 AM UTC 24 |
| Finished | Aug 23 07:34:08 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720733335 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.3720733335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4184300176 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 185847823 ps |
| CPU time | 14.85 seconds |
| Started | Aug 23 07:31:04 AM UTC 24 |
| Finished | Aug 23 07:31:19 AM UTC 24 |
| Peak memory | 297056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4184300176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_t hroughput_w_partial_write.4184300176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3107549367 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 678468582 ps |
| CPU time | 245.83 seconds |
| Started | Aug 23 07:34:35 AM UTC 24 |
| Finished | Aug 23 07:38:44 AM UTC 24 |
| Peak memory | 372836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107549367 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during _key_req.3107549367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3956934757 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 26414452 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 07:35:18 AM UTC 24 |
| Finished | Aug 23 07:35:19 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956934757 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3956934757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.505449503 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 634594537 ps |
| CPU time | 36.43 seconds |
| Started | Aug 23 07:33:57 AM UTC 24 |
| Finished | Aug 23 07:34:35 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505449503 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.505449503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.1180979497 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5385208224 ps |
| CPU time | 175.29 seconds |
| Started | Aug 23 07:34:35 AM UTC 24 |
| Finished | Aug 23 07:37:33 AM UTC 24 |
| Peak memory | 378732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180979497 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.1180979497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1160254470 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1067337742 ps |
| CPU time | 3.57 seconds |
| Started | Aug 23 07:34:34 AM UTC 24 |
| Finished | Aug 23 07:34:39 AM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160254470 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.1160254470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.4074145394 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 1217026452 ps |
| CPU time | 34.39 seconds |
| Started | Aug 23 07:34:21 AM UTC 24 |
| Finished | Aug 23 07:34:57 AM UTC 24 |
| Peak memory | 352032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 074145394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ma x_throughput.4074145394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.4117713328 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 683669500 ps |
| CPU time | 5.51 seconds |
| Started | Aug 23 07:35:06 AM UTC 24 |
| Finished | Aug 23 07:35:13 AM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117713328 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.4117713328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.1134157676 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 335407982 ps |
| CPU time | 5.58 seconds |
| Started | Aug 23 07:34:59 AM UTC 24 |
| Finished | Aug 23 07:35:06 AM UTC 24 |
| Peak memory | 224396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134157676 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.1134157676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1648790871 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 21121992080 ps |
| CPU time | 408.46 seconds |
| Started | Aug 23 07:33:57 AM UTC 24 |
| Finished | Aug 23 07:40:50 AM UTC 24 |
| Peak memory | 380844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648790871 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.1648790871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1944638774 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 507278971 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 07:34:09 AM UTC 24 |
| Finished | Aug 23 07:34:13 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944638774 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.1944638774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3456617810 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 6286661640 ps |
| CPU time | 394.86 seconds |
| Started | Aug 23 07:34:14 AM UTC 24 |
| Finished | Aug 23 07:40:53 AM UTC 24 |
| Peak memory | 213968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456617810 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acc ess_b2b.3456617810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.960611592 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 46886309 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 07:34:57 AM UTC 24 |
| Finished | Aug 23 07:34:59 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960611592 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.960611592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.2337412841 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 24611209890 ps |
| CPU time | 255.92 seconds |
| Started | Aug 23 07:34:39 AM UTC 24 |
| Finished | Aug 23 07:38:58 AM UTC 24 |
| Peak memory | 360304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337412841 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2337412841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.814861874 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 522921745 ps |
| CPU time | 26.58 seconds |
| Started | Aug 23 07:33:29 AM UTC 24 |
| Finished | Aug 23 07:33:56 AM UTC 24 |
| Peak memory | 323636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814861874 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.814861874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.677573145 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3453967765 ps |
| CPU time | 504.71 seconds |
| Started | Aug 23 07:35:14 AM UTC 24 |
| Finished | Aug 23 07:43:44 AM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677573145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.677573145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1026248489 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 8115399453 ps |
| CPU time | 47.92 seconds |
| Started | Aug 23 07:35:08 AM UTC 24 |
| Finished | Aug 23 07:35:57 AM UTC 24 |
| Peak memory | 231320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026248489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1026248489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2750819077 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 13055143514 ps |
| CPU time | 302.61 seconds |
| Started | Aug 23 07:33:57 AM UTC 24 |
| Finished | Aug 23 07:39:03 AM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750819077 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.2750819077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2637637949 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 213870085 ps |
| CPU time | 5.67 seconds |
| Started | Aug 23 07:34:27 AM UTC 24 |
| Finished | Aug 23 07:34:34 AM UTC 24 |
| Peak memory | 249624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2637637949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_t hroughput_w_partial_write.2637637949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3879190175 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 10120088387 ps |
| CPU time | 253.54 seconds |
| Started | Aug 23 07:36:23 AM UTC 24 |
| Finished | Aug 23 07:40:40 AM UTC 24 |
| Peak memory | 364692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879190175 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during _key_req.3879190175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3540347583 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 15718279 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 07:37:34 AM UTC 24 |
| Finished | Aug 23 07:37:35 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540347583 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3540347583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.2254186832 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3048257752 ps |
| CPU time | 28.71 seconds |
| Started | Aug 23 07:35:38 AM UTC 24 |
| Finished | Aug 23 07:36:08 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254186832 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.2254186832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.455412194 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 10941041365 ps |
| CPU time | 433.82 seconds |
| Started | Aug 23 07:36:31 AM UTC 24 |
| Finished | Aug 23 07:43:50 AM UTC 24 |
| Peak memory | 385156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455412194 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.455412194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2933221053 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 796830960 ps |
| CPU time | 6.46 seconds |
| Started | Aug 23 07:36:23 AM UTC 24 |
| Finished | Aug 23 07:36:31 AM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933221053 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2933221053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.467143201 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 486062584 ps |
| CPU time | 44.93 seconds |
| Started | Aug 23 07:36:08 AM UTC 24 |
| Finished | Aug 23 07:36:54 AM UTC 24 |
| Peak memory | 370808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 67143201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_max _throughput.467143201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2069225408 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 598099889 ps |
| CPU time | 5.05 seconds |
| Started | Aug 23 07:37:04 AM UTC 24 |
| Finished | Aug 23 07:37:10 AM UTC 24 |
| Peak memory | 224084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069225408 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.2069225408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3948554334 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 235581289 ps |
| CPU time | 4.8 seconds |
| Started | Aug 23 07:36:58 AM UTC 24 |
| Finished | Aug 23 07:37:03 AM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948554334 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.3948554334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1384950761 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2825504946 ps |
| CPU time | 425.46 seconds |
| Started | Aug 23 07:35:31 AM UTC 24 |
| Finished | Aug 23 07:42:41 AM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384950761 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.1384950761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2403676666 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 611554225 ps |
| CPU time | 51.21 seconds |
| Started | Aug 23 07:35:56 AM UTC 24 |
| Finished | Aug 23 07:36:49 AM UTC 24 |
| Peak memory | 366452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403676666 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.2403676666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1125026597 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 46425115158 ps |
| CPU time | 276.09 seconds |
| Started | Aug 23 07:35:58 AM UTC 24 |
| Finished | Aug 23 07:40:38 AM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125026597 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acc ess_b2b.1125026597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3710094993 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 42422495 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 07:36:55 AM UTC 24 |
| Finished | Aug 23 07:36:57 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710094993 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3710094993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.103690878 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 14904406907 ps |
| CPU time | 324.05 seconds |
| Started | Aug 23 07:36:49 AM UTC 24 |
| Finished | Aug 23 07:42:18 AM UTC 24 |
| Peak memory | 378732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103690878 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.103690878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.4264104068 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4405979493 ps |
| CPU time | 16.52 seconds |
| Started | Aug 23 07:35:20 AM UTC 24 |
| Finished | Aug 23 07:35:37 AM UTC 24 |
| Peak memory | 213864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264104068 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.4264104068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3092068016 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 164102303232 ps |
| CPU time | 2188.59 seconds |
| Started | Aug 23 07:37:12 AM UTC 24 |
| Finished | Aug 23 08:14:02 AM UTC 24 |
| Peak memory | 388716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309206801 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.3092068016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1959619112 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 12771523346 ps |
| CPU time | 148.47 seconds |
| Started | Aug 23 07:37:11 AM UTC 24 |
| Finished | Aug 23 07:39:41 AM UTC 24 |
| Peak memory | 375028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959619112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1959619112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.604745319 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2041741089 ps |
| CPU time | 183.91 seconds |
| Started | Aug 23 07:35:41 AM UTC 24 |
| Finished | Aug 23 07:38:48 AM UTC 24 |
| Peak memory | 214148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604745319 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.604745319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.4174867710 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 719605229 ps |
| CPU time | 3.02 seconds |
| Started | Aug 23 07:36:18 AM UTC 24 |
| Finished | Aug 23 07:36:22 AM UTC 24 |
| Peak memory | 231264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4174867710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_t hroughput_w_partial_write.4174867710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1200737484 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 32232285117 ps |
| CPU time | 358.25 seconds |
| Started | Aug 23 06:20:34 AM UTC 24 |
| Finished | Aug 23 06:26:36 AM UTC 24 |
| Peak memory | 382800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200737484 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_ key_req.1200737484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.358177546 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 12701992 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 06:21:26 AM UTC 24 |
| Finished | Aug 23 06:21:27 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358177546 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.358177546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.553488443 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 965811154 ps |
| CPU time | 16.52 seconds |
| Started | Aug 23 06:19:41 AM UTC 24 |
| Finished | Aug 23 06:19:59 AM UTC 24 |
| Peak memory | 213928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553488443 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.553488443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.3039297675 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1795746511 ps |
| CPU time | 35.44 seconds |
| Started | Aug 23 06:20:37 AM UTC 24 |
| Finished | Aug 23 06:21:14 AM UTC 24 |
| Peak memory | 270144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039297675 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.3039297675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.190274810 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 444684064 ps |
| CPU time | 3.86 seconds |
| Started | Aug 23 06:20:32 AM UTC 24 |
| Finished | Aug 23 06:20:37 AM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190274810 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.190274810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.2048003963 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 423752731 ps |
| CPU time | 33.4 seconds |
| Started | Aug 23 06:19:59 AM UTC 24 |
| Finished | Aug 23 06:20:33 AM UTC 24 |
| Peak memory | 333608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 048003963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max _throughput.2048003963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1022385920 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 353842903 ps |
| CPU time | 4.53 seconds |
| Started | Aug 23 06:21:15 AM UTC 24 |
| Finished | Aug 23 06:21:21 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022385920 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.1022385920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3135940877 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 334827062 ps |
| CPU time | 5.78 seconds |
| Started | Aug 23 06:21:14 AM UTC 24 |
| Finished | Aug 23 06:21:21 AM UTC 24 |
| Peak memory | 224072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135940877 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.3135940877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.4047978586 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 9445322789 ps |
| CPU time | 300.4 seconds |
| Started | Aug 23 06:19:41 AM UTC 24 |
| Finished | Aug 23 06:24:45 AM UTC 24 |
| Peak memory | 384820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047978586 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.4047978586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1797045894 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 107668402 ps |
| CPU time | 14.97 seconds |
| Started | Aug 23 06:19:42 AM UTC 24 |
| Finished | Aug 23 06:19:58 AM UTC 24 |
| Peak memory | 284528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797045894 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.1797045894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.1509453721 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 28904896267 ps |
| CPU time | 355.95 seconds |
| Started | Aug 23 06:19:49 AM UTC 24 |
| Finished | Aug 23 06:25:49 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509453721 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acce ss_b2b.1509453721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.302706290 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 37434125 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 06:21:13 AM UTC 24 |
| Finished | Aug 23 06:21:15 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302706290 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.302706290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.1261822724 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 10650207019 ps |
| CPU time | 617.98 seconds |
| Started | Aug 23 06:20:44 AM UTC 24 |
| Finished | Aug 23 06:31:08 AM UTC 24 |
| Peak memory | 386996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261822724 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1261822724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.813845472 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 340526159 ps |
| CPU time | 1.62 seconds |
| Started | Aug 23 06:21:22 AM UTC 24 |
| Finished | Aug 23 06:21:25 AM UTC 24 |
| Peak memory | 248256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813845472 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.813845472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.31193892 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 272983896 ps |
| CPU time | 7.34 seconds |
| Started | Aug 23 06:19:39 AM UTC 24 |
| Finished | Aug 23 06:19:48 AM UTC 24 |
| Peak memory | 213776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31193892 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.31193892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1541001166 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2120172509 ps |
| CPU time | 114.62 seconds |
| Started | Aug 23 06:21:16 AM UTC 24 |
| Finished | Aug 23 06:23:13 AM UTC 24 |
| Peak memory | 395188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541001166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1541001166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.453257157 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 4238645686 ps |
| CPU time | 367.93 seconds |
| Started | Aug 23 06:19:42 AM UTC 24 |
| Finished | Aug 23 06:25:54 AM UTC 24 |
| Peak memory | 213856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453257157 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.453257157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.2530283014 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 459741844 ps |
| CPU time | 30.12 seconds |
| Started | Aug 23 06:20:00 AM UTC 24 |
| Finished | Aug 23 06:20:31 AM UTC 24 |
| Peak memory | 335968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2530283014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th roughput_w_partial_write.2530283014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.4223030374 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1178580652 ps |
| CPU time | 55.17 seconds |
| Started | Aug 23 07:39:22 AM UTC 24 |
| Finished | Aug 23 07:40:18 AM UTC 24 |
| Peak memory | 321640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223030374 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during _key_req.4223030374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3887344415 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 30702083 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 07:39:59 AM UTC 24 |
| Finished | Aug 23 07:40:01 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887344415 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.3887344415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.1413951237 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3978537380 ps |
| CPU time | 57.78 seconds |
| Started | Aug 23 07:38:13 AM UTC 24 |
| Finished | Aug 23 07:39:12 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413951237 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.1413951237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3282992533 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 3641666628 ps |
| CPU time | 283.54 seconds |
| Started | Aug 23 07:39:31 AM UTC 24 |
| Finished | Aug 23 07:44:18 AM UTC 24 |
| Peak memory | 376760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282992533 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.3282992533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3906905407 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1282604731 ps |
| CPU time | 5.96 seconds |
| Started | Aug 23 07:39:14 AM UTC 24 |
| Finished | Aug 23 07:39:21 AM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906905407 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.3906905407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3129337170 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 258880518 ps |
| CPU time | 51.11 seconds |
| Started | Aug 23 07:38:59 AM UTC 24 |
| Finished | Aug 23 07:39:52 AM UTC 24 |
| Peak memory | 383088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 129337170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ma x_throughput.3129337170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.3924004186 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 146660259 ps |
| CPU time | 3.97 seconds |
| Started | Aug 23 07:39:53 AM UTC 24 |
| Finished | Aug 23 07:39:58 AM UTC 24 |
| Peak memory | 224068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924004186 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.3924004186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.571699299 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1822440408 ps |
| CPU time | 9.4 seconds |
| Started | Aug 23 07:39:44 AM UTC 24 |
| Finished | Aug 23 07:39:54 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571699299 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.571699299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.529714478 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 12936587314 ps |
| CPU time | 146.85 seconds |
| Started | Aug 23 07:37:47 AM UTC 24 |
| Finished | Aug 23 07:40:16 AM UTC 24 |
| Peak memory | 348000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529714478 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.529714478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3076456105 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 627713464 ps |
| CPU time | 42.96 seconds |
| Started | Aug 23 07:38:45 AM UTC 24 |
| Finished | Aug 23 07:39:30 AM UTC 24 |
| Peak memory | 358256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076456105 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.3076456105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.4109009059 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 34436856726 ps |
| CPU time | 369.96 seconds |
| Started | Aug 23 07:38:48 AM UTC 24 |
| Finished | Aug 23 07:45:03 AM UTC 24 |
| Peak memory | 214204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109009059 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acc ess_b2b.4109009059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3093706814 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 62889580 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 07:39:42 AM UTC 24 |
| Finished | Aug 23 07:39:43 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093706814 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3093706814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.3631422600 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 9236859972 ps |
| CPU time | 554.66 seconds |
| Started | Aug 23 07:39:39 AM UTC 24 |
| Finished | Aug 23 07:48:59 AM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631422600 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3631422600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3373622247 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 145161034 ps |
| CPU time | 52.84 seconds |
| Started | Aug 23 07:37:36 AM UTC 24 |
| Finished | Aug 23 07:38:30 AM UTC 24 |
| Peak memory | 376692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373622247 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3373622247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.148087627 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 7945425625 ps |
| CPU time | 739.02 seconds |
| Started | Aug 23 07:39:59 AM UTC 24 |
| Finished | Aug 23 07:52:26 AM UTC 24 |
| Peak memory | 382936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148087627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.148087627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1320424045 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 6784543956 ps |
| CPU time | 61.85 seconds |
| Started | Aug 23 07:39:55 AM UTC 24 |
| Finished | Aug 23 07:40:58 AM UTC 24 |
| Peak memory | 362412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320424045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1320424045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1563538776 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4863288693 ps |
| CPU time | 219.36 seconds |
| Started | Aug 23 07:38:31 AM UTC 24 |
| Finished | Aug 23 07:42:14 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563538776 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.1563538776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.4242334293 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 126913572 ps |
| CPU time | 32.29 seconds |
| Started | Aug 23 07:39:04 AM UTC 24 |
| Finished | Aug 23 07:39:38 AM UTC 24 |
| Peak memory | 335976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4242334293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_t hroughput_w_partial_write.4242334293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.930102564 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2886944611 ps |
| CPU time | 336.86 seconds |
| Started | Aug 23 07:40:54 AM UTC 24 |
| Finished | Aug 23 07:46:34 AM UTC 24 |
| Peak memory | 382820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930102564 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during_ key_req.930102564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.1149594766 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 23363804 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:41:06 AM UTC 24 |
| Finished | Aug 23 07:41:08 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149594766 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.1149594766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.1781801721 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1158053518 ps |
| CPU time | 16.16 seconds |
| Started | Aug 23 07:40:18 AM UTC 24 |
| Finished | Aug 23 07:40:36 AM UTC 24 |
| Peak memory | 213812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781801721 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.1781801721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.3134192248 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 14818819160 ps |
| CPU time | 153.02 seconds |
| Started | Aug 23 07:40:55 AM UTC 24 |
| Finished | Aug 23 07:43:30 AM UTC 24 |
| Peak memory | 360376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134192248 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.3134192248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2567559917 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 432743112 ps |
| CPU time | 5.66 seconds |
| Started | Aug 23 07:40:51 AM UTC 24 |
| Finished | Aug 23 07:40:58 AM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567559917 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.2567559917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.857116973 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1257810593 ps |
| CPU time | 23.42 seconds |
| Started | Aug 23 07:40:41 AM UTC 24 |
| Finished | Aug 23 07:41:05 AM UTC 24 |
| Peak memory | 333672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 57116973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_max _throughput.857116973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.4089532995 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 94214156 ps |
| CPU time | 4.3 seconds |
| Started | Aug 23 07:41:00 AM UTC 24 |
| Finished | Aug 23 07:41:05 AM UTC 24 |
| Peak memory | 224356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089532995 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.4089532995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.425048951 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1391456570 ps |
| CPU time | 6.19 seconds |
| Started | Aug 23 07:40:59 AM UTC 24 |
| Finished | Aug 23 07:41:06 AM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425048951 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.425048951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.530300353 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 9018550605 ps |
| CPU time | 46.6 seconds |
| Started | Aug 23 07:40:17 AM UTC 24 |
| Finished | Aug 23 07:41:05 AM UTC 24 |
| Peak memory | 282536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530300353 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.530300353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3083985206 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 458115534 ps |
| CPU time | 4.65 seconds |
| Started | Aug 23 07:40:36 AM UTC 24 |
| Finished | Aug 23 07:40:42 AM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083985206 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.3083985206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2294409964 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 13113591853 ps |
| CPU time | 289.8 seconds |
| Started | Aug 23 07:40:38 AM UTC 24 |
| Finished | Aug 23 07:45:32 AM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294409964 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acc ess_b2b.2294409964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.4217290115 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 26908779 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 07:40:58 AM UTC 24 |
| Finished | Aug 23 07:41:00 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217290115 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.4217290115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.3114064310 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 71323786594 ps |
| CPU time | 164.24 seconds |
| Started | Aug 23 07:40:56 AM UTC 24 |
| Finished | Aug 23 07:43:42 AM UTC 24 |
| Peak memory | 342012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114064310 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3114064310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.1852554618 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1029056047 ps |
| CPU time | 15.19 seconds |
| Started | Aug 23 07:40:01 AM UTC 24 |
| Finished | Aug 23 07:40:17 AM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852554618 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1852554618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.4052660843 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 92503045814 ps |
| CPU time | 1317.57 seconds |
| Started | Aug 23 07:41:06 AM UTC 24 |
| Finished | Aug 23 08:03:17 AM UTC 24 |
| Peak memory | 388788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405266084 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.4052660843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1365757171 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2283134323 ps |
| CPU time | 154.67 seconds |
| Started | Aug 23 07:41:05 AM UTC 24 |
| Finished | Aug 23 07:43:42 AM UTC 24 |
| Peak memory | 387316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365757171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1365757171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2161332118 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3790113968 ps |
| CPU time | 120.16 seconds |
| Started | Aug 23 07:40:19 AM UTC 24 |
| Finished | Aug 23 07:42:22 AM UTC 24 |
| Peak memory | 214164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161332118 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.2161332118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4209950236 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 970493666 ps |
| CPU time | 20.69 seconds |
| Started | Aug 23 07:40:43 AM UTC 24 |
| Finished | Aug 23 07:41:04 AM UTC 24 |
| Peak memory | 307044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4209950236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t hroughput_w_partial_write.4209950236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3630162317 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2855684940 ps |
| CPU time | 65.12 seconds |
| Started | Aug 23 07:42:23 AM UTC 24 |
| Finished | Aug 23 07:43:30 AM UTC 24 |
| Peak memory | 323424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630162317 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during _key_req.3630162317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.169270944 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 35655904 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 07:42:47 AM UTC 24 |
| Finished | Aug 23 07:42:49 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169270944 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.169270944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.1233224095 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 10225201968 ps |
| CPU time | 69.69 seconds |
| Started | Aug 23 07:41:08 AM UTC 24 |
| Finished | Aug 23 07:42:20 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233224095 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.1233224095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.990451096 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 12222220720 ps |
| CPU time | 378.13 seconds |
| Started | Aug 23 07:42:27 AM UTC 24 |
| Finished | Aug 23 07:48:49 AM UTC 24 |
| Peak memory | 358256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990451096 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.990451096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.769574682 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 704316516 ps |
| CPU time | 6.42 seconds |
| Started | Aug 23 07:42:21 AM UTC 24 |
| Finished | Aug 23 07:42:28 AM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769574682 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.769574682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.206071392 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 76670640 ps |
| CPU time | 9.86 seconds |
| Started | Aug 23 07:42:15 AM UTC 24 |
| Finished | Aug 23 07:42:26 AM UTC 24 |
| Peak memory | 280552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 06071392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_max _throughput.206071392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.2435349609 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 240780724 ps |
| CPU time | 4.07 seconds |
| Started | Aug 23 07:42:41 AM UTC 24 |
| Finished | Aug 23 07:42:46 AM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435349609 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.2435349609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2024512675 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 308927886 ps |
| CPU time | 4.92 seconds |
| Started | Aug 23 07:42:41 AM UTC 24 |
| Finished | Aug 23 07:42:47 AM UTC 24 |
| Peak memory | 224324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024512675 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.2024512675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2656757765 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 16506480012 ps |
| CPU time | 620.43 seconds |
| Started | Aug 23 07:41:07 AM UTC 24 |
| Finished | Aug 23 07:51:34 AM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656757765 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.2656757765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2337138225 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5165026130 ps |
| CPU time | 23.67 seconds |
| Started | Aug 23 07:41:33 AM UTC 24 |
| Finished | Aug 23 07:41:58 AM UTC 24 |
| Peak memory | 295156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337138225 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.2337138225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1036358316 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 4842465231 ps |
| CPU time | 351.14 seconds |
| Started | Aug 23 07:42:00 AM UTC 24 |
| Finished | Aug 23 07:47:56 AM UTC 24 |
| Peak memory | 213948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036358316 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acc ess_b2b.1036358316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1835565015 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 45835119 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 07:42:39 AM UTC 24 |
| Finished | Aug 23 07:42:41 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835565015 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1835565015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.3267061044 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 2896947810 ps |
| CPU time | 106.52 seconds |
| Started | Aug 23 07:42:29 AM UTC 24 |
| Finished | Aug 23 07:44:17 AM UTC 24 |
| Peak memory | 360272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267061044 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3267061044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.4176699544 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 4447940271 ps |
| CPU time | 16.31 seconds |
| Started | Aug 23 07:41:06 AM UTC 24 |
| Finished | Aug 23 07:41:24 AM UTC 24 |
| Peak memory | 296788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176699544 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.4176699544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3712361920 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 14535247404 ps |
| CPU time | 1608.88 seconds |
| Started | Aug 23 07:42:47 AM UTC 24 |
| Finished | Aug 23 08:09:53 AM UTC 24 |
| Peak memory | 386660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371236192 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.3712361920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.352924476 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3927098004 ps |
| CPU time | 80.18 seconds |
| Started | Aug 23 07:42:47 AM UTC 24 |
| Finished | Aug 23 07:44:09 AM UTC 24 |
| Peak memory | 300976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352924476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.352924476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.561493908 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 7960537992 ps |
| CPU time | 170.94 seconds |
| Started | Aug 23 07:41:24 AM UTC 24 |
| Finished | Aug 23 07:44:18 AM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561493908 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.561493908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1685685183 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 474664805 ps |
| CPU time | 26.29 seconds |
| Started | Aug 23 07:42:19 AM UTC 24 |
| Finished | Aug 23 07:42:46 AM UTC 24 |
| Peak memory | 329832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1685685183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t hroughput_w_partial_write.1685685183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3756102492 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 11413541988 ps |
| CPU time | 423.42 seconds |
| Started | Aug 23 07:43:53 AM UTC 24 |
| Finished | Aug 23 07:51:01 AM UTC 24 |
| Peak memory | 382884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756102492 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during _key_req.3756102492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2541878450 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 29086699 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 07:44:18 AM UTC 24 |
| Finished | Aug 23 07:44:20 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541878450 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2541878450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.3001650050 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 6764569747 ps |
| CPU time | 47.89 seconds |
| Started | Aug 23 07:43:05 AM UTC 24 |
| Finished | Aug 23 07:43:55 AM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001650050 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.3001650050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.1010520267 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 16009351032 ps |
| CPU time | 655.39 seconds |
| Started | Aug 23 07:43:54 AM UTC 24 |
| Finished | Aug 23 07:54:56 AM UTC 24 |
| Peak memory | 386700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010520267 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.1010520267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.4269344149 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 111030218 ps |
| CPU time | 1.7 seconds |
| Started | Aug 23 07:43:51 AM UTC 24 |
| Finished | Aug 23 07:43:54 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269344149 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.4269344149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1417282571 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 452632183 ps |
| CPU time | 37.12 seconds |
| Started | Aug 23 07:43:44 AM UTC 24 |
| Finished | Aug 23 07:44:22 AM UTC 24 |
| Peak memory | 360304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 417282571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ma x_throughput.1417282571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2311924678 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 113491964 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 07:44:09 AM UTC 24 |
| Finished | Aug 23 07:44:13 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311924678 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.2311924678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.2343494380 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 186564114 ps |
| CPU time | 8.87 seconds |
| Started | Aug 23 07:43:58 AM UTC 24 |
| Finished | Aug 23 07:44:08 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343494380 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.2343494380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1518348028 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 4898268662 ps |
| CPU time | 860.6 seconds |
| Started | Aug 23 07:42:49 AM UTC 24 |
| Finished | Aug 23 07:57:18 AM UTC 24 |
| Peak memory | 384940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518348028 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.1518348028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.4201753845 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 712796905 ps |
| CPU time | 20.15 seconds |
| Started | Aug 23 07:43:31 AM UTC 24 |
| Finished | Aug 23 07:43:52 AM UTC 24 |
| Peak memory | 296948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201753845 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.4201753845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1968278218 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 37945597512 ps |
| CPU time | 409.53 seconds |
| Started | Aug 23 07:43:43 AM UTC 24 |
| Finished | Aug 23 07:50:37 AM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968278218 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acc ess_b2b.1968278218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3424018874 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 32172261 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:43:55 AM UTC 24 |
| Finished | Aug 23 07:43:57 AM UTC 24 |
| Peak memory | 212536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424018874 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3424018874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.1352041722 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 36247375979 ps |
| CPU time | 717.65 seconds |
| Started | Aug 23 07:43:54 AM UTC 24 |
| Finished | Aug 23 07:55:59 AM UTC 24 |
| Peak memory | 387256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352041722 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1352041722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.130741525 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 377238841 ps |
| CPU time | 15.45 seconds |
| Started | Aug 23 07:42:48 AM UTC 24 |
| Finished | Aug 23 07:43:05 AM UTC 24 |
| Peak memory | 288624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130741525 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.130741525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.246965132 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5609817668 ps |
| CPU time | 154.64 seconds |
| Started | Aug 23 07:44:14 AM UTC 24 |
| Finished | Aug 23 07:46:51 AM UTC 24 |
| Peak memory | 360688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246965132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.246965132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2683615200 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 3120172734 ps |
| CPU time | 32.94 seconds |
| Started | Aug 23 07:44:10 AM UTC 24 |
| Finished | Aug 23 07:44:44 AM UTC 24 |
| Peak memory | 307260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683615200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.2683615200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.838012711 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4864689261 ps |
| CPU time | 214.75 seconds |
| Started | Aug 23 07:43:31 AM UTC 24 |
| Finished | Aug 23 07:47:08 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838012711 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.838012711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3088341156 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 149747610 ps |
| CPU time | 57.84 seconds |
| Started | Aug 23 07:43:45 AM UTC 24 |
| Finished | Aug 23 07:44:44 AM UTC 24 |
| Peak memory | 381028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3088341156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_t hroughput_w_partial_write.3088341156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1654442261 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1884642674 ps |
| CPU time | 25.6 seconds |
| Started | Aug 23 07:44:57 AM UTC 24 |
| Finished | Aug 23 07:45:24 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654442261 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during _key_req.1654442261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.478408176 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 128735345 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 07:45:16 AM UTC 24 |
| Finished | Aug 23 07:45:18 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478408176 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.478408176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1367647486 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1789197901 ps |
| CPU time | 34 seconds |
| Started | Aug 23 07:44:21 AM UTC 24 |
| Finished | Aug 23 07:44:56 AM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367647486 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.1367647486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.984291601 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 73576722577 ps |
| CPU time | 519.89 seconds |
| Started | Aug 23 07:45:02 AM UTC 24 |
| Finished | Aug 23 07:53:48 AM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984291601 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.984291601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.534855471 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1718110080 ps |
| CPU time | 4.99 seconds |
| Started | Aug 23 07:44:55 AM UTC 24 |
| Finished | Aug 23 07:45:01 AM UTC 24 |
| Peak memory | 228156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534855471 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.534855471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.82436217 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 368985676 ps |
| CPU time | 20.04 seconds |
| Started | Aug 23 07:44:45 AM UTC 24 |
| Finished | Aug 23 07:45:06 AM UTC 24 |
| Peak memory | 304944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 2436217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_max_ throughput.82436217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2896250505 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 79502648 ps |
| CPU time | 4.07 seconds |
| Started | Aug 23 07:45:10 AM UTC 24 |
| Finished | Aug 23 07:45:15 AM UTC 24 |
| Peak memory | 224300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896250505 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.2896250505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3189715990 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 71940626 ps |
| CPU time | 4.1 seconds |
| Started | Aug 23 07:45:10 AM UTC 24 |
| Finished | Aug 23 07:45:16 AM UTC 24 |
| Peak memory | 224388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189715990 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.3189715990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.999435007 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 20169018327 ps |
| CPU time | 639.45 seconds |
| Started | Aug 23 07:44:18 AM UTC 24 |
| Finished | Aug 23 07:55:05 AM UTC 24 |
| Peak memory | 387216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999435007 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.999435007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2940735107 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 2170849859 ps |
| CPU time | 8.04 seconds |
| Started | Aug 23 07:44:28 AM UTC 24 |
| Finished | Aug 23 07:44:37 AM UTC 24 |
| Peak memory | 213840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940735107 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.2940735107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.4090133211 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 14088906659 ps |
| CPU time | 235.9 seconds |
| Started | Aug 23 07:44:38 AM UTC 24 |
| Finished | Aug 23 07:48:37 AM UTC 24 |
| Peak memory | 214124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090133211 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acc ess_b2b.4090133211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.2498200897 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 115024362 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 07:45:07 AM UTC 24 |
| Finished | Aug 23 07:45:09 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498200897 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2498200897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.1380711247 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 14308555950 ps |
| CPU time | 487.84 seconds |
| Started | Aug 23 07:45:04 AM UTC 24 |
| Finished | Aug 23 07:53:17 AM UTC 24 |
| Peak memory | 384952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380711247 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1380711247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.1318318504 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 605286086 ps |
| CPU time | 7.79 seconds |
| Started | Aug 23 07:44:18 AM UTC 24 |
| Finished | Aug 23 07:44:27 AM UTC 24 |
| Peak memory | 213772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318318504 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1318318504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.780911925 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 326878604234 ps |
| CPU time | 3551.26 seconds |
| Started | Aug 23 07:45:16 AM UTC 24 |
| Finished | Aug 23 08:45:03 AM UTC 24 |
| Peak memory | 388724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780911925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.780911925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1375778170 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1601228952 ps |
| CPU time | 149.41 seconds |
| Started | Aug 23 07:45:13 AM UTC 24 |
| Finished | Aug 23 07:47:45 AM UTC 24 |
| Peak memory | 384952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375778170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1375778170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2739754188 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 43350450315 ps |
| CPU time | 271.91 seconds |
| Started | Aug 23 07:44:23 AM UTC 24 |
| Finished | Aug 23 07:48:58 AM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739754188 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.2739754188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1653669726 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 97721420 ps |
| CPU time | 8.67 seconds |
| Started | Aug 23 07:44:45 AM UTC 24 |
| Finished | Aug 23 07:44:55 AM UTC 24 |
| Peak memory | 272124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1653669726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_t hroughput_w_partial_write.1653669726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3040065064 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2296769412 ps |
| CPU time | 394.61 seconds |
| Started | Aug 23 07:47:18 AM UTC 24 |
| Finished | Aug 23 07:53:57 AM UTC 24 |
| Peak memory | 384912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040065064 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during _key_req.3040065064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.395038271 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 15635480 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 07:48:02 AM UTC 24 |
| Finished | Aug 23 07:48:04 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395038271 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.395038271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.958767288 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 8564846663 ps |
| CPU time | 77.27 seconds |
| Started | Aug 23 07:45:33 AM UTC 24 |
| Finished | Aug 23 07:46:52 AM UTC 24 |
| Peak memory | 213940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958767288 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.958767288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.325323375 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 20410946481 ps |
| CPU time | 492.93 seconds |
| Started | Aug 23 07:47:21 AM UTC 24 |
| Finished | Aug 23 07:55:39 AM UTC 24 |
| Peak memory | 384952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325323375 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.325323375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1773822230 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1976160976 ps |
| CPU time | 7.42 seconds |
| Started | Aug 23 07:47:09 AM UTC 24 |
| Finished | Aug 23 07:47:18 AM UTC 24 |
| Peak memory | 213872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773822230 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.1773822230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2799528383 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 173609299 ps |
| CPU time | 53.92 seconds |
| Started | Aug 23 07:46:52 AM UTC 24 |
| Finished | Aug 23 07:47:47 AM UTC 24 |
| Peak memory | 376688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 799528383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ma x_throughput.2799528383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2112040237 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 240540025 ps |
| CPU time | 2.69 seconds |
| Started | Aug 23 07:47:57 AM UTC 24 |
| Finished | Aug 23 07:48:01 AM UTC 24 |
| Peak memory | 224092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112040237 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.2112040237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.834281423 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 457476349 ps |
| CPU time | 8.67 seconds |
| Started | Aug 23 07:47:50 AM UTC 24 |
| Finished | Aug 23 07:48:00 AM UTC 24 |
| Peak memory | 224152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834281423 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.834281423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.4187135313 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 10973526628 ps |
| CPU time | 500.44 seconds |
| Started | Aug 23 07:45:25 AM UTC 24 |
| Finished | Aug 23 07:53:51 AM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187135313 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.4187135313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2889142485 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 951406829 ps |
| CPU time | 21.7 seconds |
| Started | Aug 23 07:46:35 AM UTC 24 |
| Finished | Aug 23 07:46:58 AM UTC 24 |
| Peak memory | 299076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889142485 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.2889142485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.339235543 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 74585602606 ps |
| CPU time | 451.04 seconds |
| Started | Aug 23 07:46:52 AM UTC 24 |
| Finished | Aug 23 07:54:28 AM UTC 24 |
| Peak memory | 213912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339235543 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acce ss_b2b.339235543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.788328972 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 26576246 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:47:48 AM UTC 24 |
| Finished | Aug 23 07:47:50 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788328972 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.788328972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.1130216752 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 1721601207 ps |
| CPU time | 272.92 seconds |
| Started | Aug 23 07:47:46 AM UTC 24 |
| Finished | Aug 23 07:52:23 AM UTC 24 |
| Peak memory | 378692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130216752 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1130216752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.2582995362 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 573335693 ps |
| CPU time | 39.07 seconds |
| Started | Aug 23 07:45:19 AM UTC 24 |
| Finished | Aug 23 07:45:59 AM UTC 24 |
| Peak memory | 346036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582995362 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2582995362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3373121144 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 7064113556 ps |
| CPU time | 1151.93 seconds |
| Started | Aug 23 07:48:01 AM UTC 24 |
| Finished | Aug 23 08:07:26 AM UTC 24 |
| Peak memory | 388660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337312114 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.3373121144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2867295711 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 2580179573 ps |
| CPU time | 100.76 seconds |
| Started | Aug 23 07:47:57 AM UTC 24 |
| Finished | Aug 23 07:49:40 AM UTC 24 |
| Peak memory | 374700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867295711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.2867295711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.2944263202 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 3738985128 ps |
| CPU time | 113.5 seconds |
| Started | Aug 23 07:46:00 AM UTC 24 |
| Finished | Aug 23 07:47:55 AM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944263202 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.2944263202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.466370408 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 105353489 ps |
| CPU time | 20.62 seconds |
| Started | Aug 23 07:46:59 AM UTC 24 |
| Finished | Aug 23 07:47:21 AM UTC 24 |
| Peak memory | 309092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 466370408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_th roughput_w_partial_write.466370408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3490009456 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2606977746 ps |
| CPU time | 415.71 seconds |
| Started | Aug 23 07:49:50 AM UTC 24 |
| Finished | Aug 23 07:56:51 AM UTC 24 |
| Peak memory | 380768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490009456 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during _key_req.3490009456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2129493760 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 13248022 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:51:35 AM UTC 24 |
| Finished | Aug 23 07:51:37 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129493760 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2129493760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.1629963486 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 26262905385 ps |
| CPU time | 63.88 seconds |
| Started | Aug 23 07:48:38 AM UTC 24 |
| Finished | Aug 23 07:49:43 AM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629963486 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.1629963486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.2936022679 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 8061033557 ps |
| CPU time | 253.59 seconds |
| Started | Aug 23 07:49:56 AM UTC 24 |
| Finished | Aug 23 07:54:12 AM UTC 24 |
| Peak memory | 335756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936022679 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.2936022679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.978217682 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 615022342 ps |
| CPU time | 3.94 seconds |
| Started | Aug 23 07:49:44 AM UTC 24 |
| Finished | Aug 23 07:49:50 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978217682 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.978217682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.4238995893 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 122531746 ps |
| CPU time | 35.81 seconds |
| Started | Aug 23 07:49:17 AM UTC 24 |
| Finished | Aug 23 07:49:54 AM UTC 24 |
| Peak memory | 344180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 238995893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ma x_throughput.4238995893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2073652942 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 173273032 ps |
| CPU time | 4.98 seconds |
| Started | Aug 23 07:50:51 AM UTC 24 |
| Finished | Aug 23 07:50:57 AM UTC 24 |
| Peak memory | 224300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073652942 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.2073652942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3871693926 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 446906464 ps |
| CPU time | 9.28 seconds |
| Started | Aug 23 07:50:40 AM UTC 24 |
| Finished | Aug 23 07:50:50 AM UTC 24 |
| Peak memory | 224124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871693926 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.3871693926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.217503272 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 17813117020 ps |
| CPU time | 581.32 seconds |
| Started | Aug 23 07:48:24 AM UTC 24 |
| Finished | Aug 23 07:58:11 AM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217503272 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.217503272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.2951523474 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 628488054 ps |
| CPU time | 16.09 seconds |
| Started | Aug 23 07:48:59 AM UTC 24 |
| Finished | Aug 23 07:49:16 AM UTC 24 |
| Peak memory | 213800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951523474 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.2951523474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2344459000 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 58250505469 ps |
| CPU time | 408.08 seconds |
| Started | Aug 23 07:49:00 AM UTC 24 |
| Finished | Aug 23 07:55:53 AM UTC 24 |
| Peak memory | 213796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344459000 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acc ess_b2b.2344459000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2404669811 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 49938052 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:50:38 AM UTC 24 |
| Finished | Aug 23 07:50:40 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404669811 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2404669811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.2673693687 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 8878770951 ps |
| CPU time | 520.74 seconds |
| Started | Aug 23 07:49:59 AM UTC 24 |
| Finished | Aug 23 07:58:45 AM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673693687 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2673693687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.490877502 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1182993371 ps |
| CPU time | 17.01 seconds |
| Started | Aug 23 07:48:05 AM UTC 24 |
| Finished | Aug 23 07:48:23 AM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490877502 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.490877502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.352688670 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 20709923353 ps |
| CPU time | 2289.98 seconds |
| Started | Aug 23 07:51:02 AM UTC 24 |
| Finished | Aug 23 08:29:36 AM UTC 24 |
| Peak memory | 397048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352688670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.352688670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1292338308 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2161569674 ps |
| CPU time | 339.67 seconds |
| Started | Aug 23 07:50:58 AM UTC 24 |
| Finished | Aug 23 07:56:42 AM UTC 24 |
| Peak memory | 376820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292338308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1292338308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3934154235 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2318158270 ps |
| CPU time | 194.8 seconds |
| Started | Aug 23 07:48:50 AM UTC 24 |
| Finished | Aug 23 07:52:08 AM UTC 24 |
| Peak memory | 214244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934154235 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.3934154235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3906788337 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 395282097 ps |
| CPU time | 15.67 seconds |
| Started | Aug 23 07:49:40 AM UTC 24 |
| Finished | Aug 23 07:49:57 AM UTC 24 |
| Peak memory | 300848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3906788337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_t hroughput_w_partial_write.3906788337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3203435917 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 5274014205 ps |
| CPU time | 909.43 seconds |
| Started | Aug 23 07:53:25 AM UTC 24 |
| Finished | Aug 23 08:08:44 AM UTC 24 |
| Peak memory | 386732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203435917 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during _key_req.3203435917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3467095858 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 17855578 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 07:54:06 AM UTC 24 |
| Finished | Aug 23 07:54:07 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467095858 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3467095858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.2639446797 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3509145611 ps |
| CPU time | 65.98 seconds |
| Started | Aug 23 07:52:09 AM UTC 24 |
| Finished | Aug 23 07:53:16 AM UTC 24 |
| Peak memory | 214000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639446797 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.2639446797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.1326750323 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 50823926007 ps |
| CPU time | 872.81 seconds |
| Started | Aug 23 07:53:29 AM UTC 24 |
| Finished | Aug 23 08:08:12 AM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326750323 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.1326750323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.338944912 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 98116099 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 07:53:22 AM UTC 24 |
| Finished | Aug 23 07:53:25 AM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338944912 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.338944912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2162724861 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 393406314 ps |
| CPU time | 10.14 seconds |
| Started | Aug 23 07:53:17 AM UTC 24 |
| Finished | Aug 23 07:53:28 AM UTC 24 |
| Peak memory | 280308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 162724861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ma x_throughput.2162724861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1130284992 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 401065693 ps |
| CPU time | 5.39 seconds |
| Started | Aug 23 07:53:58 AM UTC 24 |
| Finished | Aug 23 07:54:05 AM UTC 24 |
| Peak memory | 224316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130284992 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.1130284992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1207302549 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 751341666 ps |
| CPU time | 9.21 seconds |
| Started | Aug 23 07:53:54 AM UTC 24 |
| Finished | Aug 23 07:54:05 AM UTC 24 |
| Peak memory | 224196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207302549 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.1207302549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.268207241 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3280462859 ps |
| CPU time | 842.78 seconds |
| Started | Aug 23 07:51:53 AM UTC 24 |
| Finished | Aug 23 08:06:05 AM UTC 24 |
| Peak memory | 387092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268207241 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.268207241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2422370585 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 162066651 ps |
| CPU time | 12.56 seconds |
| Started | Aug 23 07:52:27 AM UTC 24 |
| Finished | Aug 23 07:52:41 AM UTC 24 |
| Peak memory | 278644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422370585 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.2422370585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3266630616 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 16592267022 ps |
| CPU time | 351.58 seconds |
| Started | Aug 23 07:52:42 AM UTC 24 |
| Finished | Aug 23 07:58:38 AM UTC 24 |
| Peak memory | 214324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266630616 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acc ess_b2b.3266630616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1149066453 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 28703452 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 07:53:51 AM UTC 24 |
| Finished | Aug 23 07:53:53 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149066453 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1149066453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.2435796472 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 3204792002 ps |
| CPU time | 508.08 seconds |
| Started | Aug 23 07:53:48 AM UTC 24 |
| Finished | Aug 23 08:02:22 AM UTC 24 |
| Peak memory | 387000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435796472 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2435796472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3066610028 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1785862839 ps |
| CPU time | 14.38 seconds |
| Started | Aug 23 07:51:37 AM UTC 24 |
| Finished | Aug 23 07:51:53 AM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066610028 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3066610028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1050688569 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 71735615649 ps |
| CPU time | 962.88 seconds |
| Started | Aug 23 07:54:06 AM UTC 24 |
| Finished | Aug 23 08:10:21 AM UTC 24 |
| Peak memory | 387080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105068856 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.1050688569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3697034731 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 487721314 ps |
| CPU time | 132.52 seconds |
| Started | Aug 23 07:54:02 AM UTC 24 |
| Finished | Aug 23 07:56:16 AM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697034731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3697034731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.659131160 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1506664276 ps |
| CPU time | 120.9 seconds |
| Started | Aug 23 07:52:24 AM UTC 24 |
| Finished | Aug 23 07:54:27 AM UTC 24 |
| Peak memory | 213868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659131160 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.659131160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.781784416 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 56682462 ps |
| CPU time | 2.7 seconds |
| Started | Aug 23 07:53:18 AM UTC 24 |
| Finished | Aug 23 07:53:22 AM UTC 24 |
| Peak memory | 231268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 781784416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_th roughput_w_partial_write.781784416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.4152316039 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 20697947936 ps |
| CPU time | 503.53 seconds |
| Started | Aug 23 07:55:17 AM UTC 24 |
| Finished | Aug 23 08:03:47 AM UTC 24 |
| Peak memory | 385168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152316039 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during _key_req.4152316039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1976099763 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 150103683 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 07:56:07 AM UTC 24 |
| Finished | Aug 23 07:56:08 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976099763 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1976099763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1894574365 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 8474218054 ps |
| CPU time | 44.35 seconds |
| Started | Aug 23 07:54:21 AM UTC 24 |
| Finished | Aug 23 07:55:07 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894574365 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.1894574365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1980858964 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 8837720596 ps |
| CPU time | 888.82 seconds |
| Started | Aug 23 07:55:40 AM UTC 24 |
| Finished | Aug 23 08:10:40 AM UTC 24 |
| Peak memory | 387160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980858964 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.1980858964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1431910055 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 1077689366 ps |
| CPU time | 8.12 seconds |
| Started | Aug 23 07:55:07 AM UTC 24 |
| Finished | Aug 23 07:55:16 AM UTC 24 |
| Peak memory | 224112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431910055 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.1431910055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2385661326 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 298116464 ps |
| CPU time | 45.53 seconds |
| Started | Aug 23 07:54:57 AM UTC 24 |
| Finished | Aug 23 07:55:44 AM UTC 24 |
| Peak memory | 364660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 385661326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ma x_throughput.2385661326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1129800867 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 92325226 ps |
| CPU time | 4.85 seconds |
| Started | Aug 23 07:56:00 AM UTC 24 |
| Finished | Aug 23 07:56:05 AM UTC 24 |
| Peak memory | 224084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129800867 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.1129800867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2373531789 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 284471788 ps |
| CPU time | 7.79 seconds |
| Started | Aug 23 07:55:57 AM UTC 24 |
| Finished | Aug 23 07:56:05 AM UTC 24 |
| Peak memory | 224424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373531789 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.2373531789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.935699046 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 10042505910 ps |
| CPU time | 402.17 seconds |
| Started | Aug 23 07:54:13 AM UTC 24 |
| Finished | Aug 23 08:01:00 AM UTC 24 |
| Peak memory | 386912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935699046 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.935699046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.404803628 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 983189714 ps |
| CPU time | 9.42 seconds |
| Started | Aug 23 07:54:29 AM UTC 24 |
| Finished | Aug 23 07:54:39 AM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404803628 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.404803628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2438535733 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 9371456502 ps |
| CPU time | 323.78 seconds |
| Started | Aug 23 07:54:40 AM UTC 24 |
| Finished | Aug 23 08:00:08 AM UTC 24 |
| Peak memory | 213888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438535733 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc ess_b2b.2438535733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.543538684 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 31354781 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 07:55:55 AM UTC 24 |
| Finished | Aug 23 07:55:56 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543538684 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.543538684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.2784579072 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3570246634 ps |
| CPU time | 69.8 seconds |
| Started | Aug 23 07:55:44 AM UTC 24 |
| Finished | Aug 23 07:56:56 AM UTC 24 |
| Peak memory | 315324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784579072 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2784579072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.4132590189 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 702983436 ps |
| CPU time | 11.03 seconds |
| Started | Aug 23 07:54:08 AM UTC 24 |
| Finished | Aug 23 07:54:20 AM UTC 24 |
| Peak memory | 213824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132590189 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.4132590189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2162491714 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 10375331967 ps |
| CPU time | 764.24 seconds |
| Started | Aug 23 07:56:07 AM UTC 24 |
| Finished | Aug 23 08:09:00 AM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216249171 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.2162491714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3227408645 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 361859500 ps |
| CPU time | 41.87 seconds |
| Started | Aug 23 07:56:07 AM UTC 24 |
| Finished | Aug 23 07:56:50 AM UTC 24 |
| Peak memory | 313268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227408645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3227408645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1206760679 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 23718365602 ps |
| CPU time | 157.21 seconds |
| Started | Aug 23 07:54:28 AM UTC 24 |
| Finished | Aug 23 07:57:08 AM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206760679 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.1206760679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3081862475 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 559168057 ps |
| CPU time | 59.33 seconds |
| Started | Aug 23 07:55:05 AM UTC 24 |
| Finished | Aug 23 07:56:06 AM UTC 24 |
| Peak memory | 370456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3081862475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_t hroughput_w_partial_write.3081862475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.830135819 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 8583369500 ps |
| CPU time | 228.26 seconds |
| Started | Aug 23 07:57:06 AM UTC 24 |
| Finished | Aug 23 08:00:58 AM UTC 24 |
| Peak memory | 384816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830135819 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during_ key_req.830135819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.66954467 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 43652956 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 07:57:56 AM UTC 24 |
| Finished | Aug 23 07:57:57 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66954467 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.66954467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.4248036 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 5869109506 ps |
| CPU time | 52.52 seconds |
| Started | Aug 23 07:56:17 AM UTC 24 |
| Finished | Aug 23 07:57:11 AM UTC 24 |
| Peak memory | 213812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248036 -assert nopostproc +UVM_TESTNA ME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.4248036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.534762568 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 17590221621 ps |
| CPU time | 194.71 seconds |
| Started | Aug 23 07:57:08 AM UTC 24 |
| Finished | Aug 23 08:00:26 AM UTC 24 |
| Peak memory | 376688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534762568 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.534762568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.4057764742 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 826759601 ps |
| CPU time | 7.33 seconds |
| Started | Aug 23 07:56:57 AM UTC 24 |
| Finished | Aug 23 07:57:06 AM UTC 24 |
| Peak memory | 224048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057764742 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.4057764742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.463127739 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 417028701 ps |
| CPU time | 33.92 seconds |
| Started | Aug 23 07:56:50 AM UTC 24 |
| Finished | Aug 23 07:57:25 AM UTC 24 |
| Peak memory | 343836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 63127739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_max _throughput.463127739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1663863967 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 195307742 ps |
| CPU time | 5.32 seconds |
| Started | Aug 23 07:57:26 AM UTC 24 |
| Finished | Aug 23 07:57:32 AM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663863967 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.1663863967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3521002897 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 1102910043 ps |
| CPU time | 5.31 seconds |
| Started | Aug 23 07:57:21 AM UTC 24 |
| Finished | Aug 23 07:57:27 AM UTC 24 |
| Peak memory | 224148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521002897 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.3521002897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2843337947 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 13272763839 ps |
| CPU time | 598.51 seconds |
| Started | Aug 23 07:56:17 AM UTC 24 |
| Finished | Aug 23 08:06:22 AM UTC 24 |
| Peak memory | 368560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843337947 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.2843337947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3736768506 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 401551976 ps |
| CPU time | 5.22 seconds |
| Started | Aug 23 07:56:43 AM UTC 24 |
| Finished | Aug 23 07:56:49 AM UTC 24 |
| Peak memory | 213852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736768506 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.3736768506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.2160129564 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 20564078028 ps |
| CPU time | 326.19 seconds |
| Started | Aug 23 07:56:50 AM UTC 24 |
| Finished | Aug 23 08:02:20 AM UTC 24 |
| Peak memory | 213896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160129564 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acc ess_b2b.2160129564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.193162889 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 102008104 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 07:57:19 AM UTC 24 |
| Finished | Aug 23 07:57:20 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193162889 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.193162889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.2472769081 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 7645187148 ps |
| CPU time | 307.6 seconds |
| Started | Aug 23 07:57:11 AM UTC 24 |
| Finished | Aug 23 08:02:23 AM UTC 24 |
| Peak memory | 378764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472769081 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2472769081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.29257150 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 311908986 ps |
| CPU time | 6.59 seconds |
| Started | Aug 23 07:56:09 AM UTC 24 |
| Finished | Aug 23 07:56:17 AM UTC 24 |
| Peak memory | 213848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29257150 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.29257150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1895518384 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 497540972260 ps |
| CPU time | 2273.34 seconds |
| Started | Aug 23 07:57:33 AM UTC 24 |
| Finished | Aug 23 08:35:51 AM UTC 24 |
| Peak memory | 390776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189551838 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.1895518384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2318085219 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 1794015142 ps |
| CPU time | 156.27 seconds |
| Started | Aug 23 07:56:43 AM UTC 24 |
| Finished | Aug 23 07:59:22 AM UTC 24 |
| Peak memory | 213844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318085219 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.2318085219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.2205079379 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 980735020 ps |
| CPU time | 73.2 seconds |
| Started | Aug 23 07:56:51 AM UTC 24 |
| Finished | Aug 23 07:58:06 AM UTC 24 |
| Peak memory | 380772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2205079379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_t hroughput_w_partial_write.2205079379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1994086085 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 10498627754 ps |
| CPU time | 222.64 seconds |
| Started | Aug 23 06:22:36 AM UTC 24 |
| Finished | Aug 23 06:26:22 AM UTC 24 |
| Peak memory | 362340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994086085 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_ key_req.1994086085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2603555831 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 16236886 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 06:23:20 AM UTC 24 |
| Finished | Aug 23 06:23:21 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603555831 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.2603555831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.3399382394 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 7103979041 ps |
| CPU time | 74.58 seconds |
| Started | Aug 23 06:21:31 AM UTC 24 |
| Finished | Aug 23 06:22:47 AM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399382394 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.3399382394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.1532137328 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2235217205 ps |
| CPU time | 13.56 seconds |
| Started | Aug 23 06:22:48 AM UTC 24 |
| Finished | Aug 23 06:23:03 AM UTC 24 |
| Peak memory | 245628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532137328 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.1532137328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2092930866 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 437046222 ps |
| CPU time | 4.11 seconds |
| Started | Aug 23 06:22:30 AM UTC 24 |
| Finished | Aug 23 06:22:35 AM UTC 24 |
| Peak memory | 224372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092930866 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.2092930866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.4159027667 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 158602344 ps |
| CPU time | 12.56 seconds |
| Started | Aug 23 06:22:13 AM UTC 24 |
| Finished | Aug 23 06:22:27 AM UTC 24 |
| Peak memory | 290604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 159027667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max _throughput.4159027667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2070872730 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 325439704 ps |
| CPU time | 4.8 seconds |
| Started | Aug 23 06:23:13 AM UTC 24 |
| Finished | Aug 23 06:23:19 AM UTC 24 |
| Peak memory | 224428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070872730 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.2070872730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3291889137 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 369345026 ps |
| CPU time | 4.97 seconds |
| Started | Aug 23 06:23:10 AM UTC 24 |
| Finished | Aug 23 06:23:16 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291889137 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.3291889137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2037309592 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 17647734070 ps |
| CPU time | 203.92 seconds |
| Started | Aug 23 06:21:28 AM UTC 24 |
| Finished | Aug 23 06:24:54 AM UTC 24 |
| Peak memory | 385196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037309592 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.2037309592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2740626018 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 655866530 ps |
| CPU time | 44.42 seconds |
| Started | Aug 23 06:21:44 AM UTC 24 |
| Finished | Aug 23 06:22:30 AM UTC 24 |
| Peak memory | 352056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740626018 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.2740626018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1835621597 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 118054717547 ps |
| CPU time | 376.09 seconds |
| Started | Aug 23 06:21:57 AM UTC 24 |
| Finished | Aug 23 06:28:17 AM UTC 24 |
| Peak memory | 214208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835621597 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acce ss_b2b.1835621597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1030768907 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 68748878 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 06:23:08 AM UTC 24 |
| Finished | Aug 23 06:23:10 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030768907 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1030768907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.2062831959 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1415974532 ps |
| CPU time | 72.78 seconds |
| Started | Aug 23 06:23:04 AM UTC 24 |
| Finished | Aug 23 06:24:19 AM UTC 24 |
| Peak memory | 378944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062831959 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2062831959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.177794513 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 39637153 ps |
| CPU time | 1.63 seconds |
| Started | Aug 23 06:21:27 AM UTC 24 |
| Finished | Aug 23 06:21:29 AM UTC 24 |
| Peak memory | 214460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177794513 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.177794513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3108653248 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 74704816775 ps |
| CPU time | 1277.05 seconds |
| Started | Aug 23 06:23:18 AM UTC 24 |
| Finished | Aug 23 06:44:46 AM UTC 24 |
| Peak memory | 388720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310865324 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.3108653248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.840406527 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 12412220233 ps |
| CPU time | 274.11 seconds |
| Started | Aug 23 06:21:41 AM UTC 24 |
| Finished | Aug 23 06:26:18 AM UTC 24 |
| Peak memory | 213872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840406527 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.840406527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.2786959442 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 957809039 ps |
| CPU time | 39.36 seconds |
| Started | Aug 23 06:22:27 AM UTC 24 |
| Finished | Aug 23 06:23:08 AM UTC 24 |
| Peak memory | 354368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2786959442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th roughput_w_partial_write.2786959442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.1538625349 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 9925836753 ps |
| CPU time | 595.85 seconds |
| Started | Aug 23 06:25:31 AM UTC 24 |
| Finished | Aug 23 06:35:34 AM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538625349 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_ key_req.1538625349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.861521046 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 13843603 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 06:25:56 AM UTC 24 |
| Finished | Aug 23 06:25:58 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861521046 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.861521046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.2707237484 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5084004860 ps |
| CPU time | 74.52 seconds |
| Started | Aug 23 06:24:19 AM UTC 24 |
| Finished | Aug 23 06:25:35 AM UTC 24 |
| Peak memory | 213816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707237484 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.2707237484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.4045491618 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 10697751352 ps |
| CPU time | 581.82 seconds |
| Started | Aug 23 06:25:37 AM UTC 24 |
| Finished | Aug 23 06:35:25 AM UTC 24 |
| Peak memory | 383164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045491618 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.4045491618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.791324944 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1925675434 ps |
| CPU time | 5.86 seconds |
| Started | Aug 23 06:25:23 AM UTC 24 |
| Finished | Aug 23 06:25:30 AM UTC 24 |
| Peak memory | 224412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791324944 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.791324944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3188735795 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 269536774 ps |
| CPU time | 42.31 seconds |
| Started | Aug 23 06:24:55 AM UTC 24 |
| Finished | Aug 23 06:25:39 AM UTC 24 |
| Peak memory | 372516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 188735795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max _throughput.3188735795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.361579398 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 339409029 ps |
| CPU time | 2.9 seconds |
| Started | Aug 23 06:25:51 AM UTC 24 |
| Finished | Aug 23 06:25:55 AM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361579398 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.361579398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3216194714 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1223280766 ps |
| CPU time | 5.48 seconds |
| Started | Aug 23 06:25:50 AM UTC 24 |
| Finished | Aug 23 06:25:56 AM UTC 24 |
| Peak memory | 224328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216194714 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.3216194714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3901333241 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 46847911830 ps |
| CPU time | 396.52 seconds |
| Started | Aug 23 06:23:34 AM UTC 24 |
| Finished | Aug 23 06:30:15 AM UTC 24 |
| Peak memory | 358316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901333241 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.3901333241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.4169830539 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3449367489 ps |
| CPU time | 66.43 seconds |
| Started | Aug 23 06:24:40 AM UTC 24 |
| Finished | Aug 23 06:25:48 AM UTC 24 |
| Peak memory | 377008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169830539 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.4169830539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3075404615 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 10790624979 ps |
| CPU time | 234.16 seconds |
| Started | Aug 23 06:24:46 AM UTC 24 |
| Finished | Aug 23 06:28:43 AM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075404615 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acce ss_b2b.3075404615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.804229587 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 32671803 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 06:25:49 AM UTC 24 |
| Finished | Aug 23 06:25:50 AM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804229587 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.804229587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.1062691432 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 13177281180 ps |
| CPU time | 928.13 seconds |
| Started | Aug 23 06:25:40 AM UTC 24 |
| Finished | Aug 23 06:41:17 AM UTC 24 |
| Peak memory | 382528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062691432 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1062691432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.4137981266 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 571814108 ps |
| CPU time | 54.49 seconds |
| Started | Aug 23 06:23:22 AM UTC 24 |
| Finished | Aug 23 06:24:18 AM UTC 24 |
| Peak memory | 370492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137981266 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.4137981266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3240098889 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 26484806297 ps |
| CPU time | 935.9 seconds |
| Started | Aug 23 06:25:55 AM UTC 24 |
| Finished | Aug 23 06:41:40 AM UTC 24 |
| Peak memory | 381140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324009888 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.3240098889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3663085508 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 6398890828 ps |
| CPU time | 270.27 seconds |
| Started | Aug 23 06:25:52 AM UTC 24 |
| Finished | Aug 23 06:30:26 AM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663085508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3663085508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.4035496078 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 45191536810 ps |
| CPU time | 356.45 seconds |
| Started | Aug 23 06:24:20 AM UTC 24 |
| Finished | Aug 23 06:30:21 AM UTC 24 |
| Peak memory | 213900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035496078 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.4035496078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4182374364 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 168837419 ps |
| CPU time | 49.57 seconds |
| Started | Aug 23 06:25:00 AM UTC 24 |
| Finished | Aug 23 06:25:51 AM UTC 24 |
| Peak memory | 372836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4182374364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_th roughput_w_partial_write.4182374364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.2053500957 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 11380765408 ps |
| CPU time | 505.94 seconds |
| Started | Aug 23 06:26:32 AM UTC 24 |
| Finished | Aug 23 06:35:04 AM UTC 24 |
| Peak memory | 385196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053500957 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_ key_req.2053500957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.2806329548 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 25162373 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 06:26:47 AM UTC 24 |
| Finished | Aug 23 06:26:48 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806329548 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2806329548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.118924250 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 349316708 ps |
| CPU time | 15.75 seconds |
| Started | Aug 23 06:26:03 AM UTC 24 |
| Finished | Aug 23 06:26:20 AM UTC 24 |
| Peak memory | 214184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118924250 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.118924250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.339162692 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1214764349 ps |
| CPU time | 63.17 seconds |
| Started | Aug 23 06:26:33 AM UTC 24 |
| Finished | Aug 23 06:27:37 AM UTC 24 |
| Peak memory | 358520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339162692 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.339162692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.877035457 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1290505121 ps |
| CPU time | 5.66 seconds |
| Started | Aug 23 06:26:25 AM UTC 24 |
| Finished | Aug 23 06:26:32 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877035457 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.877035457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.130199061 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 304132954 ps |
| CPU time | 14.34 seconds |
| Started | Aug 23 06:26:20 AM UTC 24 |
| Finished | Aug 23 06:26:36 AM UTC 24 |
| Peak memory | 290924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 30199061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max_ throughput.130199061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2630287605 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 87412689 ps |
| CPU time | 2.39 seconds |
| Started | Aug 23 06:26:38 AM UTC 24 |
| Finished | Aug 23 06:26:41 AM UTC 24 |
| Peak memory | 223992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630287605 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.2630287605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2367455101 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 139071676 ps |
| CPU time | 7.44 seconds |
| Started | Aug 23 06:26:38 AM UTC 24 |
| Finished | Aug 23 06:26:46 AM UTC 24 |
| Peak memory | 224412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367455101 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.2367455101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3767301577 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 754167985 ps |
| CPU time | 140.56 seconds |
| Started | Aug 23 06:25:58 AM UTC 24 |
| Finished | Aug 23 06:28:21 AM UTC 24 |
| Peak memory | 378668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767301577 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.3767301577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1197388644 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 140648039 ps |
| CPU time | 14.32 seconds |
| Started | Aug 23 06:26:09 AM UTC 24 |
| Finished | Aug 23 06:26:25 AM UTC 24 |
| Peak memory | 286644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197388644 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.1197388644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.127472231 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 13380778896 ps |
| CPU time | 319.39 seconds |
| Started | Aug 23 06:26:19 AM UTC 24 |
| Finished | Aug 23 06:31:43 AM UTC 24 |
| Peak memory | 213992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127472231 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acces s_b2b.127472231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.346585093 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 31128020 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:26:37 AM UTC 24 |
| Finished | Aug 23 06:26:38 AM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346585093 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.346585093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.818830166 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 27603455214 ps |
| CPU time | 824.3 seconds |
| Started | Aug 23 06:26:34 AM UTC 24 |
| Finished | Aug 23 06:40:25 AM UTC 24 |
| Peak memory | 387264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818830166 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.818830166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.2891220911 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 135496960 ps |
| CPU time | 4.03 seconds |
| Started | Aug 23 06:25:57 AM UTC 24 |
| Finished | Aug 23 06:26:02 AM UTC 24 |
| Peak memory | 231176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891220911 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2891220911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1330750254 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 53097024501 ps |
| CPU time | 1844.46 seconds |
| Started | Aug 23 06:26:42 AM UTC 24 |
| Finished | Aug 23 06:57:43 AM UTC 24 |
| Peak memory | 388712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133075025 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.1330750254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3553319128 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 501836235 ps |
| CPU time | 56.64 seconds |
| Started | Aug 23 06:26:39 AM UTC 24 |
| Finished | Aug 23 06:27:37 AM UTC 24 |
| Peak memory | 296888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553319128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3553319128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.4266800307 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2804520575 ps |
| CPU time | 257.86 seconds |
| Started | Aug 23 06:26:07 AM UTC 24 |
| Finished | Aug 23 06:30:28 AM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266800307 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.4266800307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1247543774 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 155618174 ps |
| CPU time | 54.7 seconds |
| Started | Aug 23 06:26:22 AM UTC 24 |
| Finished | Aug 23 06:27:18 AM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1247543774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_th roughput_w_partial_write.1247543774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1447348231 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 8083631279 ps |
| CPU time | 761.52 seconds |
| Started | Aug 23 06:28:19 AM UTC 24 |
| Finished | Aug 23 06:41:08 AM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447348231 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_ key_req.1447348231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.412569332 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 13324044 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 06:28:44 AM UTC 24 |
| Finished | Aug 23 06:28:46 AM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412569332 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.412569332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.663006147 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3033131434 ps |
| CPU time | 59.41 seconds |
| Started | Aug 23 06:27:12 AM UTC 24 |
| Finished | Aug 23 06:28:13 AM UTC 24 |
| Peak memory | 213924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663006147 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.663006147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.516759165 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3323974273 ps |
| CPU time | 562.73 seconds |
| Started | Aug 23 06:28:19 AM UTC 24 |
| Finished | Aug 23 06:37:47 AM UTC 24 |
| Peak memory | 387004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516759165 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.516759165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1540384509 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2314079904 ps |
| CPU time | 7.09 seconds |
| Started | Aug 23 06:28:14 AM UTC 24 |
| Finished | Aug 23 06:28:22 AM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540384509 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.1540384509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4009751211 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 91521706 ps |
| CPU time | 21.95 seconds |
| Started | Aug 23 06:27:38 AM UTC 24 |
| Finished | Aug 23 06:28:01 AM UTC 24 |
| Peak memory | 304932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 009751211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max _throughput.4009751211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.254412920 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 188620415 ps |
| CPU time | 5.23 seconds |
| Started | Aug 23 06:28:32 AM UTC 24 |
| Finished | Aug 23 06:28:38 AM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254412920 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.254412920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.384504311 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1315137740 ps |
| CPU time | 4.93 seconds |
| Started | Aug 23 06:28:26 AM UTC 24 |
| Finished | Aug 23 06:28:32 AM UTC 24 |
| Peak memory | 224328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384504311 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.384504311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1576048917 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3205171115 ps |
| CPU time | 415.52 seconds |
| Started | Aug 23 06:26:54 AM UTC 24 |
| Finished | Aug 23 06:33:54 AM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576048917 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.1576048917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1165018104 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 797347998 ps |
| CPU time | 57.95 seconds |
| Started | Aug 23 06:27:31 AM UTC 24 |
| Finished | Aug 23 06:28:31 AM UTC 24 |
| Peak memory | 374640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165018104 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.1165018104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3015331733 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3247459380 ps |
| CPU time | 227.88 seconds |
| Started | Aug 23 06:27:37 AM UTC 24 |
| Finished | Aug 23 06:31:28 AM UTC 24 |
| Peak memory | 213948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015331733 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acce ss_b2b.3015331733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2769467407 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 31123546 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 06:28:23 AM UTC 24 |
| Finished | Aug 23 06:28:25 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769467407 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2769467407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.21850883 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5638082756 ps |
| CPU time | 612.67 seconds |
| Started | Aug 23 06:28:22 AM UTC 24 |
| Finished | Aug 23 06:38:40 AM UTC 24 |
| Peak memory | 376952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21850883 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.21850883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3221993881 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 397727764 ps |
| CPU time | 21.7 seconds |
| Started | Aug 23 06:26:49 AM UTC 24 |
| Finished | Aug 23 06:27:12 AM UTC 24 |
| Peak memory | 317228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221993881 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3221993881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2820709100 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 32739630035 ps |
| CPU time | 1213.45 seconds |
| Started | Aug 23 06:28:39 AM UTC 24 |
| Finished | Aug 23 06:49:04 AM UTC 24 |
| Peak memory | 388720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282070910 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.2820709100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.176533045 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 15229345001 ps |
| CPU time | 166.42 seconds |
| Started | Aug 23 06:28:33 AM UTC 24 |
| Finished | Aug 23 06:31:22 AM UTC 24 |
| Peak memory | 391156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176533045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.176533045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.3624831119 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 15337331112 ps |
| CPU time | 333.07 seconds |
| Started | Aug 23 06:27:19 AM UTC 24 |
| Finished | Aug 23 06:32:56 AM UTC 24 |
| Peak memory | 213972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624831119 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.3624831119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.571436457 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 339777620 ps |
| CPU time | 14.16 seconds |
| Started | Aug 23 06:28:02 AM UTC 24 |
| Finished | Aug 23 06:28:18 AM UTC 24 |
| Peak memory | 284732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 571436457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_thr oughput_w_partial_write.571436457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.549619720 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 16094911848 ps |
| CPU time | 580.78 seconds |
| Started | Aug 23 06:30:35 AM UTC 24 |
| Finished | Aug 23 06:40:22 AM UTC 24 |
| Peak memory | 382832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549619720 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_k ey_req.549619720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2919075135 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 38797971 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 06:31:34 AM UTC 24 |
| Finished | Aug 23 06:31:36 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919075135 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2919075135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3792819353 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 29376798979 ps |
| CPU time | 59.65 seconds |
| Started | Aug 23 06:29:05 AM UTC 24 |
| Finished | Aug 23 06:30:07 AM UTC 24 |
| Peak memory | 213824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792819353 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.3792819353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.4283239333 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2953077350 ps |
| CPU time | 713.54 seconds |
| Started | Aug 23 06:30:50 AM UTC 24 |
| Finished | Aug 23 06:42:51 AM UTC 24 |
| Peak memory | 385208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283239333 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.4283239333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.855284999 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 575787854 ps |
| CPU time | 4.58 seconds |
| Started | Aug 23 06:30:29 AM UTC 24 |
| Finished | Aug 23 06:30:35 AM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855284999 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.855284999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.125737544 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1055516484 ps |
| CPU time | 56.71 seconds |
| Started | Aug 23 06:30:22 AM UTC 24 |
| Finished | Aug 23 06:31:20 AM UTC 24 |
| Peak memory | 380912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 25737544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max_ throughput.125737544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2161885770 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 689954659 ps |
| CPU time | 5.18 seconds |
| Started | Aug 23 06:31:22 AM UTC 24 |
| Finished | Aug 23 06:31:29 AM UTC 24 |
| Peak memory | 224308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161885770 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.2161885770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.108223443 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 904480399 ps |
| CPU time | 9.75 seconds |
| Started | Aug 23 06:31:22 AM UTC 24 |
| Finished | Aug 23 06:31:33 AM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108223443 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.108223443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3773958308 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 97269489277 ps |
| CPU time | 1045.73 seconds |
| Started | Aug 23 06:28:50 AM UTC 24 |
| Finished | Aug 23 06:46:26 AM UTC 24 |
| Peak memory | 385196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773958308 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.3773958308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.812613421 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1069150529 ps |
| CPU time | 40.31 seconds |
| Started | Aug 23 06:30:08 AM UTC 24 |
| Finished | Aug 23 06:30:49 AM UTC 24 |
| Peak memory | 346220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812613421 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.812613421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.713457556 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 110272776132 ps |
| CPU time | 268.61 seconds |
| Started | Aug 23 06:30:16 AM UTC 24 |
| Finished | Aug 23 06:34:48 AM UTC 24 |
| Peak memory | 213920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713457556 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acces s_b2b.713457556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3376445365 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 50690972 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:31:20 AM UTC 24 |
| Finished | Aug 23 06:31:22 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376445365 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3376445365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.1770057229 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 7410902918 ps |
| CPU time | 523.67 seconds |
| Started | Aug 23 06:31:09 AM UTC 24 |
| Finished | Aug 23 06:39:58 AM UTC 24 |
| Peak memory | 386932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770057229 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1770057229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.2849342048 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 362776314 ps |
| CPU time | 17.39 seconds |
| Started | Aug 23 06:28:46 AM UTC 24 |
| Finished | Aug 23 06:29:05 AM UTC 24 |
| Peak memory | 292724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849342048 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2849342048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2169560893 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 207000426879 ps |
| CPU time | 1520.4 seconds |
| Started | Aug 23 06:31:29 AM UTC 24 |
| Finished | Aug 23 06:57:04 AM UTC 24 |
| Peak memory | 388792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216956089 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.2169560893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.1667903063 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 2271304231 ps |
| CPU time | 113.71 seconds |
| Started | Aug 23 06:29:46 AM UTC 24 |
| Finished | Aug 23 06:31:42 AM UTC 24 |
| Peak memory | 213948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667903063 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.1667903063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2454301177 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 340849945 ps |
| CPU time | 68.69 seconds |
| Started | Aug 23 06:30:27 AM UTC 24 |
| Finished | Aug 23 06:31:37 AM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2454301177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_th roughput_w_partial_write.2454301177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |