| T791 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.4269344149 |
|
|
Aug 23 07:43:51 AM UTC 24 |
Aug 23 07:43:54 AM UTC 24 |
111030218 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.3001650050 |
|
|
Aug 23 07:43:05 AM UTC 24 |
Aug 23 07:43:55 AM UTC 24 |
6764569747 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3424018874 |
|
|
Aug 23 07:43:55 AM UTC 24 |
Aug 23 07:43:57 AM UTC 24 |
32172261 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.2343494380 |
|
|
Aug 23 07:43:58 AM UTC 24 |
Aug 23 07:44:08 AM UTC 24 |
186564114 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.352924476 |
|
|
Aug 23 07:42:47 AM UTC 24 |
Aug 23 07:44:09 AM UTC 24 |
3927098004 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2311924678 |
|
|
Aug 23 07:44:09 AM UTC 24 |
Aug 23 07:44:13 AM UTC 24 |
113491964 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.3267061044 |
|
|
Aug 23 07:42:29 AM UTC 24 |
Aug 23 07:44:17 AM UTC 24 |
2896947810 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.3282992533 |
|
|
Aug 23 07:39:31 AM UTC 24 |
Aug 23 07:44:18 AM UTC 24 |
3641666628 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.561493908 |
|
|
Aug 23 07:41:24 AM UTC 24 |
Aug 23 07:44:18 AM UTC 24 |
7960537992 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2541878450 |
|
|
Aug 23 07:44:18 AM UTC 24 |
Aug 23 07:44:20 AM UTC 24 |
29086699 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1417282571 |
|
|
Aug 23 07:43:44 AM UTC 24 |
Aug 23 07:44:22 AM UTC 24 |
452632183 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.1318318504 |
|
|
Aug 23 07:44:18 AM UTC 24 |
Aug 23 07:44:27 AM UTC 24 |
605286086 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2940735107 |
|
|
Aug 23 07:44:28 AM UTC 24 |
Aug 23 07:44:37 AM UTC 24 |
2170849859 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3088341156 |
|
|
Aug 23 07:43:45 AM UTC 24 |
Aug 23 07:44:44 AM UTC 24 |
149747610 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2683615200 |
|
|
Aug 23 07:44:10 AM UTC 24 |
Aug 23 07:44:44 AM UTC 24 |
3120172734 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1653669726 |
|
|
Aug 23 07:44:45 AM UTC 24 |
Aug 23 07:44:55 AM UTC 24 |
97721420 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1367647486 |
|
|
Aug 23 07:44:21 AM UTC 24 |
Aug 23 07:44:56 AM UTC 24 |
1789197901 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.534855471 |
|
|
Aug 23 07:44:55 AM UTC 24 |
Aug 23 07:45:01 AM UTC 24 |
1718110080 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.4109009059 |
|
|
Aug 23 07:38:48 AM UTC 24 |
Aug 23 07:45:03 AM UTC 24 |
34436856726 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.82436217 |
|
|
Aug 23 07:44:45 AM UTC 24 |
Aug 23 07:45:06 AM UTC 24 |
368985676 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.2498200897 |
|
|
Aug 23 07:45:07 AM UTC 24 |
Aug 23 07:45:09 AM UTC 24 |
115024362 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.404220282 |
|
|
Aug 23 07:32:03 AM UTC 24 |
Aug 23 07:45:10 AM UTC 24 |
30956587299 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.1231979418 |
|
|
Aug 23 06:47:42 AM UTC 24 |
Aug 23 07:45:12 AM UTC 24 |
12661904076 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2896250505 |
|
|
Aug 23 07:45:10 AM UTC 24 |
Aug 23 07:45:15 AM UTC 24 |
79502648 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3189715990 |
|
|
Aug 23 07:45:10 AM UTC 24 |
Aug 23 07:45:16 AM UTC 24 |
71940626 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.478408176 |
|
|
Aug 23 07:45:16 AM UTC 24 |
Aug 23 07:45:18 AM UTC 24 |
128735345 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1654442261 |
|
|
Aug 23 07:44:57 AM UTC 24 |
Aug 23 07:45:24 AM UTC 24 |
1884642674 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2294409964 |
|
|
Aug 23 07:40:38 AM UTC 24 |
Aug 23 07:45:32 AM UTC 24 |
13113591853 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.2582995362 |
|
|
Aug 23 07:45:19 AM UTC 24 |
Aug 23 07:45:59 AM UTC 24 |
573335693 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.930102564 |
|
|
Aug 23 07:40:54 AM UTC 24 |
Aug 23 07:46:34 AM UTC 24 |
2886944611 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.246965132 |
|
|
Aug 23 07:44:14 AM UTC 24 |
Aug 23 07:46:51 AM UTC 24 |
5609817668 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.958767288 |
|
|
Aug 23 07:45:33 AM UTC 24 |
Aug 23 07:46:52 AM UTC 24 |
8564846663 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2889142485 |
|
|
Aug 23 07:46:35 AM UTC 24 |
Aug 23 07:46:58 AM UTC 24 |
951406829 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.838012711 |
|
|
Aug 23 07:43:31 AM UTC 24 |
Aug 23 07:47:08 AM UTC 24 |
4864689261 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1773822230 |
|
|
Aug 23 07:47:09 AM UTC 24 |
Aug 23 07:47:18 AM UTC 24 |
1976160976 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.466370408 |
|
|
Aug 23 07:46:59 AM UTC 24 |
Aug 23 07:47:21 AM UTC 24 |
105353489 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1375778170 |
|
|
Aug 23 07:45:13 AM UTC 24 |
Aug 23 07:47:45 AM UTC 24 |
1601228952 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.2799528383 |
|
|
Aug 23 07:46:52 AM UTC 24 |
Aug 23 07:47:47 AM UTC 24 |
173609299 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.788328972 |
|
|
Aug 23 07:47:48 AM UTC 24 |
Aug 23 07:47:50 AM UTC 24 |
26576246 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.2944263202 |
|
|
Aug 23 07:46:00 AM UTC 24 |
Aug 23 07:47:55 AM UTC 24 |
3738985128 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.1036358316 |
|
|
Aug 23 07:42:00 AM UTC 24 |
Aug 23 07:47:56 AM UTC 24 |
4842465231 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.834281423 |
|
|
Aug 23 07:47:50 AM UTC 24 |
Aug 23 07:48:00 AM UTC 24 |
457476349 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2112040237 |
|
|
Aug 23 07:47:57 AM UTC 24 |
Aug 23 07:48:01 AM UTC 24 |
240540025 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.395038271 |
|
|
Aug 23 07:48:02 AM UTC 24 |
Aug 23 07:48:04 AM UTC 24 |
15635480 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.490877502 |
|
|
Aug 23 07:48:05 AM UTC 24 |
Aug 23 07:48:23 AM UTC 24 |
1182993371 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.4090133211 |
|
|
Aug 23 07:44:38 AM UTC 24 |
Aug 23 07:48:37 AM UTC 24 |
14088906659 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.990451096 |
|
|
Aug 23 07:42:27 AM UTC 24 |
Aug 23 07:48:49 AM UTC 24 |
12222220720 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2739754188 |
|
|
Aug 23 07:44:23 AM UTC 24 |
Aug 23 07:48:58 AM UTC 24 |
43350450315 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.3631422600 |
|
|
Aug 23 07:39:39 AM UTC 24 |
Aug 23 07:48:59 AM UTC 24 |
9236859972 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.2951523474 |
|
|
Aug 23 07:48:59 AM UTC 24 |
Aug 23 07:49:16 AM UTC 24 |
628488054 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2867295711 |
|
|
Aug 23 07:47:57 AM UTC 24 |
Aug 23 07:49:40 AM UTC 24 |
2580179573 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.1629963486 |
|
|
Aug 23 07:48:38 AM UTC 24 |
Aug 23 07:49:43 AM UTC 24 |
26262905385 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.978217682 |
|
|
Aug 23 07:49:44 AM UTC 24 |
Aug 23 07:49:50 AM UTC 24 |
615022342 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.4238995893 |
|
|
Aug 23 07:49:17 AM UTC 24 |
Aug 23 07:49:54 AM UTC 24 |
122531746 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3906788337 |
|
|
Aug 23 07:49:40 AM UTC 24 |
Aug 23 07:49:57 AM UTC 24 |
395282097 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1968278218 |
|
|
Aug 23 07:43:43 AM UTC 24 |
Aug 23 07:50:37 AM UTC 24 |
37945597512 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2404669811 |
|
|
Aug 23 07:50:38 AM UTC 24 |
Aug 23 07:50:40 AM UTC 24 |
49938052 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3871693926 |
|
|
Aug 23 07:50:40 AM UTC 24 |
Aug 23 07:50:50 AM UTC 24 |
446906464 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2073652942 |
|
|
Aug 23 07:50:51 AM UTC 24 |
Aug 23 07:50:57 AM UTC 24 |
173273032 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3756102492 |
|
|
Aug 23 07:43:53 AM UTC 24 |
Aug 23 07:51:01 AM UTC 24 |
11413541988 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2656757765 |
|
|
Aug 23 07:41:07 AM UTC 24 |
Aug 23 07:51:34 AM UTC 24 |
16506480012 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2129493760 |
|
|
Aug 23 07:51:35 AM UTC 24 |
Aug 23 07:51:37 AM UTC 24 |
13248022 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3066610028 |
|
|
Aug 23 07:51:37 AM UTC 24 |
Aug 23 07:51:53 AM UTC 24 |
1785862839 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3934154235 |
|
|
Aug 23 07:48:50 AM UTC 24 |
Aug 23 07:52:08 AM UTC 24 |
2318158270 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.1130216752 |
|
|
Aug 23 07:47:46 AM UTC 24 |
Aug 23 07:52:23 AM UTC 24 |
1721601207 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.148087627 |
|
|
Aug 23 07:39:59 AM UTC 24 |
Aug 23 07:52:26 AM UTC 24 |
7945425625 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2422370585 |
|
|
Aug 23 07:52:27 AM UTC 24 |
Aug 23 07:52:41 AM UTC 24 |
162066651 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.2639446797 |
|
|
Aug 23 07:52:09 AM UTC 24 |
Aug 23 07:53:16 AM UTC 24 |
3509145611 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.1380711247 |
|
|
Aug 23 07:45:04 AM UTC 24 |
Aug 23 07:53:17 AM UTC 24 |
14308555950 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.781784416 |
|
|
Aug 23 07:53:18 AM UTC 24 |
Aug 23 07:53:22 AM UTC 24 |
56682462 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.338944912 |
|
|
Aug 23 07:53:22 AM UTC 24 |
Aug 23 07:53:25 AM UTC 24 |
98116099 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2162724861 |
|
|
Aug 23 07:53:17 AM UTC 24 |
Aug 23 07:53:28 AM UTC 24 |
393406314 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.984291601 |
|
|
Aug 23 07:45:02 AM UTC 24 |
Aug 23 07:53:48 AM UTC 24 |
73576722577 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.4187135313 |
|
|
Aug 23 07:45:25 AM UTC 24 |
Aug 23 07:53:51 AM UTC 24 |
10973526628 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1149066453 |
|
|
Aug 23 07:53:51 AM UTC 24 |
Aug 23 07:53:53 AM UTC 24 |
28703452 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3040065064 |
|
|
Aug 23 07:47:18 AM UTC 24 |
Aug 23 07:53:57 AM UTC 24 |
2296769412 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.274141292 |
|
|
Aug 23 07:30:26 AM UTC 24 |
Aug 23 07:54:01 AM UTC 24 |
107012345302 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1207302549 |
|
|
Aug 23 07:53:54 AM UTC 24 |
Aug 23 07:54:05 AM UTC 24 |
751341666 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1130284992 |
|
|
Aug 23 07:53:58 AM UTC 24 |
Aug 23 07:54:05 AM UTC 24 |
401065693 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3467095858 |
|
|
Aug 23 07:54:06 AM UTC 24 |
Aug 23 07:54:07 AM UTC 24 |
17855578 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.2936022679 |
|
|
Aug 23 07:49:56 AM UTC 24 |
Aug 23 07:54:12 AM UTC 24 |
8061033557 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.4132590189 |
|
|
Aug 23 07:54:08 AM UTC 24 |
Aug 23 07:54:20 AM UTC 24 |
702983436 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.659131160 |
|
|
Aug 23 07:52:24 AM UTC 24 |
Aug 23 07:54:27 AM UTC 24 |
1506664276 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.339235543 |
|
|
Aug 23 07:46:52 AM UTC 24 |
Aug 23 07:54:28 AM UTC 24 |
74585602606 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.404803628 |
|
|
Aug 23 07:54:29 AM UTC 24 |
Aug 23 07:54:39 AM UTC 24 |
983189714 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.1010520267 |
|
|
Aug 23 07:43:54 AM UTC 24 |
Aug 23 07:54:56 AM UTC 24 |
16009351032 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.999435007 |
|
|
Aug 23 07:44:18 AM UTC 24 |
Aug 23 07:55:05 AM UTC 24 |
20169018327 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1894574365 |
|
|
Aug 23 07:54:21 AM UTC 24 |
Aug 23 07:55:07 AM UTC 24 |
8474218054 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.1431910055 |
|
|
Aug 23 07:55:07 AM UTC 24 |
Aug 23 07:55:16 AM UTC 24 |
1077689366 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.325323375 |
|
|
Aug 23 07:47:21 AM UTC 24 |
Aug 23 07:55:39 AM UTC 24 |
20410946481 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2385661326 |
|
|
Aug 23 07:54:57 AM UTC 24 |
Aug 23 07:55:44 AM UTC 24 |
298116464 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2344459000 |
|
|
Aug 23 07:49:00 AM UTC 24 |
Aug 23 07:55:53 AM UTC 24 |
58250505469 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.543538684 |
|
|
Aug 23 07:55:55 AM UTC 24 |
Aug 23 07:55:56 AM UTC 24 |
31354781 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.1352041722 |
|
|
Aug 23 07:43:54 AM UTC 24 |
Aug 23 07:55:59 AM UTC 24 |
36247375979 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1129800867 |
|
|
Aug 23 07:56:00 AM UTC 24 |
Aug 23 07:56:05 AM UTC 24 |
92325226 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2373531789 |
|
|
Aug 23 07:55:57 AM UTC 24 |
Aug 23 07:56:05 AM UTC 24 |
284471788 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3081862475 |
|
|
Aug 23 07:55:05 AM UTC 24 |
Aug 23 07:56:06 AM UTC 24 |
559168057 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1976099763 |
|
|
Aug 23 07:56:07 AM UTC 24 |
Aug 23 07:56:08 AM UTC 24 |
150103683 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3697034731 |
|
|
Aug 23 07:54:02 AM UTC 24 |
Aug 23 07:56:16 AM UTC 24 |
487721314 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.29257150 |
|
|
Aug 23 07:56:09 AM UTC 24 |
Aug 23 07:56:17 AM UTC 24 |
311908986 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1292338308 |
|
|
Aug 23 07:50:58 AM UTC 24 |
Aug 23 07:56:42 AM UTC 24 |
2161569674 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1650215540 |
|
|
Aug 23 07:28:19 AM UTC 24 |
Aug 23 07:56:42 AM UTC 24 |
127738896650 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3736768506 |
|
|
Aug 23 07:56:43 AM UTC 24 |
Aug 23 07:56:49 AM UTC 24 |
401551976 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3227408645 |
|
|
Aug 23 07:56:07 AM UTC 24 |
Aug 23 07:56:50 AM UTC 24 |
361859500 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3490009456 |
|
|
Aug 23 07:49:50 AM UTC 24 |
Aug 23 07:56:51 AM UTC 24 |
2606977746 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.2784579072 |
|
|
Aug 23 07:55:44 AM UTC 24 |
Aug 23 07:56:56 AM UTC 24 |
3570246634 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.4057764742 |
|
|
Aug 23 07:56:57 AM UTC 24 |
Aug 23 07:57:06 AM UTC 24 |
826759601 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1206760679 |
|
|
Aug 23 07:54:28 AM UTC 24 |
Aug 23 07:57:08 AM UTC 24 |
23718365602 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.4248036 |
|
|
Aug 23 07:56:17 AM UTC 24 |
Aug 23 07:57:11 AM UTC 24 |
5869109506 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1518348028 |
|
|
Aug 23 07:42:49 AM UTC 24 |
Aug 23 07:57:18 AM UTC 24 |
4898268662 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.193162889 |
|
|
Aug 23 07:57:19 AM UTC 24 |
Aug 23 07:57:20 AM UTC 24 |
102008104 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.463127739 |
|
|
Aug 23 07:56:50 AM UTC 24 |
Aug 23 07:57:25 AM UTC 24 |
417028701 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3521002897 |
|
|
Aug 23 07:57:21 AM UTC 24 |
Aug 23 07:57:27 AM UTC 24 |
1102910043 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.1663863967 |
|
|
Aug 23 07:57:26 AM UTC 24 |
Aug 23 07:57:32 AM UTC 24 |
195307742 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.3374531891 |
|
|
Aug 23 07:18:34 AM UTC 24 |
Aug 23 07:57:55 AM UTC 24 |
12319891421 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.66954467 |
|
|
Aug 23 07:57:56 AM UTC 24 |
Aug 23 07:57:57 AM UTC 24 |
43652956 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.2205079379 |
|
|
Aug 23 07:56:51 AM UTC 24 |
Aug 23 07:58:06 AM UTC 24 |
980735020 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.217503272 |
|
|
Aug 23 07:48:24 AM UTC 24 |
Aug 23 07:58:11 AM UTC 24 |
17813117020 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3266630616 |
|
|
Aug 23 07:52:42 AM UTC 24 |
Aug 23 07:58:38 AM UTC 24 |
16592267022 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.2673693687 |
|
|
Aug 23 07:49:59 AM UTC 24 |
Aug 23 07:58:45 AM UTC 24 |
8878770951 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2318085219 |
|
|
Aug 23 07:56:43 AM UTC 24 |
Aug 23 07:59:22 AM UTC 24 |
1794015142 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1698300438 |
|
|
Aug 23 07:14:51 AM UTC 24 |
Aug 23 07:59:38 AM UTC 24 |
97768451510 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2438535733 |
|
|
Aug 23 07:54:40 AM UTC 24 |
Aug 23 08:00:08 AM UTC 24 |
9371456502 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.115020069 |
|
|
Aug 23 07:08:51 AM UTC 24 |
Aug 23 08:00:14 AM UTC 24 |
82170732702 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.534762568 |
|
|
Aug 23 07:57:08 AM UTC 24 |
Aug 23 08:00:26 AM UTC 24 |
17590221621 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.830135819 |
|
|
Aug 23 07:57:06 AM UTC 24 |
Aug 23 08:00:58 AM UTC 24 |
8583369500 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.935699046 |
|
|
Aug 23 07:54:13 AM UTC 24 |
Aug 23 08:01:00 AM UTC 24 |
10042505910 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.2160129564 |
|
|
Aug 23 07:56:50 AM UTC 24 |
Aug 23 08:02:20 AM UTC 24 |
20564078028 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.2435796472 |
|
|
Aug 23 07:53:48 AM UTC 24 |
Aug 23 08:02:22 AM UTC 24 |
3204792002 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.2472769081 |
|
|
Aug 23 07:57:11 AM UTC 24 |
Aug 23 08:02:23 AM UTC 24 |
7645187148 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.4052660843 |
|
|
Aug 23 07:41:06 AM UTC 24 |
Aug 23 08:03:17 AM UTC 24 |
92503045814 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.4152316039 |
|
|
Aug 23 07:55:17 AM UTC 24 |
Aug 23 08:03:47 AM UTC 24 |
20697947936 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.268207241 |
|
|
Aug 23 07:51:53 AM UTC 24 |
Aug 23 08:06:05 AM UTC 24 |
3280462859 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.2843337947 |
|
|
Aug 23 07:56:17 AM UTC 24 |
Aug 23 08:06:22 AM UTC 24 |
13272763839 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.3373121144 |
|
|
Aug 23 07:48:01 AM UTC 24 |
Aug 23 08:07:26 AM UTC 24 |
7064113556 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.1326750323 |
|
|
Aug 23 07:53:29 AM UTC 24 |
Aug 23 08:08:12 AM UTC 24 |
50823926007 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3203435917 |
|
|
Aug 23 07:53:25 AM UTC 24 |
Aug 23 08:08:44 AM UTC 24 |
5274014205 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2162491714 |
|
|
Aug 23 07:56:07 AM UTC 24 |
Aug 23 08:09:00 AM UTC 24 |
10375331967 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3712361920 |
|
|
Aug 23 07:42:47 AM UTC 24 |
Aug 23 08:09:53 AM UTC 24 |
14535247404 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1050688569 |
|
|
Aug 23 07:54:06 AM UTC 24 |
Aug 23 08:10:21 AM UTC 24 |
71735615649 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1980858964 |
|
|
Aug 23 07:55:40 AM UTC 24 |
Aug 23 08:10:40 AM UTC 24 |
8837720596 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3092068016 |
|
|
Aug 23 07:37:12 AM UTC 24 |
Aug 23 08:14:02 AM UTC 24 |
164102303232 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1002028189 |
|
|
Aug 23 07:22:50 AM UTC 24 |
Aug 23 08:18:15 AM UTC 24 |
109000192215 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.352688670 |
|
|
Aug 23 07:51:02 AM UTC 24 |
Aug 23 08:29:36 AM UTC 24 |
20709923353 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1895518384 |
|
|
Aug 23 07:57:33 AM UTC 24 |
Aug 23 08:35:51 AM UTC 24 |
497540972260 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.780911925 |
|
|
Aug 23 07:45:16 AM UTC 24 |
Aug 23 08:45:03 AM UTC 24 |
326878604234 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.554628380 |
|
|
Aug 23 07:57:58 AM UTC 24 |
Aug 23 07:58:01 AM UTC 24 |
851965269 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1707072861 |
|
|
Aug 23 07:58:02 AM UTC 24 |
Aug 23 07:58:07 AM UTC 24 |
716353198 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.305243577 |
|
|
Aug 23 07:58:07 AM UTC 24 |
Aug 23 07:58:10 AM UTC 24 |
183003878 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1631003656 |
|
|
Aug 23 07:58:08 AM UTC 24 |
Aug 23 07:58:10 AM UTC 24 |
44131977 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3676292565 |
|
|
Aug 23 07:58:10 AM UTC 24 |
Aug 23 07:58:12 AM UTC 24 |
61086352 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2423655591 |
|
|
Aug 23 07:58:10 AM UTC 24 |
Aug 23 07:58:13 AM UTC 24 |
124214611 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2347356766 |
|
|
Aug 23 07:58:12 AM UTC 24 |
Aug 23 07:58:14 AM UTC 24 |
20474415 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1710386232 |
|
|
Aug 23 07:58:12 AM UTC 24 |
Aug 23 07:58:14 AM UTC 24 |
292138626 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.125236559 |
|
|
Aug 23 07:58:14 AM UTC 24 |
Aug 23 07:58:17 AM UTC 24 |
114492620 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.704155627 |
|
|
Aug 23 07:58:14 AM UTC 24 |
Aug 23 07:58:18 AM UTC 24 |
1048965733 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1758043431 |
|
|
Aug 23 07:58:19 AM UTC 24 |
Aug 23 07:58:20 AM UTC 24 |
26195030 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.326270968 |
|
|
Aug 23 07:58:14 AM UTC 24 |
Aug 23 07:58:21 AM UTC 24 |
233970131 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1174462701 |
|
|
Aug 23 07:58:18 AM UTC 24 |
Aug 23 07:58:21 AM UTC 24 |
487647098 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.120790297 |
|
|
Aug 23 07:58:21 AM UTC 24 |
Aug 23 07:58:22 AM UTC 24 |
43161222 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2612251350 |
|
|
Aug 23 07:58:22 AM UTC 24 |
Aug 23 07:58:24 AM UTC 24 |
28990838 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3676304888 |
|
|
Aug 23 07:58:23 AM UTC 24 |
Aug 23 07:58:25 AM UTC 24 |
33277587 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2082994015 |
|
|
Aug 23 07:58:22 AM UTC 24 |
Aug 23 07:58:25 AM UTC 24 |
122607819 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.296669578 |
|
|
Aug 23 07:58:25 AM UTC 24 |
Aug 23 07:58:27 AM UTC 24 |
37114697 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1831289701 |
|
|
Aug 23 07:58:25 AM UTC 24 |
Aug 23 07:58:28 AM UTC 24 |
237167979 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.580509248 |
|
|
Aug 23 07:59:08 AM UTC 24 |
Aug 23 07:59:10 AM UTC 24 |
13098105 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2817475664 |
|
|
Aug 23 07:58:26 AM UTC 24 |
Aug 23 07:58:30 AM UTC 24 |
170062570 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2971224202 |
|
|
Aug 23 07:58:29 AM UTC 24 |
Aug 23 07:58:31 AM UTC 24 |
25445178 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2167756 |
|
|
Aug 23 07:58:28 AM UTC 24 |
Aug 23 07:58:31 AM UTC 24 |
257381371 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1920553183 |
|
|
Aug 23 07:58:30 AM UTC 24 |
Aug 23 07:58:32 AM UTC 24 |
29834545 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2209294631 |
|
|
Aug 23 07:58:31 AM UTC 24 |
Aug 23 07:58:34 AM UTC 24 |
140874589 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3242692251 |
|
|
Aug 23 07:58:33 AM UTC 24 |
Aug 23 07:58:34 AM UTC 24 |
21438246 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3635515156 |
|
|
Aug 23 07:58:33 AM UTC 24 |
Aug 23 07:58:34 AM UTC 24 |
16052092 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3851072169 |
|
|
Aug 23 07:58:35 AM UTC 24 |
Aug 23 07:58:38 AM UTC 24 |
263022357 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1504272991 |
|
|
Aug 23 07:58:35 AM UTC 24 |
Aug 23 07:58:38 AM UTC 24 |
452025836 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3973880392 |
|
|
Aug 23 07:58:39 AM UTC 24 |
Aug 23 07:58:41 AM UTC 24 |
18020792 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2941310994 |
|
|
Aug 23 07:58:39 AM UTC 24 |
Aug 23 07:58:41 AM UTC 24 |
17191115 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2196961692 |
|
|
Aug 23 07:58:38 AM UTC 24 |
Aug 23 07:58:41 AM UTC 24 |
182003725 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2309474740 |
|
|
Aug 23 07:58:40 AM UTC 24 |
Aug 23 07:58:42 AM UTC 24 |
46910081 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2797204904 |
|
|
Aug 23 07:58:39 AM UTC 24 |
Aug 23 07:58:42 AM UTC 24 |
180501593 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1703509261 |
|
|
Aug 23 07:58:41 AM UTC 24 |
Aug 23 07:58:43 AM UTC 24 |
47160861 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1565572280 |
|
|
Aug 23 07:58:41 AM UTC 24 |
Aug 23 07:58:43 AM UTC 24 |
33052996 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1655578684 |
|
|
Aug 23 07:58:44 AM UTC 24 |
Aug 23 07:58:45 AM UTC 24 |
22272073 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2226789808 |
|
|
Aug 23 07:58:44 AM UTC 24 |
Aug 23 07:58:45 AM UTC 24 |
45594137 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4001455003 |
|
|
Aug 23 07:58:43 AM UTC 24 |
Aug 23 07:58:46 AM UTC 24 |
179022723 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.4191339811 |
|
|
Aug 23 07:58:43 AM UTC 24 |
Aug 23 07:58:47 AM UTC 24 |
681738604 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2585190338 |
|
|
Aug 23 07:58:43 AM UTC 24 |
Aug 23 07:58:47 AM UTC 24 |
1703712297 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1569248239 |
|
|
Aug 23 07:58:46 AM UTC 24 |
Aug 23 07:58:48 AM UTC 24 |
59379130 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2599817589 |
|
|
Aug 23 07:58:46 AM UTC 24 |
Aug 23 07:58:48 AM UTC 24 |
161681933 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.920224254 |
|
|
Aug 23 07:58:46 AM UTC 24 |
Aug 23 07:58:48 AM UTC 24 |
605920258 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3312670985 |
|
|
Aug 23 07:58:47 AM UTC 24 |
Aug 23 07:58:49 AM UTC 24 |
102038755 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2209334798 |
|
|
Aug 23 07:58:48 AM UTC 24 |
Aug 23 07:58:50 AM UTC 24 |
15835620 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3669962920 |
|
|
Aug 23 07:58:47 AM UTC 24 |
Aug 23 07:58:50 AM UTC 24 |
1040860651 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.383125536 |
|
|
Aug 23 07:58:48 AM UTC 24 |
Aug 23 07:58:51 AM UTC 24 |
577812748 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.414507012 |
|
|
Aug 23 07:58:50 AM UTC 24 |
Aug 23 07:58:52 AM UTC 24 |
20041187 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3946960634 |
|
|
Aug 23 07:58:48 AM UTC 24 |
Aug 23 07:58:52 AM UTC 24 |
32002938 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3228104071 |
|
|
Aug 23 07:58:50 AM UTC 24 |
Aug 23 07:58:52 AM UTC 24 |
33566455 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.249285968 |
|
|
Aug 23 07:58:52 AM UTC 24 |
Aug 23 07:58:54 AM UTC 24 |
36080832 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3777671053 |
|
|
Aug 23 07:58:51 AM UTC 24 |
Aug 23 07:58:55 AM UTC 24 |
413503803 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2927954271 |
|
|
Aug 23 07:58:53 AM UTC 24 |
Aug 23 07:58:55 AM UTC 24 |
30599138 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1062389898 |
|
|
Aug 23 07:58:52 AM UTC 24 |
Aug 23 07:58:55 AM UTC 24 |
355336936 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4061228239 |
|
|
Aug 23 07:58:51 AM UTC 24 |
Aug 23 07:58:56 AM UTC 24 |
42215820 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2569634126 |
|
|
Aug 23 07:58:53 AM UTC 24 |
Aug 23 07:58:57 AM UTC 24 |
153308935 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1908318740 |
|
|
Aug 23 07:58:57 AM UTC 24 |
Aug 23 07:58:59 AM UTC 24 |
14164636 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.972919750 |
|
|
Aug 23 07:58:57 AM UTC 24 |
Aug 23 07:58:59 AM UTC 24 |
32775120 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3579793615 |
|
|
Aug 23 07:58:55 AM UTC 24 |
Aug 23 07:58:59 AM UTC 24 |
369180813 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.272094162 |
|
|
Aug 23 07:58:54 AM UTC 24 |
Aug 23 07:58:59 AM UTC 24 |
979149654 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2271626847 |
|
|
Aug 23 07:58:55 AM UTC 24 |
Aug 23 07:59:00 AM UTC 24 |
35990106 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1017557039 |
|
|
Aug 23 07:58:58 AM UTC 24 |
Aug 23 07:59:01 AM UTC 24 |
70601925 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.642119521 |
|
|
Aug 23 07:59:00 AM UTC 24 |
Aug 23 07:59:02 AM UTC 24 |
17636111 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3764768481 |
|
|
Aug 23 07:59:00 AM UTC 24 |
Aug 23 07:59:02 AM UTC 24 |
65063455 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2512246573 |
|
|
Aug 23 07:58:59 AM UTC 24 |
Aug 23 07:59:02 AM UTC 24 |
433084773 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2543018267 |
|
|
Aug 23 07:59:00 AM UTC 24 |
Aug 23 07:59:03 AM UTC 24 |
261507222 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1578332346 |
|
|
Aug 23 07:59:01 AM UTC 24 |
Aug 23 07:59:04 AM UTC 24 |
145279860 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.670399305 |
|
|
Aug 23 07:59:00 AM UTC 24 |
Aug 23 07:59:05 AM UTC 24 |
116881385 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1162998312 |
|
|
Aug 23 07:59:04 AM UTC 24 |
Aug 23 07:59:06 AM UTC 24 |
31887812 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.553076015 |
|
|
Aug 23 07:59:03 AM UTC 24 |
Aug 23 07:59:06 AM UTC 24 |
195098267 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1190371853 |
|
|
Aug 23 07:59:04 AM UTC 24 |
Aug 23 07:59:06 AM UTC 24 |
222610058 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4023730846 |
|
|
Aug 23 07:59:03 AM UTC 24 |
Aug 23 07:59:07 AM UTC 24 |
151602499 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3327832359 |
|
|
Aug 23 07:59:05 AM UTC 24 |
Aug 23 07:59:07 AM UTC 24 |
37444092 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4208324118 |
|
|
Aug 23 07:59:06 AM UTC 24 |
Aug 23 07:59:08 AM UTC 24 |
102770568 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3806292403 |
|
|
Aug 23 07:59:08 AM UTC 24 |
Aug 23 07:59:10 AM UTC 24 |
13375946 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.473372957 |
|
|
Aug 23 07:59:06 AM UTC 24 |
Aug 23 07:59:10 AM UTC 24 |
237579002 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1379281770 |
|
|
Aug 23 07:59:06 AM UTC 24 |
Aug 23 07:59:11 AM UTC 24 |
1624161557 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2763297310 |
|
|
Aug 23 07:59:08 AM UTC 24 |
Aug 23 07:59:11 AM UTC 24 |
717245858 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1577650008 |
|
|
Aug 23 07:59:09 AM UTC 24 |
Aug 23 07:59:12 AM UTC 24 |
142585854 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3905685626 |
|
|
Aug 23 07:59:10 AM UTC 24 |
Aug 23 07:59:13 AM UTC 24 |
76592537 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1125136653 |
|
|
Aug 23 07:59:12 AM UTC 24 |
Aug 23 07:59:14 AM UTC 24 |
108606554 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3739677577 |
|
|
Aug 23 07:59:12 AM UTC 24 |
Aug 23 07:59:14 AM UTC 24 |
79842558 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.262183101 |
|
|
Aug 23 07:59:13 AM UTC 24 |
Aug 23 07:59:15 AM UTC 24 |
42987187 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2631184906 |
|
|
Aug 23 07:59:10 AM UTC 24 |
Aug 23 07:59:17 AM UTC 24 |
163959103 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1836309596 |
|
|
Aug 23 07:59:14 AM UTC 24 |
Aug 23 07:59:18 AM UTC 24 |
186688247 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2573048973 |
|
|
Aug 23 07:59:16 AM UTC 24 |
Aug 23 07:59:18 AM UTC 24 |
26430405 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3774018054 |
|
|
Aug 23 07:59:14 AM UTC 24 |
Aug 23 07:59:19 AM UTC 24 |
3501731114 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3380131904 |
|
|
Aug 23 07:59:18 AM UTC 24 |
Aug 23 07:59:19 AM UTC 24 |
28613383 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1965880951 |
|
|
Aug 23 07:59:10 AM UTC 24 |
Aug 23 07:59:20 AM UTC 24 |
2093135489 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3285399026 |
|
|
Aug 23 07:59:14 AM UTC 24 |
Aug 23 07:59:20 AM UTC 24 |
130098321 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1660364232 |
|
|
Aug 23 07:59:19 AM UTC 24 |
Aug 23 07:59:21 AM UTC 24 |
46276348 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2756949383 |
|
|
Aug 23 07:59:19 AM UTC 24 |
Aug 23 07:59:22 AM UTC 24 |
207823139 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2198835679 |
|
|
Aug 23 07:59:22 AM UTC 24 |
Aug 23 07:59:23 AM UTC 24 |
13320654 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1432366525 |
|
|
Aug 23 07:59:20 AM UTC 24 |
Aug 23 07:59:23 AM UTC 24 |
289437311 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2073938765 |
|
|
Aug 23 07:59:22 AM UTC 24 |
Aug 23 07:59:23 AM UTC 24 |
40974573 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3064852802 |
|
|
Aug 23 07:59:22 AM UTC 24 |
Aug 23 07:59:24 AM UTC 24 |
36265836 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2674828523 |
|
|
Aug 23 07:59:20 AM UTC 24 |
Aug 23 07:59:25 AM UTC 24 |
712225674 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3370523210 |
|
|
Aug 23 07:59:23 AM UTC 24 |
Aug 23 07:59:26 AM UTC 24 |
1501252392 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3112022659 |
|
|
Aug 23 07:59:24 AM UTC 24 |
Aug 23 07:59:26 AM UTC 24 |
23273150 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1323460101 |
|
|
Aug 23 07:59:25 AM UTC 24 |
Aug 23 07:59:26 AM UTC 24 |
14352125 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1845678171 |
|
|
Aug 23 07:59:23 AM UTC 24 |
Aug 23 07:59:26 AM UTC 24 |
65630256 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.687593685 |
|
|
Aug 23 07:59:25 AM UTC 24 |
Aug 23 07:59:26 AM UTC 24 |
57409562 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1288802654 |
|
|
Aug 23 07:59:24 AM UTC 24 |
Aug 23 07:59:27 AM UTC 24 |
435061789 ps |