| T545 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3226279753 |
|
|
Aug 23 07:14:38 AM UTC 24 |
Aug 23 07:14:40 AM UTC 24 |
78332088 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1950208292 |
|
|
Aug 23 07:09:16 AM UTC 24 |
Aug 23 07:14:40 AM UTC 24 |
6384958161 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2982828976 |
|
|
Aug 23 07:14:41 AM UTC 24 |
Aug 23 07:14:45 AM UTC 24 |
193019866 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2093667714 |
|
|
Aug 23 07:14:40 AM UTC 24 |
Aug 23 07:14:50 AM UTC 24 |
449911946 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.1333656529 |
|
|
Aug 23 07:14:06 AM UTC 24 |
Aug 23 07:15:08 AM UTC 24 |
5844369787 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2892416064 |
|
|
Aug 23 07:15:09 AM UTC 24 |
Aug 23 07:15:11 AM UTC 24 |
23806395 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.3743238810 |
|
|
Aug 23 07:15:11 AM UTC 24 |
Aug 23 07:15:14 AM UTC 24 |
67138252 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1291567930 |
|
|
Aug 23 07:11:50 AM UTC 24 |
Aug 23 07:15:28 AM UTC 24 |
7961656860 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.1339193858 |
|
|
Aug 23 07:03:56 AM UTC 24 |
Aug 23 07:16:11 AM UTC 24 |
91389745425 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3541719918 |
|
|
Aug 23 07:11:04 AM UTC 24 |
Aug 23 07:16:23 AM UTC 24 |
2139935339 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.2164304073 |
|
|
Aug 23 07:15:30 AM UTC 24 |
Aug 23 07:16:26 AM UTC 24 |
15314978710 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.3888927419 |
|
|
Aug 23 07:12:30 AM UTC 24 |
Aug 23 07:16:45 AM UTC 24 |
70774178752 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3772508517 |
|
|
Aug 23 07:16:24 AM UTC 24 |
Aug 23 07:17:18 AM UTC 24 |
839552518 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2335252472 |
|
|
Aug 23 07:16:46 AM UTC 24 |
Aug 23 07:17:37 AM UTC 24 |
776960237 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.885103604 |
|
|
Aug 23 07:17:19 AM UTC 24 |
Aug 23 07:17:38 AM UTC 24 |
107409744 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.1292153182 |
|
|
Aug 23 07:17:37 AM UTC 24 |
Aug 23 07:17:40 AM UTC 24 |
133103365 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.119908651 |
|
|
Aug 23 07:03:56 AM UTC 24 |
Aug 23 07:17:49 AM UTC 24 |
55635755878 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.348976463 |
|
|
Aug 23 07:07:30 AM UTC 24 |
Aug 23 07:18:20 AM UTC 24 |
3017251392 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3614608951 |
|
|
Aug 23 07:10:41 AM UTC 24 |
Aug 23 07:18:20 AM UTC 24 |
72793703582 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.362595324 |
|
|
Aug 23 07:18:21 AM UTC 24 |
Aug 23 07:18:23 AM UTC 24 |
109196701 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1636984318 |
|
|
Aug 23 07:18:25 AM UTC 24 |
Aug 23 07:18:31 AM UTC 24 |
351268634 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.686033917 |
|
|
Aug 23 07:18:21 AM UTC 24 |
Aug 23 07:18:32 AM UTC 24 |
925333937 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.2495157332 |
|
|
Aug 23 07:01:56 AM UTC 24 |
Aug 23 07:18:39 AM UTC 24 |
23660442105 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.744540097 |
|
|
Aug 23 07:18:40 AM UTC 24 |
Aug 23 07:18:41 AM UTC 24 |
18025392 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3134374428 |
|
|
Aug 23 06:51:27 AM UTC 24 |
Aug 23 07:18:47 AM UTC 24 |
74616509202 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2849309931 |
|
|
Aug 23 07:18:42 AM UTC 24 |
Aug 23 07:18:59 AM UTC 24 |
4080660274 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.1436851298 |
|
|
Aug 23 07:04:56 AM UTC 24 |
Aug 23 07:19:12 AM UTC 24 |
14700172822 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.4186374402 |
|
|
Aug 23 07:01:43 AM UTC 24 |
Aug 23 07:19:45 AM UTC 24 |
93521615850 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1239669064 |
|
|
Aug 23 07:19:46 AM UTC 24 |
Aug 23 07:19:53 AM UTC 24 |
429947625 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.790245140 |
|
|
Aug 23 07:19:00 AM UTC 24 |
Aug 23 07:19:59 AM UTC 24 |
1027542207 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.321203323 |
|
|
Aug 23 07:20:00 AM UTC 24 |
Aug 23 07:20:15 AM UTC 24 |
424136368 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.951928480 |
|
|
Aug 23 06:45:08 AM UTC 24 |
Aug 23 07:20:27 AM UTC 24 |
252891553184 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3617717257 |
|
|
Aug 23 07:14:46 AM UTC 24 |
Aug 23 07:20:31 AM UTC 24 |
1503626338 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.1592163576 |
|
|
Aug 23 07:20:28 AM UTC 24 |
Aug 23 07:20:37 AM UTC 24 |
1433366055 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.3084002747 |
|
|
Aug 23 07:17:40 AM UTC 24 |
Aug 23 07:20:40 AM UTC 24 |
4764501797 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2042977369 |
|
|
Aug 23 06:56:41 AM UTC 24 |
Aug 23 07:20:54 AM UTC 24 |
103689319454 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3621493336 |
|
|
Aug 23 07:20:55 AM UTC 24 |
Aug 23 07:20:56 AM UTC 24 |
28049739 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.398391271 |
|
|
Aug 23 07:20:57 AM UTC 24 |
Aug 23 07:21:03 AM UTC 24 |
378251461 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.890051573 |
|
|
Aug 23 07:20:16 AM UTC 24 |
Aug 23 07:21:06 AM UTC 24 |
139055639 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.3956816111 |
|
|
Aug 23 07:21:04 AM UTC 24 |
Aug 23 07:21:08 AM UTC 24 |
496094631 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.67591005 |
|
|
Aug 23 07:20:37 AM UTC 24 |
Aug 23 07:21:13 AM UTC 24 |
8228336947 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2197574282 |
|
|
Aug 23 07:21:14 AM UTC 24 |
Aug 23 07:21:15 AM UTC 24 |
29949667 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3565366054 |
|
|
Aug 23 07:21:07 AM UTC 24 |
Aug 23 07:21:19 AM UTC 24 |
257852479 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.426977153 |
|
|
Aug 23 07:21:16 AM UTC 24 |
Aug 23 07:21:22 AM UTC 24 |
117596170 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.1194371871 |
|
|
Aug 23 06:57:47 AM UTC 24 |
Aug 23 07:21:35 AM UTC 24 |
20270796897 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.2803842859 |
|
|
Aug 23 07:11:08 AM UTC 24 |
Aug 23 07:21:40 AM UTC 24 |
18456169082 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.2880169562 |
|
|
Aug 23 07:16:27 AM UTC 24 |
Aug 23 07:21:41 AM UTC 24 |
9517119225 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.3819467301 |
|
|
Aug 23 07:13:28 AM UTC 24 |
Aug 23 07:21:51 AM UTC 24 |
3169902181 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1333415385 |
|
|
Aug 23 07:16:13 AM UTC 24 |
Aug 23 07:21:52 AM UTC 24 |
7437836134 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2424972666 |
|
|
Aug 23 07:21:51 AM UTC 24 |
Aug 23 07:21:57 AM UTC 24 |
103773094 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.124299612 |
|
|
Aug 23 07:21:59 AM UTC 24 |
Aug 23 07:22:02 AM UTC 24 |
674822619 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3399191054 |
|
|
Aug 23 07:18:32 AM UTC 24 |
Aug 23 07:22:11 AM UTC 24 |
1651046802 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3581708044 |
|
|
Aug 23 07:21:41 AM UTC 24 |
Aug 23 07:22:27 AM UTC 24 |
775438097 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1357906776 |
|
|
Aug 23 07:19:13 AM UTC 24 |
Aug 23 07:22:42 AM UTC 24 |
2375197685 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.974475537 |
|
|
Aug 23 06:59:50 AM UTC 24 |
Aug 23 07:22:43 AM UTC 24 |
77724096361 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.534552440 |
|
|
Aug 23 07:22:43 AM UTC 24 |
Aug 23 07:22:45 AM UTC 24 |
89495339 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.2246858211 |
|
|
Aug 23 07:21:22 AM UTC 24 |
Aug 23 07:22:47 AM UTC 24 |
54046903993 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.355749015 |
|
|
Aug 23 07:21:52 AM UTC 24 |
Aug 23 07:22:49 AM UTC 24 |
590054620 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2541295677 |
|
|
Aug 23 07:22:44 AM UTC 24 |
Aug 23 07:22:50 AM UTC 24 |
920572511 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1545391684 |
|
|
Aug 23 07:15:14 AM UTC 24 |
Aug 23 07:22:51 AM UTC 24 |
11239991318 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.875890459 |
|
|
Aug 23 07:22:45 AM UTC 24 |
Aug 23 07:22:51 AM UTC 24 |
172560354 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1895826493 |
|
|
Aug 23 07:22:51 AM UTC 24 |
Aug 23 07:22:53 AM UTC 24 |
12129640 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.2684019190 |
|
|
Aug 23 07:19:53 AM UTC 24 |
Aug 23 07:22:57 AM UTC 24 |
11634794689 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.272332643 |
|
|
Aug 23 07:22:51 AM UTC 24 |
Aug 23 07:23:08 AM UTC 24 |
3156474069 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1142297805 |
|
|
Aug 23 07:23:09 AM UTC 24 |
Aug 23 07:23:12 AM UTC 24 |
79168768 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_regwen.699935044 |
|
|
Aug 23 07:20:41 AM UTC 24 |
Aug 23 07:23:15 AM UTC 24 |
3045601026 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1876596394 |
|
|
Aug 23 07:06:56 AM UTC 24 |
Aug 23 07:23:21 AM UTC 24 |
5472664122 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.617912702 |
|
|
Aug 23 07:23:22 AM UTC 24 |
Aug 23 07:23:24 AM UTC 24 |
149948695 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3419163934 |
|
|
Aug 23 07:23:25 AM UTC 24 |
Aug 23 07:23:28 AM UTC 24 |
517332374 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1939280323 |
|
|
Aug 23 07:23:16 AM UTC 24 |
Aug 23 07:23:35 AM UTC 24 |
95148245 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.1673391008 |
|
|
Aug 23 07:22:53 AM UTC 24 |
Aug 23 07:23:54 AM UTC 24 |
1051269307 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1485101029 |
|
|
Aug 23 07:22:48 AM UTC 24 |
Aug 23 07:24:26 AM UTC 24 |
11438010853 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2883149900 |
|
|
Aug 23 07:24:26 AM UTC 24 |
Aug 23 07:24:28 AM UTC 24 |
91591439 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3978395430 |
|
|
Aug 23 07:21:36 AM UTC 24 |
Aug 23 07:24:34 AM UTC 24 |
4329830634 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3441431033 |
|
|
Aug 23 07:24:28 AM UTC 24 |
Aug 23 07:24:35 AM UTC 24 |
349995854 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3633463190 |
|
|
Aug 23 07:24:35 AM UTC 24 |
Aug 23 07:24:41 AM UTC 24 |
92460877 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.4079975277 |
|
|
Aug 23 07:20:31 AM UTC 24 |
Aug 23 07:24:53 AM UTC 24 |
5029110276 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.1614737448 |
|
|
Aug 23 07:24:53 AM UTC 24 |
Aug 23 07:24:55 AM UTC 24 |
14981862 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.3390297575 |
|
|
Aug 23 07:24:55 AM UTC 24 |
Aug 23 07:25:04 AM UTC 24 |
381112451 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.4067707240 |
|
|
Aug 23 07:02:18 AM UTC 24 |
Aug 23 07:25:07 AM UTC 24 |
57521826041 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.2679616598 |
|
|
Aug 23 07:25:07 AM UTC 24 |
Aug 23 07:25:29 AM UTC 24 |
2150899133 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.1039208788 |
|
|
Aug 23 07:11:15 AM UTC 24 |
Aug 23 07:25:29 AM UTC 24 |
64550038977 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.622990564 |
|
|
Aug 23 06:32:55 AM UTC 24 |
Aug 23 07:25:31 AM UTC 24 |
26410976286 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1377083688 |
|
|
Aug 23 06:58:45 AM UTC 24 |
Aug 23 07:25:37 AM UTC 24 |
141026288746 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.226845297 |
|
|
Aug 23 07:21:20 AM UTC 24 |
Aug 23 07:25:38 AM UTC 24 |
13121588749 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.531385378 |
|
|
Aug 23 07:25:30 AM UTC 24 |
Aug 23 07:25:42 AM UTC 24 |
111728961 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.803269759 |
|
|
Aug 23 07:25:43 AM UTC 24 |
Aug 23 07:25:49 AM UTC 24 |
739362225 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1763452379 |
|
|
Aug 23 07:25:39 AM UTC 24 |
Aug 23 07:25:51 AM UTC 24 |
160065401 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2191857745 |
|
|
Aug 23 07:18:48 AM UTC 24 |
Aug 23 07:26:00 AM UTC 24 |
33988878927 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2972741609 |
|
|
Aug 23 07:25:38 AM UTC 24 |
Aug 23 07:26:09 AM UTC 24 |
114917254 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.4114085141 |
|
|
Aug 23 07:26:10 AM UTC 24 |
Aug 23 07:26:12 AM UTC 24 |
45377497 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1361650122 |
|
|
Aug 23 07:26:12 AM UTC 24 |
Aug 23 07:26:18 AM UTC 24 |
188914832 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1769553640 |
|
|
Aug 23 07:26:19 AM UTC 24 |
Aug 23 07:26:24 AM UTC 24 |
291635906 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2158613077 |
|
|
Aug 23 07:22:52 AM UTC 24 |
Aug 23 07:26:40 AM UTC 24 |
6459794722 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.3063296731 |
|
|
Aug 23 07:22:28 AM UTC 24 |
Aug 23 07:26:43 AM UTC 24 |
13521116834 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3847014185 |
|
|
Aug 23 07:26:43 AM UTC 24 |
Aug 23 07:26:45 AM UTC 24 |
12882650 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.1528604085 |
|
|
Aug 23 07:21:42 AM UTC 24 |
Aug 23 07:26:49 AM UTC 24 |
12630379575 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.4136884678 |
|
|
Aug 23 07:26:45 AM UTC 24 |
Aug 23 07:27:01 AM UTC 24 |
2650251286 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.2902151015 |
|
|
Aug 23 07:25:04 AM UTC 24 |
Aug 23 07:27:19 AM UTC 24 |
11894706389 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.3608245806 |
|
|
Aug 23 07:27:02 AM UTC 24 |
Aug 23 07:27:23 AM UTC 24 |
1361279986 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.234726330 |
|
|
Aug 23 07:27:24 AM UTC 24 |
Aug 23 07:27:33 AM UTC 24 |
2462178857 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.1091839747 |
|
|
Aug 23 07:22:58 AM UTC 24 |
Aug 23 07:27:37 AM UTC 24 |
5918617193 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.124557871 |
|
|
Aug 23 07:27:38 AM UTC 24 |
Aug 23 07:27:40 AM UTC 24 |
391648729 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.1328166002 |
|
|
Aug 23 07:17:49 AM UTC 24 |
Aug 23 07:27:48 AM UTC 24 |
2269583984 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.2046778235 |
|
|
Aug 23 07:27:41 AM UTC 24 |
Aug 23 07:27:51 AM UTC 24 |
80583758 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.314438760 |
|
|
Aug 23 07:27:48 AM UTC 24 |
Aug 23 07:27:53 AM UTC 24 |
309577158 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.207658972 |
|
|
Aug 23 07:25:51 AM UTC 24 |
Aug 23 07:27:53 AM UTC 24 |
5618839868 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.4077195680 |
|
|
Aug 23 07:00:11 AM UTC 24 |
Aug 23 07:28:01 AM UTC 24 |
130946860142 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2181670545 |
|
|
Aug 23 07:28:02 AM UTC 24 |
Aug 23 07:28:04 AM UTC 24 |
84407530 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3823638227 |
|
|
Aug 23 07:28:04 AM UTC 24 |
Aug 23 07:28:13 AM UTC 24 |
656372500 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2042773590 |
|
|
Aug 23 06:46:10 AM UTC 24 |
Aug 23 07:28:15 AM UTC 24 |
24739252143 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.937485520 |
|
|
Aug 23 07:28:13 AM UTC 24 |
Aug 23 07:28:17 AM UTC 24 |
101169356 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.4182701109 |
|
|
Aug 23 07:25:30 AM UTC 24 |
Aug 23 07:28:43 AM UTC 24 |
2204433558 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.77091006 |
|
|
Aug 23 07:23:13 AM UTC 24 |
Aug 23 07:28:44 AM UTC 24 |
48574732872 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.2505035465 |
|
|
Aug 23 07:28:44 AM UTC 24 |
Aug 23 07:28:45 AM UTC 24 |
11300228 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.2129032663 |
|
|
Aug 23 07:28:45 AM UTC 24 |
Aug 23 07:28:52 AM UTC 24 |
126999946 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3741786200 |
|
|
Aug 23 07:26:25 AM UTC 24 |
Aug 23 07:29:09 AM UTC 24 |
2285033387 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3339175394 |
|
|
Aug 23 07:25:32 AM UTC 24 |
Aug 23 07:29:10 AM UTC 24 |
33785374991 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.3472581397 |
|
|
Aug 23 07:29:11 AM UTC 24 |
Aug 23 07:29:18 AM UTC 24 |
149026558 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3683620509 |
|
|
Aug 23 07:24:36 AM UTC 24 |
Aug 23 07:29:21 AM UTC 24 |
3601497119 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.1588344037 |
|
|
Aug 23 07:28:53 AM UTC 24 |
Aug 23 07:29:22 AM UTC 24 |
6016553583 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.73958366 |
|
|
Aug 23 07:29:22 AM UTC 24 |
Aug 23 07:29:28 AM UTC 24 |
634116837 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2941466743 |
|
|
Aug 23 07:29:29 AM UTC 24 |
Aug 23 07:29:40 AM UTC 24 |
1161417362 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2008053809 |
|
|
Aug 23 07:13:21 AM UTC 24 |
Aug 23 07:29:40 AM UTC 24 |
7662751423 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1995587355 |
|
|
Aug 23 07:27:20 AM UTC 24 |
Aug 23 07:29:51 AM UTC 24 |
6555173912 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.3850834362 |
|
|
Aug 23 07:29:21 AM UTC 24 |
Aug 23 07:30:07 AM UTC 24 |
122994283 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1526047286 |
|
|
Aug 23 07:30:08 AM UTC 24 |
Aug 23 07:30:09 AM UTC 24 |
48511533 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.4202937445 |
|
|
Aug 23 07:27:54 AM UTC 24 |
Aug 23 07:30:18 AM UTC 24 |
713216940 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.4291730997 |
|
|
Aug 23 07:30:10 AM UTC 24 |
Aug 23 07:30:20 AM UTC 24 |
786906833 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2423689902 |
|
|
Aug 23 07:30:19 AM UTC 24 |
Aug 23 07:30:25 AM UTC 24 |
183088778 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1918491612 |
|
|
Aug 23 07:30:21 AM UTC 24 |
Aug 23 07:30:31 AM UTC 24 |
606543911 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.3881840945 |
|
|
Aug 23 07:30:32 AM UTC 24 |
Aug 23 07:30:34 AM UTC 24 |
22052868 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.830380585 |
|
|
Aug 23 07:22:12 AM UTC 24 |
Aug 23 07:30:34 AM UTC 24 |
16688536159 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.4193583167 |
|
|
Aug 23 07:27:34 AM UTC 24 |
Aug 23 07:30:35 AM UTC 24 |
69096909863 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2571483455 |
|
|
Aug 23 07:04:15 AM UTC 24 |
Aug 23 07:30:36 AM UTC 24 |
22024208555 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.833717368 |
|
|
Aug 23 07:17:39 AM UTC 24 |
Aug 23 07:30:40 AM UTC 24 |
29876962084 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.4180880569 |
|
|
Aug 23 07:22:03 AM UTC 24 |
Aug 23 07:30:46 AM UTC 24 |
7005953107 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3065023204 |
|
|
Aug 23 07:30:40 AM UTC 24 |
Aug 23 07:30:57 AM UTC 24 |
1745788864 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.1163729899 |
|
|
Aug 23 07:23:36 AM UTC 24 |
Aug 23 07:31:03 AM UTC 24 |
22136472143 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.1584395622 |
|
|
Aug 23 07:30:35 AM UTC 24 |
Aug 23 07:31:12 AM UTC 24 |
571214372 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.3916576282 |
|
|
Aug 23 07:30:36 AM UTC 24 |
Aug 23 07:31:14 AM UTC 24 |
6715493793 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1454204441 |
|
|
Aug 23 07:31:14 AM UTC 24 |
Aug 23 07:31:19 AM UTC 24 |
1472478157 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4184300176 |
|
|
Aug 23 07:31:04 AM UTC 24 |
Aug 23 07:31:19 AM UTC 24 |
185847823 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.276114971 |
|
|
Aug 23 07:26:01 AM UTC 24 |
Aug 23 07:31:41 AM UTC 24 |
6835996794 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1566600991 |
|
|
Aug 23 07:31:42 AM UTC 24 |
Aug 23 07:31:44 AM UTC 24 |
29274256 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.3222580721 |
|
|
Aug 23 07:31:44 AM UTC 24 |
Aug 23 07:31:55 AM UTC 24 |
490357285 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1019766553 |
|
|
Aug 23 07:30:58 AM UTC 24 |
Aug 23 07:32:00 AM UTC 24 |
262186885 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.759027141 |
|
|
Aug 23 07:31:56 AM UTC 24 |
Aug 23 07:32:02 AM UTC 24 |
97329688 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.2379347440 |
|
|
Aug 23 07:29:41 AM UTC 24 |
Aug 23 07:33:25 AM UTC 24 |
16002746439 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3924970858 |
|
|
Aug 23 07:33:27 AM UTC 24 |
Aug 23 07:33:28 AM UTC 24 |
88078763 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3214687460 |
|
|
Aug 23 07:28:15 AM UTC 24 |
Aug 23 07:33:56 AM UTC 24 |
10002499339 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.2906631681 |
|
|
Aug 23 07:29:10 AM UTC 24 |
Aug 23 07:33:56 AM UTC 24 |
3525818994 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.814861874 |
|
|
Aug 23 07:33:29 AM UTC 24 |
Aug 23 07:33:56 AM UTC 24 |
522921745 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.3720733335 |
|
|
Aug 23 07:30:37 AM UTC 24 |
Aug 23 07:34:08 AM UTC 24 |
14294817107 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1944638774 |
|
|
Aug 23 07:34:09 AM UTC 24 |
Aug 23 07:34:13 AM UTC 24 |
507278971 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.530887984 |
|
|
Aug 23 07:28:46 AM UTC 24 |
Aug 23 07:34:20 AM UTC 24 |
80715476117 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.3523672569 |
|
|
Aug 23 07:23:55 AM UTC 24 |
Aug 23 07:34:27 AM UTC 24 |
20000075763 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2637637949 |
|
|
Aug 23 07:34:27 AM UTC 24 |
Aug 23 07:34:34 AM UTC 24 |
213870085 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.505449503 |
|
|
Aug 23 07:33:57 AM UTC 24 |
Aug 23 07:34:35 AM UTC 24 |
634594537 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.2390652281 |
|
|
Aug 23 07:21:08 AM UTC 24 |
Aug 23 07:34:35 AM UTC 24 |
19218417648 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1160254470 |
|
|
Aug 23 07:34:34 AM UTC 24 |
Aug 23 07:34:39 AM UTC 24 |
1067337742 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.4074145394 |
|
|
Aug 23 07:34:21 AM UTC 24 |
Aug 23 07:34:57 AM UTC 24 |
1217026452 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.960611592 |
|
|
Aug 23 07:34:57 AM UTC 24 |
Aug 23 07:34:59 AM UTC 24 |
46886309 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.1134157676 |
|
|
Aug 23 07:34:59 AM UTC 24 |
Aug 23 07:35:06 AM UTC 24 |
335407982 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1928927113 |
|
|
Aug 23 07:26:50 AM UTC 24 |
Aug 23 07:35:06 AM UTC 24 |
4766762745 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.4117713328 |
|
|
Aug 23 07:35:06 AM UTC 24 |
Aug 23 07:35:13 AM UTC 24 |
683669500 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.4025442081 |
|
|
Aug 23 07:31:20 AM UTC 24 |
Aug 23 07:35:17 AM UTC 24 |
7000777876 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3956934757 |
|
|
Aug 23 07:35:18 AM UTC 24 |
Aug 23 07:35:19 AM UTC 24 |
26414452 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2597307131 |
|
|
Aug 23 07:30:35 AM UTC 24 |
Aug 23 07:35:30 AM UTC 24 |
11546234541 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.4264104068 |
|
|
Aug 23 07:35:20 AM UTC 24 |
Aug 23 07:35:37 AM UTC 24 |
4405979493 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.4104381485 |
|
|
Aug 23 07:29:19 AM UTC 24 |
Aug 23 07:35:40 AM UTC 24 |
15992113133 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.3261866332 |
|
|
Aug 23 07:31:21 AM UTC 24 |
Aug 23 07:35:55 AM UTC 24 |
2557147617 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1026248489 |
|
|
Aug 23 07:35:08 AM UTC 24 |
Aug 23 07:35:57 AM UTC 24 |
8115399453 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.2254186832 |
|
|
Aug 23 07:35:38 AM UTC 24 |
Aug 23 07:36:08 AM UTC 24 |
3048257752 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1737886884 |
|
|
Aug 23 07:30:47 AM UTC 24 |
Aug 23 07:36:18 AM UTC 24 |
18854712653 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.4174867710 |
|
|
Aug 23 07:36:18 AM UTC 24 |
Aug 23 07:36:22 AM UTC 24 |
719605229 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.157054944 |
|
|
Aug 23 07:27:51 AM UTC 24 |
Aug 23 07:36:22 AM UTC 24 |
2751703693 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2933221053 |
|
|
Aug 23 07:36:23 AM UTC 24 |
Aug 23 07:36:31 AM UTC 24 |
796830960 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2403676666 |
|
|
Aug 23 07:35:56 AM UTC 24 |
Aug 23 07:36:49 AM UTC 24 |
611554225 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.467143201 |
|
|
Aug 23 07:36:08 AM UTC 24 |
Aug 23 07:36:54 AM UTC 24 |
486062584 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3710094993 |
|
|
Aug 23 07:36:55 AM UTC 24 |
Aug 23 07:36:57 AM UTC 24 |
42422495 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3948554334 |
|
|
Aug 23 07:36:58 AM UTC 24 |
Aug 23 07:37:03 AM UTC 24 |
235581289 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2069225408 |
|
|
Aug 23 07:37:04 AM UTC 24 |
Aug 23 07:37:10 AM UTC 24 |
598099889 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.47893999 |
|
|
Aug 23 07:24:42 AM UTC 24 |
Aug 23 07:37:11 AM UTC 24 |
19924648803 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.1180979497 |
|
|
Aug 23 07:34:35 AM UTC 24 |
Aug 23 07:37:33 AM UTC 24 |
5385208224 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3540347583 |
|
|
Aug 23 07:37:34 AM UTC 24 |
Aug 23 07:37:35 AM UTC 24 |
15718279 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1529537295 |
|
|
Aug 23 07:23:29 AM UTC 24 |
Aug 23 07:37:46 AM UTC 24 |
3985981463 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.4184602334 |
|
|
Aug 23 07:25:50 AM UTC 24 |
Aug 23 07:38:13 AM UTC 24 |
42196123871 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.3373622247 |
|
|
Aug 23 07:37:36 AM UTC 24 |
Aug 23 07:38:30 AM UTC 24 |
145161034 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3107549367 |
|
|
Aug 23 07:34:35 AM UTC 24 |
Aug 23 07:38:44 AM UTC 24 |
678468582 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.604745319 |
|
|
Aug 23 07:35:41 AM UTC 24 |
Aug 23 07:38:48 AM UTC 24 |
2041741089 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.2337412841 |
|
|
Aug 23 07:34:39 AM UTC 24 |
Aug 23 07:38:58 AM UTC 24 |
24611209890 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2750819077 |
|
|
Aug 23 07:33:57 AM UTC 24 |
Aug 23 07:39:03 AM UTC 24 |
13055143514 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.1413951237 |
|
|
Aug 23 07:38:13 AM UTC 24 |
Aug 23 07:39:12 AM UTC 24 |
3978537380 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3906905407 |
|
|
Aug 23 07:39:14 AM UTC 24 |
Aug 23 07:39:21 AM UTC 24 |
1282604731 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3076456105 |
|
|
Aug 23 07:38:45 AM UTC 24 |
Aug 23 07:39:30 AM UTC 24 |
627713464 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.4242334293 |
|
|
Aug 23 07:39:04 AM UTC 24 |
Aug 23 07:39:38 AM UTC 24 |
126913572 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1959619112 |
|
|
Aug 23 07:37:11 AM UTC 24 |
Aug 23 07:39:41 AM UTC 24 |
12771523346 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3093706814 |
|
|
Aug 23 07:39:42 AM UTC 24 |
Aug 23 07:39:43 AM UTC 24 |
62889580 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3129337170 |
|
|
Aug 23 07:38:59 AM UTC 24 |
Aug 23 07:39:52 AM UTC 24 |
258880518 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.571699299 |
|
|
Aug 23 07:39:44 AM UTC 24 |
Aug 23 07:39:54 AM UTC 24 |
1822440408 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.3924004186 |
|
|
Aug 23 07:39:53 AM UTC 24 |
Aug 23 07:39:58 AM UTC 24 |
146660259 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.4216486292 |
|
|
Aug 23 07:29:52 AM UTC 24 |
Aug 23 07:39:58 AM UTC 24 |
5019828322 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3887344415 |
|
|
Aug 23 07:39:59 AM UTC 24 |
Aug 23 07:40:01 AM UTC 24 |
30702083 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.529714478 |
|
|
Aug 23 07:37:47 AM UTC 24 |
Aug 23 07:40:16 AM UTC 24 |
12936587314 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.1852554618 |
|
|
Aug 23 07:40:01 AM UTC 24 |
Aug 23 07:40:17 AM UTC 24 |
1029056047 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.4223030374 |
|
|
Aug 23 07:39:22 AM UTC 24 |
Aug 23 07:40:18 AM UTC 24 |
1178580652 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.1781801721 |
|
|
Aug 23 07:40:18 AM UTC 24 |
Aug 23 07:40:36 AM UTC 24 |
1158053518 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.1125026597 |
|
|
Aug 23 07:35:58 AM UTC 24 |
Aug 23 07:40:38 AM UTC 24 |
46425115158 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3879190175 |
|
|
Aug 23 07:36:23 AM UTC 24 |
Aug 23 07:40:40 AM UTC 24 |
10120088387 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3083985206 |
|
|
Aug 23 07:40:36 AM UTC 24 |
Aug 23 07:40:42 AM UTC 24 |
458115534 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1648790871 |
|
|
Aug 23 07:33:57 AM UTC 24 |
Aug 23 07:40:50 AM UTC 24 |
21121992080 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3456617810 |
|
|
Aug 23 07:34:14 AM UTC 24 |
Aug 23 07:40:53 AM UTC 24 |
6286661640 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.200187734 |
|
|
Aug 23 07:31:15 AM UTC 24 |
Aug 23 07:40:54 AM UTC 24 |
5404894590 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.4201052048 |
|
|
Aug 23 07:27:54 AM UTC 24 |
Aug 23 07:40:55 AM UTC 24 |
61922653076 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2567559917 |
|
|
Aug 23 07:40:51 AM UTC 24 |
Aug 23 07:40:58 AM UTC 24 |
432743112 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1320424045 |
|
|
Aug 23 07:39:55 AM UTC 24 |
Aug 23 07:40:58 AM UTC 24 |
6784543956 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.4217290115 |
|
|
Aug 23 07:40:58 AM UTC 24 |
Aug 23 07:41:00 AM UTC 24 |
26908779 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4209950236 |
|
|
Aug 23 07:40:43 AM UTC 24 |
Aug 23 07:41:04 AM UTC 24 |
970493666 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.4089532995 |
|
|
Aug 23 07:41:00 AM UTC 24 |
Aug 23 07:41:05 AM UTC 24 |
94214156 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.857116973 |
|
|
Aug 23 07:40:41 AM UTC 24 |
Aug 23 07:41:05 AM UTC 24 |
1257810593 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.530300353 |
|
|
Aug 23 07:40:17 AM UTC 24 |
Aug 23 07:41:05 AM UTC 24 |
9018550605 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.425048951 |
|
|
Aug 23 07:40:59 AM UTC 24 |
Aug 23 07:41:06 AM UTC 24 |
1391456570 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.1149594766 |
|
|
Aug 23 07:41:06 AM UTC 24 |
Aug 23 07:41:08 AM UTC 24 |
23363804 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.4176699544 |
|
|
Aug 23 07:41:06 AM UTC 24 |
Aug 23 07:41:24 AM UTC 24 |
4447940271 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1499507467 |
|
|
Aug 23 07:32:01 AM UTC 24 |
Aug 23 07:41:33 AM UTC 24 |
8382487104 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2337138225 |
|
|
Aug 23 07:41:33 AM UTC 24 |
Aug 23 07:41:58 AM UTC 24 |
5165026130 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.1563538776 |
|
|
Aug 23 07:38:31 AM UTC 24 |
Aug 23 07:42:14 AM UTC 24 |
4863288693 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.103690878 |
|
|
Aug 23 07:36:49 AM UTC 24 |
Aug 23 07:42:18 AM UTC 24 |
14904406907 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.1233224095 |
|
|
Aug 23 07:41:08 AM UTC 24 |
Aug 23 07:42:20 AM UTC 24 |
10225201968 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2161332118 |
|
|
Aug 23 07:40:19 AM UTC 24 |
Aug 23 07:42:22 AM UTC 24 |
3790113968 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.206071392 |
|
|
Aug 23 07:42:15 AM UTC 24 |
Aug 23 07:42:26 AM UTC 24 |
76670640 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.769574682 |
|
|
Aug 23 07:42:21 AM UTC 24 |
Aug 23 07:42:28 AM UTC 24 |
704316516 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3286696698 |
|
|
Aug 23 07:29:41 AM UTC 24 |
Aug 23 07:42:39 AM UTC 24 |
4517224143 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1835565015 |
|
|
Aug 23 07:42:39 AM UTC 24 |
Aug 23 07:42:41 AM UTC 24 |
45835119 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1384950761 |
|
|
Aug 23 07:35:31 AM UTC 24 |
Aug 23 07:42:41 AM UTC 24 |
2825504946 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.2435349609 |
|
|
Aug 23 07:42:41 AM UTC 24 |
Aug 23 07:42:46 AM UTC 24 |
240780724 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1685685183 |
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Aug 23 07:42:19 AM UTC 24 |
Aug 23 07:42:46 AM UTC 24 |
474664805 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.662005538 |
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|
Aug 23 07:26:40 AM UTC 24 |
Aug 23 07:42:46 AM UTC 24 |
4587753224 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2024512675 |
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Aug 23 07:42:41 AM UTC 24 |
Aug 23 07:42:47 AM UTC 24 |
308927886 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.169270944 |
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Aug 23 07:42:47 AM UTC 24 |
Aug 23 07:42:49 AM UTC 24 |
35655904 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.130741525 |
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Aug 23 07:42:48 AM UTC 24 |
Aug 23 07:43:05 AM UTC 24 |
377238841 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3630162317 |
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Aug 23 07:42:23 AM UTC 24 |
Aug 23 07:43:30 AM UTC 24 |
2855684940 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.3134192248 |
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Aug 23 07:40:55 AM UTC 24 |
Aug 23 07:43:30 AM UTC 24 |
14818819160 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1365757171 |
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Aug 23 07:41:05 AM UTC 24 |
Aug 23 07:43:42 AM UTC 24 |
2283134323 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.3114064310 |
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Aug 23 07:40:56 AM UTC 24 |
Aug 23 07:43:42 AM UTC 24 |
71323786594 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.677573145 |
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Aug 23 07:35:14 AM UTC 24 |
Aug 23 07:43:44 AM UTC 24 |
3453967765 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.455412194 |
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Aug 23 07:36:31 AM UTC 24 |
Aug 23 07:43:50 AM UTC 24 |
10941041365 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.4201753845 |
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Aug 23 07:43:31 AM UTC 24 |
Aug 23 07:43:52 AM UTC 24 |
712796905 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2796589504 |
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Aug 23 07:11:35 AM UTC 24 |
Aug 23 07:43:54 AM UTC 24 |
33245373435 ps |