| T305 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1562702970 |
|
|
Aug 27 08:17:15 AM UTC 24 |
Aug 27 08:17:31 AM UTC 24 |
691683289 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.2700441231 |
|
|
Aug 27 07:59:56 AM UTC 24 |
Aug 27 08:17:32 AM UTC 24 |
62067414861 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.3368279205 |
|
|
Aug 27 08:17:29 AM UTC 24 |
Aug 27 08:17:43 AM UTC 24 |
331529400 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1868016327 |
|
|
Aug 27 08:16:47 AM UTC 24 |
Aug 27 08:17:50 AM UTC 24 |
135195684 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.175209294 |
|
|
Aug 27 08:12:36 AM UTC 24 |
Aug 27 08:17:57 AM UTC 24 |
2644318565 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.310677835 |
|
|
Aug 27 08:16:35 AM UTC 24 |
Aug 27 08:18:01 AM UTC 24 |
218273977 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.2189745977 |
|
|
Aug 27 08:17:32 AM UTC 24 |
Aug 27 08:18:03 AM UTC 24 |
16719002298 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2608274456 |
|
|
Aug 27 08:05:13 AM UTC 24 |
Aug 27 08:18:16 AM UTC 24 |
29713724594 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1081268986 |
|
|
Aug 27 08:12:26 AM UTC 24 |
Aug 27 08:18:18 AM UTC 24 |
29280793784 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.799272439 |
|
|
Aug 27 08:17:50 AM UTC 24 |
Aug 27 08:18:21 AM UTC 24 |
5627957226 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2219231172 |
|
|
Aug 27 08:13:21 AM UTC 24 |
Aug 27 08:18:24 AM UTC 24 |
122445121099 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2559137782 |
|
|
Aug 27 08:18:17 AM UTC 24 |
Aug 27 08:18:31 AM UTC 24 |
2131267503 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.4038460360 |
|
|
Aug 27 08:17:25 AM UTC 24 |
Aug 27 08:18:31 AM UTC 24 |
4440803281 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.432579111 |
|
|
Aug 27 08:18:31 AM UTC 24 |
Aug 27 08:18:34 AM UTC 24 |
112690332 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.3132847177 |
|
|
Aug 27 08:09:08 AM UTC 24 |
Aug 27 08:18:34 AM UTC 24 |
12412990972 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3703275470 |
|
|
Aug 27 08:18:31 AM UTC 24 |
Aug 27 08:18:39 AM UTC 24 |
182923418 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.365763536 |
|
|
Aug 27 08:18:35 AM UTC 24 |
Aug 27 08:18:44 AM UTC 24 |
187586646 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2985586550 |
|
|
Aug 27 08:18:45 AM UTC 24 |
Aug 27 08:18:47 AM UTC 24 |
28851951 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.3524197248 |
|
|
Aug 27 08:18:48 AM UTC 24 |
Aug 27 08:19:06 AM UTC 24 |
226302157 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2615954387 |
|
|
Aug 27 08:15:09 AM UTC 24 |
Aug 27 08:19:07 AM UTC 24 |
1885528131 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.520039456 |
|
|
Aug 27 08:18:05 AM UTC 24 |
Aug 27 08:19:09 AM UTC 24 |
454050635 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.3343974507 |
|
|
Aug 27 07:59:32 AM UTC 24 |
Aug 27 08:19:13 AM UTC 24 |
10409886806 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2525115373 |
|
|
Aug 27 08:15:19 AM UTC 24 |
Aug 27 08:19:19 AM UTC 24 |
3339264439 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.3047440402 |
|
|
Aug 27 08:12:28 AM UTC 24 |
Aug 27 08:19:20 AM UTC 24 |
6958781613 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.369216642 |
|
|
Aug 27 08:00:47 AM UTC 24 |
Aug 27 08:19:23 AM UTC 24 |
13693018162 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.3486065081 |
|
|
Aug 27 08:19:08 AM UTC 24 |
Aug 27 08:19:27 AM UTC 24 |
2457667475 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.397429418 |
|
|
Aug 27 08:18:02 AM UTC 24 |
Aug 27 08:19:36 AM UTC 24 |
895022442 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.723640429 |
|
|
Aug 27 08:19:28 AM UTC 24 |
Aug 27 08:19:36 AM UTC 24 |
1697080545 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3161232981 |
|
|
Aug 27 08:19:24 AM UTC 24 |
Aug 27 08:19:54 AM UTC 24 |
287821817 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.4212934532 |
|
|
Aug 27 08:13:09 AM UTC 24 |
Aug 27 08:20:02 AM UTC 24 |
7186243199 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.903140097 |
|
|
Aug 27 08:20:03 AM UTC 24 |
Aug 27 08:20:05 AM UTC 24 |
86020850 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.1280878562 |
|
|
Aug 27 08:20:06 AM UTC 24 |
Aug 27 08:20:15 AM UTC 24 |
801306741 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1693606993 |
|
|
Aug 27 08:10:42 AM UTC 24 |
Aug 27 08:20:18 AM UTC 24 |
36616150997 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.83781833 |
|
|
Aug 27 08:20:16 AM UTC 24 |
Aug 27 08:20:21 AM UTC 24 |
99745242 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2664342862 |
|
|
Aug 27 08:19:13 AM UTC 24 |
Aug 27 08:20:22 AM UTC 24 |
1157333027 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2646290238 |
|
|
Aug 27 08:20:23 AM UTC 24 |
Aug 27 08:20:25 AM UTC 24 |
52070284 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.105337412 |
|
|
Aug 27 08:02:48 AM UTC 24 |
Aug 27 08:20:26 AM UTC 24 |
2681349446 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3533202075 |
|
|
Aug 27 08:04:00 AM UTC 24 |
Aug 27 08:20:35 AM UTC 24 |
13468957309 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3403517642 |
|
|
Aug 27 08:11:04 AM UTC 24 |
Aug 27 08:20:39 AM UTC 24 |
34708068567 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.123762079 |
|
|
Aug 27 08:19:21 AM UTC 24 |
Aug 27 08:20:51 AM UTC 24 |
2022325326 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.1049579650 |
|
|
Aug 27 08:20:26 AM UTC 24 |
Aug 27 08:20:56 AM UTC 24 |
970475300 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.220704667 |
|
|
Aug 27 08:12:07 AM UTC 24 |
Aug 27 08:21:00 AM UTC 24 |
18429099074 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.2736768114 |
|
|
Aug 27 08:21:01 AM UTC 24 |
Aug 27 08:21:06 AM UTC 24 |
49834777 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3113481846 |
|
|
Aug 27 08:21:07 AM UTC 24 |
Aug 27 08:21:20 AM UTC 24 |
4698857711 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3635327170 |
|
|
Aug 27 08:20:40 AM UTC 24 |
Aug 27 08:21:25 AM UTC 24 |
197215774 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2448476229 |
|
|
Aug 27 08:16:27 AM UTC 24 |
Aug 27 08:21:33 AM UTC 24 |
2417365835 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2443536966 |
|
|
Aug 27 08:20:57 AM UTC 24 |
Aug 27 08:21:40 AM UTC 24 |
90280735 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.4053446167 |
|
|
Aug 27 08:21:41 AM UTC 24 |
Aug 27 08:21:44 AM UTC 24 |
30796936 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.3948702601 |
|
|
Aug 27 08:22:00 AM UTC 24 |
Aug 27 08:22:07 AM UTC 24 |
214002895 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.1268825912 |
|
|
Aug 27 08:19:54 AM UTC 24 |
Aug 27 08:21:47 AM UTC 24 |
3561765148 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3436871201 |
|
|
Aug 27 08:21:45 AM UTC 24 |
Aug 27 08:21:51 AM UTC 24 |
200874195 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.1035535311 |
|
|
Aug 27 08:13:46 AM UTC 24 |
Aug 27 08:21:55 AM UTC 24 |
16738357443 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.4014669809 |
|
|
Aug 27 08:21:48 AM UTC 24 |
Aug 27 08:21:57 AM UTC 24 |
310957616 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2651470781 |
|
|
Aug 27 08:21:57 AM UTC 24 |
Aug 27 08:22:00 AM UTC 24 |
40226114 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1283844135 |
|
|
Aug 27 08:21:52 AM UTC 24 |
Aug 27 08:22:04 AM UTC 24 |
799750759 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.905725073 |
|
|
Aug 27 08:20:31 AM UTC 24 |
Aug 27 08:22:04 AM UTC 24 |
13805913354 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.242741396 |
|
|
Aug 27 08:14:59 AM UTC 24 |
Aug 27 08:22:19 AM UTC 24 |
6947898579 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.19275874 |
|
|
Aug 27 08:22:20 AM UTC 24 |
Aug 27 08:22:24 AM UTC 24 |
196755868 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.156539083 |
|
|
Aug 27 08:02:01 AM UTC 24 |
Aug 27 08:22:27 AM UTC 24 |
17506575842 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3961047520 |
|
|
Aug 27 08:22:28 AM UTC 24 |
Aug 27 08:22:39 AM UTC 24 |
227162437 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.88059606 |
|
|
Aug 27 08:19:37 AM UTC 24 |
Aug 27 08:22:54 AM UTC 24 |
2623387984 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.284387664 |
|
|
Aug 27 08:22:55 AM UTC 24 |
Aug 27 08:23:00 AM UTC 24 |
689652270 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.3575358502 |
|
|
Aug 27 08:16:10 AM UTC 24 |
Aug 27 08:23:02 AM UTC 24 |
9687462416 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3728239850 |
|
|
Aug 27 08:17:43 AM UTC 24 |
Aug 27 08:23:07 AM UTC 24 |
10484554963 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1183000360 |
|
|
Aug 27 08:22:39 AM UTC 24 |
Aug 27 08:23:14 AM UTC 24 |
144689897 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3836753139 |
|
|
Aug 27 08:23:15 AM UTC 24 |
Aug 27 08:23:17 AM UTC 24 |
86823001 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.1576781651 |
|
|
Aug 27 08:23:18 AM UTC 24 |
Aug 27 08:23:27 AM UTC 24 |
229919273 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1625693505 |
|
|
Aug 27 08:23:28 AM UTC 24 |
Aug 27 08:23:33 AM UTC 24 |
107958338 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.537192820 |
|
|
Aug 27 08:12:17 AM UTC 24 |
Aug 27 08:23:40 AM UTC 24 |
9230529405 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1060790055 |
|
|
Aug 27 08:14:29 AM UTC 24 |
Aug 27 08:23:40 AM UTC 24 |
7134707757 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.3979986875 |
|
|
Aug 27 08:23:42 AM UTC 24 |
Aug 27 08:23:44 AM UTC 24 |
18227880 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.2936764331 |
|
|
Aug 27 08:22:06 AM UTC 24 |
Aug 27 08:23:47 AM UTC 24 |
11478271944 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1594427322 |
|
|
Aug 27 08:23:34 AM UTC 24 |
Aug 27 08:23:48 AM UTC 24 |
292696247 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.2242316049 |
|
|
Aug 27 08:06:34 AM UTC 24 |
Aug 27 08:23:55 AM UTC 24 |
16125088783 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.1378349456 |
|
|
Aug 27 08:09:17 AM UTC 24 |
Aug 27 08:23:57 AM UTC 24 |
2185373947 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.771497059 |
|
|
Aug 27 08:06:18 AM UTC 24 |
Aug 27 08:24:04 AM UTC 24 |
58287891071 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1422677604 |
|
|
Aug 27 08:23:56 AM UTC 24 |
Aug 27 08:24:05 AM UTC 24 |
330583079 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.4284895278 |
|
|
Aug 27 08:18:19 AM UTC 24 |
Aug 27 08:24:13 AM UTC 24 |
25708238656 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.359726185 |
|
|
Aug 27 08:23:08 AM UTC 24 |
Aug 27 08:24:20 AM UTC 24 |
4862454867 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.26493772 |
|
|
Aug 27 08:24:14 AM UTC 24 |
Aug 27 08:24:25 AM UTC 24 |
2555554462 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.1283569393 |
|
|
Aug 27 08:23:49 AM UTC 24 |
Aug 27 08:24:25 AM UTC 24 |
489763166 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.1120917457 |
|
|
Aug 27 08:20:36 AM UTC 24 |
Aug 27 08:24:32 AM UTC 24 |
7436242502 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.4281407977 |
|
|
Aug 27 08:23:45 AM UTC 24 |
Aug 27 08:24:34 AM UTC 24 |
429077331 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2049869439 |
|
|
Aug 27 08:24:32 AM UTC 24 |
Aug 27 08:24:35 AM UTC 24 |
50167671 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.870043748 |
|
|
Aug 27 08:24:36 AM UTC 24 |
Aug 27 08:24:41 AM UTC 24 |
374030661 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3824522127 |
|
|
Aug 27 08:13:45 AM UTC 24 |
Aug 27 08:24:44 AM UTC 24 |
9854054063 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.401782275 |
|
|
Aug 27 08:19:21 AM UTC 24 |
Aug 27 08:24:45 AM UTC 24 |
3530077356 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2925090689 |
|
|
Aug 27 08:24:35 AM UTC 24 |
Aug 27 08:24:45 AM UTC 24 |
744236588 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.3592445186 |
|
|
Aug 27 08:24:46 AM UTC 24 |
Aug 27 08:24:48 AM UTC 24 |
27133589 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.997616886 |
|
|
Aug 27 08:10:55 AM UTC 24 |
Aug 27 08:24:59 AM UTC 24 |
8645767729 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.1252678223 |
|
|
Aug 27 08:15:46 AM UTC 24 |
Aug 27 08:25:15 AM UTC 24 |
22057751655 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.4260441518 |
|
|
Aug 27 08:20:52 AM UTC 24 |
Aug 27 08:25:15 AM UTC 24 |
32240522171 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.772393544 |
|
|
Aug 27 08:24:46 AM UTC 24 |
Aug 27 08:25:19 AM UTC 24 |
3811871822 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1030890226 |
|
|
Aug 27 08:25:16 AM UTC 24 |
Aug 27 08:25:35 AM UTC 24 |
2237338837 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3093634875 |
|
|
Aug 27 08:24:05 AM UTC 24 |
Aug 27 08:25:35 AM UTC 24 |
146244535 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1033584651 |
|
|
Aug 27 08:18:21 AM UTC 24 |
Aug 27 08:25:38 AM UTC 24 |
16055657358 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1128743289 |
|
|
Aug 27 08:24:06 AM UTC 24 |
Aug 27 08:25:38 AM UTC 24 |
581504970 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.4170259335 |
|
|
Aug 27 08:25:36 AM UTC 24 |
Aug 27 08:25:43 AM UTC 24 |
187083537 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1259593131 |
|
|
Aug 27 08:25:39 AM UTC 24 |
Aug 27 08:25:44 AM UTC 24 |
226643182 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.941967895 |
|
|
Aug 27 08:17:31 AM UTC 24 |
Aug 27 08:25:49 AM UTC 24 |
42517933229 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.2238891052 |
|
|
Aug 27 08:25:00 AM UTC 24 |
Aug 27 08:25:50 AM UTC 24 |
612977687 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1124796167 |
|
|
Aug 27 08:25:50 AM UTC 24 |
Aug 27 08:25:52 AM UTC 24 |
47782335 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2628644555 |
|
|
Aug 27 08:25:51 AM UTC 24 |
Aug 27 08:25:58 AM UTC 24 |
147902924 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.4106909473 |
|
|
Aug 27 08:25:53 AM UTC 24 |
Aug 27 08:26:03 AM UTC 24 |
196761855 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.4178107062 |
|
|
Aug 27 08:25:44 AM UTC 24 |
Aug 27 08:26:04 AM UTC 24 |
1011224348 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.4224140034 |
|
|
Aug 27 08:26:05 AM UTC 24 |
Aug 27 08:26:07 AM UTC 24 |
12941188 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.4036296023 |
|
|
Aug 27 08:24:42 AM UTC 24 |
Aug 27 08:26:10 AM UTC 24 |
803320706 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.4099246733 |
|
|
Aug 27 08:23:48 AM UTC 24 |
Aug 27 08:26:18 AM UTC 24 |
3434480824 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.4268408 |
|
|
Aug 27 08:26:08 AM UTC 24 |
Aug 27 08:26:19 AM UTC 24 |
499405864 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1220555449 |
|
|
Aug 27 08:17:58 AM UTC 24 |
Aug 27 08:26:32 AM UTC 24 |
17249248445 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.2153019874 |
|
|
Aug 27 08:17:10 AM UTC 24 |
Aug 27 08:26:35 AM UTC 24 |
4181229678 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.258274757 |
|
|
Aug 27 08:15:46 AM UTC 24 |
Aug 27 08:26:36 AM UTC 24 |
2987479311 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1139817155 |
|
|
Aug 27 08:26:33 AM UTC 24 |
Aug 27 08:26:54 AM UTC 24 |
946248424 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1304009647 |
|
|
Aug 27 08:19:09 AM UTC 24 |
Aug 27 08:27:01 AM UTC 24 |
16036109716 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1996159733 |
|
|
Aug 27 08:16:43 AM UTC 24 |
Aug 27 08:27:05 AM UTC 24 |
67546412294 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2212440633 |
|
|
Aug 27 08:27:01 AM UTC 24 |
Aug 27 08:27:13 AM UTC 24 |
1323009773 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2875599733 |
|
|
Aug 27 08:26:37 AM UTC 24 |
Aug 27 08:27:14 AM UTC 24 |
96757196 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.3406797955 |
|
|
Aug 27 08:26:19 AM UTC 24 |
Aug 27 08:27:15 AM UTC 24 |
5231918910 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.4016923578 |
|
|
Aug 27 08:27:16 AM UTC 24 |
Aug 27 08:27:18 AM UTC 24 |
70666875 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.1097755113 |
|
|
Aug 27 08:22:08 AM UTC 24 |
Aug 27 08:27:24 AM UTC 24 |
12744490794 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3680667892 |
|
|
Aug 27 08:27:25 AM UTC 24 |
Aug 27 08:27:30 AM UTC 24 |
90488099 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.188324175 |
|
|
Aug 27 08:25:36 AM UTC 24 |
Aug 27 08:27:30 AM UTC 24 |
153195772 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3390276014 |
|
|
Aug 27 08:27:19 AM UTC 24 |
Aug 27 08:27:31 AM UTC 24 |
290590260 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.329804814 |
|
|
Aug 27 08:27:31 AM UTC 24 |
Aug 27 08:27:34 AM UTC 24 |
71756834 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.1186402702 |
|
|
Aug 27 08:27:34 AM UTC 24 |
Aug 27 08:27:37 AM UTC 24 |
152145677 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3851898660 |
|
|
Aug 27 08:00:53 AM UTC 24 |
Aug 27 08:27:39 AM UTC 24 |
20119753264 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.3592790243 |
|
|
Aug 27 08:24:26 AM UTC 24 |
Aug 27 08:27:41 AM UTC 24 |
1668750454 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2974214302 |
|
|
Aug 27 08:19:07 AM UTC 24 |
Aug 27 08:27:44 AM UTC 24 |
11672482982 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.4121824625 |
|
|
Aug 27 08:21:20 AM UTC 24 |
Aug 27 08:27:52 AM UTC 24 |
1811689216 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2546245555 |
|
|
Aug 27 08:26:54 AM UTC 24 |
Aug 27 08:27:53 AM UTC 24 |
480823123 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.3564722107 |
|
|
Aug 27 08:20:27 AM UTC 24 |
Aug 27 08:28:06 AM UTC 24 |
12678241645 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3196988591 |
|
|
Aug 27 08:27:54 AM UTC 24 |
Aug 27 08:28:06 AM UTC 24 |
280389493 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.12573497 |
|
|
Aug 27 08:19:37 AM UTC 24 |
Aug 27 08:28:10 AM UTC 24 |
5930493946 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1898208673 |
|
|
Aug 27 08:28:07 AM UTC 24 |
Aug 27 08:28:21 AM UTC 24 |
5830678947 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3076271365 |
|
|
Aug 27 08:28:06 AM UTC 24 |
Aug 27 08:28:23 AM UTC 24 |
703918583 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1139394853 |
|
|
Aug 27 08:28:24 AM UTC 24 |
Aug 27 08:28:26 AM UTC 24 |
35258098 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1894079133 |
|
|
Aug 27 08:21:27 AM UTC 24 |
Aug 27 08:28:30 AM UTC 24 |
10210491117 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.3422457440 |
|
|
Aug 27 08:28:27 AM UTC 24 |
Aug 27 08:28:37 AM UTC 24 |
893852778 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.546556952 |
|
|
Aug 27 08:28:31 AM UTC 24 |
Aug 27 08:28:39 AM UTC 24 |
192646921 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3098109388 |
|
|
Aug 27 08:27:40 AM UTC 24 |
Aug 27 08:28:50 AM UTC 24 |
4855599780 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.858891471 |
|
|
Aug 27 08:12:46 AM UTC 24 |
Aug 27 08:28:51 AM UTC 24 |
51001974416 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.582393150 |
|
|
Aug 27 08:28:52 AM UTC 24 |
Aug 27 08:28:54 AM UTC 24 |
12435995 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3273637045 |
|
|
Aug 27 08:17:25 AM UTC 24 |
Aug 27 08:29:07 AM UTC 24 |
4355464963 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.67761141 |
|
|
Aug 27 08:27:45 AM UTC 24 |
Aug 27 08:29:13 AM UTC 24 |
520908742 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.1500810350 |
|
|
Aug 27 08:18:24 AM UTC 24 |
Aug 27 08:29:22 AM UTC 24 |
11168285894 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.2559700070 |
|
|
Aug 27 08:23:54 AM UTC 24 |
Aug 27 08:29:30 AM UTC 24 |
6753070055 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4265825968 |
|
|
Aug 27 08:26:00 AM UTC 24 |
Aug 27 08:29:36 AM UTC 24 |
5146925825 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.4141240509 |
|
|
Aug 27 08:29:22 AM UTC 24 |
Aug 27 08:29:47 AM UTC 24 |
6859875565 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2628878409 |
|
|
Aug 27 08:25:16 AM UTC 24 |
Aug 27 08:29:56 AM UTC 24 |
2884367223 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2499748432 |
|
|
Aug 27 08:29:36 AM UTC 24 |
Aug 27 08:29:59 AM UTC 24 |
197653972 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2023936943 |
|
|
Aug 27 08:29:08 AM UTC 24 |
Aug 27 08:30:09 AM UTC 24 |
6284144926 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.3234213692 |
|
|
Aug 27 08:28:52 AM UTC 24 |
Aug 27 08:30:12 AM UTC 24 |
2957800109 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.81576093 |
|
|
Aug 27 08:29:57 AM UTC 24 |
Aug 27 08:30:14 AM UTC 24 |
3816686337 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3467984216 |
|
|
Aug 27 08:30:16 AM UTC 24 |
Aug 27 08:30:18 AM UTC 24 |
43291493 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2005818685 |
|
|
Aug 27 08:23:58 AM UTC 24 |
Aug 27 08:30:28 AM UTC 24 |
5129428702 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3930801025 |
|
|
Aug 27 08:30:20 AM UTC 24 |
Aug 27 08:30:34 AM UTC 24 |
456973967 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.2271380660 |
|
|
Aug 27 08:30:30 AM UTC 24 |
Aug 27 08:30:35 AM UTC 24 |
283704921 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1096834650 |
|
|
Aug 27 08:30:48 AM UTC 24 |
Aug 27 08:30:50 AM UTC 24 |
38445434 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.1171453766 |
|
|
Aug 27 08:30:51 AM UTC 24 |
Aug 27 08:31:00 AM UTC 24 |
563654982 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.622745653 |
|
|
Aug 27 08:26:36 AM UTC 24 |
Aug 27 08:31:03 AM UTC 24 |
36818009587 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2351734391 |
|
|
Aug 27 08:29:48 AM UTC 24 |
Aug 27 08:31:06 AM UTC 24 |
147018584 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2988388817 |
|
|
Aug 27 08:26:20 AM UTC 24 |
Aug 27 08:31:18 AM UTC 24 |
2402042335 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.1246171368 |
|
|
Aug 27 08:31:19 AM UTC 24 |
Aug 27 08:31:26 AM UTC 24 |
254442370 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3835781323 |
|
|
Aug 27 08:27:06 AM UTC 24 |
Aug 27 08:31:33 AM UTC 24 |
8545058619 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1173795054 |
|
|
Aug 27 08:27:53 AM UTC 24 |
Aug 27 08:31:39 AM UTC 24 |
15889283655 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.3545391708 |
|
|
Aug 27 08:31:05 AM UTC 24 |
Aug 27 08:31:41 AM UTC 24 |
1759535608 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2545500789 |
|
|
Aug 27 08:30:01 AM UTC 24 |
Aug 27 08:31:48 AM UTC 24 |
2217354304 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.3074878629 |
|
|
Aug 27 08:22:25 AM UTC 24 |
Aug 27 08:31:48 AM UTC 24 |
87240685630 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1909312272 |
|
|
Aug 27 08:31:41 AM UTC 24 |
Aug 27 08:31:50 AM UTC 24 |
420478412 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.4239465036 |
|
|
Aug 27 08:31:40 AM UTC 24 |
Aug 27 08:32:03 AM UTC 24 |
155418182 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2241066362 |
|
|
Aug 27 08:32:04 AM UTC 24 |
Aug 27 08:32:06 AM UTC 24 |
237110745 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.2775876174 |
|
|
Aug 27 08:32:07 AM UTC 24 |
Aug 27 08:32:15 AM UTC 24 |
262731849 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3317685426 |
|
|
Aug 27 08:32:16 AM UTC 24 |
Aug 27 08:32:24 AM UTC 24 |
107671870 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3791709541 |
|
|
Aug 27 08:31:33 AM UTC 24 |
Aug 27 08:32:32 AM UTC 24 |
131816965 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2091051231 |
|
|
Aug 27 08:25:20 AM UTC 24 |
Aug 27 08:32:34 AM UTC 24 |
6552443896 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.3880196265 |
|
|
Aug 27 08:32:34 AM UTC 24 |
Aug 27 08:32:36 AM UTC 24 |
32310631 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.3237329707 |
|
|
Aug 27 08:32:38 AM UTC 24 |
Aug 27 08:32:40 AM UTC 24 |
40206147 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3872714426 |
|
|
Aug 27 08:27:31 AM UTC 24 |
Aug 27 08:32:46 AM UTC 24 |
15917107012 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.925381048 |
|
|
Aug 27 08:33:50 AM UTC 24 |
Aug 27 08:34:23 AM UTC 24 |
844794744 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.1490476500 |
|
|
Aug 27 08:16:19 AM UTC 24 |
Aug 27 08:32:47 AM UTC 24 |
18174052529 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3743891864 |
|
|
Aug 27 08:04:20 AM UTC 24 |
Aug 27 08:32:49 AM UTC 24 |
30632838508 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1711035698 |
|
|
Aug 27 08:32:48 AM UTC 24 |
Aug 27 08:32:53 AM UTC 24 |
113632137 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3936634909 |
|
|
Aug 27 08:08:58 AM UTC 24 |
Aug 27 08:32:54 AM UTC 24 |
3967098259 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.555462729 |
|
|
Aug 27 08:27:16 AM UTC 24 |
Aug 27 08:33:12 AM UTC 24 |
4304602299 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.238769324 |
|
|
Aug 27 08:15:37 AM UTC 24 |
Aug 27 08:33:18 AM UTC 24 |
13970450759 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.3133199752 |
|
|
Aug 27 08:25:43 AM UTC 24 |
Aug 27 08:33:20 AM UTC 24 |
17760189951 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2416289289 |
|
|
Aug 27 08:33:13 AM UTC 24 |
Aug 27 08:33:21 AM UTC 24 |
1239282339 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1870740768 |
|
|
Aug 27 08:32:53 AM UTC 24 |
Aug 27 08:33:22 AM UTC 24 |
103014703 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.4208452299 |
|
|
Aug 27 08:25:39 AM UTC 24 |
Aug 27 08:33:23 AM UTC 24 |
32427163612 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.346979602 |
|
|
Aug 27 08:33:23 AM UTC 24 |
Aug 27 08:33:25 AM UTC 24 |
273815130 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1091619989 |
|
|
Aug 27 08:31:07 AM UTC 24 |
Aug 27 08:33:35 AM UTC 24 |
5660614614 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.4050003501 |
|
|
Aug 27 08:33:26 AM UTC 24 |
Aug 27 08:33:35 AM UTC 24 |
762758223 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1082076095 |
|
|
Aug 27 08:06:22 AM UTC 24 |
Aug 27 08:33:37 AM UTC 24 |
63095666990 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3464799990 |
|
|
Aug 27 08:33:39 AM UTC 24 |
Aug 27 08:33:41 AM UTC 24 |
16467456 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.577603751 |
|
|
Aug 27 08:33:24 AM UTC 24 |
Aug 27 08:33:41 AM UTC 24 |
4093143209 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3661262136 |
|
|
Aug 27 08:33:36 AM UTC 24 |
Aug 27 08:33:49 AM UTC 24 |
352389777 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.486626652 |
|
|
Aug 27 08:17:10 AM UTC 24 |
Aug 27 08:33:52 AM UTC 24 |
2529556656 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.1786376456 |
|
|
Aug 27 08:33:42 AM UTC 24 |
Aug 27 08:33:53 AM UTC 24 |
3318963080 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.4053266778 |
|
|
Aug 27 08:32:47 AM UTC 24 |
Aug 27 08:33:56 AM UTC 24 |
6484796189 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1806226583 |
|
|
Aug 27 08:32:54 AM UTC 24 |
Aug 27 08:34:02 AM UTC 24 |
278231119 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.126013070 |
|
|
Aug 27 08:34:03 AM UTC 24 |
Aug 27 08:34:06 AM UTC 24 |
83634562 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3966959744 |
|
|
Aug 27 08:34:07 AM UTC 24 |
Aug 27 08:34:09 AM UTC 24 |
36756061 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2105197762 |
|
|
Aug 27 08:24:21 AM UTC 24 |
Aug 27 08:34:16 AM UTC 24 |
3143833400 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.738105152 |
|
|
Aug 27 08:21:34 AM UTC 24 |
Aug 27 08:34:17 AM UTC 24 |
25881730734 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1923543280 |
|
|
Aug 27 08:34:11 AM UTC 24 |
Aug 27 08:34:21 AM UTC 24 |
409329330 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2562782977 |
|
|
Aug 27 08:33:54 AM UTC 24 |
Aug 27 08:34:22 AM UTC 24 |
2795310571 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2430044991 |
|
|
Aug 27 08:34:23 AM UTC 24 |
Aug 27 08:34:26 AM UTC 24 |
58437058 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3746227589 |
|
|
Aug 27 08:34:17 AM UTC 24 |
Aug 27 08:34:31 AM UTC 24 |
569114468 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.835600075 |
|
|
Aug 27 08:34:26 AM UTC 24 |
Aug 27 08:34:32 AM UTC 24 |
424553133 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1458547498 |
|
|
Aug 27 08:34:24 AM UTC 24 |
Aug 27 08:34:34 AM UTC 24 |
344872906 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3917722338 |
|
|
Aug 27 08:34:35 AM UTC 24 |
Aug 27 08:34:37 AM UTC 24 |
14464389 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.152694307 |
|
|
Aug 27 08:27:42 AM UTC 24 |
Aug 27 08:34:41 AM UTC 24 |
8503097308 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3456315840 |
|
|
Aug 27 08:34:32 AM UTC 24 |
Aug 27 08:35:06 AM UTC 24 |
3187239019 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2863356419 |
|
|
Aug 27 07:58:44 AM UTC 24 |
Aug 27 08:35:19 AM UTC 24 |
72956318004 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.593780342 |
|
|
Aug 27 08:35:19 AM UTC 24 |
Aug 27 08:35:22 AM UTC 24 |
172462277 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.54117457 |
|
|
Aug 27 08:34:38 AM UTC 24 |
Aug 27 08:35:49 AM UTC 24 |
528754643 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.1337462016 |
|
|
Aug 27 08:29:14 AM UTC 24 |
Aug 27 08:35:51 AM UTC 24 |
32751691901 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3810528685 |
|
|
Aug 27 08:35:52 AM UTC 24 |
Aug 27 08:36:01 AM UTC 24 |
106328157 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3288709913 |
|
|
Aug 27 08:35:51 AM UTC 24 |
Aug 27 08:36:08 AM UTC 24 |
77250379 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.540130625 |
|
|
Aug 27 08:36:02 AM UTC 24 |
Aug 27 08:36:08 AM UTC 24 |
614021012 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.1084475288 |
|
|
Aug 27 08:13:49 AM UTC 24 |
Aug 27 08:36:10 AM UTC 24 |
13273670220 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.3445310495 |
|
|
Aug 27 08:35:07 AM UTC 24 |
Aug 27 08:36:17 AM UTC 24 |
989852950 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3064301782 |
|
|
Aug 27 08:23:04 AM UTC 24 |
Aug 27 08:36:19 AM UTC 24 |
8595258160 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1592687020 |
|
|
Aug 27 08:36:19 AM UTC 24 |
Aug 27 08:36:21 AM UTC 24 |
45322459 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.2638619450 |
|
|
Aug 27 08:34:18 AM UTC 24 |
Aug 27 08:36:24 AM UTC 24 |
2464906042 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2216473373 |
|
|
Aug 27 08:36:22 AM UTC 24 |
Aug 27 08:36:28 AM UTC 24 |
1034909309 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.1066751295 |
|
|
Aug 27 08:36:21 AM UTC 24 |
Aug 27 08:36:34 AM UTC 24 |
712078578 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2996933560 |
|
|
Aug 27 08:36:35 AM UTC 24 |
Aug 27 08:36:37 AM UTC 24 |
12898661 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.133143935 |
|
|
Aug 27 08:11:37 AM UTC 24 |
Aug 27 08:36:37 AM UTC 24 |
13149545840 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.46815546 |
|
|
Aug 27 08:36:38 AM UTC 24 |
Aug 27 08:36:43 AM UTC 24 |
112107399 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.671271971 |
|
|
Aug 27 08:28:55 AM UTC 24 |
Aug 27 08:36:56 AM UTC 24 |
2425795228 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2409978376 |
|
|
Aug 27 08:28:39 AM UTC 24 |
Aug 27 08:36:58 AM UTC 24 |
11861567928 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1647252042 |
|
|
Aug 27 08:37:00 AM UTC 24 |
Aug 27 08:37:10 AM UTC 24 |
2100980350 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.648869165 |
|
|
Aug 27 08:29:31 AM UTC 24 |
Aug 27 08:37:12 AM UTC 24 |
27776933084 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.311118378 |
|
|
Aug 27 08:31:27 AM UTC 24 |
Aug 27 08:37:25 AM UTC 24 |
68308813248 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2157671497 |
|
|
Aug 27 08:37:13 AM UTC 24 |
Aug 27 08:37:29 AM UTC 24 |
146160579 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.1960851249 |
|
|
Aug 27 08:36:43 AM UTC 24 |
Aug 27 08:37:43 AM UTC 24 |
3629077835 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3707407420 |
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Aug 27 08:37:30 AM UTC 24 |
Aug 27 08:37:48 AM UTC 24 |
2810481705 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3429340158 |
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Aug 27 08:36:09 AM UTC 24 |
Aug 27 08:37:56 AM UTC 24 |
488231476 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2672419178 |
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Aug 27 08:37:58 AM UTC 24 |
Aug 27 08:38:00 AM UTC 24 |
31387429 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.2391293473 |
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Aug 27 08:31:01 AM UTC 24 |
Aug 27 08:38:08 AM UTC 24 |
12205759039 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.153861049 |
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Aug 27 08:38:01 AM UTC 24 |
Aug 27 08:38:16 AM UTC 24 |
462943987 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2348784484 |
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Aug 27 08:38:09 AM UTC 24 |
Aug 27 08:38:17 AM UTC 24 |
160794579 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2647521484 |
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Aug 27 08:32:48 AM UTC 24 |
Aug 27 08:38:20 AM UTC 24 |
3526250318 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.208067474 |
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Aug 27 08:05:57 AM UTC 24 |
Aug 27 08:38:21 AM UTC 24 |
79487566256 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1463799474 |
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Aug 27 08:35:13 AM UTC 24 |
Aug 27 08:38:22 AM UTC 24 |
1570278859 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3741818349 |
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Aug 27 08:38:21 AM UTC 24 |
Aug 27 08:38:24 AM UTC 24 |
46740363 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.872077659 |
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Aug 27 08:38:21 AM UTC 24 |
Aug 27 08:38:37 AM UTC 24 |
659374590 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.136841046 |
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Aug 27 08:38:17 AM UTC 24 |
Aug 27 08:38:37 AM UTC 24 |
381715766 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.101780828 |
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Aug 27 08:33:57 AM UTC 24 |
Aug 27 08:38:47 AM UTC 24 |
8985032212 ps |