Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44


Total test records in report: 1027
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1003 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1567846419 Aug 27 09:10:16 AM UTC 24 Aug 27 09:10:25 AM UTC 24 134921140 ps
T1004 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.25465116 Aug 27 09:10:21 AM UTC 24 Aug 27 09:10:25 AM UTC 24 321633846 ps
T1005 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2921001150 Aug 27 09:10:21 AM UTC 24 Aug 27 09:10:26 AM UTC 24 308059754 ps
T1006 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4189730814 Aug 27 09:10:24 AM UTC 24 Aug 27 09:10:26 AM UTC 24 51587310 ps
T1007 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.16820434 Aug 27 09:10:21 AM UTC 24 Aug 27 09:10:28 AM UTC 24 39454336 ps
T1008 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1666470354 Aug 27 09:10:24 AM UTC 24 Aug 27 09:10:28 AM UTC 24 229850033 ps
T1009 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3335187156 Aug 27 09:10:27 AM UTC 24 Aug 27 09:10:29 AM UTC 24 12601631 ps
T1010 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3922563445 Aug 27 09:10:25 AM UTC 24 Aug 27 09:10:29 AM UTC 24 85782412 ps
T1011 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1121756209 Aug 27 09:10:27 AM UTC 24 Aug 27 09:10:29 AM UTC 24 88011980 ps
T1012 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2284373508 Aug 27 09:10:27 AM UTC 24 Aug 27 09:10:31 AM UTC 24 255011021 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1011588418 Aug 27 09:10:31 AM UTC 24 Aug 27 09:10:32 AM UTC 24 10698510 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2542630528 Aug 27 09:10:31 AM UTC 24 Aug 27 09:10:33 AM UTC 24 203305985 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.835118266 Aug 27 09:10:29 AM UTC 24 Aug 27 09:10:33 AM UTC 24 33051798 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3911189341 Aug 27 09:10:30 AM UTC 24 Aug 27 09:10:33 AM UTC 24 76417058 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.518117650 Aug 27 09:10:29 AM UTC 24 Aug 27 09:10:35 AM UTC 24 2079631491 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1421952363 Aug 27 09:10:34 AM UTC 24 Aug 27 09:10:36 AM UTC 24 29852269 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1285823866 Aug 27 09:10:31 AM UTC 24 Aug 27 09:10:36 AM UTC 24 5584871936 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.154192094 Aug 27 09:10:32 AM UTC 24 Aug 27 09:10:37 AM UTC 24 86177371 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2620000957 Aug 27 09:10:34 AM UTC 24 Aug 27 09:10:37 AM UTC 24 296347256 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3505620735 Aug 27 09:10:35 AM UTC 24 Aug 27 09:10:37 AM UTC 24 24339864 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1365022754 Aug 27 09:10:35 AM UTC 24 Aug 27 09:10:38 AM UTC 24 32913268 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2722043348 Aug 27 09:10:37 AM UTC 24 Aug 27 09:10:39 AM UTC 24 17804702 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2763367489 Aug 27 09:10:37 AM UTC 24 Aug 27 09:10:39 AM UTC 24 21984939 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.822766817 Aug 27 09:10:37 AM UTC 24 Aug 27 09:10:41 AM UTC 24 337129874 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.349137176 Aug 27 09:10:35 AM UTC 24 Aug 27 09:10:41 AM UTC 24 429039523 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.884945873 Aug 27 09:10:39 AM UTC 24 Aug 27 09:10:43 AM UTC 24 66862275 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3603710295 Aug 27 09:10:37 AM UTC 24 Aug 27 09:10:44 AM UTC 24 62834162 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3566888640
Short name T5
Test name
Test status
Simulation time 94985098 ps
CPU time 2.92 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:48 AM UTC 24
Peak memory 224184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566888640 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.3566888640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1683261174
Short name T24
Test name
Test status
Simulation time 644805996 ps
CPU time 32.46 seconds
Started Aug 27 07:59:41 AM UTC 24
Finished Aug 27 08:00:15 AM UTC 24
Peak memory 274296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683261174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1683261174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3003266292
Short name T7
Test name
Test status
Simulation time 674755484 ps
CPU time 4.88 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:50 AM UTC 24
Peak memory 213744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003266292 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.3003266292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.177624220
Short name T48
Test name
Test status
Simulation time 6762766454 ps
CPU time 23.55 seconds
Started Aug 27 08:11:22 AM UTC 24
Finished Aug 27 08:11:47 AM UTC 24
Peak memory 231272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177624220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.177624220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2463822399
Short name T4
Test name
Test status
Simulation time 807205573 ps
CPU time 2.07 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:47 AM UTC 24
Peak memory 247016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463822399 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2463822399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_regwen.1005632474
Short name T136
Test name
Test status
Simulation time 22255656218 ps
CPU time 708.57 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 08:10:40 AM UTC 24
Peak memory 387144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005632474 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1005632474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.305797188
Short name T63
Test name
Test status
Simulation time 392085011 ps
CPU time 3.98 seconds
Started Aug 27 09:09:00 AM UTC 24
Finished Aug 27 09:09:06 AM UTC 24
Peak memory 221716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30579
7188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_int
g_err.305797188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2498938247
Short name T40
Test name
Test status
Simulation time 14128699641 ps
CPU time 89.66 seconds
Started Aug 27 08:01:01 AM UTC 24
Finished Aug 27 08:02:33 AM UTC 24
Peak memory 323548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498938247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2498938247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3855705075
Short name T159
Test name
Test status
Simulation time 24318536590 ps
CPU time 339.38 seconds
Started Aug 27 08:06:09 AM UTC 24
Finished Aug 27 08:11:55 AM UTC 24
Peak memory 213932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855705075 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_acc
ess_b2b.3855705075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.382671452
Short name T66
Test name
Test status
Simulation time 203666072 ps
CPU time 2.91 seconds
Started Aug 27 09:08:47 AM UTC 24
Finished Aug 27 09:08:51 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38
2671452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_pas
sthru_mem_tl_intg_err.382671452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1585036574
Short name T103
Test name
Test status
Simulation time 6482669588 ps
CPU time 167.82 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:01:34 AM UTC 24
Peak memory 214168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585036574 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.1585036574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.815233448
Short name T30
Test name
Test status
Simulation time 28143295 ps
CPU time 0.92 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 07:59:34 AM UTC 24
Peak memory 212420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815233448 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.815233448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_executable.1308473109
Short name T139
Test name
Test status
Simulation time 4857041215 ps
CPU time 879.48 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 08:13:33 AM UTC 24
Peak memory 380840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308473109 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.1308473109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.564348837
Short name T20
Test name
Test status
Simulation time 6980654848 ps
CPU time 13.24 seconds
Started Aug 27 07:59:37 AM UTC 24
Finished Aug 27 07:59:51 AM UTC 24
Peak memory 214144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564348837 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.564348837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1910013481
Short name T128
Test name
Test status
Simulation time 275409266 ps
CPU time 3.21 seconds
Started Aug 27 09:10:07 AM UTC 24
Finished Aug 27 09:10:11 AM UTC 24
Peak memory 221616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19100
13481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i
ntg_err.1910013481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1342444692
Short name T11
Test name
Test status
Simulation time 19248539 ps
CPU time 0.81 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 07:58:46 AM UTC 24
Peak memory 212576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342444692 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1342444692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3911189341
Short name T133
Test name
Test status
Simulation time 76417058 ps
CPU time 1.94 seconds
Started Aug 27 09:10:30 AM UTC 24
Finished Aug 27 09:10:33 AM UTC 24
Peak memory 220408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39111
89341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i
ntg_err.3911189341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2609521605
Short name T54
Test name
Test status
Simulation time 1035686344 ps
CPU time 270.16 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 08:03:18 AM UTC 24
Peak memory 376676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609521605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2609521605
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.2685670059
Short name T559
Test name
Test status
Simulation time 8255839102 ps
CPU time 328.44 seconds
Started Aug 27 08:34:22 AM UTC 24
Finished Aug 27 08:39:55 AM UTC 24
Peak memory 384892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685670059 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2685670059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.459541127
Short name T62
Test name
Test status
Simulation time 244304398 ps
CPU time 2.15 seconds
Started Aug 27 09:08:49 AM UTC 24
Finished Aug 27 09:08:53 AM UTC 24
Peak memory 221804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45954
1127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_int
g_err.459541127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2620000957
Short name T129
Test name
Test status
Simulation time 296347256 ps
CPU time 2.62 seconds
Started Aug 27 09:10:34 AM UTC 24
Finished Aug 27 09:10:37 AM UTC 24
Peak memory 221160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26200
00957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_i
ntg_err.2620000957
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3448608139
Short name T22
Test name
Test status
Simulation time 346322128 ps
CPU time 18.86 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:59:03 AM UTC 24
Peak memory 313440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
448608139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_max
_throughput.3448608139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.507065215
Short name T98
Test name
Test status
Simulation time 31690246 ps
CPU time 0.94 seconds
Started Aug 27 09:10:13 AM UTC 24
Finished Aug 27 09:10:15 AM UTC 24
Peak memory 209600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507065215 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.507065215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1088599229
Short name T155
Test name
Test status
Simulation time 15090435856 ps
CPU time 626.52 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:09:17 AM UTC 24
Peak memory 395120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108859922
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.1088599229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2481788362
Short name T75
Test name
Test status
Simulation time 21368213 ps
CPU time 0.98 seconds
Started Aug 27 09:08:55 AM UTC 24
Finished Aug 27 09:08:57 AM UTC 24
Peak memory 210372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24817883
62 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_alia
sing.2481788362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3173572728
Short name T110
Test name
Test status
Simulation time 29576564 ps
CPU time 1.66 seconds
Started Aug 27 09:08:55 AM UTC 24
Finished Aug 27 09:08:57 AM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31735727
28 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_
bash.3173572728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1143797083
Short name T67
Test name
Test status
Simulation time 38543020 ps
CPU time 0.9 seconds
Started Aug 27 09:08:52 AM UTC 24
Finished Aug 27 09:08:53 AM UTC 24
Peak memory 210372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11437970
83 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_r
eset.1143797083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1998673776
Short name T937
Test name
Test status
Simulation time 102827775 ps
CPU time 2.61 seconds
Started Aug 27 09:08:58 AM UTC 24
Finished Aug 27 09:09:02 AM UTC 24
Peak memory 221976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1998673776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1998673776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3319105223
Short name T100
Test name
Test status
Simulation time 33198936 ps
CPU time 0.88 seconds
Started Aug 27 09:08:54 AM UTC 24
Finished Aug 27 09:08:55 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319105223 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.3319105223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3778775123
Short name T76
Test name
Test status
Simulation time 60892539 ps
CPU time 0.96 seconds
Started Aug 27 09:08:56 AM UTC 24
Finished Aug 27 09:08:58 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3778775123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_c
trl_same_csr_outstanding.3778775123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3763877391
Short name T936
Test name
Test status
Simulation time 339822639 ps
CPU time 4.81 seconds
Started Aug 27 09:08:48 AM UTC 24
Finished Aug 27 09:08:54 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763877391 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.3763877391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.374322062
Short name T79
Test name
Test status
Simulation time 47053400 ps
CPU time 0.98 seconds
Started Aug 27 09:09:05 AM UTC 24
Finished Aug 27 09:09:07 AM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37432206
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_alias
ing.374322062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.799262402
Short name T939
Test name
Test status
Simulation time 244188139 ps
CPU time 2.87 seconds
Started Aug 27 09:09:05 AM UTC 24
Finished Aug 27 09:09:09 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79926240
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_b
ash.799262402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2030106931
Short name T78
Test name
Test status
Simulation time 196096880 ps
CPU time 0.96 seconds
Started Aug 27 09:09:03 AM UTC 24
Finished Aug 27 09:09:05 AM UTC 24
Peak memory 210224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20301069
31 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_r
eset.2030106931
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1696279365
Short name T940
Test name
Test status
Simulation time 67311356 ps
CPU time 2.8 seconds
Started Aug 27 09:09:06 AM UTC 24
Finished Aug 27 09:09:10 AM UTC 24
Peak memory 221788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1696279365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1696279365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.261143156
Short name T101
Test name
Test status
Simulation time 12606579 ps
CPU time 0.99 seconds
Started Aug 27 09:09:04 AM UTC 24
Finished Aug 27 09:09:06 AM UTC 24
Peak memory 210728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261143156 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.261143156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4154674617
Short name T77
Test name
Test status
Simulation time 358412804 ps
CPU time 3.52 seconds
Started Aug 27 09:08:58 AM UTC 24
Finished Aug 27 09:09:03 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41
54674617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_pa
ssthru_mem_tl_intg_err.4154674617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.61528599
Short name T80
Test name
Test status
Simulation time 21366382 ps
CPU time 1.11 seconds
Started Aug 27 09:09:06 AM UTC 24
Finished Aug 27 09:09:08 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=61528599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctr
l_same_csr_outstanding.61528599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.242489477
Short name T938
Test name
Test status
Simulation time 137784012 ps
CPU time 4.03 seconds
Started Aug 27 09:08:59 AM UTC 24
Finished Aug 27 09:09:04 AM UTC 24
Peak memory 221912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242489477 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.242489477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3255408108
Short name T979
Test name
Test status
Simulation time 38415225 ps
CPU time 2.66 seconds
Started Aug 27 09:09:59 AM UTC 24
Finished Aug 27 09:10:03 AM UTC 24
Peak memory 221780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3255408108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3255408108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4180837680
Short name T976
Test name
Test status
Simulation time 13991457 ps
CPU time 0.95 seconds
Started Aug 27 09:09:59 AM UTC 24
Finished Aug 27 09:10:01 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180837680 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.4180837680
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3017087189
Short name T977
Test name
Test status
Simulation time 230904642 ps
CPU time 3.11 seconds
Started Aug 27 09:09:57 AM UTC 24
Finished Aug 27 09:10:01 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30
17087189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_p
assthru_mem_tl_intg_err.3017087189
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4119768308
Short name T978
Test name
Test status
Simulation time 56976505 ps
CPU time 1.06 seconds
Started Aug 27 09:09:59 AM UTC 24
Finished Aug 27 09:10:01 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4119768308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_
ctrl_same_csr_outstanding.4119768308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1163564048
Short name T980
Test name
Test status
Simulation time 624268661 ps
CPU time 5.36 seconds
Started Aug 27 09:09:57 AM UTC 24
Finished Aug 27 09:10:04 AM UTC 24
Peak memory 211444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163564048 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.1163564048
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2863456651
Short name T975
Test name
Test status
Simulation time 110805371 ps
CPU time 2.06 seconds
Started Aug 27 09:09:57 AM UTC 24
Finished Aug 27 09:10:00 AM UTC 24
Peak memory 221548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28634
56651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_i
ntg_err.2863456651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2399138064
Short name T986
Test name
Test status
Simulation time 24522689 ps
CPU time 1.36 seconds
Started Aug 27 09:10:05 AM UTC 24
Finished Aug 27 09:10:08 AM UTC 24
Peak memory 210048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2399138064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2399138064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1286635858
Short name T981
Test name
Test status
Simulation time 15447223 ps
CPU time 0.97 seconds
Started Aug 27 09:10:02 AM UTC 24
Finished Aug 27 09:10:04 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286635858 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.1286635858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2158952077
Short name T983
Test name
Test status
Simulation time 2768597011 ps
CPU time 6.03 seconds
Started Aug 27 09:09:59 AM UTC 24
Finished Aug 27 09:10:07 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21
58952077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_p
assthru_mem_tl_intg_err.2158952077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4088703478
Short name T982
Test name
Test status
Simulation time 16707752 ps
CPU time 1.15 seconds
Started Aug 27 09:10:03 AM UTC 24
Finished Aug 27 09:10:06 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4088703478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_
ctrl_same_csr_outstanding.4088703478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1953695812
Short name T984
Test name
Test status
Simulation time 79764804 ps
CPU time 3.34 seconds
Started Aug 27 09:10:02 AM UTC 24
Finished Aug 27 09:10:07 AM UTC 24
Peak memory 211632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953695812 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.1953695812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.961964101
Short name T985
Test name
Test status
Simulation time 538445613 ps
CPU time 4.77 seconds
Started Aug 27 09:10:02 AM UTC 24
Finished Aug 27 09:10:08 AM UTC 24
Peak memory 221656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96196
4101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_in
tg_err.961964101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3216987655
Short name T990
Test name
Test status
Simulation time 139106868 ps
CPU time 1.76 seconds
Started Aug 27 09:10:10 AM UTC 24
Finished Aug 27 09:10:13 AM UTC 24
Peak memory 220284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3216987655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3216987655
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.481405798
Short name T987
Test name
Test status
Simulation time 11311814 ps
CPU time 0.98 seconds
Started Aug 27 09:10:08 AM UTC 24
Finished Aug 27 09:10:11 AM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481405798 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.481405798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1375046231
Short name T989
Test name
Test status
Simulation time 485721400 ps
CPU time 4.97 seconds
Started Aug 27 09:10:05 AM UTC 24
Finished Aug 27 09:10:12 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13
75046231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_p
assthru_mem_tl_intg_err.1375046231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1086454218
Short name T988
Test name
Test status
Simulation time 66991849 ps
CPU time 1.08 seconds
Started Aug 27 09:10:08 AM UTC 24
Finished Aug 27 09:10:11 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1086454218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_
ctrl_same_csr_outstanding.1086454218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3829034867
Short name T991
Test name
Test status
Simulation time 713857202 ps
CPU time 7.84 seconds
Started Aug 27 09:10:06 AM UTC 24
Finished Aug 27 09:10:15 AM UTC 24
Peak memory 221248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829034867 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.3829034867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1714242422
Short name T994
Test name
Test status
Simulation time 39847906 ps
CPU time 1.63 seconds
Started Aug 27 09:10:14 AM UTC 24
Finished Aug 27 09:10:17 AM UTC 24
Peak memory 220284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1714242422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1714242422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2420259504
Short name T992
Test name
Test status
Simulation time 234317695 ps
CPU time 3.76 seconds
Started Aug 27 09:10:10 AM UTC 24
Finished Aug 27 09:10:15 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24
20259504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_p
assthru_mem_tl_intg_err.2420259504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1516451142
Short name T993
Test name
Test status
Simulation time 36336060 ps
CPU time 0.99 seconds
Started Aug 27 09:10:14 AM UTC 24
Finished Aug 27 09:10:16 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1516451142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_
ctrl_same_csr_outstanding.1516451142
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2107097594
Short name T995
Test name
Test status
Simulation time 62274361 ps
CPU time 4.84 seconds
Started Aug 27 09:10:13 AM UTC 24
Finished Aug 27 09:10:19 AM UTC 24
Peak memory 221872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107097594 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.2107097594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3677706177
Short name T132
Test name
Test status
Simulation time 255884483 ps
CPU time 4.24 seconds
Started Aug 27 09:10:13 AM UTC 24
Finished Aug 27 09:10:18 AM UTC 24
Peak memory 221592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36777
06177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_i
ntg_err.3677706177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2718604255
Short name T1000
Test name
Test status
Simulation time 141334451 ps
CPU time 2.18 seconds
Started Aug 27 09:10:19 AM UTC 24
Finished Aug 27 09:10:23 AM UTC 24
Peak memory 221928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2718604255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2718604255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1128196128
Short name T997
Test name
Test status
Simulation time 35361831 ps
CPU time 0.87 seconds
Started Aug 27 09:10:18 AM UTC 24
Finished Aug 27 09:10:20 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128196128 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.1128196128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3162867376
Short name T999
Test name
Test status
Simulation time 5309750292 ps
CPU time 4.57 seconds
Started Aug 27 09:10:16 AM UTC 24
Finished Aug 27 09:10:22 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31
62867376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_p
assthru_mem_tl_intg_err.3162867376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1148088135
Short name T998
Test name
Test status
Simulation time 53057355 ps
CPU time 1 seconds
Started Aug 27 09:10:18 AM UTC 24
Finished Aug 27 09:10:20 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1148088135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_
ctrl_same_csr_outstanding.1148088135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1567846419
Short name T1003
Test name
Test status
Simulation time 134921140 ps
CPU time 7.55 seconds
Started Aug 27 09:10:16 AM UTC 24
Finished Aug 27 09:10:25 AM UTC 24
Peak memory 211568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567846419 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.1567846419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.881800758
Short name T996
Test name
Test status
Simulation time 355245955 ps
CPU time 2.29 seconds
Started Aug 27 09:10:16 AM UTC 24
Finished Aug 27 09:10:19 AM UTC 24
Peak memory 221536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88180
0758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_in
tg_err.881800758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4189730814
Short name T1006
Test name
Test status
Simulation time 51587310 ps
CPU time 1.3 seconds
Started Aug 27 09:10:24 AM UTC 24
Finished Aug 27 09:10:26 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=4189730814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.4189730814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2888803559
Short name T1001
Test name
Test status
Simulation time 16747027 ps
CPU time 0.85 seconds
Started Aug 27 09:10:21 AM UTC 24
Finished Aug 27 09:10:23 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888803559 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.2888803559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2921001150
Short name T1005
Test name
Test status
Simulation time 308059754 ps
CPU time 3.93 seconds
Started Aug 27 09:10:21 AM UTC 24
Finished Aug 27 09:10:26 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29
21001150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_p
assthru_mem_tl_intg_err.2921001150
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2000230538
Short name T1002
Test name
Test status
Simulation time 58375647 ps
CPU time 0.97 seconds
Started Aug 27 09:10:22 AM UTC 24
Finished Aug 27 09:10:25 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2000230538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_
ctrl_same_csr_outstanding.2000230538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.16820434
Short name T1007
Test name
Test status
Simulation time 39454336 ps
CPU time 5.64 seconds
Started Aug 27 09:10:21 AM UTC 24
Finished Aug 27 09:10:28 AM UTC 24
Peak memory 221612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16820434 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.16820434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.25465116
Short name T1004
Test name
Test status
Simulation time 321633846 ps
CPU time 2.81 seconds
Started Aug 27 09:10:21 AM UTC 24
Finished Aug 27 09:10:25 AM UTC 24
Peak memory 221732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25465
116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_int
g_err.25465116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3335187156
Short name T1009
Test name
Test status
Simulation time 12601631 ps
CPU time 0.86 seconds
Started Aug 27 09:10:27 AM UTC 24
Finished Aug 27 09:10:29 AM UTC 24
Peak memory 210428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335187156 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.3335187156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1666470354
Short name T1008
Test name
Test status
Simulation time 229850033 ps
CPU time 3.04 seconds
Started Aug 27 09:10:24 AM UTC 24
Finished Aug 27 09:10:28 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16
66470354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_p
assthru_mem_tl_intg_err.1666470354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1121756209
Short name T1011
Test name
Test status
Simulation time 88011980 ps
CPU time 1.17 seconds
Started Aug 27 09:10:27 AM UTC 24
Finished Aug 27 09:10:29 AM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1121756209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_
ctrl_same_csr_outstanding.1121756209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3922563445
Short name T1010
Test name
Test status
Simulation time 85782412 ps
CPU time 2.77 seconds
Started Aug 27 09:10:25 AM UTC 24
Finished Aug 27 09:10:29 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922563445 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.3922563445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2284373508
Short name T1012
Test name
Test status
Simulation time 255011021 ps
CPU time 2.93 seconds
Started Aug 27 09:10:27 AM UTC 24
Finished Aug 27 09:10:31 AM UTC 24
Peak memory 211360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22843
73508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_i
ntg_err.2284373508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1011588418
Short name T1013
Test name
Test status
Simulation time 10698510 ps
CPU time 0.94 seconds
Started Aug 27 09:10:31 AM UTC 24
Finished Aug 27 09:10:32 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011588418 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.1011588418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.518117650
Short name T1016
Test name
Test status
Simulation time 2079631491 ps
CPU time 5.58 seconds
Started Aug 27 09:10:29 AM UTC 24
Finished Aug 27 09:10:35 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51
8117650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_pa
ssthru_mem_tl_intg_err.518117650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2542630528
Short name T1014
Test name
Test status
Simulation time 203305985 ps
CPU time 1.15 seconds
Started Aug 27 09:10:31 AM UTC 24
Finished Aug 27 09:10:33 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2542630528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_
ctrl_same_csr_outstanding.2542630528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.835118266
Short name T1015
Test name
Test status
Simulation time 33051798 ps
CPU time 3.31 seconds
Started Aug 27 09:10:29 AM UTC 24
Finished Aug 27 09:10:33 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835118266 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.835118266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1365022754
Short name T1021
Test name
Test status
Simulation time 32913268 ps
CPU time 1.43 seconds
Started Aug 27 09:10:35 AM UTC 24
Finished Aug 27 09:10:38 AM UTC 24
Peak memory 220344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1365022754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1365022754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1421952363
Short name T1017
Test name
Test status
Simulation time 29852269 ps
CPU time 0.87 seconds
Started Aug 27 09:10:34 AM UTC 24
Finished Aug 27 09:10:36 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421952363 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.1421952363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1285823866
Short name T1018
Test name
Test status
Simulation time 5584871936 ps
CPU time 4.43 seconds
Started Aug 27 09:10:31 AM UTC 24
Finished Aug 27 09:10:36 AM UTC 24
Peak memory 211592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12
85823866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_p
assthru_mem_tl_intg_err.1285823866
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3505620735
Short name T1020
Test name
Test status
Simulation time 24339864 ps
CPU time 1.16 seconds
Started Aug 27 09:10:35 AM UTC 24
Finished Aug 27 09:10:37 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3505620735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_
ctrl_same_csr_outstanding.3505620735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.154192094
Short name T1019
Test name
Test status
Simulation time 86177371 ps
CPU time 3.65 seconds
Started Aug 27 09:10:32 AM UTC 24
Finished Aug 27 09:10:37 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154192094 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.154192094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.884945873
Short name T1026
Test name
Test status
Simulation time 66862275 ps
CPU time 3.04 seconds
Started Aug 27 09:10:39 AM UTC 24
Finished Aug 27 09:10:43 AM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=884945873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.884945873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2722043348
Short name T1022
Test name
Test status
Simulation time 17804702 ps
CPU time 0.88 seconds
Started Aug 27 09:10:37 AM UTC 24
Finished Aug 27 09:10:39 AM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722043348 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.2722043348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.349137176
Short name T1025
Test name
Test status
Simulation time 429039523 ps
CPU time 4.61 seconds
Started Aug 27 09:10:35 AM UTC 24
Finished Aug 27 09:10:41 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34
9137176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_pa
ssthru_mem_tl_intg_err.349137176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2763367489
Short name T1023
Test name
Test status
Simulation time 21984939 ps
CPU time 1.03 seconds
Started Aug 27 09:10:37 AM UTC 24
Finished Aug 27 09:10:39 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2763367489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_
ctrl_same_csr_outstanding.2763367489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3603710295
Short name T1027
Test name
Test status
Simulation time 62834162 ps
CPU time 5.54 seconds
Started Aug 27 09:10:37 AM UTC 24
Finished Aug 27 09:10:44 AM UTC 24
Peak memory 221928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603710295 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.3603710295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.822766817
Short name T1024
Test name
Test status
Simulation time 337129874 ps
CPU time 2.71 seconds
Started Aug 27 09:10:37 AM UTC 24
Finished Aug 27 09:10:41 AM UTC 24
Peak memory 221596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82276
6817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_in
tg_err.822766817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.390379970
Short name T944
Test name
Test status
Simulation time 20315552 ps
CPU time 1.03 seconds
Started Aug 27 09:09:14 AM UTC 24
Finished Aug 27 09:09:16 AM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39037997
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_alias
ing.390379970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.510426726
Short name T945
Test name
Test status
Simulation time 298119953 ps
CPU time 2.37 seconds
Started Aug 27 09:09:13 AM UTC 24
Finished Aug 27 09:09:16 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51042672
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_b
ash.510426726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.455298443
Short name T942
Test name
Test status
Simulation time 17896974 ps
CPU time 0.97 seconds
Started Aug 27 09:09:11 AM UTC 24
Finished Aug 27 09:09:13 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45529844
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_re
set.455298443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1835682321
Short name T947
Test name
Test status
Simulation time 137401669 ps
CPU time 2.7 seconds
Started Aug 27 09:09:15 AM UTC 24
Finished Aug 27 09:09:19 AM UTC 24
Peak memory 221864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1835682321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1835682321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3044607445
Short name T941
Test name
Test status
Simulation time 62889710 ps
CPU time 0.94 seconds
Started Aug 27 09:09:11 AM UTC 24
Finished Aug 27 09:09:13 AM UTC 24
Peak memory 210428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044607445 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.3044607445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3907686820
Short name T81
Test name
Test status
Simulation time 826251620 ps
CPU time 2.19 seconds
Started Aug 27 09:09:08 AM UTC 24
Finished Aug 27 09:09:11 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39
07686820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_pa
ssthru_mem_tl_intg_err.3907686820
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1020836821
Short name T102
Test name
Test status
Simulation time 38813743 ps
CPU time 1.02 seconds
Started Aug 27 09:09:14 AM UTC 24
Finished Aug 27 09:09:16 AM UTC 24
Peak memory 210456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1020836821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_c
trl_same_csr_outstanding.1020836821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2861636408
Short name T943
Test name
Test status
Simulation time 21704556 ps
CPU time 2.4 seconds
Started Aug 27 09:09:10 AM UTC 24
Finished Aug 27 09:09:13 AM UTC 24
Peak memory 221652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861636408 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.2861636408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3915420242
Short name T64
Test name
Test status
Simulation time 322743601 ps
CPU time 2.24 seconds
Started Aug 27 09:09:10 AM UTC 24
Finished Aug 27 09:09:13 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39154
20242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_in
tg_err.3915420242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2317035636
Short name T84
Test name
Test status
Simulation time 21850098 ps
CPU time 0.99 seconds
Started Aug 27 09:09:21 AM UTC 24
Finished Aug 27 09:09:23 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23170356
36 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_alia
sing.2317035636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.297844981
Short name T948
Test name
Test status
Simulation time 92251116 ps
CPU time 2.07 seconds
Started Aug 27 09:09:20 AM UTC 24
Finished Aug 27 09:09:23 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29784498
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit_b
ash.297844981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.685767712
Short name T946
Test name
Test status
Simulation time 128988984 ps
CPU time 1.18 seconds
Started Aug 27 09:09:17 AM UTC 24
Finished Aug 27 09:09:19 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68576771
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_re
set.685767712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.783019142
Short name T951
Test name
Test status
Simulation time 35932355 ps
CPU time 2.59 seconds
Started Aug 27 09:09:23 AM UTC 24
Finished Aug 27 09:09:27 AM UTC 24
Peak memory 223880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=783019142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.783019142
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1552558931
Short name T83
Test name
Test status
Simulation time 15714245 ps
CPU time 0.91 seconds
Started Aug 27 09:09:20 AM UTC 24
Finished Aug 27 09:09:22 AM UTC 24
Peak memory 210788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552558931 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.1552558931
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.70523511
Short name T82
Test name
Test status
Simulation time 3350732453 ps
CPU time 4.47 seconds
Started Aug 27 09:09:15 AM UTC 24
Finished Aug 27 09:09:21 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70
523511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_pass
thru_mem_tl_intg_err.70523511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2796987243
Short name T950
Test name
Test status
Simulation time 237925372 ps
CPU time 1.05 seconds
Started Aug 27 09:09:23 AM UTC 24
Finished Aug 27 09:09:25 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2796987243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_c
trl_same_csr_outstanding.2796987243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1307098695
Short name T949
Test name
Test status
Simulation time 483401966 ps
CPU time 6.85 seconds
Started Aug 27 09:09:17 AM UTC 24
Finished Aug 27 09:09:25 AM UTC 24
Peak memory 211444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307098695 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.1307098695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2046789968
Short name T124
Test name
Test status
Simulation time 526436499 ps
CPU time 3.45 seconds
Started Aug 27 09:09:17 AM UTC 24
Finished Aug 27 09:09:21 AM UTC 24
Peak memory 221668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20467
89968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_in
tg_err.2046789968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4032367440
Short name T86
Test name
Test status
Simulation time 16597340 ps
CPU time 1 seconds
Started Aug 27 09:09:31 AM UTC 24
Finished Aug 27 09:09:33 AM UTC 24
Peak memory 210456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40323674
40 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_alia
sing.4032367440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2382576929
Short name T954
Test name
Test status
Simulation time 70282567 ps
CPU time 1.9 seconds
Started Aug 27 09:09:29 AM UTC 24
Finished Aug 27 09:09:32 AM UTC 24
Peak memory 210596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23825769
29 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit_
bash.2382576929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.126678393
Short name T85
Test name
Test status
Simulation time 15855957 ps
CPU time 0.94 seconds
Started Aug 27 09:09:26 AM UTC 24
Finished Aug 27 09:09:28 AM UTC 24
Peak memory 210780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12667839
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_re
set.126678393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4247322543
Short name T959
Test name
Test status
Simulation time 141774384 ps
CPU time 3.76 seconds
Started Aug 27 09:09:33 AM UTC 24
Finished Aug 27 09:09:37 AM UTC 24
Peak memory 221844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=4247322543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.4247322543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1500606692
Short name T953
Test name
Test status
Simulation time 44834618 ps
CPU time 1.02 seconds
Started Aug 27 09:09:29 AM UTC 24
Finished Aug 27 09:09:31 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500606692 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.1500606692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.321143463
Short name T952
Test name
Test status
Simulation time 890920572 ps
CPU time 3.29 seconds
Started Aug 27 09:09:24 AM UTC 24
Finished Aug 27 09:09:29 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32
1143463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_pas
sthru_mem_tl_intg_err.321143463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1765089525
Short name T955
Test name
Test status
Simulation time 84530366 ps
CPU time 1.06 seconds
Started Aug 27 09:09:31 AM UTC 24
Finished Aug 27 09:09:33 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1765089525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_c
trl_same_csr_outstanding.1765089525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.37904863
Short name T123
Test name
Test status
Simulation time 471840250 ps
CPU time 6.4 seconds
Started Aug 27 09:09:24 AM UTC 24
Finished Aug 27 09:09:32 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37904863 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.37904863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2641646980
Short name T130
Test name
Test status
Simulation time 159877099 ps
CPU time 1.95 seconds
Started Aug 27 09:09:26 AM UTC 24
Finished Aug 27 09:09:29 AM UTC 24
Peak memory 220408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26416
46980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_in
tg_err.2641646980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1761416583
Short name T960
Test name
Test status
Simulation time 116645589 ps
CPU time 2.27 seconds
Started Aug 27 09:09:38 AM UTC 24
Finished Aug 27 09:09:42 AM UTC 24
Peak memory 221892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=1761416583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1761416583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1770523454
Short name T956
Test name
Test status
Simulation time 14227916 ps
CPU time 0.93 seconds
Started Aug 27 09:09:34 AM UTC 24
Finished Aug 27 09:09:36 AM UTC 24
Peak memory 210784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770523454 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.1770523454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4290777801
Short name T91
Test name
Test status
Simulation time 1365347816 ps
CPU time 5.22 seconds
Started Aug 27 09:09:33 AM UTC 24
Finished Aug 27 09:09:39 AM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42
90777801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_pa
ssthru_mem_tl_intg_err.4290777801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3772317475
Short name T957
Test name
Test status
Simulation time 17144564 ps
CPU time 1.05 seconds
Started Aug 27 09:09:34 AM UTC 24
Finished Aug 27 09:09:36 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3772317475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_c
trl_same_csr_outstanding.3772317475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1840871833
Short name T958
Test name
Test status
Simulation time 69996922 ps
CPU time 2.75 seconds
Started Aug 27 09:09:33 AM UTC 24
Finished Aug 27 09:09:37 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840871833 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.1840871833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3350997815
Short name T125
Test name
Test status
Simulation time 182315744 ps
CPU time 3.13 seconds
Started Aug 27 09:09:34 AM UTC 24
Finished Aug 27 09:09:38 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33509
97815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_in
tg_err.3350997815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.224990446
Short name T963
Test name
Test status
Simulation time 56432877 ps
CPU time 2.53 seconds
Started Aug 27 09:09:42 AM UTC 24
Finished Aug 27 09:09:45 AM UTC 24
Peak memory 223888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=224990446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.224990446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3077243925
Short name T92
Test name
Test status
Simulation time 14483050 ps
CPU time 0.87 seconds
Started Aug 27 09:09:41 AM UTC 24
Finished Aug 27 09:09:43 AM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077243925 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.3077243925
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.429128482
Short name T95
Test name
Test status
Simulation time 326289808 ps
CPU time 3.23 seconds
Started Aug 27 09:09:39 AM UTC 24
Finished Aug 27 09:09:43 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42
9128482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_pas
sthru_mem_tl_intg_err.429128482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2792477742
Short name T961
Test name
Test status
Simulation time 77088109 ps
CPU time 1.1 seconds
Started Aug 27 09:09:42 AM UTC 24
Finished Aug 27 09:09:44 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2792477742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c
trl_same_csr_outstanding.2792477742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3293485793
Short name T962
Test name
Test status
Simulation time 137177521 ps
CPU time 4.79 seconds
Started Aug 27 09:09:39 AM UTC 24
Finished Aug 27 09:09:44 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293485793 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.3293485793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2214207147
Short name T134
Test name
Test status
Simulation time 101384931 ps
CPU time 2.4 seconds
Started Aug 27 09:09:41 AM UTC 24
Finished Aug 27 09:09:45 AM UTC 24
Peak memory 221672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22142
07147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_in
tg_err.2214207147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2626066474
Short name T966
Test name
Test status
Simulation time 59307532 ps
CPU time 1.29 seconds
Started Aug 27 09:09:47 AM UTC 24
Finished Aug 27 09:09:49 AM UTC 24
Peak memory 210048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2626066474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2626066474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2438885241
Short name T964
Test name
Test status
Simulation time 22504867 ps
CPU time 0.9 seconds
Started Aug 27 09:09:45 AM UTC 24
Finished Aug 27 09:09:47 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438885241 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.2438885241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3617727097
Short name T93
Test name
Test status
Simulation time 803998921 ps
CPU time 4.02 seconds
Started Aug 27 09:09:43 AM UTC 24
Finished Aug 27 09:09:48 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36
17727097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_pa
ssthru_mem_tl_intg_err.3617727097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.723939826
Short name T965
Test name
Test status
Simulation time 39943485 ps
CPU time 1.02 seconds
Started Aug 27 09:09:47 AM UTC 24
Finished Aug 27 09:09:49 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=723939826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ct
rl_same_csr_outstanding.723939826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3147577361
Short name T967
Test name
Test status
Simulation time 141436338 ps
CPU time 3.63 seconds
Started Aug 27 09:09:45 AM UTC 24
Finished Aug 27 09:09:50 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147577361 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.3147577361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3044143258
Short name T131
Test name
Test status
Simulation time 133177208 ps
CPU time 2.07 seconds
Started Aug 27 09:09:45 AM UTC 24
Finished Aug 27 09:09:48 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30441
43258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_in
tg_err.3044143258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2013767055
Short name T970
Test name
Test status
Simulation time 167676013 ps
CPU time 2.6 seconds
Started Aug 27 09:09:50 AM UTC 24
Finished Aug 27 09:09:54 AM UTC 24
Peak memory 221796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=2013767055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2013767055
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4237582179
Short name T96
Test name
Test status
Simulation time 14735045 ps
CPU time 0.97 seconds
Started Aug 27 09:09:50 AM UTC 24
Finished Aug 27 09:09:52 AM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237582179 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.4237582179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2756114944
Short name T94
Test name
Test status
Simulation time 241705145 ps
CPU time 3.31 seconds
Started Aug 27 09:09:47 AM UTC 24
Finished Aug 27 09:09:51 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27
56114944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pa
ssthru_mem_tl_intg_err.2756114944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4072958386
Short name T968
Test name
Test status
Simulation time 79052535 ps
CPU time 1.1 seconds
Started Aug 27 09:09:50 AM UTC 24
Finished Aug 27 09:09:52 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4072958386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_c
trl_same_csr_outstanding.4072958386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.299452716
Short name T969
Test name
Test status
Simulation time 74358313 ps
CPU time 4.56 seconds
Started Aug 27 09:09:48 AM UTC 24
Finished Aug 27 09:09:54 AM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299452716 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.299452716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3680422645
Short name T126
Test name
Test status
Simulation time 359906546 ps
CPU time 4.38 seconds
Started Aug 27 09:09:50 AM UTC 24
Finished Aug 27 09:09:55 AM UTC 24
Peak memory 221676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36804
22645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_in
tg_err.3680422645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3635026896
Short name T974
Test name
Test status
Simulation time 60022206 ps
CPU time 2.35 seconds
Started Aug 27 09:09:55 AM UTC 24
Finished Aug 27 09:09:58 AM UTC 24
Peak memory 224012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep
o/hw/dv/tools/sim.tcl +ntb_random_seed=3635026896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3635026896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1496525295
Short name T971
Test name
Test status
Simulation time 54709973 ps
CPU time 1.03 seconds
Started Aug 27 09:09:53 AM UTC 24
Finished Aug 27 09:09:55 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496525295 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.1496525295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.968512487
Short name T97
Test name
Test status
Simulation time 1591409293 ps
CPU time 4.17 seconds
Started Aug 27 09:09:52 AM UTC 24
Finished Aug 27 09:09:57 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96
8512487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_pas
sthru_mem_tl_intg_err.968512487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.545553135
Short name T973
Test name
Test status
Simulation time 82593293 ps
CPU time 1.04 seconds
Started Aug 27 09:09:55 AM UTC 24
Finished Aug 27 09:09:57 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=100000
0000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=545553135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ct
rl_same_csr_outstanding.545553135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2564054216
Short name T972
Test name
Test status
Simulation time 32619844 ps
CPU time 3.04 seconds
Started Aug 27 09:09:52 AM UTC 24
Finished Aug 27 09:09:56 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564054216 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.2564054216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1500092360
Short name T127
Test name
Test status
Simulation time 334329365 ps
CPU time 3.48 seconds
Started Aug 27 09:09:53 AM UTC 24
Finished Aug 27 09:09:58 AM UTC 24
Peak memory 221668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15000
92360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_in
tg_err.1500092360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.4148775715
Short name T37
Test name
Test status
Simulation time 2555994652 ps
CPU time 475.84 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:06:45 AM UTC 24
Peak memory 384940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148775715 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during_
key_req.4148775715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1103598017
Short name T2
Test name
Test status
Simulation time 62250548 ps
CPU time 0.56 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:45 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103598017 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1103598017
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_bijection.517549662
Short name T16
Test name
Test status
Simulation time 11620940914 ps
CPU time 46.59 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:59:31 AM UTC 24
Peak memory 213644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517549662 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.517549662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_executable.3393587019
Short name T286
Test name
Test status
Simulation time 21476962728 ps
CPU time 1025.88 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:16:00 AM UTC 24
Peak memory 384852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393587019 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.3393587019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3041579619
Short name T9
Test name
Test status
Simulation time 3404253986 ps
CPU time 6.15 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:50 AM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041579619 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.3041579619
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2347264868
Short name T13
Test name
Test status
Simulation time 93609115 ps
CPU time 4.46 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:49 AM UTC 24
Peak memory 224376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347264868 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.2347264868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.3877205847
Short name T252
Test name
Test status
Simulation time 9169937197 ps
CPU time 821.99 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:12:34 AM UTC 24
Peak memory 383004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877205847 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.3877205847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2364452406
Short name T28
Test name
Test status
Simulation time 227019088 ps
CPU time 10.39 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:55 AM UTC 24
Peak memory 213604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364452406 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.2364452406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.2424056550
Short name T109
Test name
Test status
Simulation time 4805127573 ps
CPU time 346.03 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:04:34 AM UTC 24
Peak memory 213932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424056550 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acce
ss_b2b.2424056550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3110076668
Short name T1
Test name
Test status
Simulation time 74958560 ps
CPU time 0.67 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:45 AM UTC 24
Peak memory 213160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110076668 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3110076668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_regwen.2483802739
Short name T18
Test name
Test status
Simulation time 2184735023 ps
CPU time 228.84 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:02:35 AM UTC 24
Peak memory 343996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483802739 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2483802739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_smoke.722371056
Short name T36
Test name
Test status
Simulation time 153161055 ps
CPU time 8.12 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:52 AM UTC 24
Peak memory 211972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722371056 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.722371056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1847229139
Short name T23
Test name
Test status
Simulation time 8405607232 ps
CPU time 48.54 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:59:34 AM UTC 24
Peak memory 339956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847229139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1847229139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2078708380
Short name T3
Test name
Test status
Simulation time 190649880 ps
CPU time 1.21 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:45 AM UTC 24
Peak memory 222768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2078708380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_th
roughput_w_partial_write.2078708380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.624792641
Short name T274
Test name
Test status
Simulation time 3799818014 ps
CPU time 974.06 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:15:08 AM UTC 24
Peak memory 383148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624792641 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_during_k
ey_req.624792641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_bijection.568397461
Short name T168
Test name
Test status
Simulation time 3531787295 ps
CPU time 47.47 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:59:33 AM UTC 24
Peak memory 213872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568397461 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.568397461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.706451291
Short name T27
Test name
Test status
Simulation time 74165000 ps
CPU time 9.71 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:55 AM UTC 24
Peak memory 270448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7
06451291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_max_
throughput.706451291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3218692948
Short name T33
Test name
Test status
Simulation time 177811114 ps
CPU time 4.82 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 07:58:50 AM UTC 24
Peak memory 223976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218692948 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.3218692948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.458242726
Short name T41
Test name
Test status
Simulation time 461389060 ps
CPU time 9.22 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 07:58:54 AM UTC 24
Peak memory 224120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458242726 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.458242726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1483215197
Short name T153
Test name
Test status
Simulation time 30466486418 ps
CPU time 311.16 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:03:59 AM UTC 24
Peak memory 384868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483215197 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.1483215197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access.1411652613
Short name T8
Test name
Test status
Simulation time 505752743 ps
CPU time 3.51 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:48 AM UTC 24
Peak memory 213728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411652613 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.1411652613
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.982686708
Short name T105
Test name
Test status
Simulation time 19568305298 ps
CPU time 302.53 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:03:50 AM UTC 24
Peak memory 213892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982686708 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acces
s_b2b.982686708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.875327206
Short name T12
Test name
Test status
Simulation time 81771027 ps
CPU time 1.02 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 07:58:46 AM UTC 24
Peak memory 212392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875327206 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.875327206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2219624950
Short name T6
Test name
Test status
Simulation time 222089297 ps
CPU time 2.71 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 07:58:48 AM UTC 24
Peak memory 250096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219624950 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2219624950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_smoke.835734325
Short name T34
Test name
Test status
Simulation time 108035836 ps
CPU time 6.72 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:58:51 AM UTC 24
Peak memory 213932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835734325 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.835734325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2863356419
Short name T509
Test name
Test status
Simulation time 72956318004 ps
CPU time 2170.29 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 08:35:19 AM UTC 24
Peak memory 396912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286335641
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.2863356419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2902562325
Short name T106
Test name
Test status
Simulation time 10619762452 ps
CPU time 318.92 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 08:04:07 AM UTC 24
Peak memory 214204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902562325 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.2902562325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.1295685744
Short name T29
Test name
Test status
Simulation time 219487075 ps
CPU time 25.37 seconds
Started Aug 27 07:58:43 AM UTC 24
Finished Aug 27 07:59:10 AM UTC 24
Peak memory 315248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1295685744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_th
roughput_w_partial_write.1295685744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.771497059
Short name T374
Test name
Test status
Simulation time 58287891071 ps
CPU time 1055.13 seconds
Started Aug 27 08:06:18 AM UTC 24
Finished Aug 27 08:24:04 AM UTC 24
Peak memory 385200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771497059 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_during_
key_req.771497059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2767842572
Short name T214
Test name
Test status
Simulation time 46661809 ps
CPU time 0.85 seconds
Started Aug 27 08:07:20 AM UTC 24
Finished Aug 27 08:07:21 AM UTC 24
Peak memory 212576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767842572 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.2767842572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_bijection.1124988364
Short name T211
Test name
Test status
Simulation time 6070337149 ps
CPU time 44.42 seconds
Started Aug 27 08:06:01 AM UTC 24
Finished Aug 27 08:06:47 AM UTC 24
Peak memory 213992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124988364 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.1124988364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.1082076095
Short name T489
Test name
Test status
Simulation time 63095666990 ps
CPU time 1619.29 seconds
Started Aug 27 08:06:22 AM UTC 24
Finished Aug 27 08:33:37 AM UTC 24
Peak memory 384872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082076095 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.1082076095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3369675735
Short name T210
Test name
Test status
Simulation time 1888756066 ps
CPU time 14.39 seconds
Started Aug 27 08:06:18 AM UTC 24
Finished Aug 27 08:06:33 AM UTC 24
Peak memory 213808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369675735 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.3369675735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.929834183
Short name T209
Test name
Test status
Simulation time 231280940 ps
CPU time 6.19 seconds
Started Aug 27 08:06:14 AM UTC 24
Finished Aug 27 08:06:21 AM UTC 24
Peak memory 235380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9
29834183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_max
_throughput.929834183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.702267160
Short name T151
Test name
Test status
Simulation time 146681202 ps
CPU time 4.23 seconds
Started Aug 27 08:06:49 AM UTC 24
Finished Aug 27 08:06:55 AM UTC 24
Peak memory 224388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702267160 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.702267160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2466607745
Short name T213
Test name
Test status
Simulation time 98854028 ps
CPU time 6.76 seconds
Started Aug 27 08:06:48 AM UTC 24
Finished Aug 27 08:06:56 AM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466607745 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.2466607745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2162796680
Short name T293
Test name
Test status
Simulation time 42367335653 ps
CPU time 635.7 seconds
Started Aug 27 08:06:00 AM UTC 24
Finished Aug 27 08:16:43 AM UTC 24
Peak memory 385196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162796680 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.2162796680
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_partial_access.433800634
Short name T205
Test name
Test status
Simulation time 162484402 ps
CPU time 7.52 seconds
Started Aug 27 08:06:04 AM UTC 24
Finished Aug 27 08:06:13 AM UTC 24
Peak memory 239484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433800634 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.433800634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1777971169
Short name T212
Test name
Test status
Simulation time 64715511 ps
CPU time 1.07 seconds
Started Aug 27 08:06:46 AM UTC 24
Finished Aug 27 08:06:48 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777971169 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1777971169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_regwen.2242316049
Short name T372
Test name
Test status
Simulation time 16125088783 ps
CPU time 1029.97 seconds
Started Aug 27 08:06:34 AM UTC 24
Finished Aug 27 08:23:55 AM UTC 24
Peak memory 386996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242316049 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2242316049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_smoke.1070527578
Short name T206
Test name
Test status
Simulation time 180043451 ps
CPU time 13.93 seconds
Started Aug 27 08:05:58 AM UTC 24
Finished Aug 27 08:06:13 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070527578 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1070527578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.293045538
Short name T585
Test name
Test status
Simulation time 43491113531 ps
CPU time 2091.93 seconds
Started Aug 27 08:06:56 AM UTC 24
Finished Aug 27 08:42:09 AM UTC 24
Peak memory 386868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293045538
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.293045538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1449789845
Short name T219
Test name
Test status
Simulation time 19365218552 ps
CPU time 69.17 seconds
Started Aug 27 08:06:55 AM UTC 24
Finished Aug 27 08:08:06 AM UTC 24
Peak memory 231408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449789845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1449789845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.952533629
Short name T239
Test name
Test status
Simulation time 13283196692 ps
CPU time 310.98 seconds
Started Aug 27 08:06:02 AM UTC 24
Finished Aug 27 08:11:17 AM UTC 24
Peak memory 214160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952533629 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.952533629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1162211963
Short name T207
Test name
Test status
Simulation time 38866812 ps
CPU time 1.77 seconds
Started Aug 27 08:06:14 AM UTC 24
Finished Aug 27 08:06:16 AM UTC 24
Peak memory 222864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1162211963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_t
hroughput_w_partial_write.1162211963
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3936634909
Short name T479
Test name
Test status
Simulation time 3967098259 ps
CPU time 1420.83 seconds
Started Aug 27 08:08:58 AM UTC 24
Finished Aug 27 08:32:54 AM UTC 24
Peak memory 384872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936634909 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_during
_key_req.3936634909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_alert_test.4143605917
Short name T227
Test name
Test status
Simulation time 167086271 ps
CPU time 0.88 seconds
Started Aug 27 08:09:30 AM UTC 24
Finished Aug 27 08:09:32 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143605917 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.4143605917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_bijection.1705227990
Short name T220
Test name
Test status
Simulation time 7446566681 ps
CPU time 61.86 seconds
Started Aug 27 08:07:37 AM UTC 24
Finished Aug 27 08:08:40 AM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705227990 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.1705227990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.3132847177
Short name T317
Test name
Test status
Simulation time 12412990972 ps
CPU time 560.24 seconds
Started Aug 27 08:09:08 AM UTC 24
Finished Aug 27 08:18:34 AM UTC 24
Peak memory 372580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132847177 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.3132847177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.2301367331
Short name T222
Test name
Test status
Simulation time 715372279 ps
CPU time 10.45 seconds
Started Aug 27 08:08:45 AM UTC 24
Finished Aug 27 08:08:57 AM UTC 24
Peak memory 213808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301367331 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.2301367331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2861913367
Short name T224
Test name
Test status
Simulation time 1242101603 ps
CPU time 33.63 seconds
Started Aug 27 08:08:41 AM UTC 24
Finished Aug 27 08:09:16 AM UTC 24
Peak memory 313132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
861913367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ma
x_throughput.2861913367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1691453085
Short name T226
Test name
Test status
Simulation time 340802506 ps
CPU time 4.51 seconds
Started Aug 27 08:09:21 AM UTC 24
Finished Aug 27 08:09:26 AM UTC 24
Peak memory 224112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691453085 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.1691453085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.1937383082
Short name T228
Test name
Test status
Simulation time 2715229646 ps
CPU time 15.89 seconds
Started Aug 27 08:09:18 AM UTC 24
Finished Aug 27 08:09:35 AM UTC 24
Peak memory 224400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937383082 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.1937383082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3466436850
Short name T276
Test name
Test status
Simulation time 25902265627 ps
CPU time 468.36 seconds
Started Aug 27 08:07:29 AM UTC 24
Finished Aug 27 08:15:23 AM UTC 24
Peak memory 374576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466436850 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.3466436850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2323810610
Short name T221
Test name
Test status
Simulation time 263861978 ps
CPU time 39.63 seconds
Started Aug 27 08:08:03 AM UTC 24
Finished Aug 27 08:08:44 AM UTC 24
Peak memory 305016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323810610 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.2323810610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.766230190
Short name T247
Test name
Test status
Simulation time 2649473757 ps
CPU time 237.7 seconds
Started Aug 27 08:08:07 AM UTC 24
Finished Aug 27 08:12:08 AM UTC 24
Peak memory 213904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766230190 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acce
ss_b2b.766230190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.786514980
Short name T225
Test name
Test status
Simulation time 48289929 ps
CPU time 1.21 seconds
Started Aug 27 08:09:17 AM UTC 24
Finished Aug 27 08:09:20 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786514980 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.786514980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.1378349456
Short name T373
Test name
Test status
Simulation time 2185373947 ps
CPU time 870.66 seconds
Started Aug 27 08:09:17 AM UTC 24
Finished Aug 27 08:23:57 AM UTC 24
Peak memory 376964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378349456 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1378349456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_smoke.4207703195
Short name T217
Test name
Test status
Simulation time 444860779 ps
CPU time 24.61 seconds
Started Aug 27 08:07:23 AM UTC 24
Finished Aug 27 08:07:49 AM UTC 24
Peak memory 302896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207703195 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.4207703195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3070715988
Short name T147
Test name
Test status
Simulation time 9683030972 ps
CPU time 414.44 seconds
Started Aug 27 08:09:27 AM UTC 24
Finished Aug 27 08:16:26 AM UTC 24
Peak memory 395096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307071598
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all.3070715988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2890351809
Short name T49
Test name
Test status
Simulation time 3493282312 ps
CPU time 343.25 seconds
Started Aug 27 08:09:26 AM UTC 24
Finished Aug 27 08:15:13 AM UTC 24
Peak memory 389024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890351809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2890351809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3530219961
Short name T244
Test name
Test status
Simulation time 3695925483 ps
CPU time 246.83 seconds
Started Aug 27 08:07:50 AM UTC 24
Finished Aug 27 08:12:01 AM UTC 24
Peak memory 213984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530219961 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.3530219961
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.3670946477
Short name T223
Test name
Test status
Simulation time 93520990 ps
CPU time 23.66 seconds
Started Aug 27 08:08:42 AM UTC 24
Finished Aug 27 08:09:07 AM UTC 24
Peak memory 282472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3670946477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_t
hroughput_w_partial_write.3670946477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.997616886
Short name T388
Test name
Test status
Simulation time 8645767729 ps
CPU time 834.73 seconds
Started Aug 27 08:10:55 AM UTC 24
Finished Aug 27 08:24:59 AM UTC 24
Peak memory 374832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997616886 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_during_
key_req.997616886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_alert_test.2186667942
Short name T242
Test name
Test status
Simulation time 19204921 ps
CPU time 0.87 seconds
Started Aug 27 08:11:30 AM UTC 24
Finished Aug 27 08:11:32 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186667942 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.2186667942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_bijection.1759758258
Short name T233
Test name
Test status
Simulation time 9250380105 ps
CPU time 66.79 seconds
Started Aug 27 08:09:40 AM UTC 24
Finished Aug 27 08:10:49 AM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759758258 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.1759758258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_executable.3403517642
Short name T338
Test name
Test status
Simulation time 34708068567 ps
CPU time 569.59 seconds
Started Aug 27 08:11:04 AM UTC 24
Finished Aug 27 08:20:39 AM UTC 24
Peak memory 384880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403517642 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.3403517642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2220143598
Short name T235
Test name
Test status
Simulation time 10245407603 ps
CPU time 11.26 seconds
Started Aug 27 08:10:51 AM UTC 24
Finished Aug 27 08:11:03 AM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220143598 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.2220143598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2527714936
Short name T234
Test name
Test status
Simulation time 124885553 ps
CPU time 8.12 seconds
Started Aug 27 08:10:45 AM UTC 24
Finished Aug 27 08:10:54 AM UTC 24
Peak memory 263968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
527714936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ma
x_throughput.2527714936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1764598259
Short name T240
Test name
Test status
Simulation time 379446551 ps
CPU time 4.98 seconds
Started Aug 27 08:11:18 AM UTC 24
Finished Aug 27 08:11:24 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764598259 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.1764598259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.144930862
Short name T241
Test name
Test status
Simulation time 3112960694 ps
CPU time 15.31 seconds
Started Aug 27 08:11:13 AM UTC 24
Finished Aug 27 08:11:29 AM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144930862 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.144930862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.156789277
Short name T292
Test name
Test status
Simulation time 44122974005 ps
CPU time 413.53 seconds
Started Aug 27 08:09:35 AM UTC 24
Finished Aug 27 08:16:34 AM UTC 24
Peak memory 356276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156789277 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.156789277
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3380483542
Short name T236
Test name
Test status
Simulation time 1033374945 ps
CPU time 25.12 seconds
Started Aug 27 08:10:41 AM UTC 24
Finished Aug 27 08:11:07 AM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380483542 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.3380483542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1693606993
Short name T332
Test name
Test status
Simulation time 36616150997 ps
CPU time 569.58 seconds
Started Aug 27 08:10:42 AM UTC 24
Finished Aug 27 08:20:18 AM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693606993 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_acc
ess_b2b.1693606993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2103520265
Short name T238
Test name
Test status
Simulation time 48590118 ps
CPU time 1.03 seconds
Started Aug 27 08:11:10 AM UTC 24
Finished Aug 27 08:11:12 AM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103520265 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2103520265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.539233657
Short name T301
Test name
Test status
Simulation time 2861678313 ps
CPU time 370.8 seconds
Started Aug 27 08:11:08 AM UTC 24
Finished Aug 27 08:17:23 AM UTC 24
Peak memory 387000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539233657 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.539233657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_smoke.3219642244
Short name T230
Test name
Test status
Simulation time 1141028096 ps
CPU time 18.11 seconds
Started Aug 27 08:09:33 AM UTC 24
Finished Aug 27 08:09:52 AM UTC 24
Peak memory 214092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219642244 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3219642244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.4077866369
Short name T780
Test name
Test status
Simulation time 8872690829 ps
CPU time 2930.19 seconds
Started Aug 27 08:11:25 AM UTC 24
Finished Aug 27 09:00:44 AM UTC 24
Peak memory 397080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407786636
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.4077866369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2528231010
Short name T279
Test name
Test status
Simulation time 10815592686 ps
CPU time 338.3 seconds
Started Aug 27 08:09:53 AM UTC 24
Finished Aug 27 08:15:36 AM UTC 24
Peak memory 214140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528231010 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.2528231010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.4145443814
Short name T237
Test name
Test status
Simulation time 83489341 ps
CPU time 17.84 seconds
Started Aug 27 08:10:50 AM UTC 24
Finished Aug 27 08:11:09 AM UTC 24
Peak memory 276260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4145443814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_t
hroughput_w_partial_write.4145443814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.537192820
Short name T368
Test name
Test status
Simulation time 9230529405 ps
CPU time 675 seconds
Started Aug 27 08:12:17 AM UTC 24
Finished Aug 27 08:23:40 AM UTC 24
Peak memory 376748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537192820 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_during_
key_req.537192820
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_alert_test.685212523
Short name T256
Test name
Test status
Simulation time 23263560 ps
CPU time 0.97 seconds
Started Aug 27 08:12:42 AM UTC 24
Finished Aug 27 08:12:44 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685212523 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.685212523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_bijection.2662127239
Short name T248
Test name
Test status
Simulation time 6841904453 ps
CPU time 36.29 seconds
Started Aug 27 08:11:47 AM UTC 24
Finished Aug 27 08:12:25 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662127239 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.2662127239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.1081268986
Short name T312
Test name
Test status
Simulation time 29280793784 ps
CPU time 347.73 seconds
Started Aug 27 08:12:26 AM UTC 24
Finished Aug 27 08:18:18 AM UTC 24
Peak memory 352196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081268986 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.1081268986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.4211301935
Short name T250
Test name
Test status
Simulation time 2050310428 ps
CPU time 10.65 seconds
Started Aug 27 08:12:17 AM UTC 24
Finished Aug 27 08:12:29 AM UTC 24
Peak memory 213844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211301935 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.4211301935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.29397420
Short name T258
Test name
Test status
Simulation time 286094793 ps
CPU time 53.69 seconds
Started Aug 27 08:12:09 AM UTC 24
Finished Aug 27 08:13:04 AM UTC 24
Peak memory 352112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
9397420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_max_
throughput.29397420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2904547222
Short name T254
Test name
Test status
Simulation time 598596339 ps
CPU time 4 seconds
Started Aug 27 08:12:34 AM UTC 24
Finished Aug 27 08:12:40 AM UTC 24
Peak memory 223992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904547222 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.2904547222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2098201754
Short name T257
Test name
Test status
Simulation time 1781096938 ps
CPU time 11.17 seconds
Started Aug 27 08:12:32 AM UTC 24
Finished Aug 27 08:12:45 AM UTC 24
Peak memory 224396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098201754 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.2098201754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.133143935
Short name T524
Test name
Test status
Simulation time 13149545840 ps
CPU time 1484.43 seconds
Started Aug 27 08:11:37 AM UTC 24
Finished Aug 27 08:36:37 AM UTC 24
Peak memory 384944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133143935 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.133143935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3868123859
Short name T261
Test name
Test status
Simulation time 2122386972 ps
CPU time 78.55 seconds
Started Aug 27 08:12:01 AM UTC 24
Finished Aug 27 08:13:22 AM UTC 24
Peak memory 341704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868123859 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.3868123859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.220704667
Short name T341
Test name
Test status
Simulation time 18429099074 ps
CPU time 526.59 seconds
Started Aug 27 08:12:07 AM UTC 24
Finished Aug 27 08:21:00 AM UTC 24
Peak memory 213932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220704667 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acce
ss_b2b.220704667
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.2184698735
Short name T251
Test name
Test status
Simulation time 74036039 ps
CPU time 1.44 seconds
Started Aug 27 08:12:29 AM UTC 24
Finished Aug 27 08:12:32 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184698735 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2184698735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_regwen.3047440402
Short name T145
Test name
Test status
Simulation time 6958781613 ps
CPU time 406.25 seconds
Started Aug 27 08:12:28 AM UTC 24
Finished Aug 27 08:19:20 AM UTC 24
Peak memory 385012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047440402 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3047440402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_smoke.4009706027
Short name T243
Test name
Test status
Simulation time 108593138 ps
CPU time 1.89 seconds
Started Aug 27 08:11:33 AM UTC 24
Finished Aug 27 08:11:36 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009706027 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.4009706027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3185969543
Short name T588
Test name
Test status
Simulation time 466137751228 ps
CPU time 1769.68 seconds
Started Aug 27 08:12:41 AM UTC 24
Finished Aug 27 08:42:28 AM UTC 24
Peak memory 388976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318596954
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.3185969543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.175209294
Short name T309
Test name
Test status
Simulation time 2644318565 ps
CPU time 316.08 seconds
Started Aug 27 08:12:36 AM UTC 24
Finished Aug 27 08:17:57 AM UTC 24
Peak memory 383284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175209294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.175209294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.3560189669
Short name T275
Test name
Test status
Simulation time 9847323257 ps
CPU time 200.37 seconds
Started Aug 27 08:11:55 AM UTC 24
Finished Aug 27 08:15:19 AM UTC 24
Peak memory 213916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560189669 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.3560189669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.2098106488
Short name T255
Test name
Test status
Simulation time 228011104 ps
CPU time 29.55 seconds
Started Aug 27 08:12:10 AM UTC 24
Finished Aug 27 08:12:41 AM UTC 24
Peak memory 313168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2098106488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_t
hroughput_w_partial_write.2098106488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3824522127
Short name T384
Test name
Test status
Simulation time 9854054063 ps
CPU time 651.64 seconds
Started Aug 27 08:13:45 AM UTC 24
Finished Aug 27 08:24:44 AM UTC 24
Peak memory 384864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824522127 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_during
_key_req.3824522127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_alert_test.4126084662
Short name T271
Test name
Test status
Simulation time 14382469 ps
CPU time 0.99 seconds
Started Aug 27 08:14:52 AM UTC 24
Finished Aug 27 08:14:54 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126084662 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.4126084662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_bijection.1319685500
Short name T263
Test name
Test status
Simulation time 2095354603 ps
CPU time 37.33 seconds
Started Aug 27 08:13:05 AM UTC 24
Finished Aug 27 08:13:44 AM UTC 24
Peak memory 213824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319685500 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.1319685500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_executable.1035535311
Short name T351
Test name
Test status
Simulation time 16738357443 ps
CPU time 483.33 seconds
Started Aug 27 08:13:46 AM UTC 24
Finished Aug 27 08:21:55 AM UTC 24
Peak memory 384896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035535311 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.1035535311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3600187192
Short name T265
Test name
Test status
Simulation time 1007306980 ps
CPU time 12.01 seconds
Started Aug 27 08:13:35 AM UTC 24
Finished Aug 27 08:13:48 AM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600187192 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.3600187192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1838620229
Short name T262
Test name
Test status
Simulation time 147621341 ps
CPU time 1.94 seconds
Started Aug 27 08:13:23 AM UTC 24
Finished Aug 27 08:13:26 AM UTC 24
Peak memory 222648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
838620229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ma
x_throughput.1838620229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3718762268
Short name T269
Test name
Test status
Simulation time 92341278 ps
CPU time 3.47 seconds
Started Aug 27 08:14:24 AM UTC 24
Finished Aug 27 08:14:29 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718762268 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.3718762268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.683881258
Short name T268
Test name
Test status
Simulation time 2629609768 ps
CPU time 13.69 seconds
Started Aug 27 08:14:08 AM UTC 24
Finished Aug 27 08:14:23 AM UTC 24
Peak memory 214132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683881258 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.683881258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.858891471
Short name T437
Test name
Test status
Simulation time 51001974416 ps
CPU time 954.84 seconds
Started Aug 27 08:12:46 AM UTC 24
Finished Aug 27 08:28:51 AM UTC 24
Peak memory 382828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858891471 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.858891471
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1290314684
Short name T272
Test name
Test status
Simulation time 3092597744 ps
CPU time 100.93 seconds
Started Aug 27 08:13:15 AM UTC 24
Finished Aug 27 08:14:58 AM UTC 24
Peak memory 378812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290314684 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.1290314684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2219231172
Short name T314
Test name
Test status
Simulation time 122445121099 ps
CPU time 298.39 seconds
Started Aug 27 08:13:21 AM UTC 24
Finished Aug 27 08:18:24 AM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219231172 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_acc
ess_b2b.2219231172
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.732233700
Short name T267
Test name
Test status
Simulation time 78602658 ps
CPU time 1.11 seconds
Started Aug 27 08:14:05 AM UTC 24
Finished Aug 27 08:14:08 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732233700 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.732233700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.1084475288
Short name T516
Test name
Test status
Simulation time 13273670220 ps
CPU time 1327.72 seconds
Started Aug 27 08:13:49 AM UTC 24
Finished Aug 27 08:36:10 AM UTC 24
Peak memory 385268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084475288 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1084475288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_smoke.3851146329
Short name T266
Test name
Test status
Simulation time 237926623 ps
CPU time 77.84 seconds
Started Aug 27 08:12:45 AM UTC 24
Finished Aug 27 08:14:04 AM UTC 24
Peak memory 362364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851146329 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.3851146329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.4101725303
Short name T756
Test name
Test status
Simulation time 42913363582 ps
CPU time 2623.93 seconds
Started Aug 27 08:14:41 AM UTC 24
Finished Aug 27 08:58:52 AM UTC 24
Peak memory 388728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410172530
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.4101725303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1060790055
Short name T369
Test name
Test status
Simulation time 7134707757 ps
CPU time 545.02 seconds
Started Aug 27 08:14:29 AM UTC 24
Finished Aug 27 08:23:40 AM UTC 24
Peak memory 391096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060790055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1060790055
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.4212934532
Short name T329
Test name
Test status
Simulation time 7186243199 ps
CPU time 407.24 seconds
Started Aug 27 08:13:09 AM UTC 24
Finished Aug 27 08:20:02 AM UTC 24
Peak memory 213976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212934532 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.4212934532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.936360568
Short name T264
Test name
Test status
Simulation time 282333503 ps
CPU time 15.75 seconds
Started Aug 27 08:13:27 AM UTC 24
Finished Aug 27 08:13:44 AM UTC 24
Peak memory 264044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
936360568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_th
roughput_w_partial_write.936360568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.238769324
Short name T481
Test name
Test status
Simulation time 13970450759 ps
CPU time 1048.86 seconds
Started Aug 27 08:15:37 AM UTC 24
Finished Aug 27 08:33:18 AM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238769324 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_during_
key_req.238769324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_alert_test.725826765
Short name T289
Test name
Test status
Simulation time 31627843 ps
CPU time 0.91 seconds
Started Aug 27 08:16:14 AM UTC 24
Finished Aug 27 08:16:15 AM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725826765 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.725826765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_bijection.1908101320
Short name T278
Test name
Test status
Simulation time 1044045554 ps
CPU time 28.76 seconds
Started Aug 27 08:15:06 AM UTC 24
Finished Aug 27 08:15:36 AM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908101320 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.1908101320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.1252678223
Short name T389
Test name
Test status
Simulation time 22057751655 ps
CPU time 562.2 seconds
Started Aug 27 08:15:46 AM UTC 24
Finished Aug 27 08:25:15 AM UTC 24
Peak memory 384948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252678223 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.1252678223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.384481325
Short name T282
Test name
Test status
Simulation time 1561927148 ps
CPU time 9.5 seconds
Started Aug 27 08:15:37 AM UTC 24
Finished Aug 27 08:15:48 AM UTC 24
Peak memory 213872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384481325 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.384481325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1593219348
Short name T290
Test name
Test status
Simulation time 116264558 ps
CPU time 53.08 seconds
Started Aug 27 08:15:23 AM UTC 24
Finished Aug 27 08:16:18 AM UTC 24
Peak memory 331824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
593219348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ma
x_throughput.1593219348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1716583999
Short name T287
Test name
Test status
Simulation time 199663823 ps
CPU time 8.17 seconds
Started Aug 27 08:16:00 AM UTC 24
Finished Aug 27 08:16:09 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716583999 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.1716583999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.544780777
Short name T284
Test name
Test status
Simulation time 74450994 ps
CPU time 6.13 seconds
Started Aug 27 08:15:52 AM UTC 24
Finished Aug 27 08:16:00 AM UTC 24
Peak memory 224152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544780777 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.544780777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.242741396
Short name T356
Test name
Test status
Simulation time 6947898579 ps
CPU time 434.65 seconds
Started Aug 27 08:14:59 AM UTC 24
Finished Aug 27 08:22:19 AM UTC 24
Peak memory 384944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242741396 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.242741396
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access.402998626
Short name T281
Test name
Test status
Simulation time 449732211 ps
CPU time 29.65 seconds
Started Aug 27 08:15:14 AM UTC 24
Finished Aug 27 08:15:45 AM UTC 24
Peak memory 298868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402998626 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.402998626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2525115373
Short name T324
Test name
Test status
Simulation time 3339264439 ps
CPU time 236.67 seconds
Started Aug 27 08:15:19 AM UTC 24
Finished Aug 27 08:19:19 AM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525115373 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_acc
ess_b2b.2525115373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1135212008
Short name T283
Test name
Test status
Simulation time 32573108 ps
CPU time 1.08 seconds
Started Aug 27 08:15:49 AM UTC 24
Finished Aug 27 08:15:51 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135212008 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1135212008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.258274757
Short name T409
Test name
Test status
Simulation time 2987479311 ps
CPU time 643.05 seconds
Started Aug 27 08:15:46 AM UTC 24
Finished Aug 27 08:26:36 AM UTC 24
Peak memory 386996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258274757 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.258274757
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_smoke.539072243
Short name T277
Test name
Test status
Simulation time 203957906 ps
CPU time 38.23 seconds
Started Aug 27 08:14:55 AM UTC 24
Finished Aug 27 08:15:34 AM UTC 24
Peak memory 335732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539072243 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.539072243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all.3575358502
Short name T362
Test name
Test status
Simulation time 9687462416 ps
CPU time 407.12 seconds
Started Aug 27 08:16:10 AM UTC 24
Finished Aug 27 08:23:02 AM UTC 24
Peak memory 384948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357535850
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.3575358502
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3370328444
Short name T291
Test name
Test status
Simulation time 488351632 ps
CPU time 22.99 seconds
Started Aug 27 08:16:01 AM UTC 24
Finished Aug 27 08:16:26 AM UTC 24
Peak memory 224440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370328444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3370328444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2615954387
Short name T322
Test name
Test status
Simulation time 1885528131 ps
CPU time 234.5 seconds
Started Aug 27 08:15:09 AM UTC 24
Finished Aug 27 08:19:07 AM UTC 24
Peak memory 214156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615954387 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.2615954387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2555590382
Short name T294
Test name
Test status
Simulation time 513225311 ps
CPU time 77.89 seconds
Started Aug 27 08:15:35 AM UTC 24
Finished Aug 27 08:16:56 AM UTC 24
Peak memory 358252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2555590382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t
hroughput_w_partial_write.2555590382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3919190465
Short name T557
Test name
Test status
Simulation time 22404023084 ps
CPU time 1351.31 seconds
Started Aug 27 08:17:05 AM UTC 24
Finished Aug 27 08:39:50 AM UTC 24
Peak memory 385204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919190465 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_during
_key_req.3919190465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.4198806836
Short name T304
Test name
Test status
Simulation time 28500716 ps
CPU time 0.88 seconds
Started Aug 27 08:17:26 AM UTC 24
Finished Aug 27 08:17:28 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198806836 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.4198806836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_bijection.1523855778
Short name T299
Test name
Test status
Simulation time 1391241229 ps
CPU time 45.74 seconds
Started Aug 27 08:16:27 AM UTC 24
Finished Aug 27 08:17:14 AM UTC 24
Peak memory 213800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523855778 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.1523855778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.2153019874
Short name T408
Test name
Test status
Simulation time 4181229678 ps
CPU time 557.87 seconds
Started Aug 27 08:17:10 AM UTC 24
Finished Aug 27 08:26:35 AM UTC 24
Peak memory 385208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153019874 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.2153019874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.729534220
Short name T296
Test name
Test status
Simulation time 1052340436 ps
CPU time 10.02 seconds
Started Aug 27 08:16:58 AM UTC 24
Finished Aug 27 08:17:09 AM UTC 24
Peak memory 224108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729534220 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.729534220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1868016327
Short name T308
Test name
Test status
Simulation time 135195684 ps
CPU time 61.79 seconds
Started Aug 27 08:16:47 AM UTC 24
Finished Aug 27 08:17:50 AM UTC 24
Peak memory 370544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
868016327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ma
x_throughput.1868016327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3965705271
Short name T302
Test name
Test status
Simulation time 353587698 ps
CPU time 4.21 seconds
Started Aug 27 08:17:18 AM UTC 24
Finished Aug 27 08:17:24 AM UTC 24
Peak memory 224344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965705271 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.3965705271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1562702970
Short name T305
Test name
Test status
Simulation time 691683289 ps
CPU time 14.11 seconds
Started Aug 27 08:17:15 AM UTC 24
Finished Aug 27 08:17:31 AM UTC 24
Peak memory 224056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562702970 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.1562702970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.1490476500
Short name T476
Test name
Test status
Simulation time 18174052529 ps
CPU time 978.55 seconds
Started Aug 27 08:16:19 AM UTC 24
Finished Aug 27 08:32:47 AM UTC 24
Peak memory 384940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490476500 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.1490476500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.310677835
Short name T310
Test name
Test status
Simulation time 218273977 ps
CPU time 83.86 seconds
Started Aug 27 08:16:35 AM UTC 24
Finished Aug 27 08:18:01 AM UTC 24
Peak memory 378740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310677835 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.310677835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1996159733
Short name T412
Test name
Test status
Simulation time 67546412294 ps
CPU time 614.14 seconds
Started Aug 27 08:16:43 AM UTC 24
Finished Aug 27 08:27:05 AM UTC 24
Peak memory 213996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996159733 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_acc
ess_b2b.1996159733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.1664871269
Short name T300
Test name
Test status
Simulation time 28053145 ps
CPU time 1.12 seconds
Started Aug 27 08:17:15 AM UTC 24
Finished Aug 27 08:17:17 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664871269 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1664871269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_regwen.486626652
Short name T492
Test name
Test status
Simulation time 2529556656 ps
CPU time 990.63 seconds
Started Aug 27 08:17:10 AM UTC 24
Finished Aug 27 08:33:52 AM UTC 24
Peak memory 387252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486626652 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.486626652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_smoke.67686866
Short name T285
Test name
Test status
Simulation time 421706525 ps
CPU time 28.15 seconds
Started Aug 27 08:16:17 AM UTC 24
Finished Aug 27 08:16:46 AM UTC 24
Peak memory 286588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67686866 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.67686866
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3273637045
Short name T439
Test name
Test status
Simulation time 4355464963 ps
CPU time 695.34 seconds
Started Aug 27 08:17:25 AM UTC 24
Finished Aug 27 08:29:07 AM UTC 24
Peak memory 395120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327363704
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.3273637045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.4038460360
Short name T111
Test name
Test status
Simulation time 4440803281 ps
CPU time 64.08 seconds
Started Aug 27 08:17:25 AM UTC 24
Finished Aug 27 08:18:31 AM UTC 24
Peak memory 295152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038460360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.4038460360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2448476229
Short name T345
Test name
Test status
Simulation time 2417365835 ps
CPU time 301.36 seconds
Started Aug 27 08:16:27 AM UTC 24
Finished Aug 27 08:21:33 AM UTC 24
Peak memory 213964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448476229 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.2448476229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.535565941
Short name T297
Test name
Test status
Simulation time 131872213 ps
CPU time 10.24 seconds
Started Aug 27 08:16:58 AM UTC 24
Finished Aug 27 08:17:09 AM UTC 24
Peak memory 254060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
535565941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_th
roughput_w_partial_write.535565941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.4284895278
Short name T376
Test name
Test status
Simulation time 25708238656 ps
CPU time 349.55 seconds
Started Aug 27 08:18:19 AM UTC 24
Finished Aug 27 08:24:13 AM UTC 24
Peak memory 370800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284895278 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_during
_key_req.4284895278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2985586550
Short name T320
Test name
Test status
Simulation time 28851951 ps
CPU time 0.98 seconds
Started Aug 27 08:18:45 AM UTC 24
Finished Aug 27 08:18:47 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985586550 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2985586550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.2189745977
Short name T311
Test name
Test status
Simulation time 16719002298 ps
CPU time 30.06 seconds
Started Aug 27 08:17:32 AM UTC 24
Finished Aug 27 08:18:03 AM UTC 24
Peak memory 213812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189745977 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.2189745977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_executable.1033584651
Short name T394
Test name
Test status
Simulation time 16055657358 ps
CPU time 432.07 seconds
Started Aug 27 08:18:21 AM UTC 24
Finished Aug 27 08:25:38 AM UTC 24
Peak memory 354500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033584651 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.1033584651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2559137782
Short name T315
Test name
Test status
Simulation time 2131267503 ps
CPU time 12.61 seconds
Started Aug 27 08:18:17 AM UTC 24
Finished Aug 27 08:18:31 AM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559137782 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2559137782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.397429418
Short name T326
Test name
Test status
Simulation time 895022442 ps
CPU time 92.42 seconds
Started Aug 27 08:18:02 AM UTC 24
Finished Aug 27 08:19:36 AM UTC 24
Peak memory 376952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
97429418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_max
_throughput.397429418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.365763536
Short name T319
Test name
Test status
Simulation time 187586646 ps
CPU time 8.85 seconds
Started Aug 27 08:18:35 AM UTC 24
Finished Aug 27 08:18:44 AM UTC 24
Peak memory 223980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365763536 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.365763536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3703275470
Short name T318
Test name
Test status
Simulation time 182923418 ps
CPU time 6.52 seconds
Started Aug 27 08:18:31 AM UTC 24
Finished Aug 27 08:18:39 AM UTC 24
Peak memory 224008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703275470 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.3703275470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.941967895
Short name T398
Test name
Test status
Simulation time 42517933229 ps
CPU time 492.07 seconds
Started Aug 27 08:17:31 AM UTC 24
Finished Aug 27 08:25:49 AM UTC 24
Peak memory 350380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941967895 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.941967895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.799272439
Short name T313
Test name
Test status
Simulation time 5627957226 ps
CPU time 29.02 seconds
Started Aug 27 08:17:50 AM UTC 24
Finished Aug 27 08:18:21 AM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799272439 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.799272439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1220555449
Short name T407
Test name
Test status
Simulation time 17249248445 ps
CPU time 507.98 seconds
Started Aug 27 08:17:58 AM UTC 24
Finished Aug 27 08:26:32 AM UTC 24
Peak memory 213900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220555449 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_acc
ess_b2b.1220555449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.432579111
Short name T316
Test name
Test status
Simulation time 112690332 ps
CPU time 1.06 seconds
Started Aug 27 08:18:31 AM UTC 24
Finished Aug 27 08:18:34 AM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432579111 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.432579111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.1500810350
Short name T441
Test name
Test status
Simulation time 11168285894 ps
CPU time 649.9 seconds
Started Aug 27 08:18:24 AM UTC 24
Finished Aug 27 08:29:22 AM UTC 24
Peak memory 383160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500810350 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1500810350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.3368279205
Short name T307
Test name
Test status
Simulation time 331529400 ps
CPU time 12.32 seconds
Started Aug 27 08:17:29 AM UTC 24
Finished Aug 27 08:17:43 AM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368279205 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3368279205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2561026496
Short name T928
Test name
Test status
Simulation time 276502918008 ps
CPU time 4264.52 seconds
Started Aug 27 08:18:40 AM UTC 24
Finished Aug 27 09:30:27 AM UTC 24
Peak memory 388704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256102649
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.2561026496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3728239850
Short name T363
Test name
Test status
Simulation time 10484554963 ps
CPU time 319.35 seconds
Started Aug 27 08:17:43 AM UTC 24
Finished Aug 27 08:23:07 AM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728239850 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.3728239850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.520039456
Short name T323
Test name
Test status
Simulation time 454050635 ps
CPU time 62.14 seconds
Started Aug 27 08:18:05 AM UTC 24
Finished Aug 27 08:19:09 AM UTC 24
Peak memory 331552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
520039456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_th
roughput_w_partial_write.520039456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.12573497
Short name T429
Test name
Test status
Simulation time 5930493946 ps
CPU time 507.18 seconds
Started Aug 27 08:19:37 AM UTC 24
Finished Aug 27 08:28:10 AM UTC 24
Peak memory 370600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12573497 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_during_k
ey_req.12573497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2646290238
Short name T335
Test name
Test status
Simulation time 52070284 ps
CPU time 0.94 seconds
Started Aug 27 08:20:23 AM UTC 24
Finished Aug 27 08:20:25 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646290238 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2646290238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.3486065081
Short name T325
Test name
Test status
Simulation time 2457667475 ps
CPU time 17.78 seconds
Started Aug 27 08:19:08 AM UTC 24
Finished Aug 27 08:19:27 AM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486065081 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.3486065081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.88059606
Short name T360
Test name
Test status
Simulation time 2623387984 ps
CPU time 194.1 seconds
Started Aug 27 08:19:37 AM UTC 24
Finished Aug 27 08:22:54 AM UTC 24
Peak memory 329532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88059606 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.88059606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.723640429
Short name T327
Test name
Test status
Simulation time 1697080545 ps
CPU time 7.2 seconds
Started Aug 27 08:19:28 AM UTC 24
Finished Aug 27 08:19:36 AM UTC 24
Peak memory 228164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723640429 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.723640429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.123762079
Short name T339
Test name
Test status
Simulation time 2022325326 ps
CPU time 88.37 seconds
Started Aug 27 08:19:21 AM UTC 24
Finished Aug 27 08:20:51 AM UTC 24
Peak memory 374972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
23762079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_max
_throughput.123762079
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.83781833
Short name T333
Test name
Test status
Simulation time 99745242 ps
CPU time 4.2 seconds
Started Aug 27 08:20:16 AM UTC 24
Finished Aug 27 08:20:21 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83781833 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.83781833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.1280878562
Short name T331
Test name
Test status
Simulation time 801306741 ps
CPU time 7.71 seconds
Started Aug 27 08:20:06 AM UTC 24
Finished Aug 27 08:20:15 AM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280878562 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.1280878562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2974214302
Short name T424
Test name
Test status
Simulation time 11672482982 ps
CPU time 510.6 seconds
Started Aug 27 08:19:07 AM UTC 24
Finished Aug 27 08:27:44 AM UTC 24
Peak memory 366436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974214302 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.2974214302
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2664342862
Short name T334
Test name
Test status
Simulation time 1157333027 ps
CPU time 66.62 seconds
Started Aug 27 08:19:13 AM UTC 24
Finished Aug 27 08:20:22 AM UTC 24
Peak memory 337732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664342862 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.2664342862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.401782275
Short name T385
Test name
Test status
Simulation time 3530077356 ps
CPU time 319.6 seconds
Started Aug 27 08:19:21 AM UTC 24
Finished Aug 27 08:24:45 AM UTC 24
Peak memory 213992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401782275 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_acce
ss_b2b.401782275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.903140097
Short name T330
Test name
Test status
Simulation time 86020850 ps
CPU time 1.03 seconds
Started Aug 27 08:20:03 AM UTC 24
Finished Aug 27 08:20:05 AM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903140097 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.903140097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.1268825912
Short name T349
Test name
Test status
Simulation time 3561765148 ps
CPU time 110.39 seconds
Started Aug 27 08:19:54 AM UTC 24
Finished Aug 27 08:21:47 AM UTC 24
Peak memory 342200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268825912 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1268825912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.3524197248
Short name T321
Test name
Test status
Simulation time 226302157 ps
CPU time 16.55 seconds
Started Aug 27 08:18:48 AM UTC 24
Finished Aug 27 08:19:06 AM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524197248 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3524197248
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3650111880
Short name T776
Test name
Test status
Simulation time 39215997710 ps
CPU time 2367.96 seconds
Started Aug 27 08:20:22 AM UTC 24
Finished Aug 27 09:00:13 AM UTC 24
Peak memory 388720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365011188
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all.3650111880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1304009647
Short name T411
Test name
Test status
Simulation time 16036109716 ps
CPU time 465.18 seconds
Started Aug 27 08:19:09 AM UTC 24
Finished Aug 27 08:27:01 AM UTC 24
Peak memory 213916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304009647 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.1304009647
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3161232981
Short name T328
Test name
Test status
Simulation time 287821817 ps
CPU time 28.56 seconds
Started Aug 27 08:19:24 AM UTC 24
Finished Aug 27 08:19:54 AM UTC 24
Peak memory 309096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3161232981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_t
hroughput_w_partial_write.3161232981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.4121824625
Short name T425
Test name
Test status
Simulation time 1811689216 ps
CPU time 387.41 seconds
Started Aug 27 08:21:20 AM UTC 24
Finished Aug 27 08:27:52 AM UTC 24
Peak memory 364320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121824625 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_during
_key_req.4121824625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2651470781
Short name T353
Test name
Test status
Simulation time 40226114 ps
CPU time 0.88 seconds
Started Aug 27 08:21:57 AM UTC 24
Finished Aug 27 08:22:00 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651470781 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.2651470781
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.905725073
Short name T355
Test name
Test status
Simulation time 13805913354 ps
CPU time 91.93 seconds
Started Aug 27 08:20:31 AM UTC 24
Finished Aug 27 08:22:04 AM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905725073 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.905725073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1894079133
Short name T433
Test name
Test status
Simulation time 10210491117 ps
CPU time 418.36 seconds
Started Aug 27 08:21:27 AM UTC 24
Finished Aug 27 08:28:30 AM UTC 24
Peak memory 376692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894079133 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.1894079133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3113481846
Short name T343
Test name
Test status
Simulation time 4698857711 ps
CPU time 11.37 seconds
Started Aug 27 08:21:07 AM UTC 24
Finished Aug 27 08:21:20 AM UTC 24
Peak memory 224124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113481846 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.3113481846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2443536966
Short name T346
Test name
Test status
Simulation time 90280735 ps
CPU time 41.09 seconds
Started Aug 27 08:20:57 AM UTC 24
Finished Aug 27 08:21:40 AM UTC 24
Peak memory 304936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
443536966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ma
x_throughput.2443536966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.4014669809
Short name T352
Test name
Test status
Simulation time 310957616 ps
CPU time 7.24 seconds
Started Aug 27 08:21:48 AM UTC 24
Finished Aug 27 08:21:57 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014669809 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.4014669809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3436871201
Short name T350
Test name
Test status
Simulation time 200874195 ps
CPU time 5.17 seconds
Started Aug 27 08:21:45 AM UTC 24
Finished Aug 27 08:21:51 AM UTC 24
Peak memory 224008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436871201 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.3436871201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.3564722107
Short name T427
Test name
Test status
Simulation time 12678241645 ps
CPU time 452.97 seconds
Started Aug 27 08:20:27 AM UTC 24
Finished Aug 27 08:28:06 AM UTC 24
Peak memory 384944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564722107 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.3564722107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3635327170
Short name T344
Test name
Test status
Simulation time 197215774 ps
CPU time 44.13 seconds
Started Aug 27 08:20:40 AM UTC 24
Finished Aug 27 08:21:25 AM UTC 24
Peak memory 362616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635327170 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.3635327170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.4260441518
Short name T390
Test name
Test status
Simulation time 32240522171 ps
CPU time 259.16 seconds
Started Aug 27 08:20:52 AM UTC 24
Finished Aug 27 08:25:15 AM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260441518 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_acc
ess_b2b.4260441518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.4053446167
Short name T347
Test name
Test status
Simulation time 30796936 ps
CPU time 1.21 seconds
Started Aug 27 08:21:41 AM UTC 24
Finished Aug 27 08:21:44 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053446167 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.4053446167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.738105152
Short name T499
Test name
Test status
Simulation time 25881730734 ps
CPU time 753.29 seconds
Started Aug 27 08:21:34 AM UTC 24
Finished Aug 27 08:34:17 AM UTC 24
Peak memory 366520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738105152 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.738105152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.1049579650
Short name T340
Test name
Test status
Simulation time 970475300 ps
CPU time 28.13 seconds
Started Aug 27 08:20:26 AM UTC 24
Finished Aug 27 08:20:56 AM UTC 24
Peak memory 213824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049579650 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.1049579650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2446150208
Short name T911
Test name
Test status
Simulation time 226685462447 ps
CPU time 3413.71 seconds
Started Aug 27 08:21:55 AM UTC 24
Finished Aug 27 09:19:24 AM UTC 24
Peak memory 388788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244615020
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all.2446150208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1283844135
Short name T354
Test name
Test status
Simulation time 799750759 ps
CPU time 10.61 seconds
Started Aug 27 08:21:52 AM UTC 24
Finished Aug 27 08:22:04 AM UTC 24
Peak memory 231212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283844135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.1283844135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.1120917457
Short name T380
Test name
Test status
Simulation time 7436242502 ps
CPU time 232.67 seconds
Started Aug 27 08:20:36 AM UTC 24
Finished Aug 27 08:24:32 AM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120917457 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.1120917457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.2736768114
Short name T342
Test name
Test status
Simulation time 49834777 ps
CPU time 4.3 seconds
Started Aug 27 08:21:01 AM UTC 24
Finished Aug 27 08:21:06 AM UTC 24
Peak memory 231536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2736768114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_t
hroughput_w_partial_write.2736768114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1929908505
Short name T260
Test name
Test status
Simulation time 3350501677 ps
CPU time 812.7 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 08:13:14 AM UTC 24
Peak memory 384916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929908505 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during_
key_req.1929908505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2246238198
Short name T14
Test name
Test status
Simulation time 54690088 ps
CPU time 0.62 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 07:59:34 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246238198 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.2246238198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_bijection.3684653210
Short name T162
Test name
Test status
Simulation time 12719439130 ps
CPU time 67.87 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 07:59:54 AM UTC 24
Peak memory 213792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684653210 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.3684653210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_executable.3343974507
Short name T144
Test name
Test status
Simulation time 10409886806 ps
CPU time 1168.36 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 08:19:13 AM UTC 24
Peak memory 386796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343974507 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.3343974507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2591681183
Short name T10
Test name
Test status
Simulation time 524872271 ps
CPU time 6.07 seconds
Started Aug 27 07:59:31 AM UTC 24
Finished Aug 27 07:59:38 AM UTC 24
Peak memory 214132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591681183 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.2591681183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3728537880
Short name T171
Test name
Test status
Simulation time 904789215 ps
CPU time 45.75 seconds
Started Aug 27 07:59:31 AM UTC 24
Finished Aug 27 08:00:18 AM UTC 24
Peak memory 345892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
728537880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_max
_throughput.3728537880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.4232831863
Short name T42
Test name
Test status
Simulation time 326118767 ps
CPU time 5.87 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 07:59:39 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232831863 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.4232831863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.889194716
Short name T46
Test name
Test status
Simulation time 411612296 ps
CPU time 5.02 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 07:59:39 AM UTC 24
Peak memory 223828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889194716 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.889194716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4093094574
Short name T229
Test name
Test status
Simulation time 34889681425 ps
CPU time 648.06 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 08:09:39 AM UTC 24
Peak memory 386872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093094574 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.4093094574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access.4037706253
Short name T26
Test name
Test status
Simulation time 4842528949 ps
CPU time 19.83 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 07:59:05 AM UTC 24
Peak memory 213892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037706253 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.4037706253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1110918425
Short name T150
Test name
Test status
Simulation time 68287492482 ps
CPU time 421 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 08:05:50 AM UTC 24
Peak memory 213984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110918425 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acce
ss_b2b.1110918425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_regwen.1675243049
Short name T19
Test name
Test status
Simulation time 29822649746 ps
CPU time 253.72 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 08:03:50 AM UTC 24
Peak memory 362188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675243049 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1675243049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2386743816
Short name T31
Test name
Test status
Simulation time 597467482 ps
CPU time 5.41 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 07:59:39 AM UTC 24
Peak memory 250132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386743816 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2386743816
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_smoke.258348117
Short name T35
Test name
Test status
Simulation time 439877151 ps
CPU time 6.56 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 07:58:52 AM UTC 24
Peak memory 213944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258348117 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.258348117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1812905875
Short name T607
Test name
Test status
Simulation time 71445550534 ps
CPU time 2634.28 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 08:43:54 AM UTC 24
Peak memory 397108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181290587
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.1812905875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4213483007
Short name T25
Test name
Test status
Simulation time 906118147 ps
CPU time 64.99 seconds
Started Aug 27 07:59:32 AM UTC 24
Finished Aug 27 08:00:39 AM UTC 24
Peak memory 345964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213483007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.4213483007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.4228042882
Short name T203
Test name
Test status
Simulation time 3874813676 ps
CPU time 431.96 seconds
Started Aug 27 07:58:44 AM UTC 24
Finished Aug 27 08:06:02 AM UTC 24
Peak memory 213820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228042882 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.4228042882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3233605501
Short name T119
Test name
Test status
Simulation time 175624349 ps
CPU time 77.68 seconds
Started Aug 27 07:59:31 AM UTC 24
Finished Aug 27 08:00:50 AM UTC 24
Peak memory 374636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3233605501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_th
roughput_w_partial_write.3233605501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3418069887
Short name T597
Test name
Test status
Simulation time 6768143447 ps
CPU time 1181.49 seconds
Started Aug 27 08:23:01 AM UTC 24
Finished Aug 27 08:42:55 AM UTC 24
Peak memory 384880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418069887 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_during
_key_req.3418069887
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.3979986875
Short name T370
Test name
Test status
Simulation time 18227880 ps
CPU time 0.93 seconds
Started Aug 27 08:23:42 AM UTC 24
Finished Aug 27 08:23:44 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979986875 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.3979986875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.2936764331
Short name T371
Test name
Test status
Simulation time 11478271944 ps
CPU time 99.14 seconds
Started Aug 27 08:22:06 AM UTC 24
Finished Aug 27 08:23:47 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936764331 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.2936764331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_executable.3064301782
Short name T518
Test name
Test status
Simulation time 8595258160 ps
CPU time 786.89 seconds
Started Aug 27 08:23:04 AM UTC 24
Finished Aug 27 08:36:19 AM UTC 24
Peak memory 384884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064301782 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.3064301782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.284387664
Short name T361
Test name
Test status
Simulation time 689652270 ps
CPU time 3.36 seconds
Started Aug 27 08:22:55 AM UTC 24
Finished Aug 27 08:23:00 AM UTC 24
Peak memory 213988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284387664 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.284387664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.3961047520
Short name T359
Test name
Test status
Simulation time 227162437 ps
CPU time 9.27 seconds
Started Aug 27 08:22:28 AM UTC 24
Finished Aug 27 08:22:39 AM UTC 24
Peak memory 252012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
961047520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ma
x_throughput.3961047520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1625693505
Short name T367
Test name
Test status
Simulation time 107958338 ps
CPU time 3.93 seconds
Started Aug 27 08:23:28 AM UTC 24
Finished Aug 27 08:23:33 AM UTC 24
Peak memory 223960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625693505 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.1625693505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.1576781651
Short name T366
Test name
Test status
Simulation time 229919273 ps
CPU time 7.85 seconds
Started Aug 27 08:23:18 AM UTC 24
Finished Aug 27 08:23:27 AM UTC 24
Peak memory 224396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576781651 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.1576781651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3219756423
Short name T606
Test name
Test status
Simulation time 64900282935 ps
CPU time 1292.41 seconds
Started Aug 27 08:22:05 AM UTC 24
Finished Aug 27 08:43:51 AM UTC 24
Peak memory 387244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219756423 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.3219756423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.19275874
Short name T357
Test name
Test status
Simulation time 196755868 ps
CPU time 2.79 seconds
Started Aug 27 08:22:20 AM UTC 24
Finished Aug 27 08:22:24 AM UTC 24
Peak memory 214160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19275874 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.19275874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.3074878629
Short name T464
Test name
Test status
Simulation time 87240685630 ps
CPU time 556.11 seconds
Started Aug 27 08:22:25 AM UTC 24
Finished Aug 27 08:31:48 AM UTC 24
Peak memory 214272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074878629 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc
ess_b2b.3074878629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3836753139
Short name T365
Test name
Test status
Simulation time 86823001 ps
CPU time 1.04 seconds
Started Aug 27 08:23:15 AM UTC 24
Finished Aug 27 08:23:17 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836753139 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3836753139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.359726185
Short name T377
Test name
Test status
Simulation time 4862454867 ps
CPU time 70.59 seconds
Started Aug 27 08:23:08 AM UTC 24
Finished Aug 27 08:24:20 AM UTC 24
Peak memory 290676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359726185 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.359726185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.3948702601
Short name T348
Test name
Test status
Simulation time 214002895 ps
CPU time 5.2 seconds
Started Aug 27 08:22:00 AM UTC 24
Finished Aug 27 08:22:07 AM UTC 24
Peak memory 213860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948702601 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3948702601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3086947787
Short name T830
Test name
Test status
Simulation time 41040849679 ps
CPU time 2413.21 seconds
Started Aug 27 08:23:41 AM UTC 24
Finished Aug 27 09:04:19 AM UTC 24
Peak memory 388712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308694778
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.3086947787
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1594427322
Short name T112
Test name
Test status
Simulation time 292696247 ps
CPU time 12.37 seconds
Started Aug 27 08:23:34 AM UTC 24
Finished Aug 27 08:23:48 AM UTC 24
Peak memory 224232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594427322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1594427322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.1097755113
Short name T417
Test name
Test status
Simulation time 12744490794 ps
CPU time 311.39 seconds
Started Aug 27 08:22:08 AM UTC 24
Finished Aug 27 08:27:24 AM UTC 24
Peak memory 213960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097755113 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.1097755113
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1183000360
Short name T364
Test name
Test status
Simulation time 144689897 ps
CPU time 33.02 seconds
Started Aug 27 08:22:39 AM UTC 24
Finished Aug 27 08:23:14 AM UTC 24
Peak memory 296940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1183000360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_t
hroughput_w_partial_write.1183000360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2105197762
Short name T498
Test name
Test status
Simulation time 3143833400 ps
CPU time 588.39 seconds
Started Aug 27 08:24:21 AM UTC 24
Finished Aug 27 08:34:16 AM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105197762 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_during
_key_req.2105197762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.3592445186
Short name T387
Test name
Test status
Simulation time 27133589 ps
CPU time 0.92 seconds
Started Aug 27 08:24:46 AM UTC 24
Finished Aug 27 08:24:48 AM UTC 24
Peak memory 212576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592445186 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.3592445186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.1283569393
Short name T379
Test name
Test status
Simulation time 489763166 ps
CPU time 34.78 seconds
Started Aug 27 08:23:49 AM UTC 24
Finished Aug 27 08:24:25 AM UTC 24
Peak memory 213820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283569393 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.1283569393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1468652025
Short name T549
Test name
Test status
Simulation time 27605922716 ps
CPU time 875.26 seconds
Started Aug 27 08:24:26 AM UTC 24
Finished Aug 27 08:39:11 AM UTC 24
Peak memory 376968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468652025 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.1468652025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.26493772
Short name T378
Test name
Test status
Simulation time 2555554462 ps
CPU time 10.03 seconds
Started Aug 27 08:24:14 AM UTC 24
Finished Aug 27 08:24:25 AM UTC 24
Peak memory 224452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26493772 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.26493772
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3093634875
Short name T393
Test name
Test status
Simulation time 146244535 ps
CPU time 88.27 seconds
Started Aug 27 08:24:05 AM UTC 24
Finished Aug 27 08:25:35 AM UTC 24
Peak memory 374632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
093634875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ma
x_throughput.3093634875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.870043748
Short name T383
Test name
Test status
Simulation time 374030661 ps
CPU time 4.18 seconds
Started Aug 27 08:24:36 AM UTC 24
Finished Aug 27 08:24:41 AM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870043748 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.870043748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.2925090689
Short name T386
Test name
Test status
Simulation time 744236588 ps
CPU time 9.72 seconds
Started Aug 27 08:24:35 AM UTC 24
Finished Aug 27 08:24:45 AM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925090689 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.2925090689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.4099246733
Short name T405
Test name
Test status
Simulation time 3434480824 ps
CPU time 147.43 seconds
Started Aug 27 08:23:48 AM UTC 24
Finished Aug 27 08:26:18 AM UTC 24
Peak memory 385196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099246733 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.4099246733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1422677604
Short name T375
Test name
Test status
Simulation time 330583079 ps
CPU time 7.59 seconds
Started Aug 27 08:23:56 AM UTC 24
Finished Aug 27 08:24:05 AM UTC 24
Peak memory 235512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422677604 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.1422677604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2005818685
Short name T451
Test name
Test status
Simulation time 5129428702 ps
CPU time 384.12 seconds
Started Aug 27 08:23:58 AM UTC 24
Finished Aug 27 08:30:28 AM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005818685 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_acc
ess_b2b.2005818685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2049869439
Short name T382
Test name
Test status
Simulation time 50167671 ps
CPU time 1.21 seconds
Started Aug 27 08:24:32 AM UTC 24
Finished Aug 27 08:24:35 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049869439 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2049869439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.3592790243
Short name T423
Test name
Test status
Simulation time 1668750454 ps
CPU time 191.75 seconds
Started Aug 27 08:24:26 AM UTC 24
Finished Aug 27 08:27:41 AM UTC 24
Peak memory 384888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592790243 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3592790243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.4281407977
Short name T381
Test name
Test status
Simulation time 429077331 ps
CPU time 47.82 seconds
Started Aug 27 08:23:45 AM UTC 24
Finished Aug 27 08:24:34 AM UTC 24
Peak memory 317556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281407977 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.4281407977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.54622475
Short name T742
Test name
Test status
Simulation time 127561515051 ps
CPU time 1934.41 seconds
Started Aug 27 08:24:45 AM UTC 24
Finished Aug 27 08:57:19 AM UTC 24
Peak memory 387236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54622475
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.54622475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.4036296023
Short name T404
Test name
Test status
Simulation time 803320706 ps
CPU time 85.61 seconds
Started Aug 27 08:24:42 AM UTC 24
Finished Aug 27 08:26:10 AM UTC 24
Peak memory 311140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036296023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.4036296023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.2559700070
Short name T442
Test name
Test status
Simulation time 6753070055 ps
CPU time 331.25 seconds
Started Aug 27 08:23:54 AM UTC 24
Finished Aug 27 08:29:30 AM UTC 24
Peak memory 213904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559700070 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.2559700070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1128743289
Short name T395
Test name
Test status
Simulation time 581504970 ps
CPU time 90.48 seconds
Started Aug 27 08:24:06 AM UTC 24
Finished Aug 27 08:25:38 AM UTC 24
Peak memory 380776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1128743289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_t
hroughput_w_partial_write.1128743289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.4208452299
Short name T485
Test name
Test status
Simulation time 32427163612 ps
CPU time 458.37 seconds
Started Aug 27 08:25:39 AM UTC 24
Finished Aug 27 08:33:23 AM UTC 24
Peak memory 360560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208452299 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_during
_key_req.4208452299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.4224140034
Short name T403
Test name
Test status
Simulation time 12941188 ps
CPU time 0.86 seconds
Started Aug 27 08:26:05 AM UTC 24
Finished Aug 27 08:26:07 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224140034 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.4224140034
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.2238891052
Short name T399
Test name
Test status
Simulation time 612977687 ps
CPU time 48.18 seconds
Started Aug 27 08:25:00 AM UTC 24
Finished Aug 27 08:25:50 AM UTC 24
Peak memory 214104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238891052 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.2238891052
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.3133199752
Short name T482
Test name
Test status
Simulation time 17760189951 ps
CPU time 451.62 seconds
Started Aug 27 08:25:43 AM UTC 24
Finished Aug 27 08:33:20 AM UTC 24
Peak memory 374708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133199752 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.3133199752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1259593131
Short name T397
Test name
Test status
Simulation time 226643182 ps
CPU time 3.8 seconds
Started Aug 27 08:25:39 AM UTC 24
Finished Aug 27 08:25:44 AM UTC 24
Peak memory 228160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259593131 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.1259593131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.188324175
Short name T419
Test name
Test status
Simulation time 153195772 ps
CPU time 111.66 seconds
Started Aug 27 08:25:36 AM UTC 24
Finished Aug 27 08:27:30 AM UTC 24
Peak memory 380792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
88324175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_max
_throughput.188324175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.4106909473
Short name T90
Test name
Test status
Simulation time 196761855 ps
CPU time 8.88 seconds
Started Aug 27 08:25:53 AM UTC 24
Finished Aug 27 08:26:03 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106909473 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.4106909473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2628644555
Short name T401
Test name
Test status
Simulation time 147902924 ps
CPU time 6.49 seconds
Started Aug 27 08:25:51 AM UTC 24
Finished Aug 27 08:25:58 AM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628644555 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.2628644555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.1991485903
Short name T581
Test name
Test status
Simulation time 17709009913 ps
CPU time 1003.16 seconds
Started Aug 27 08:24:49 AM UTC 24
Finished Aug 27 08:41:44 AM UTC 24
Peak memory 384872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991485903 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.1991485903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1030890226
Short name T392
Test name
Test status
Simulation time 2237338837 ps
CPU time 17.95 seconds
Started Aug 27 08:25:16 AM UTC 24
Finished Aug 27 08:25:35 AM UTC 24
Peak memory 213976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030890226 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.1030890226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2091051231
Short name T471
Test name
Test status
Simulation time 6552443896 ps
CPU time 428.85 seconds
Started Aug 27 08:25:20 AM UTC 24
Finished Aug 27 08:32:34 AM UTC 24
Peak memory 213984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091051231 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_acc
ess_b2b.2091051231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1124796167
Short name T400
Test name
Test status
Simulation time 47782335 ps
CPU time 1.09 seconds
Started Aug 27 08:25:50 AM UTC 24
Finished Aug 27 08:25:52 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124796167 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1124796167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_regwen.4178107062
Short name T402
Test name
Test status
Simulation time 1011224348 ps
CPU time 18.48 seconds
Started Aug 27 08:25:44 AM UTC 24
Finished Aug 27 08:26:04 AM UTC 24
Peak memory 213864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178107062 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.4178107062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.772393544
Short name T391
Test name
Test status
Simulation time 3811871822 ps
CPU time 31.23 seconds
Started Aug 27 08:24:46 AM UTC 24
Finished Aug 27 08:25:19 AM UTC 24
Peak memory 290740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772393544 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.772393544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.4150037042
Short name T881
Test name
Test status
Simulation time 50097457411 ps
CPU time 2652.62 seconds
Started Aug 27 08:26:04 AM UTC 24
Finished Aug 27 09:10:43 AM UTC 24
Peak memory 390840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415003704
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.4150037042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4265825968
Short name T443
Test name
Test status
Simulation time 5146925825 ps
CPU time 212.75 seconds
Started Aug 27 08:26:00 AM UTC 24
Finished Aug 27 08:29:36 AM UTC 24
Peak memory 391084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265825968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.4265825968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2628878409
Short name T445
Test name
Test status
Simulation time 2884367223 ps
CPU time 276.61 seconds
Started Aug 27 08:25:16 AM UTC 24
Finished Aug 27 08:29:56 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628878409 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.2628878409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.4170259335
Short name T396
Test name
Test status
Simulation time 187083537 ps
CPU time 5.5 seconds
Started Aug 27 08:25:36 AM UTC 24
Finished Aug 27 08:25:43 AM UTC 24
Peak memory 233328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4170259335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_t
hroughput_w_partial_write.4170259335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3835781323
Short name T460
Test name
Test status
Simulation time 8545058619 ps
CPU time 262.27 seconds
Started Aug 27 08:27:06 AM UTC 24
Finished Aug 27 08:31:33 AM UTC 24
Peak memory 377000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835781323 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_during
_key_req.3835781323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.329804814
Short name T421
Test name
Test status
Simulation time 71756834 ps
CPU time 0.93 seconds
Started Aug 27 08:27:31 AM UTC 24
Finished Aug 27 08:27:34 AM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329804814 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.329804814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.3406797955
Short name T415
Test name
Test status
Simulation time 5231918910 ps
CPU time 54.63 seconds
Started Aug 27 08:26:19 AM UTC 24
Finished Aug 27 08:27:15 AM UTC 24
Peak memory 214036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406797955 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.3406797955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.2614124417
Short name T578
Test name
Test status
Simulation time 9718250473 ps
CPU time 839.81 seconds
Started Aug 27 08:27:14 AM UTC 24
Finished Aug 27 08:41:24 AM UTC 24
Peak memory 384960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614124417 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.2614124417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2212440633
Short name T413
Test name
Test status
Simulation time 1323009773 ps
CPU time 11.03 seconds
Started Aug 27 08:27:01 AM UTC 24
Finished Aug 27 08:27:13 AM UTC 24
Peak memory 213904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212440633 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.2212440633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2875599733
Short name T414
Test name
Test status
Simulation time 96757196 ps
CPU time 34.99 seconds
Started Aug 27 08:26:37 AM UTC 24
Finished Aug 27 08:27:14 AM UTC 24
Peak memory 305008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
875599733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ma
x_throughput.2875599733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3680667892
Short name T418
Test name
Test status
Simulation time 90488099 ps
CPU time 3.95 seconds
Started Aug 27 08:27:25 AM UTC 24
Finished Aug 27 08:27:30 AM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680667892 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3680667892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3390276014
Short name T420
Test name
Test status
Simulation time 290590260 ps
CPU time 10.72 seconds
Started Aug 27 08:27:19 AM UTC 24
Finished Aug 27 08:27:31 AM UTC 24
Peak memory 224188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390276014 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.3390276014
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3518492831
Short name T653
Test name
Test status
Simulation time 11024798976 ps
CPU time 1321.1 seconds
Started Aug 27 08:26:10 AM UTC 24
Finished Aug 27 08:48:25 AM UTC 24
Peak memory 385152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518492831 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.3518492831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1139817155
Short name T410
Test name
Test status
Simulation time 946248424 ps
CPU time 19.56 seconds
Started Aug 27 08:26:33 AM UTC 24
Finished Aug 27 08:26:54 AM UTC 24
Peak memory 214076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139817155 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.1139817155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.622745653
Short name T456
Test name
Test status
Simulation time 36818009587 ps
CPU time 263.76 seconds
Started Aug 27 08:26:36 AM UTC 24
Finished Aug 27 08:31:03 AM UTC 24
Peak memory 214308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622745653 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_acce
ss_b2b.622745653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.4016923578
Short name T416
Test name
Test status
Simulation time 70666875 ps
CPU time 1.17 seconds
Started Aug 27 08:27:16 AM UTC 24
Finished Aug 27 08:27:18 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016923578 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.4016923578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.555462729
Short name T480
Test name
Test status
Simulation time 4304602299 ps
CPU time 351.89 seconds
Started Aug 27 08:27:16 AM UTC 24
Finished Aug 27 08:33:12 AM UTC 24
Peak memory 343920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555462729 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.555462729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.4268408
Short name T406
Test name
Test status
Simulation time 499405864 ps
CPU time 9.62 seconds
Started Aug 27 08:26:08 AM UTC 24
Finished Aug 27 08:26:19 AM UTC 24
Peak memory 214180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268408 -assert nopostproc +UVM_TESTNA
ME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.4268408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1626211784
Short name T931
Test name
Test status
Simulation time 158844498899 ps
CPU time 4454.63 seconds
Started Aug 27 08:27:31 AM UTC 24
Finished Aug 27 09:42:29 AM UTC 24
Peak memory 388792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162621178
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.1626211784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3872714426
Short name T474
Test name
Test status
Simulation time 15917107012 ps
CPU time 310.19 seconds
Started Aug 27 08:27:31 AM UTC 24
Finished Aug 27 08:32:46 AM UTC 24
Peak memory 391344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872714426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3872714426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2988388817
Short name T458
Test name
Test status
Simulation time 2402042335 ps
CPU time 294.24 seconds
Started Aug 27 08:26:20 AM UTC 24
Finished Aug 27 08:31:18 AM UTC 24
Peak memory 214164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988388817 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.2988388817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2546245555
Short name T426
Test name
Test status
Simulation time 480823123 ps
CPU time 56.93 seconds
Started Aug 27 08:26:54 AM UTC 24
Finished Aug 27 08:27:53 AM UTC 24
Peak memory 339816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2546245555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_t
hroughput_w_partial_write.2546245555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3877693806
Short name T595
Test name
Test status
Simulation time 8180912888 ps
CPU time 863.4 seconds
Started Aug 27 08:28:11 AM UTC 24
Finished Aug 27 08:42:44 AM UTC 24
Peak memory 384840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877693806 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_during
_key_req.3877693806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.582393150
Short name T438
Test name
Test status
Simulation time 12435995 ps
CPU time 1.01 seconds
Started Aug 27 08:28:52 AM UTC 24
Finished Aug 27 08:28:54 AM UTC 24
Peak memory 212816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582393150 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.582393150
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3098109388
Short name T436
Test name
Test status
Simulation time 4855599780 ps
CPU time 68.98 seconds
Started Aug 27 08:27:40 AM UTC 24
Finished Aug 27 08:28:50 AM UTC 24
Peak memory 213860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098109388 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.3098109388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.2289958969
Short name T570
Test name
Test status
Simulation time 17182557196 ps
CPU time 765.16 seconds
Started Aug 27 08:28:14 AM UTC 24
Finished Aug 27 08:41:07 AM UTC 24
Peak memory 384872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289958969 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.2289958969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1898208673
Short name T430
Test name
Test status
Simulation time 5830678947 ps
CPU time 12.2 seconds
Started Aug 27 08:28:07 AM UTC 24
Finished Aug 27 08:28:21 AM UTC 24
Peak memory 213812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898208673 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.1898208673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3196988591
Short name T428
Test name
Test status
Simulation time 280389493 ps
CPU time 10.73 seconds
Started Aug 27 08:27:54 AM UTC 24
Finished Aug 27 08:28:06 AM UTC 24
Peak memory 264048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
196988591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ma
x_throughput.3196988591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.546556952
Short name T435
Test name
Test status
Simulation time 192646921 ps
CPU time 6.33 seconds
Started Aug 27 08:28:31 AM UTC 24
Finished Aug 27 08:28:39 AM UTC 24
Peak memory 223972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546556952 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.546556952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.3422457440
Short name T434
Test name
Test status
Simulation time 893852778 ps
CPU time 8.42 seconds
Started Aug 27 08:28:27 AM UTC 24
Finished Aug 27 08:28:37 AM UTC 24
Peak memory 224028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422457440 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.3422457440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.347777457
Short name T614
Test name
Test status
Simulation time 15767496066 ps
CPU time 981.52 seconds
Started Aug 27 08:27:39 AM UTC 24
Finished Aug 27 08:44:11 AM UTC 24
Peak memory 386936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347777457 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.347777457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.67761141
Short name T440
Test name
Test status
Simulation time 520908742 ps
CPU time 86 seconds
Started Aug 27 08:27:45 AM UTC 24
Finished Aug 27 08:29:13 AM UTC 24
Peak memory 374896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67761141 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.67761141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1173795054
Short name T461
Test name
Test status
Simulation time 15889283655 ps
CPU time 222.68 seconds
Started Aug 27 08:27:53 AM UTC 24
Finished Aug 27 08:31:39 AM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173795054 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_acc
ess_b2b.1173795054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1139394853
Short name T432
Test name
Test status
Simulation time 35258098 ps
CPU time 1.02 seconds
Started Aug 27 08:28:24 AM UTC 24
Finished Aug 27 08:28:26 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139394853 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1139394853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.3158804871
Short name T554
Test name
Test status
Simulation time 26509606243 ps
CPU time 655.07 seconds
Started Aug 27 08:28:22 AM UTC 24
Finished Aug 27 08:39:25 AM UTC 24
Peak memory 387252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158804871 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3158804871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.1186402702
Short name T422
Test name
Test status
Simulation time 152145677 ps
CPU time 1.78 seconds
Started Aug 27 08:27:34 AM UTC 24
Finished Aug 27 08:27:37 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186402702 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1186402702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2409978376
Short name T527
Test name
Test status
Simulation time 11861567928 ps
CPU time 492.44 seconds
Started Aug 27 08:28:39 AM UTC 24
Finished Aug 27 08:36:58 AM UTC 24
Peak memory 358260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240997837
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.2409978376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2040934267
Short name T638
Test name
Test status
Simulation time 12789015265 ps
CPU time 1086.04 seconds
Started Aug 27 08:28:37 AM UTC 24
Finished Aug 27 08:46:56 AM UTC 24
Peak memory 393124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040934267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2040934267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.152694307
Short name T507
Test name
Test status
Simulation time 8503097308 ps
CPU time 413.44 seconds
Started Aug 27 08:27:42 AM UTC 24
Finished Aug 27 08:34:41 AM UTC 24
Peak memory 214112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152694307 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.152694307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3076271365
Short name T431
Test name
Test status
Simulation time 703918583 ps
CPU time 15.9 seconds
Started Aug 27 08:28:06 AM UTC 24
Finished Aug 27 08:28:23 AM UTC 24
Peak memory 266092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3076271365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_t
hroughput_w_partial_write.3076271365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2545500789
Short name T463
Test name
Test status
Simulation time 2217354304 ps
CPU time 104.21 seconds
Started Aug 27 08:30:01 AM UTC 24
Finished Aug 27 08:31:48 AM UTC 24
Peak memory 259928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545500789 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_during
_key_req.2545500789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1096834650
Short name T454
Test name
Test status
Simulation time 38445434 ps
CPU time 1.01 seconds
Started Aug 27 08:30:48 AM UTC 24
Finished Aug 27 08:30:50 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096834650 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1096834650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.2023936943
Short name T447
Test name
Test status
Simulation time 6284144926 ps
CPU time 59.02 seconds
Started Aug 27 08:29:08 AM UTC 24
Finished Aug 27 08:30:09 AM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023936943 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.2023936943
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.655565507
Short name T662
Test name
Test status
Simulation time 167577345809 ps
CPU time 1129.42 seconds
Started Aug 27 08:30:09 AM UTC 24
Finished Aug 27 08:49:11 AM UTC 24
Peak memory 386916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655565507 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.655565507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.81576093
Short name T449
Test name
Test status
Simulation time 3816686337 ps
CPU time 16.11 seconds
Started Aug 27 08:29:57 AM UTC 24
Finished Aug 27 08:30:14 AM UTC 24
Peak memory 213952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81576093 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.81576093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2499748432
Short name T446
Test name
Test status
Simulation time 197653972 ps
CPU time 21.09 seconds
Started Aug 27 08:29:36 AM UTC 24
Finished Aug 27 08:29:59 AM UTC 24
Peak memory 284788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
499748432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ma
x_throughput.2499748432
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.2271380660
Short name T453
Test name
Test status
Simulation time 283704921 ps
CPU time 4.21 seconds
Started Aug 27 08:30:30 AM UTC 24
Finished Aug 27 08:30:35 AM UTC 24
Peak memory 224368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271380660 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.2271380660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3930801025
Short name T452
Test name
Test status
Simulation time 456973967 ps
CPU time 13.26 seconds
Started Aug 27 08:30:20 AM UTC 24
Finished Aug 27 08:30:34 AM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930801025 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.3930801025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.671271971
Short name T526
Test name
Test status
Simulation time 2425795228 ps
CPU time 474.91 seconds
Started Aug 27 08:28:55 AM UTC 24
Finished Aug 27 08:36:56 AM UTC 24
Peak memory 384872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671271971 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.671271971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.4141240509
Short name T444
Test name
Test status
Simulation time 6859875565 ps
CPU time 23.12 seconds
Started Aug 27 08:29:22 AM UTC 24
Finished Aug 27 08:29:47 AM UTC 24
Peak memory 213952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141240509 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.4141240509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.648869165
Short name T529
Test name
Test status
Simulation time 27776933084 ps
CPU time 454.8 seconds
Started Aug 27 08:29:31 AM UTC 24
Finished Aug 27 08:37:12 AM UTC 24
Peak memory 213964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648869165 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_acce
ss_b2b.648869165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3467984216
Short name T450
Test name
Test status
Simulation time 43291493 ps
CPU time 1.02 seconds
Started Aug 27 08:30:16 AM UTC 24
Finished Aug 27 08:30:18 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467984216 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3467984216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.2328208273
Short name T600
Test name
Test status
Simulation time 9498980097 ps
CPU time 776.35 seconds
Started Aug 27 08:30:13 AM UTC 24
Finished Aug 27 08:43:19 AM UTC 24
Peak memory 374712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328208273 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2328208273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.3234213692
Short name T448
Test name
Test status
Simulation time 2957800109 ps
CPU time 79.01 seconds
Started Aug 27 08:28:52 AM UTC 24
Finished Aug 27 08:30:12 AM UTC 24
Peak memory 378812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234213692 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3234213692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1298097691
Short name T913
Test name
Test status
Simulation time 246178308474 ps
CPU time 2941.48 seconds
Started Aug 27 08:30:36 AM UTC 24
Finished Aug 27 09:20:08 AM UTC 24
Peak memory 388664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129809769
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.1298097691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.1337462016
Short name T512
Test name
Test status
Simulation time 32751691901 ps
CPU time 391.51 seconds
Started Aug 27 08:29:14 AM UTC 24
Finished Aug 27 08:35:51 AM UTC 24
Peak memory 214156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337462016 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.1337462016
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2351734391
Short name T457
Test name
Test status
Simulation time 147018584 ps
CPU time 76.62 seconds
Started Aug 27 08:29:48 AM UTC 24
Finished Aug 27 08:31:06 AM UTC 24
Peak memory 374700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2351734391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_t
hroughput_w_partial_write.2351734391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2540192832
Short name T663
Test name
Test status
Simulation time 4020965314 ps
CPU time 1048.89 seconds
Started Aug 27 08:31:48 AM UTC 24
Finished Aug 27 08:49:30 AM UTC 24
Peak memory 384932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540192832 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_during
_key_req.2540192832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.3880196265
Short name T472
Test name
Test status
Simulation time 32310631 ps
CPU time 0.91 seconds
Started Aug 27 08:32:34 AM UTC 24
Finished Aug 27 08:32:36 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880196265 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.3880196265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.3545391708
Short name T462
Test name
Test status
Simulation time 1759535608 ps
CPU time 34.75 seconds
Started Aug 27 08:31:05 AM UTC 24
Finished Aug 27 08:31:41 AM UTC 24
Peak memory 213992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545391708 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.3545391708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.2783798197
Short name T565
Test name
Test status
Simulation time 2880786107 ps
CPU time 539.93 seconds
Started Aug 27 08:31:50 AM UTC 24
Finished Aug 27 08:40:56 AM UTC 24
Peak memory 378808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783798197 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.2783798197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1909312272
Short name T465
Test name
Test status
Simulation time 420478412 ps
CPU time 7.32 seconds
Started Aug 27 08:31:41 AM UTC 24
Finished Aug 27 08:31:50 AM UTC 24
Peak memory 214028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909312272 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.1909312272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3791709541
Short name T470
Test name
Test status
Simulation time 131816965 ps
CPU time 57.8 seconds
Started Aug 27 08:31:33 AM UTC 24
Finished Aug 27 08:32:32 AM UTC 24
Peak memory 368752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
791709541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ma
x_throughput.3791709541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3317685426
Short name T469
Test name
Test status
Simulation time 107671870 ps
CPU time 7.22 seconds
Started Aug 27 08:32:16 AM UTC 24
Finished Aug 27 08:32:24 AM UTC 24
Peak memory 224120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317685426 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.3317685426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.2775876174
Short name T468
Test name
Test status
Simulation time 262731849 ps
CPU time 6.12 seconds
Started Aug 27 08:32:07 AM UTC 24
Finished Aug 27 08:32:15 AM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775876174 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.2775876174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.2391293473
Short name T536
Test name
Test status
Simulation time 12205759039 ps
CPU time 421.5 seconds
Started Aug 27 08:31:01 AM UTC 24
Finished Aug 27 08:38:08 AM UTC 24
Peak memory 378992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391293473 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.2391293473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.1246171368
Short name T459
Test name
Test status
Simulation time 254442370 ps
CPU time 6.57 seconds
Started Aug 27 08:31:19 AM UTC 24
Finished Aug 27 08:31:26 AM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246171368 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.1246171368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.311118378
Short name T530
Test name
Test status
Simulation time 68308813248 ps
CPU time 353.13 seconds
Started Aug 27 08:31:27 AM UTC 24
Finished Aug 27 08:37:25 AM UTC 24
Peak memory 213880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311118378 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acce
ss_b2b.311118378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2241066362
Short name T467
Test name
Test status
Simulation time 237110745 ps
CPU time 1.04 seconds
Started Aug 27 08:32:04 AM UTC 24
Finished Aug 27 08:32:06 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241066362 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2241066362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.22999619
Short name T668
Test name
Test status
Simulation time 28813617705 ps
CPU time 1074.87 seconds
Started Aug 27 08:31:51 AM UTC 24
Finished Aug 27 08:49:58 AM UTC 24
Peak memory 378808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22999619 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.22999619
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.1171453766
Short name T455
Test name
Test status
Simulation time 563654982 ps
CPU time 7.86 seconds
Started Aug 27 08:30:51 AM UTC 24
Finished Aug 27 08:31:00 AM UTC 24
Peak memory 214112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171453766 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1171453766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3884330472
Short name T871
Test name
Test status
Simulation time 10272733070 ps
CPU time 2147.55 seconds
Started Aug 27 08:32:33 AM UTC 24
Finished Aug 27 09:08:42 AM UTC 24
Peak memory 381108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388433047
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.3884330472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1091619989
Short name T487
Test name
Test status
Simulation time 5660614614 ps
CPU time 145.66 seconds
Started Aug 27 08:31:07 AM UTC 24
Finished Aug 27 08:33:35 AM UTC 24
Peak memory 213904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091619989 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.1091619989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.4239465036
Short name T466
Test name
Test status
Simulation time 155418182 ps
CPU time 21.88 seconds
Started Aug 27 08:31:40 AM UTC 24
Finished Aug 27 08:32:03 AM UTC 24
Peak memory 280428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4239465036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_t
hroughput_w_partial_write.4239465036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.339240376
Short name T675
Test name
Test status
Simulation time 15149779203 ps
CPU time 1003.82 seconds
Started Aug 27 08:33:19 AM UTC 24
Finished Aug 27 08:50:14 AM UTC 24
Peak memory 384864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339240376 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during_
key_req.339240376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3464799990
Short name T490
Test name
Test status
Simulation time 16467456 ps
CPU time 0.93 seconds
Started Aug 27 08:33:39 AM UTC 24
Finished Aug 27 08:33:41 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464799990 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3464799990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.4053266778
Short name T494
Test name
Test status
Simulation time 6484796189 ps
CPU time 67.99 seconds
Started Aug 27 08:32:47 AM UTC 24
Finished Aug 27 08:33:56 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053266778 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.4053266778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.3583999942
Short name T649
Test name
Test status
Simulation time 16843971124 ps
CPU time 855.15 seconds
Started Aug 27 08:33:21 AM UTC 24
Finished Aug 27 08:47:45 AM UTC 24
Peak memory 382900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583999942 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.3583999942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2416289289
Short name T483
Test name
Test status
Simulation time 1239282339 ps
CPU time 6.84 seconds
Started Aug 27 08:33:13 AM UTC 24
Finished Aug 27 08:33:21 AM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416289289 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.2416289289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1870740768
Short name T484
Test name
Test status
Simulation time 103014703 ps
CPU time 27.9 seconds
Started Aug 27 08:32:53 AM UTC 24
Finished Aug 27 08:33:22 AM UTC 24
Peak memory 296744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
870740768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ma
x_throughput.1870740768
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.4050003501
Short name T488
Test name
Test status
Simulation time 762758223 ps
CPU time 7.7 seconds
Started Aug 27 08:33:26 AM UTC 24
Finished Aug 27 08:33:35 AM UTC 24
Peak memory 224016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050003501 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.4050003501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.577603751
Short name T491
Test name
Test status
Simulation time 4093143209 ps
CPU time 15.64 seconds
Started Aug 27 08:33:24 AM UTC 24
Finished Aug 27 08:33:41 AM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577603751 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.577603751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2793091934
Short name T583
Test name
Test status
Simulation time 1382518693 ps
CPU time 543.6 seconds
Started Aug 27 08:32:42 AM UTC 24
Finished Aug 27 08:41:52 AM UTC 24
Peak memory 386868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793091934 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.2793091934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1711035698
Short name T478
Test name
Test status
Simulation time 113632137 ps
CPU time 3.3 seconds
Started Aug 27 08:32:48 AM UTC 24
Finished Aug 27 08:32:53 AM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711035698 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.1711035698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.889079299
Short name T590
Test name
Test status
Simulation time 74393175532 ps
CPU time 578.16 seconds
Started Aug 27 08:32:50 AM UTC 24
Finished Aug 27 08:42:36 AM UTC 24
Peak memory 213864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889079299 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_acce
ss_b2b.889079299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.346979602
Short name T486
Test name
Test status
Simulation time 273815130 ps
CPU time 1.1 seconds
Started Aug 27 08:33:23 AM UTC 24
Finished Aug 27 08:33:25 AM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346979602 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.346979602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.1293033192
Short name T569
Test name
Test status
Simulation time 4418673035 ps
CPU time 459.61 seconds
Started Aug 27 08:33:22 AM UTC 24
Finished Aug 27 08:41:07 AM UTC 24
Peak memory 382824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293033192 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1293033192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.3237329707
Short name T473
Test name
Test status
Simulation time 40206147 ps
CPU time 1.34 seconds
Started Aug 27 08:32:38 AM UTC 24
Finished Aug 27 08:32:40 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237329707 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3237329707
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.899171218
Short name T925
Test name
Test status
Simulation time 64910274631 ps
CPU time 3187.7 seconds
Started Aug 27 08:33:36 AM UTC 24
Finished Aug 27 09:27:18 AM UTC 24
Peak memory 388668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899171218
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.899171218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3661262136
Short name T113
Test name
Test status
Simulation time 352389777 ps
CPU time 12.72 seconds
Started Aug 27 08:33:36 AM UTC 24
Finished Aug 27 08:33:49 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661262136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3661262136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2647521484
Short name T539
Test name
Test status
Simulation time 3526250318 ps
CPU time 327.31 seconds
Started Aug 27 08:32:48 AM UTC 24
Finished Aug 27 08:38:20 AM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647521484 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2647521484
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1806226583
Short name T495
Test name
Test status
Simulation time 278231119 ps
CPU time 65.73 seconds
Started Aug 27 08:32:54 AM UTC 24
Finished Aug 27 08:34:02 AM UTC 24
Peak memory 364324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1806226583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_t
hroughput_w_partial_write.1806226583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3746227589
Short name T503
Test name
Test status
Simulation time 569114468 ps
CPU time 13.17 seconds
Started Aug 27 08:34:17 AM UTC 24
Finished Aug 27 08:34:31 AM UTC 24
Peak memory 235364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746227589 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_during
_key_req.3746227589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3917722338
Short name T506
Test name
Test status
Simulation time 14464389 ps
CPU time 1.04 seconds
Started Aug 27 08:34:35 AM UTC 24
Finished Aug 27 08:34:37 AM UTC 24
Peak memory 212576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917722338 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3917722338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.925381048
Short name T475
Test name
Test status
Simulation time 844794744 ps
CPU time 31.9 seconds
Started Aug 27 08:33:50 AM UTC 24
Finished Aug 27 08:34:23 AM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925381048 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.925381048
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_executable.2638619450
Short name T520
Test name
Test status
Simulation time 2464906042 ps
CPU time 123.73 seconds
Started Aug 27 08:34:18 AM UTC 24
Finished Aug 27 08:36:24 AM UTC 24
Peak memory 325568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638619450 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.2638619450
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1923543280
Short name T500
Test name
Test status
Simulation time 409329330 ps
CPU time 9.5 seconds
Started Aug 27 08:34:11 AM UTC 24
Finished Aug 27 08:34:21 AM UTC 24
Peak memory 213784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923543280 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.1923543280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.126013070
Short name T496
Test name
Test status
Simulation time 83634562 ps
CPU time 1.8 seconds
Started Aug 27 08:34:03 AM UTC 24
Finished Aug 27 08:34:06 AM UTC 24
Peak memory 224420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
26013070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_max
_throughput.126013070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.835600075
Short name T504
Test name
Test status
Simulation time 424553133 ps
CPU time 3.81 seconds
Started Aug 27 08:34:26 AM UTC 24
Finished Aug 27 08:34:32 AM UTC 24
Peak memory 223980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835600075 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.835600075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1458547498
Short name T505
Test name
Test status
Simulation time 344872906 ps
CPU time 8.3 seconds
Started Aug 27 08:34:24 AM UTC 24
Finished Aug 27 08:34:34 AM UTC 24
Peak memory 224456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458547498 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.1458547498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1139068469
Short name T630
Test name
Test status
Simulation time 12106996249 ps
CPU time 700.37 seconds
Started Aug 27 08:33:42 AM UTC 24
Finished Aug 27 08:45:31 AM UTC 24
Peak memory 387244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139068469 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.1139068469
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2562782977
Short name T501
Test name
Test status
Simulation time 2795310571 ps
CPU time 26.23 seconds
Started Aug 27 08:33:54 AM UTC 24
Finished Aug 27 08:34:22 AM UTC 24
Peak memory 213824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562782977 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.2562782977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.101780828
Short name T545
Test name
Test status
Simulation time 8985032212 ps
CPU time 285.13 seconds
Started Aug 27 08:33:57 AM UTC 24
Finished Aug 27 08:38:47 AM UTC 24
Peak memory 214168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101780828 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_acce
ss_b2b.101780828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2430044991
Short name T502
Test name
Test status
Simulation time 58437058 ps
CPU time 1.06 seconds
Started Aug 27 08:34:23 AM UTC 24
Finished Aug 27 08:34:26 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430044991 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2430044991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.1786376456
Short name T493
Test name
Test status
Simulation time 3318963080 ps
CPU time 10.3 seconds
Started Aug 27 08:33:42 AM UTC 24
Finished Aug 27 08:33:53 AM UTC 24
Peak memory 214256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786376456 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1786376456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2986081306
Short name T876
Test name
Test status
Simulation time 159953857780 ps
CPU time 2045.97 seconds
Started Aug 27 08:34:33 AM UTC 24
Finished Aug 27 09:09:00 AM UTC 24
Peak memory 387252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298608130
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all.2986081306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3456315840
Short name T508
Test name
Test status
Simulation time 3187239019 ps
CPU time 33.1 seconds
Started Aug 27 08:34:32 AM UTC 24
Finished Aug 27 08:35:06 AM UTC 24
Peak memory 224472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456315840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.3456315840
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.539350078
Short name T550
Test name
Test status
Simulation time 18394908385 ps
CPU time 313.5 seconds
Started Aug 27 08:33:53 AM UTC 24
Finished Aug 27 08:39:11 AM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539350078 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.539350078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3966959744
Short name T497
Test name
Test status
Simulation time 36756061 ps
CPU time 1.66 seconds
Started Aug 27 08:34:07 AM UTC 24
Finished Aug 27 08:34:09 AM UTC 24
Peak memory 212524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3966959744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_t
hroughput_w_partial_write.3966959744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3429340158
Short name T534
Test name
Test status
Simulation time 488231476 ps
CPU time 104.86 seconds
Started Aug 27 08:36:09 AM UTC 24
Finished Aug 27 08:37:56 AM UTC 24
Peak memory 358176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429340158 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during
_key_req.3429340158
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2996933560
Short name T523
Test name
Test status
Simulation time 12898661 ps
CPU time 0.84 seconds
Started Aug 27 08:36:35 AM UTC 24
Finished Aug 27 08:36:37 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996933560 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.2996933560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.3445310495
Short name T517
Test name
Test status
Simulation time 989852950 ps
CPU time 68.42 seconds
Started Aug 27 08:35:07 AM UTC 24
Finished Aug 27 08:36:17 AM UTC 24
Peak memory 213844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445310495 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.3445310495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.399444210
Short name T568
Test name
Test status
Simulation time 1350466646 ps
CPU time 289.89 seconds
Started Aug 27 08:36:09 AM UTC 24
Finished Aug 27 08:41:03 AM UTC 24
Peak memory 376564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399444210 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.399444210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.540130625
Short name T515
Test name
Test status
Simulation time 614021012 ps
CPU time 5.14 seconds
Started Aug 27 08:36:02 AM UTC 24
Finished Aug 27 08:36:08 AM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540130625 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.540130625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3288709913
Short name T514
Test name
Test status
Simulation time 77250379 ps
CPU time 16.1 seconds
Started Aug 27 08:35:51 AM UTC 24
Finished Aug 27 08:36:08 AM UTC 24
Peak memory 272496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
288709913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ma
x_throughput.3288709913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2216473373
Short name T521
Test name
Test status
Simulation time 1034909309 ps
CPU time 4.98 seconds
Started Aug 27 08:36:22 AM UTC 24
Finished Aug 27 08:36:28 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216473373 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.2216473373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.1066751295
Short name T522
Test name
Test status
Simulation time 712078578 ps
CPU time 12.41 seconds
Started Aug 27 08:36:21 AM UTC 24
Finished Aug 27 08:36:34 AM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066751295 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.1066751295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1090989717
Short name T633
Test name
Test status
Simulation time 3260199758 ps
CPU time 666.38 seconds
Started Aug 27 08:34:42 AM UTC 24
Finished Aug 27 08:45:56 AM UTC 24
Peak memory 385136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090989717 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.1090989717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.593780342
Short name T510
Test name
Test status
Simulation time 172462277 ps
CPU time 1.19 seconds
Started Aug 27 08:35:19 AM UTC 24
Finished Aug 27 08:35:22 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593780342 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.593780342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1195774646
Short name T566
Test name
Test status
Simulation time 26575792131 ps
CPU time 334.63 seconds
Started Aug 27 08:35:23 AM UTC 24
Finished Aug 27 08:41:02 AM UTC 24
Peak memory 213996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195774646 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_acc
ess_b2b.1195774646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.1592687020
Short name T519
Test name
Test status
Simulation time 45322459 ps
CPU time 1.26 seconds
Started Aug 27 08:36:19 AM UTC 24
Finished Aug 27 08:36:21 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592687020 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1592687020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.801638666
Short name T706
Test name
Test status
Simulation time 21909858528 ps
CPU time 1049.23 seconds
Started Aug 27 08:36:10 AM UTC 24
Finished Aug 27 08:53:51 AM UTC 24
Peak memory 386864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801638666 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.801638666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.54117457
Short name T511
Test name
Test status
Simulation time 528754643 ps
CPU time 69.72 seconds
Started Aug 27 08:34:38 AM UTC 24
Finished Aug 27 08:35:49 AM UTC 24
Peak memory 341880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54117457 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.54117457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.2066504351
Short name T929
Test name
Test status
Simulation time 302904697344 ps
CPU time 3506.39 seconds
Started Aug 27 08:36:29 AM UTC 24
Finished Aug 27 09:35:31 AM UTC 24
Peak memory 388736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206650435
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.2066504351
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1463799474
Short name T541
Test name
Test status
Simulation time 1570278859 ps
CPU time 185.59 seconds
Started Aug 27 08:35:13 AM UTC 24
Finished Aug 27 08:38:22 AM UTC 24
Peak memory 213796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463799474 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.1463799474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3810528685
Short name T513
Test name
Test status
Simulation time 106328157 ps
CPU time 7.93 seconds
Started Aug 27 08:35:52 AM UTC 24
Finished Aug 27 08:36:01 AM UTC 24
Peak memory 247592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3810528685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_t
hroughput_w_partial_write.3810528685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3618301244
Short name T259
Test name
Test status
Simulation time 16040447944 ps
CPU time 806.39 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:13:08 AM UTC 24
Peak memory 376752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618301244 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during_
key_req.3618301244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_alert_test.39075741
Short name T71
Test name
Test status
Simulation time 95232514 ps
CPU time 0.74 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:35 AM UTC 24
Peak memory 212540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39075741 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.39075741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_bijection.1637459606
Short name T122
Test name
Test status
Simulation time 5581425959 ps
CPU time 89.15 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:01:04 AM UTC 24
Peak memory 213812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637459606 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.1637459606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_executable.1090161390
Short name T138
Test name
Test status
Simulation time 16558241691 ps
CPU time 300.95 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:04:38 AM UTC 24
Peak memory 384868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090161390 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.1090161390
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2356525421
Short name T68
Test name
Test status
Simulation time 1364594682 ps
CPU time 4.18 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:38 AM UTC 24
Peak memory 226204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356525421 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.2356525421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2083798253
Short name T170
Test name
Test status
Simulation time 86780355 ps
CPU time 30.16 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:00:04 AM UTC 24
Peak memory 296808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
083798253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_max
_throughput.2083798253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3274695762
Short name T74
Test name
Test status
Simulation time 241465239 ps
CPU time 4.26 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:38 AM UTC 24
Peak memory 224352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274695762 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.3274695762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.4190230892
Short name T43
Test name
Test status
Simulation time 5015794062 ps
CPU time 15.25 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:50 AM UTC 24
Peak memory 224120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190230892 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.4190230892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.3922056135
Short name T295
Test name
Test status
Simulation time 20209359673 ps
CPU time 1040.76 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:17:04 AM UTC 24
Peak memory 383148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922056135 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.3922056135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3713300397
Short name T58
Test name
Test status
Simulation time 180180093 ps
CPU time 8.8 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:43 AM UTC 24
Peak memory 214240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713300397 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.3713300397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.1609635431
Short name T107
Test name
Test status
Simulation time 17236631043 ps
CPU time 281.35 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:04:18 AM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609635431 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acce
ss_b2b.1609635431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2430530300
Short name T72
Test name
Test status
Simulation time 30280689 ps
CPU time 1.1 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:35 AM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430530300 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2430530300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_regwen.3482854305
Short name T137
Test name
Test status
Simulation time 44971719339 ps
CPU time 754.31 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:12:16 AM UTC 24
Peak memory 384944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482854305 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.3482854305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.4921169
Short name T15
Test name
Test status
Simulation time 868940113 ps
CPU time 2.84 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:37 AM UTC 24
Peak memory 250124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4921169 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.4921169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_smoke.389833107
Short name T60
Test name
Test status
Simulation time 673159994 ps
CPU time 12.07 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:46 AM UTC 24
Peak memory 214148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389833107 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.389833107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.237338657
Short name T700
Test name
Test status
Simulation time 223840536252 ps
CPU time 3153.32 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:52:37 AM UTC 24
Peak memory 388592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237338657
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.237338657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1850440223
Short name T53
Test name
Test status
Simulation time 1003839546 ps
CPU time 215.68 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:03:12 AM UTC 24
Peak memory 350132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850440223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1850440223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1232387729
Short name T191
Test name
Test status
Simulation time 4742862093 ps
CPU time 299.91 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:04:37 AM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232387729 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.1232387729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1396874148
Short name T73
Test name
Test status
Simulation time 46422097 ps
CPU time 3.47 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:37 AM UTC 24
Peak memory 231076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1396874148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_th
roughput_w_partial_write.1396874148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.454159070
Short name T697
Test name
Test status
Simulation time 47053065796 ps
CPU time 862.58 seconds
Started Aug 27 08:37:43 AM UTC 24
Finished Aug 27 08:52:16 AM UTC 24
Peak memory 378792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454159070 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_during_
key_req.454159070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3741818349
Short name T542
Test name
Test status
Simulation time 46740363 ps
CPU time 0.96 seconds
Started Aug 27 08:38:21 AM UTC 24
Finished Aug 27 08:38:24 AM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741818349 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3741818349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.1960851249
Short name T532
Test name
Test status
Simulation time 3629077835 ps
CPU time 57.45 seconds
Started Aug 27 08:36:43 AM UTC 24
Finished Aug 27 08:37:43 AM UTC 24
Peak memory 213816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960851249 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.1960851249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.1634949126
Short name T567
Test name
Test status
Simulation time 2862796247 ps
CPU time 195.81 seconds
Started Aug 27 08:37:44 AM UTC 24
Finished Aug 27 08:41:03 AM UTC 24
Peak memory 364408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634949126 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.1634949126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3707407420
Short name T533
Test name
Test status
Simulation time 2810481705 ps
CPU time 16.91 seconds
Started Aug 27 08:37:30 AM UTC 24
Finished Aug 27 08:37:48 AM UTC 24
Peak memory 224320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707407420 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.3707407420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2157671497
Short name T531
Test name
Test status
Simulation time 146160579 ps
CPU time 14.8 seconds
Started Aug 27 08:37:13 AM UTC 24
Finished Aug 27 08:37:29 AM UTC 24
Peak memory 284532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
157671497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ma
x_throughput.2157671497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2348784484
Short name T538
Test name
Test status
Simulation time 160794579 ps
CPU time 6.6 seconds
Started Aug 27 08:38:09 AM UTC 24
Finished Aug 27 08:38:17 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348784484 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.2348784484
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.153861049
Short name T537
Test name
Test status
Simulation time 462943987 ps
CPU time 14.53 seconds
Started Aug 27 08:38:01 AM UTC 24
Finished Aug 27 08:38:16 AM UTC 24
Peak memory 224056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153861049 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.153861049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.4112710938
Short name T721
Test name
Test status
Simulation time 72894598884 ps
CPU time 1092.74 seconds
Started Aug 27 08:36:38 AM UTC 24
Finished Aug 27 08:55:03 AM UTC 24
Peak memory 384940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112710938 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.4112710938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1647252042
Short name T528
Test name
Test status
Simulation time 2100980350 ps
CPU time 9.04 seconds
Started Aug 27 08:37:00 AM UTC 24
Finished Aug 27 08:37:10 AM UTC 24
Peak memory 213780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647252042 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.1647252042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.710417883
Short name T573
Test name
Test status
Simulation time 6274659128 ps
CPU time 236.46 seconds
Started Aug 27 08:37:11 AM UTC 24
Finished Aug 27 08:41:11 AM UTC 24
Peak memory 213960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710417883 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_acce
ss_b2b.710417883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2672419178
Short name T535
Test name
Test status
Simulation time 31387429 ps
CPU time 1.07 seconds
Started Aug 27 08:37:58 AM UTC 24
Finished Aug 27 08:38:00 AM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672419178 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2672419178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.604522694
Short name T785
Test name
Test status
Simulation time 13285471183 ps
CPU time 1373.83 seconds
Started Aug 27 08:37:50 AM UTC 24
Finished Aug 27 09:00:57 AM UTC 24
Peak memory 384952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604522694 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.604522694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_smoke.46815546
Short name T525
Test name
Test status
Simulation time 112107399 ps
CPU time 3.63 seconds
Started Aug 27 08:36:38 AM UTC 24
Finished Aug 27 08:36:43 AM UTC 24
Peak memory 213780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46815546 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.46815546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.812958519
Short name T924
Test name
Test status
Simulation time 8449488941 ps
CPU time 2891.66 seconds
Started Aug 27 08:38:17 AM UTC 24
Finished Aug 27 09:26:56 AM UTC 24
Peak memory 388792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812958519
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.812958519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.136841046
Short name T544
Test name
Test status
Simulation time 381715766 ps
CPU time 18.73 seconds
Started Aug 27 08:38:17 AM UTC 24
Finished Aug 27 08:38:37 AM UTC 24
Peak memory 257920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136841046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.136841046
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.546175976
Short name T548
Test name
Test status
Simulation time 2334362663 ps
CPU time 126.44 seconds
Started Aug 27 08:36:57 AM UTC 24
Finished Aug 27 08:39:06 AM UTC 24
Peak memory 213896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546175976 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.546175976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3416174407
Short name T547
Test name
Test status
Simulation time 130573956 ps
CPU time 87.73 seconds
Started Aug 27 08:37:26 AM UTC 24
Finished Aug 27 08:38:56 AM UTC 24
Peak memory 354156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3416174407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_t
hroughput_w_partial_write.3416174407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.3181290857
Short name T707
Test name
Test status
Simulation time 3080953805 ps
CPU time 872.27 seconds
Started Aug 27 08:39:12 AM UTC 24
Finished Aug 27 08:53:53 AM UTC 24
Peak memory 378696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181290857 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_during
_key_req.3181290857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2801327140
Short name T558
Test name
Test status
Simulation time 31747567 ps
CPU time 0.85 seconds
Started Aug 27 08:39:50 AM UTC 24
Finished Aug 27 08:39:53 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801327140 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2801327140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.1322406257
Short name T561
Test name
Test status
Simulation time 10403901615 ps
CPU time 94.29 seconds
Started Aug 27 08:38:25 AM UTC 24
Finished Aug 27 08:40:01 AM UTC 24
Peak memory 213816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322406257 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.1322406257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.540681602
Short name T728
Test name
Test status
Simulation time 3033839593 ps
CPU time 961.57 seconds
Started Aug 27 08:39:12 AM UTC 24
Finished Aug 27 08:55:23 AM UTC 24
Peak memory 381100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540681602 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.540681602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3823264396
Short name T552
Test name
Test status
Simulation time 1094400283 ps
CPU time 11.21 seconds
Started Aug 27 08:39:07 AM UTC 24
Finished Aug 27 08:39:20 AM UTC 24
Peak memory 214220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823264396 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.3823264396
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.3247741929
Short name T562
Test name
Test status
Simulation time 130753734 ps
CPU time 73.54 seconds
Started Aug 27 08:38:56 AM UTC 24
Finished Aug 27 08:40:11 AM UTC 24
Peak memory 354416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
247741929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ma
x_throughput.3247741929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1439549200
Short name T555
Test name
Test status
Simulation time 64097319 ps
CPU time 4.12 seconds
Started Aug 27 08:39:25 AM UTC 24
Finished Aug 27 08:39:30 AM UTC 24
Peak memory 224112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439549200 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.1439549200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.4204497273
Short name T556
Test name
Test status
Simulation time 840256000 ps
CPU time 8.86 seconds
Started Aug 27 08:39:24 AM UTC 24
Finished Aug 27 08:39:34 AM UTC 24
Peak memory 226468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204497273 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.4204497273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1353148559
Short name T666
Test name
Test status
Simulation time 9403856140 ps
CPU time 678.88 seconds
Started Aug 27 08:38:23 AM UTC 24
Finished Aug 27 08:49:51 AM UTC 24
Peak memory 383152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353148559 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.1353148559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2846979806
Short name T546
Test name
Test status
Simulation time 5414578835 ps
CPU time 16.39 seconds
Started Aug 27 08:38:38 AM UTC 24
Finished Aug 27 08:38:56 AM UTC 24
Peak memory 214000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846979806 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.2846979806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3662537300
Short name T640
Test name
Test status
Simulation time 64380315868 ps
CPU time 489.43 seconds
Started Aug 27 08:38:48 AM UTC 24
Finished Aug 27 08:47:03 AM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662537300 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_acc
ess_b2b.3662537300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3397271905
Short name T553
Test name
Test status
Simulation time 30784840 ps
CPU time 1.18 seconds
Started Aug 27 08:39:21 AM UTC 24
Finished Aug 27 08:39:23 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397271905 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3397271905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.872077659
Short name T543
Test name
Test status
Simulation time 659374590 ps
CPU time 14.22 seconds
Started Aug 27 08:38:21 AM UTC 24
Finished Aug 27 08:38:37 AM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872077659 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.872077659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.1748232703
Short name T934
Test name
Test status
Simulation time 210376229874 ps
CPU time 4650.06 seconds
Started Aug 27 08:39:34 AM UTC 24
Finished Aug 27 09:57:53 AM UTC 24
Peak memory 388708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174823270
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.1748232703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1699644001
Short name T596
Test name
Test status
Simulation time 11093295488 ps
CPU time 248.73 seconds
Started Aug 27 08:38:38 AM UTC 24
Finished Aug 27 08:42:50 AM UTC 24
Peak memory 213984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699644001 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.1699644001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2937294548
Short name T551
Test name
Test status
Simulation time 93369691 ps
CPU time 19.76 seconds
Started Aug 27 08:38:57 AM UTC 24
Finished Aug 27 08:39:18 AM UTC 24
Peak memory 288620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2937294548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_t
hroughput_w_partial_write.2937294548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.1676353507
Short name T752
Test name
Test status
Simulation time 13422666853 ps
CPU time 996.83 seconds
Started Aug 27 08:41:03 AM UTC 24
Finished Aug 27 08:57:51 AM UTC 24
Peak memory 386936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676353507 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during
_key_req.1676353507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.668701305
Short name T576
Test name
Test status
Simulation time 17201540 ps
CPU time 0.99 seconds
Started Aug 27 08:41:15 AM UTC 24
Finished Aug 27 08:41:17 AM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668701305 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.668701305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.1008589178
Short name T579
Test name
Test status
Simulation time 4448247424 ps
CPU time 84.94 seconds
Started Aug 27 08:40:01 AM UTC 24
Finished Aug 27 08:41:28 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008589178 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.1008589178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.2216521223
Short name T777
Test name
Test status
Simulation time 16806744225 ps
CPU time 1146.32 seconds
Started Aug 27 08:41:04 AM UTC 24
Finished Aug 27 09:00:22 AM UTC 24
Peak memory 382864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216521223 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.2216521223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.357069462
Short name T571
Test name
Test status
Simulation time 828991338 ps
CPU time 9.77 seconds
Started Aug 27 08:40:56 AM UTC 24
Finished Aug 27 08:41:07 AM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357069462 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.357069462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.886912218
Short name T564
Test name
Test status
Simulation time 61120843 ps
CPU time 7.5 seconds
Started Aug 27 08:40:36 AM UTC 24
Finished Aug 27 08:40:45 AM UTC 24
Peak memory 247672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8
86912218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_max
_throughput.886912218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3741644517
Short name T574
Test name
Test status
Simulation time 102764972 ps
CPU time 4.52 seconds
Started Aug 27 08:41:08 AM UTC 24
Finished Aug 27 08:41:14 AM UTC 24
Peak memory 224368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741644517 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.3741644517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3306780045
Short name T575
Test name
Test status
Simulation time 76464255 ps
CPU time 5.97 seconds
Started Aug 27 08:41:08 AM UTC 24
Finished Aug 27 08:41:15 AM UTC 24
Peak memory 224340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306780045 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.3306780045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.4103948358
Short name T853
Test name
Test status
Simulation time 21314976101 ps
CPU time 1567.64 seconds
Started Aug 27 08:39:57 AM UTC 24
Finished Aug 27 09:06:21 AM UTC 24
Peak memory 384836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103948358 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.4103948358
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1989016805
Short name T563
Test name
Test status
Simulation time 3469215929 ps
CPU time 22.06 seconds
Started Aug 27 08:40:12 AM UTC 24
Finished Aug 27 08:40:35 AM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989016805 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.1989016805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3926529646
Short name T601
Test name
Test status
Simulation time 8241485600 ps
CPU time 175.32 seconds
Started Aug 27 08:40:28 AM UTC 24
Finished Aug 27 08:43:26 AM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926529646 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_acc
ess_b2b.3926529646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.3194629784
Short name T572
Test name
Test status
Simulation time 82583073 ps
CPU time 1.07 seconds
Started Aug 27 08:41:08 AM UTC 24
Finished Aug 27 08:41:10 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194629784 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3194629784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.2419865637
Short name T604
Test name
Test status
Simulation time 2578935045 ps
CPU time 161.21 seconds
Started Aug 27 08:41:04 AM UTC 24
Finished Aug 27 08:43:48 AM UTC 24
Peak memory 384952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419865637 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2419865637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.1005644638
Short name T560
Test name
Test status
Simulation time 157679886 ps
CPU time 3.59 seconds
Started Aug 27 08:39:54 AM UTC 24
Finished Aug 27 08:39:59 AM UTC 24
Peak memory 213832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005644638 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1005644638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1723867120
Short name T914
Test name
Test status
Simulation time 91675786399 ps
CPU time 2341.61 seconds
Started Aug 27 08:41:12 AM UTC 24
Finished Aug 27 09:20:38 AM UTC 24
Peak memory 397300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172386712
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.1723867120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.826997833
Short name T711
Test name
Test status
Simulation time 54284806093 ps
CPU time 762.27 seconds
Started Aug 27 08:41:11 AM UTC 24
Finished Aug 27 08:54:02 AM UTC 24
Peak memory 389356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826997833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.826997833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1611581699
Short name T628
Test name
Test status
Simulation time 2640384284 ps
CPU time 296.78 seconds
Started Aug 27 08:40:02 AM UTC 24
Finished Aug 27 08:45:03 AM UTC 24
Peak memory 213936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611581699 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.1611581699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1990177400
Short name T586
Test name
Test status
Simulation time 144212135 ps
CPU time 94.38 seconds
Started Aug 27 08:40:45 AM UTC 24
Finished Aug 27 08:42:22 AM UTC 24
Peak memory 368492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1990177400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_t
hroughput_w_partial_write.1990177400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1608345733
Short name T690
Test name
Test status
Simulation time 9518804363 ps
CPU time 575.57 seconds
Started Aug 27 08:41:53 AM UTC 24
Finished Aug 27 08:51:35 AM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608345733 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during
_key_req.1608345733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3580377256
Short name T593
Test name
Test status
Simulation time 19214752 ps
CPU time 1 seconds
Started Aug 27 08:42:39 AM UTC 24
Finished Aug 27 08:42:41 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580377256 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3580377256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.690328480
Short name T592
Test name
Test status
Simulation time 17021316473 ps
CPU time 75.63 seconds
Started Aug 27 08:41:20 AM UTC 24
Finished Aug 27 08:42:38 AM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690328480 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.690328480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.3860528145
Short name T611
Test name
Test status
Simulation time 13351962602 ps
CPU time 119.73 seconds
Started Aug 27 08:42:00 AM UTC 24
Finished Aug 27 08:44:02 AM UTC 24
Peak memory 370884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860528145 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.3860528145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.352186678
Short name T584
Test name
Test status
Simulation time 1349088770 ps
CPU time 7.96 seconds
Started Aug 27 08:41:50 AM UTC 24
Finished Aug 27 08:41:59 AM UTC 24
Peak memory 214080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352186678 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.352186678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2028947726
Short name T594
Test name
Test status
Simulation time 476354370 ps
CPU time 63.62 seconds
Started Aug 27 08:41:38 AM UTC 24
Finished Aug 27 08:42:44 AM UTC 24
Peak memory 358252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
028947726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ma
x_throughput.2028947726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1234536794
Short name T591
Test name
Test status
Simulation time 170036658 ps
CPU time 6.89 seconds
Started Aug 27 08:42:29 AM UTC 24
Finished Aug 27 08:42:38 AM UTC 24
Peak memory 224256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234536794 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.1234536794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1145327843
Short name T589
Test name
Test status
Simulation time 173289272 ps
CPU time 6.75 seconds
Started Aug 27 08:42:25 AM UTC 24
Finished Aug 27 08:42:33 AM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145327843 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.1145327843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1847939190
Short name T621
Test name
Test status
Simulation time 4581553507 ps
CPU time 199.15 seconds
Started Aug 27 08:41:18 AM UTC 24
Finished Aug 27 08:44:40 AM UTC 24
Peak memory 376696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847939190 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.1847939190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3140129281
Short name T580
Test name
Test status
Simulation time 390902342 ps
CPU time 7.9 seconds
Started Aug 27 08:41:28 AM UTC 24
Finished Aug 27 08:41:37 AM UTC 24
Peak memory 243448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140129281 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.3140129281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3546774070
Short name T643
Test name
Test status
Simulation time 16940538177 ps
CPU time 333.58 seconds
Started Aug 27 08:41:35 AM UTC 24
Finished Aug 27 08:47:14 AM UTC 24
Peak memory 214148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546774070 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_acc
ess_b2b.3546774070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3578037356
Short name T587
Test name
Test status
Simulation time 158866867 ps
CPU time 1.06 seconds
Started Aug 27 08:42:22 AM UTC 24
Finished Aug 27 08:42:24 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578037356 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3578037356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.281021873
Short name T665
Test name
Test status
Simulation time 1756066203 ps
CPU time 451.59 seconds
Started Aug 27 08:42:10 AM UTC 24
Finished Aug 27 08:49:47 AM UTC 24
Peak memory 374640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281021873 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.281021873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.3186885671
Short name T577
Test name
Test status
Simulation time 36436937 ps
CPU time 1.86 seconds
Started Aug 27 08:41:16 AM UTC 24
Finished Aug 27 08:41:19 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186885671 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3186885671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.211291363
Short name T930
Test name
Test status
Simulation time 265945744051 ps
CPU time 3394.91 seconds
Started Aug 27 08:42:37 AM UTC 24
Finished Aug 27 09:39:47 AM UTC 24
Peak memory 388660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211291363
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.211291363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2183482950
Short name T50
Test name
Test status
Simulation time 2168130866 ps
CPU time 96.37 seconds
Started Aug 27 08:42:34 AM UTC 24
Finished Aug 27 08:44:12 AM UTC 24
Peak memory 354348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183482950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2183482950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2346214193
Short name T616
Test name
Test status
Simulation time 5810159946 ps
CPU time 168.56 seconds
Started Aug 27 08:41:25 AM UTC 24
Finished Aug 27 08:44:17 AM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346214193 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.2346214193
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3102836068
Short name T582
Test name
Test status
Simulation time 43456363 ps
CPU time 3.16 seconds
Started Aug 27 08:41:45 AM UTC 24
Finished Aug 27 08:41:49 AM UTC 24
Peak memory 230540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3102836068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_t
hroughput_w_partial_write.3102836068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.453352233
Short name T705
Test name
Test status
Simulation time 3772098373 ps
CPU time 615 seconds
Started Aug 27 08:43:27 AM UTC 24
Finished Aug 27 08:53:49 AM UTC 24
Peak memory 384868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453352233 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_during_
key_req.453352233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.1842196718
Short name T610
Test name
Test status
Simulation time 32564262 ps
CPU time 0.91 seconds
Started Aug 27 08:43:59 AM UTC 24
Finished Aug 27 08:44:01 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842196718 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1842196718
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.3677068091
Short name T603
Test name
Test status
Simulation time 2039736246 ps
CPU time 51.83 seconds
Started Aug 27 08:42:45 AM UTC 24
Finished Aug 27 08:43:39 AM UTC 24
Peak memory 213824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677068091 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.3677068091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.1162721752
Short name T735
Test name
Test status
Simulation time 48317920291 ps
CPU time 747.42 seconds
Started Aug 27 08:43:30 AM UTC 24
Finished Aug 27 08:56:05 AM UTC 24
Peak memory 384952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162721752 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.1162721752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1309974918
Short name T602
Test name
Test status
Simulation time 516807738 ps
CPU time 8.01 seconds
Started Aug 27 08:43:20 AM UTC 24
Finished Aug 27 08:43:29 AM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309974918 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.1309974918
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2198624640
Short name T608
Test name
Test status
Simulation time 395376606 ps
CPU time 51.33 seconds
Started Aug 27 08:43:03 AM UTC 24
Finished Aug 27 08:43:56 AM UTC 24
Peak memory 323372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
198624640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ma
x_throughput.2198624640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.890988596
Short name T609
Test name
Test status
Simulation time 239583157 ps
CPU time 5.19 seconds
Started Aug 27 08:43:52 AM UTC 24
Finished Aug 27 08:43:58 AM UTC 24
Peak memory 224300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890988596 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.890988596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2041219537
Short name T612
Test name
Test status
Simulation time 1429462117 ps
CPU time 12.27 seconds
Started Aug 27 08:43:52 AM UTC 24
Finished Aug 27 08:44:05 AM UTC 24
Peak memory 224340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041219537 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.2041219537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.3701663095
Short name T681
Test name
Test status
Simulation time 2686892000 ps
CPU time 485.9 seconds
Started Aug 27 08:42:42 AM UTC 24
Finished Aug 27 08:50:54 AM UTC 24
Peak memory 384940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701663095 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.3701663095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.373108522
Short name T598
Test name
Test status
Simulation time 143199717 ps
CPU time 9.58 seconds
Started Aug 27 08:42:51 AM UTC 24
Finished Aug 27 08:43:02 AM UTC 24
Peak memory 213788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373108522 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.373108522
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3182155850
Short name T645
Test name
Test status
Simulation time 15598414885 ps
CPU time 259.65 seconds
Started Aug 27 08:42:57 AM UTC 24
Finished Aug 27 08:47:20 AM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182155850 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_acc
ess_b2b.3182155850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2294264955
Short name T605
Test name
Test status
Simulation time 27662774 ps
CPU time 1.03 seconds
Started Aug 27 08:43:48 AM UTC 24
Finished Aug 27 08:43:50 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294264955 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2294264955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.451266934
Short name T755
Test name
Test status
Simulation time 17074164524 ps
CPU time 866.06 seconds
Started Aug 27 08:43:39 AM UTC 24
Finished Aug 27 08:58:15 AM UTC 24
Peak memory 384852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451266934 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.451266934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.120622333
Short name T613
Test name
Test status
Simulation time 2593323935 ps
CPU time 88.07 seconds
Started Aug 27 08:42:39 AM UTC 24
Finished Aug 27 08:44:09 AM UTC 24
Peak memory 364468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120622333 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.120622333
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.4279577050
Short name T920
Test name
Test status
Simulation time 128745857336 ps
CPU time 2338.32 seconds
Started Aug 27 08:43:57 AM UTC 24
Finished Aug 27 09:23:20 AM UTC 24
Peak memory 385056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427957705
0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.4279577050
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1959620193
Short name T620
Test name
Test status
Simulation time 1807737056 ps
CPU time 42.56 seconds
Started Aug 27 08:43:55 AM UTC 24
Finished Aug 27 08:44:39 AM UTC 24
Peak memory 298928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959620193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1959620193
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.3669557589
Short name T635
Test name
Test status
Simulation time 3407273610 ps
CPU time 211.03 seconds
Started Aug 27 08:42:45 AM UTC 24
Finished Aug 27 08:46:20 AM UTC 24
Peak memory 213956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669557589 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.3669557589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2178047007
Short name T615
Test name
Test status
Simulation time 155195308 ps
CPU time 59.81 seconds
Started Aug 27 08:43:10 AM UTC 24
Finished Aug 27 08:44:12 AM UTC 24
Peak memory 349988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2178047007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_t
hroughput_w_partial_write.2178047007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.2918231298
Short name T751
Test name
Test status
Simulation time 3916846312 ps
CPU time 787.9 seconds
Started Aug 27 08:44:26 AM UTC 24
Finished Aug 27 08:57:42 AM UTC 24
Peak memory 386980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918231298 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_during
_key_req.2918231298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.150024970
Short name T627
Test name
Test status
Simulation time 22711038 ps
CPU time 0.87 seconds
Started Aug 27 08:44:52 AM UTC 24
Finished Aug 27 08:44:54 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150024970 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.150024970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.4035343278
Short name T622
Test name
Test status
Simulation time 1345767394 ps
CPU time 34.23 seconds
Started Aug 27 08:44:06 AM UTC 24
Finished Aug 27 08:44:42 AM UTC 24
Peak memory 214104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035343278 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.4035343278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.2909975156
Short name T794
Test name
Test status
Simulation time 12311990015 ps
CPU time 1004.04 seconds
Started Aug 27 08:44:35 AM UTC 24
Finished Aug 27 09:01:30 AM UTC 24
Peak memory 386940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909975156 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.2909975156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.69895798
Short name T618
Test name
Test status
Simulation time 1160054770 ps
CPU time 5.37 seconds
Started Aug 27 08:44:19 AM UTC 24
Finished Aug 27 08:44:25 AM UTC 24
Peak memory 224156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69895798 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.69895798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1863870310
Short name T624
Test name
Test status
Simulation time 100170886 ps
CPU time 30.98 seconds
Started Aug 27 08:44:13 AM UTC 24
Finished Aug 27 08:44:45 AM UTC 24
Peak memory 319344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
863870310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma
x_throughput.1863870310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.261777348
Short name T625
Test name
Test status
Simulation time 108108386 ps
CPU time 4.38 seconds
Started Aug 27 08:44:44 AM UTC 24
Finished Aug 27 08:44:49 AM UTC 24
Peak memory 223996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261777348 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.261777348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.1791254904
Short name T626
Test name
Test status
Simulation time 140401096 ps
CPU time 7.56 seconds
Started Aug 27 08:44:43 AM UTC 24
Finished Aug 27 08:44:51 AM UTC 24
Peak memory 224440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791254904 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.1791254904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3561473674
Short name T889
Test name
Test status
Simulation time 37685331213 ps
CPU time 1685.98 seconds
Started Aug 27 08:44:03 AM UTC 24
Finished Aug 27 09:12:28 AM UTC 24
Peak memory 386992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561473674 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.3561473674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.392240365
Short name T617
Test name
Test status
Simulation time 64776282 ps
CPU time 5.55 seconds
Started Aug 27 08:44:12 AM UTC 24
Finished Aug 27 08:44:18 AM UTC 24
Peak memory 233204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392240365 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.392240365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3126887689
Short name T683
Test name
Test status
Simulation time 263557273111 ps
CPU time 405.65 seconds
Started Aug 27 08:44:13 AM UTC 24
Finished Aug 27 08:51:04 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126887689 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_acc
ess_b2b.3126887689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2761175369
Short name T623
Test name
Test status
Simulation time 104854978 ps
CPU time 1.2 seconds
Started Aug 27 08:44:41 AM UTC 24
Finished Aug 27 08:44:43 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761175369 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2761175369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.1204113743
Short name T717
Test name
Test status
Simulation time 2332546765 ps
CPU time 598.69 seconds
Started Aug 27 08:44:39 AM UTC 24
Finished Aug 27 08:54:45 AM UTC 24
Peak memory 384880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204113743 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1204113743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.3777796314
Short name T632
Test name
Test status
Simulation time 655881766 ps
CPU time 108.14 seconds
Started Aug 27 08:44:02 AM UTC 24
Finished Aug 27 08:45:52 AM UTC 24
Peak memory 378812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777796314 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3777796314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3289689292
Short name T903
Test name
Test status
Simulation time 39223800405 ps
CPU time 1816.39 seconds
Started Aug 27 08:44:50 AM UTC 24
Finished Aug 27 09:15:26 AM UTC 24
Peak memory 388976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328968929
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.3289689292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.590061675
Short name T672
Test name
Test status
Simulation time 5819203726 ps
CPU time 352.71 seconds
Started Aug 27 08:44:09 AM UTC 24
Finished Aug 27 08:50:07 AM UTC 24
Peak memory 214216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590061675 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.590061675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.3403154207
Short name T619
Test name
Test status
Simulation time 201309033 ps
CPU time 15.53 seconds
Started Aug 27 08:44:18 AM UTC 24
Finished Aug 27 08:44:35 AM UTC 24
Peak memory 272232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3403154207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_t
hroughput_w_partial_write.3403154207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1153773728
Short name T736
Test name
Test status
Simulation time 9415703282 ps
CPU time 619.89 seconds
Started Aug 27 08:46:22 AM UTC 24
Finished Aug 27 08:56:50 AM UTC 24
Peak memory 382900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153773728 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during
_key_req.1153773728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1735868021
Short name T644
Test name
Test status
Simulation time 40914052 ps
CPU time 0.88 seconds
Started Aug 27 08:47:14 AM UTC 24
Finished Aug 27 08:47:16 AM UTC 24
Peak memory 212816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735868021 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1735868021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.2157382951
Short name T631
Test name
Test status
Simulation time 2291143170 ps
CPU time 26.74 seconds
Started Aug 27 08:45:18 AM UTC 24
Finished Aug 27 08:45:46 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157382951 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.2157382951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1246712503
Short name T783
Test name
Test status
Simulation time 11918308345 ps
CPU time 849.66 seconds
Started Aug 27 08:46:34 AM UTC 24
Finished Aug 27 09:00:53 AM UTC 24
Peak memory 384904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246712503 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.1246712503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2039974298
Short name T637
Test name
Test status
Simulation time 2642442334 ps
CPU time 11.18 seconds
Started Aug 27 08:46:20 AM UTC 24
Finished Aug 27 08:46:33 AM UTC 24
Peak memory 224488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039974298 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.2039974298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1455877129
Short name T647
Test name
Test status
Simulation time 512939259 ps
CPU time 97.36 seconds
Started Aug 27 08:45:57 AM UTC 24
Finished Aug 27 08:47:36 AM UTC 24
Peak memory 380780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
455877129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ma
x_throughput.1455877129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.3487896879
Short name T642
Test name
Test status
Simulation time 161817638 ps
CPU time 7.25 seconds
Started Aug 27 08:47:04 AM UTC 24
Finished Aug 27 08:47:12 AM UTC 24
Peak memory 224016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487896879 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.3487896879
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3376515528
Short name T641
Test name
Test status
Simulation time 146888613 ps
CPU time 6.42 seconds
Started Aug 27 08:46:59 AM UTC 24
Finished Aug 27 08:47:07 AM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376515528 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.3376515528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.538125651
Short name T750
Test name
Test status
Simulation time 16382561052 ps
CPU time 743.23 seconds
Started Aug 27 08:45:03 AM UTC 24
Finished Aug 27 08:57:35 AM UTC 24
Peak memory 386992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538125651 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.538125651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.4018549799
Short name T648
Test name
Test status
Simulation time 659544102 ps
CPU time 108.2 seconds
Started Aug 27 08:45:47 AM UTC 24
Finished Aug 27 08:47:37 AM UTC 24
Peak memory 372804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018549799 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.4018549799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2231727028
Short name T738
Test name
Test status
Simulation time 78069569464 ps
CPU time 661.58 seconds
Started Aug 27 08:45:53 AM UTC 24
Finished Aug 27 08:57:03 AM UTC 24
Peak memory 213840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231727028 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_acc
ess_b2b.2231727028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.838349102
Short name T639
Test name
Test status
Simulation time 38217621 ps
CPU time 1.02 seconds
Started Aug 27 08:46:56 AM UTC 24
Finished Aug 27 08:46:58 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838349102 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.838349102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.3460864646
Short name T687
Test name
Test status
Simulation time 3506844495 ps
CPU time 288.09 seconds
Started Aug 27 08:46:39 AM UTC 24
Finished Aug 27 08:51:31 AM UTC 24
Peak memory 366516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460864646 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.3460864646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.327832968
Short name T629
Test name
Test status
Simulation time 96099377 ps
CPU time 18.92 seconds
Started Aug 27 08:44:55 AM UTC 24
Finished Aug 27 08:45:16 AM UTC 24
Peak memory 280436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327832968 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.327832968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3289488727
Short name T671
Test name
Test status
Simulation time 13977654099 ps
CPU time 166.36 seconds
Started Aug 27 08:47:13 AM UTC 24
Finished Aug 27 08:50:02 AM UTC 24
Peak memory 342188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328948872
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.3289488727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1271759613
Short name T114
Test name
Test status
Simulation time 5743083277 ps
CPU time 68.62 seconds
Started Aug 27 08:47:07 AM UTC 24
Finished Aug 27 08:48:18 AM UTC 24
Peak memory 325540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271759613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1271759613
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3330545622
Short name T658
Test name
Test status
Simulation time 1806990102 ps
CPU time 202.69 seconds
Started Aug 27 08:45:32 AM UTC 24
Finished Aug 27 08:48:58 AM UTC 24
Peak memory 213916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330545622 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.3330545622
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.2366725922
Short name T636
Test name
Test status
Simulation time 241231861 ps
CPU time 20.51 seconds
Started Aug 27 08:46:00 AM UTC 24
Finished Aug 27 08:46:22 AM UTC 24
Peak memory 282476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2366725922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_t
hroughput_w_partial_write.2366725922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.3851562134
Short name T664
Test name
Test status
Simulation time 1751540082 ps
CPU time 76.79 seconds
Started Aug 27 08:48:26 AM UTC 24
Finished Aug 27 08:49:44 AM UTC 24
Peak memory 313192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851562134 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_during
_key_req.3851562134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1867479897
Short name T661
Test name
Test status
Simulation time 12072417 ps
CPU time 0.81 seconds
Started Aug 27 08:49:01 AM UTC 24
Finished Aug 27 08:49:02 AM UTC 24
Peak memory 212748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867479897 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1867479897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.438646436
Short name T655
Test name
Test status
Simulation time 1458937497 ps
CPU time 62.24 seconds
Started Aug 27 08:47:34 AM UTC 24
Finished Aug 27 08:48:38 AM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438646436 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.438646436
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.855476744
Short name T696
Test name
Test status
Simulation time 1896795481 ps
CPU time 225.81 seconds
Started Aug 27 08:48:26 AM UTC 24
Finished Aug 27 08:52:15 AM UTC 24
Peak memory 380712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855476744 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.855476744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1934402814
Short name T654
Test name
Test status
Simulation time 3292497184 ps
CPU time 7.06 seconds
Started Aug 27 08:48:24 AM UTC 24
Finished Aug 27 08:48:32 AM UTC 24
Peak memory 214308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934402814 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.1934402814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.477715235
Short name T652
Test name
Test status
Simulation time 180717327 ps
CPU time 33.13 seconds
Started Aug 27 08:47:50 AM UTC 24
Finished Aug 27 08:48:25 AM UTC 24
Peak memory 305272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
77715235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_max
_throughput.477715235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2303100187
Short name T659
Test name
Test status
Simulation time 575583815 ps
CPU time 7.33 seconds
Started Aug 27 08:48:49 AM UTC 24
Finished Aug 27 08:48:58 AM UTC 24
Peak memory 224048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303100187 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.2303100187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1563920477
Short name T657
Test name
Test status
Simulation time 92927592 ps
CPU time 5.19 seconds
Started Aug 27 08:48:42 AM UTC 24
Finished Aug 27 08:48:49 AM UTC 24
Peak memory 213772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563920477 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.1563920477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3926088737
Short name T734
Test name
Test status
Simulation time 7650159251 ps
CPU time 509.63 seconds
Started Aug 27 08:47:21 AM UTC 24
Finished Aug 27 08:55:56 AM UTC 24
Peak memory 380780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926088737 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.3926088737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.644321598
Short name T650
Test name
Test status
Simulation time 191088977 ps
CPU time 10.26 seconds
Started Aug 27 08:47:38 AM UTC 24
Finished Aug 27 08:47:49 AM UTC 24
Peak memory 214204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644321598 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.644321598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.4119002476
Short name T719
Test name
Test status
Simulation time 52267180516 ps
CPU time 426.1 seconds
Started Aug 27 08:47:46 AM UTC 24
Finished Aug 27 08:54:58 AM UTC 24
Peak memory 213988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119002476 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_acc
ess_b2b.4119002476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1462183015
Short name T656
Test name
Test status
Simulation time 31340208 ps
CPU time 1.09 seconds
Started Aug 27 08:48:39 AM UTC 24
Finished Aug 27 08:48:41 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462183015 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1462183015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.4124896732
Short name T660
Test name
Test status
Simulation time 1219340656 ps
CPU time 25.7 seconds
Started Aug 27 08:48:33 AM UTC 24
Finished Aug 27 08:49:00 AM UTC 24
Peak memory 214112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124896732 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.4124896732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.2273975241
Short name T646
Test name
Test status
Simulation time 702533637 ps
CPU time 14.81 seconds
Started Aug 27 08:47:18 AM UTC 24
Finished Aug 27 08:47:34 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273975241 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2273975241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3338711934
Short name T916
Test name
Test status
Simulation time 33122721256 ps
CPU time 1927.26 seconds
Started Aug 27 08:48:59 AM UTC 24
Finished Aug 27 09:21:26 AM UTC 24
Peak memory 384868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333871193
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.3338711934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.762309163
Short name T680
Test name
Test status
Simulation time 2244506398 ps
CPU time 95.6 seconds
Started Aug 27 08:48:58 AM UTC 24
Finished Aug 27 08:50:36 AM UTC 24
Peak memory 226292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762309163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.762309163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2032615522
Short name T694
Test name
Test status
Simulation time 2181306659 ps
CPU time 266.01 seconds
Started Aug 27 08:47:37 AM UTC 24
Finished Aug 27 08:52:07 AM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032615522 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.2032615522
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4087718817
Short name T651
Test name
Test status
Simulation time 91251096 ps
CPU time 2.95 seconds
Started Aug 27 08:48:18 AM UTC 24
Finished Aug 27 08:48:22 AM UTC 24
Peak memory 230544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4087718817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_t
hroughput_w_partial_write.4087718817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.501533315
Short name T720
Test name
Test status
Simulation time 6759038275 ps
CPU time 295.74 seconds
Started Aug 27 08:50:03 AM UTC 24
Finished Aug 27 08:55:02 AM UTC 24
Peak memory 356520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501533315 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_during_
key_req.501533315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3212378940
Short name T679
Test name
Test status
Simulation time 22013222 ps
CPU time 0.94 seconds
Started Aug 27 08:50:30 AM UTC 24
Finished Aug 27 08:50:32 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212378940 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.3212378940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2057851796
Short name T689
Test name
Test status
Simulation time 13884770553 ps
CPU time 118.46 seconds
Started Aug 27 08:49:30 AM UTC 24
Finished Aug 27 08:51:31 AM UTC 24
Peak memory 213788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057851796 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.2057851796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.2894891902
Short name T685
Test name
Test status
Simulation time 900634652 ps
CPU time 77.91 seconds
Started Aug 27 08:50:04 AM UTC 24
Finished Aug 27 08:51:23 AM UTC 24
Peak memory 364404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894891902 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.2894891902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.621329505
Short name T673
Test name
Test status
Simulation time 1324806982 ps
CPU time 7.45 seconds
Started Aug 27 08:49:59 AM UTC 24
Finished Aug 27 08:50:07 AM UTC 24
Peak memory 213880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621329505 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.621329505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1042311664
Short name T678
Test name
Test status
Simulation time 348063389 ps
CPU time 31.93 seconds
Started Aug 27 08:49:55 AM UTC 24
Finished Aug 27 08:50:29 AM UTC 24
Peak memory 313204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
042311664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ma
x_throughput.1042311664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.4262461573
Short name T676
Test name
Test status
Simulation time 699344080 ps
CPU time 7.09 seconds
Started Aug 27 08:50:14 AM UTC 24
Finished Aug 27 08:50:22 AM UTC 24
Peak memory 224008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262461573 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.4262461573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.275343552
Short name T677
Test name
Test status
Simulation time 1639856300 ps
CPU time 10.54 seconds
Started Aug 27 08:50:11 AM UTC 24
Finished Aug 27 08:50:23 AM UTC 24
Peak memory 224076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275343552 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.275343552
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1841517415
Short name T757
Test name
Test status
Simulation time 20648690758 ps
CPU time 574.42 seconds
Started Aug 27 08:49:12 AM UTC 24
Finished Aug 27 08:58:53 AM UTC 24
Peak memory 368816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841517415 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.1841517415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.57859267
Short name T669
Test name
Test status
Simulation time 151980517 ps
CPU time 9.39 seconds
Started Aug 27 08:49:47 AM UTC 24
Finished Aug 27 08:49:58 AM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57859267 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.57859267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2319855953
Short name T753
Test name
Test status
Simulation time 78616130643 ps
CPU time 475.06 seconds
Started Aug 27 08:49:51 AM UTC 24
Finished Aug 27 08:57:53 AM UTC 24
Peak memory 214220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319855953 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_acc
ess_b2b.2319855953
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4220764928
Short name T674
Test name
Test status
Simulation time 165708591 ps
CPU time 1.04 seconds
Started Aug 27 08:50:08 AM UTC 24
Finished Aug 27 08:50:10 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220764928 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.4220764928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.3821962661
Short name T701
Test name
Test status
Simulation time 1393167625 ps
CPU time 158.2 seconds
Started Aug 27 08:50:08 AM UTC 24
Finished Aug 27 08:52:49 AM UTC 24
Peak memory 315508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821962661 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3821962661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.2637643685
Short name T667
Test name
Test status
Simulation time 306093251 ps
CPU time 49.38 seconds
Started Aug 27 08:49:04 AM UTC 24
Finished Aug 27 08:49:55 AM UTC 24
Peak memory 325756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637643685 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2637643685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.840286348
Short name T921
Test name
Test status
Simulation time 46797607306 ps
CPU time 1961.14 seconds
Started Aug 27 08:50:24 AM UTC 24
Finished Aug 27 09:23:24 AM UTC 24
Peak memory 393236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840286348
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.840286348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2293668267
Short name T115
Test name
Test status
Simulation time 8964415243 ps
CPU time 223.36 seconds
Started Aug 27 08:50:23 AM UTC 24
Finished Aug 27 08:54:10 AM UTC 24
Peak memory 387052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293668267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2293668267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2961535248
Short name T718
Test name
Test status
Simulation time 3070764600 ps
CPU time 300.67 seconds
Started Aug 27 08:49:45 AM UTC 24
Finished Aug 27 08:54:51 AM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961535248 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.2961535248
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.793250445
Short name T670
Test name
Test status
Simulation time 47391362 ps
CPU time 2.21 seconds
Started Aug 27 08:49:59 AM UTC 24
Finished Aug 27 08:50:02 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
793250445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_th
roughput_w_partial_write.793250445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3691555805
Short name T807
Test name
Test status
Simulation time 3293555081 ps
CPU time 634.14 seconds
Started Aug 27 08:51:32 AM UTC 24
Finished Aug 27 09:02:14 AM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691555805 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_during
_key_req.3691555805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.751274540
Short name T698
Test name
Test status
Simulation time 39194940 ps
CPU time 0.97 seconds
Started Aug 27 08:52:16 AM UTC 24
Finished Aug 27 08:52:18 AM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751274540 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.751274540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.949895938
Short name T684
Test name
Test status
Simulation time 1046734932 ps
CPU time 24.12 seconds
Started Aug 27 08:50:55 AM UTC 24
Finished Aug 27 08:51:20 AM UTC 24
Peak memory 214080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949895938 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.949895938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.3249479789
Short name T774
Test name
Test status
Simulation time 16913897076 ps
CPU time 489.71 seconds
Started Aug 27 08:51:32 AM UTC 24
Finished Aug 27 08:59:48 AM UTC 24
Peak memory 387256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249479789 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.3249479789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.4249440701
Short name T691
Test name
Test status
Simulation time 1774698157 ps
CPU time 10.12 seconds
Started Aug 27 08:51:32 AM UTC 24
Finished Aug 27 08:51:43 AM UTC 24
Peak memory 214132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249440701 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.4249440701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.825806364
Short name T688
Test name
Test status
Simulation time 48622999 ps
CPU time 5.38 seconds
Started Aug 27 08:51:25 AM UTC 24
Finished Aug 27 08:51:31 AM UTC 24
Peak memory 235388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8
25806364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_max
_throughput.825806364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.1808713128
Short name T695
Test name
Test status
Simulation time 97535627 ps
CPU time 4.45 seconds
Started Aug 27 08:52:05 AM UTC 24
Finished Aug 27 08:52:10 AM UTC 24
Peak memory 224112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808713128 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.1808713128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.528676897
Short name T693
Test name
Test status
Simulation time 1302812616 ps
CPU time 15.14 seconds
Started Aug 27 08:51:47 AM UTC 24
Finished Aug 27 08:52:04 AM UTC 24
Peak memory 213812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528676897 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.528676897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.479579299
Short name T789
Test name
Test status
Simulation time 55425236014 ps
CPU time 623.21 seconds
Started Aug 27 08:50:37 AM UTC 24
Finished Aug 27 09:01:07 AM UTC 24
Peak memory 382896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479579299 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.479579299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.655686915
Short name T686
Test name
Test status
Simulation time 4421720138 ps
CPU time 22.56 seconds
Started Aug 27 08:51:04 AM UTC 24
Finished Aug 27 08:51:28 AM UTC 24
Peak memory 213980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655686915 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.655686915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2209692089
Short name T754
Test name
Test status
Simulation time 4696668236 ps
CPU time 404.23 seconds
Started Aug 27 08:51:21 AM UTC 24
Finished Aug 27 08:58:11 AM UTC 24
Peak memory 214216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209692089 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_acc
ess_b2b.2209692089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3676468691
Short name T692
Test name
Test status
Simulation time 34202536 ps
CPU time 1.03 seconds
Started Aug 27 08:51:44 AM UTC 24
Finished Aug 27 08:51:46 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676468691 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3676468691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2168655508
Short name T888
Test name
Test status
Simulation time 31976608616 ps
CPU time 1212.59 seconds
Started Aug 27 08:51:36 AM UTC 24
Finished Aug 27 09:12:02 AM UTC 24
Peak memory 384952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168655508 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2168655508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.1505597555
Short name T682
Test name
Test status
Simulation time 348155410 ps
CPU time 22.44 seconds
Started Aug 27 08:50:33 AM UTC 24
Finished Aug 27 08:50:56 AM UTC 24
Peak memory 284796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505597555 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1505597555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.4207621901
Short name T918
Test name
Test status
Simulation time 17502263330 ps
CPU time 1819.58 seconds
Started Aug 27 08:52:11 AM UTC 24
Finished Aug 27 09:22:51 AM UTC 24
Peak memory 395108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420762190
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.4207621901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.253369230
Short name T723
Test name
Test status
Simulation time 4301990698 ps
CPU time 180.08 seconds
Started Aug 27 08:52:08 AM UTC 24
Finished Aug 27 08:55:11 AM UTC 24
Peak memory 323828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253369230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.253369230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.806799938
Short name T704
Test name
Test status
Simulation time 1403569773 ps
CPU time 159.53 seconds
Started Aug 27 08:50:57 AM UTC 24
Finished Aug 27 08:53:39 AM UTC 24
Peak memory 213832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806799938 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.806799938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.2419013347
Short name T703
Test name
Test status
Simulation time 615300179 ps
CPU time 88.69 seconds
Started Aug 27 08:51:29 AM UTC 24
Finished Aug 27 08:52:59 AM UTC 24
Peak memory 381036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2419013347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_t
hroughput_w_partial_write.2419013347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1591271155
Short name T38
Test name
Test status
Simulation time 4299652486 ps
CPU time 579.79 seconds
Started Aug 27 07:59:39 AM UTC 24
Finished Aug 27 08:09:25 AM UTC 24
Peak memory 370216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591271155 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_during_
key_req.1591271155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3006670370
Short name T59
Test name
Test status
Simulation time 20071522 ps
CPU time 0.91 seconds
Started Aug 27 07:59:43 AM UTC 24
Finished Aug 27 07:59:45 AM UTC 24
Peak memory 212808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006670370 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.3006670370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_bijection.1189196834
Short name T117
Test name
Test status
Simulation time 3372484404 ps
CPU time 64.88 seconds
Started Aug 27 07:59:34 AM UTC 24
Finished Aug 27 08:00:41 AM UTC 24
Peak memory 213792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189196834 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.1189196834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_executable.1136036298
Short name T65
Test name
Test status
Simulation time 8728345648 ps
CPU time 60.69 seconds
Started Aug 27 07:59:39 AM UTC 24
Finished Aug 27 08:00:41 AM UTC 24
Peak memory 302616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136036298 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.1136036298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1139771506
Short name T121
Test name
Test status
Simulation time 134973786 ps
CPU time 81.91 seconds
Started Aug 27 07:59:37 AM UTC 24
Finished Aug 27 08:01:00 AM UTC 24
Peak memory 376680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
139771506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max
_throughput.1139771506
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.159756289
Short name T45
Test name
Test status
Simulation time 188636409 ps
CPU time 4.9 seconds
Started Aug 27 07:59:41 AM UTC 24
Finished Aug 27 07:59:47 AM UTC 24
Peak memory 224316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159756289 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.159756289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.795212424
Short name T51
Test name
Test status
Simulation time 708858969 ps
CPU time 12.97 seconds
Started Aug 27 07:59:41 AM UTC 24
Finished Aug 27 07:59:55 AM UTC 24
Peak memory 224068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795212424 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.795212424
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.869604952
Short name T273
Test name
Test status
Simulation time 3856509780 ps
CPU time 921.58 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 08:15:05 AM UTC 24
Peak memory 385204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869604952 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.869604952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3277749252
Short name T99
Test name
Test status
Simulation time 552341334 ps
CPU time 3.69 seconds
Started Aug 27 07:59:34 AM UTC 24
Finished Aug 27 07:59:39 AM UTC 24
Peak memory 213820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277749252 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.3277749252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2521366985
Short name T215
Test name
Test status
Simulation time 6013425686 ps
CPU time 465.14 seconds
Started Aug 27 07:59:36 AM UTC 24
Finished Aug 27 08:07:27 AM UTC 24
Peak memory 214096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521366985 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acce
ss_b2b.2521366985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.4278823236
Short name T57
Test name
Test status
Simulation time 28273897 ps
CPU time 1.27 seconds
Started Aug 27 07:59:39 AM UTC 24
Finished Aug 27 07:59:41 AM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278823236 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.4278823236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_regwen.2516170539
Short name T141
Test name
Test status
Simulation time 13273026080 ps
CPU time 812.51 seconds
Started Aug 27 07:59:39 AM UTC 24
Finished Aug 27 08:13:20 AM UTC 24
Peak memory 387260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516170539 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.2516170539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1049221531
Short name T32
Test name
Test status
Simulation time 1747263732 ps
CPU time 3.41 seconds
Started Aug 27 07:59:41 AM UTC 24
Finished Aug 27 07:59:46 AM UTC 24
Peak memory 250096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049221531 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1049221531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_smoke.205377776
Short name T165
Test name
Test status
Simulation time 1030371928 ps
CPU time 18.36 seconds
Started Aug 27 07:59:33 AM UTC 24
Finished Aug 27 07:59:53 AM UTC 24
Peak memory 213728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205377776 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.205377776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2856514698
Short name T926
Test name
Test status
Simulation time 296833611572 ps
CPU time 5293.7 seconds
Started Aug 27 07:59:41 AM UTC 24
Finished Aug 27 09:28:52 AM UTC 24
Peak memory 396912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285651469
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.2856514698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.3296133545
Short name T108
Test name
Test status
Simulation time 23865744581 ps
CPU time 291.19 seconds
Started Aug 27 07:59:34 AM UTC 24
Finished Aug 27 08:04:30 AM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296133545 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.3296133545
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1257868196
Short name T61
Test name
Test status
Simulation time 296547660 ps
CPU time 13.99 seconds
Started Aug 27 07:59:37 AM UTC 24
Finished Aug 27 07:59:52 AM UTC 24
Peak memory 264040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1257868196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th
roughput_w_partial_write.1257868196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.2579600777
Short name T814
Test name
Test status
Simulation time 3935081217 ps
CPU time 572.35 seconds
Started Aug 27 08:53:51 AM UTC 24
Finished Aug 27 09:03:30 AM UTC 24
Peak memory 382812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579600777 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_during
_key_req.2579600777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.42711780
Short name T715
Test name
Test status
Simulation time 24757889 ps
CPU time 1.06 seconds
Started Aug 27 08:54:11 AM UTC 24
Finished Aug 27 08:54:13 AM UTC 24
Peak memory 212820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42711780 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.42711780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.3158163165
Short name T712
Test name
Test status
Simulation time 3099821898 ps
CPU time 91.13 seconds
Started Aug 27 08:52:34 AM UTC 24
Finished Aug 27 08:54:07 AM UTC 24
Peak memory 213864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158163165 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.3158163165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.2823662898
Short name T805
Test name
Test status
Simulation time 5701519714 ps
CPU time 484.79 seconds
Started Aug 27 08:53:53 AM UTC 24
Finished Aug 27 09:02:04 AM UTC 24
Peak memory 384912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823662898 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.2823662898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.4209294686
Short name T708
Test name
Test status
Simulation time 468980547 ps
CPU time 6.04 seconds
Started Aug 27 08:53:50 AM UTC 24
Finished Aug 27 08:53:57 AM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209294686 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.4209294686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.410046423
Short name T716
Test name
Test status
Simulation time 139354983 ps
CPU time 97.53 seconds
Started Aug 27 08:53:00 AM UTC 24
Finished Aug 27 08:54:39 AM UTC 24
Peak memory 374648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
10046423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_max
_throughput.410046423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1514775861
Short name T714
Test name
Test status
Simulation time 156138923 ps
CPU time 6.57 seconds
Started Aug 27 08:54:03 AM UTC 24
Finished Aug 27 08:54:10 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514775861 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.1514775861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2421923407
Short name T713
Test name
Test status
Simulation time 96323043 ps
CPU time 6.57 seconds
Started Aug 27 08:54:02 AM UTC 24
Finished Aug 27 08:54:09 AM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421923407 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.2421923407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3896122280
Short name T733
Test name
Test status
Simulation time 5030452874 ps
CPU time 198.66 seconds
Started Aug 27 08:52:19 AM UTC 24
Finished Aug 27 08:55:41 AM UTC 24
Peak memory 360368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896122280 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.3896122280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.991875587
Short name T702
Test name
Test status
Simulation time 74279976 ps
CPU time 2.34 seconds
Started Aug 27 08:52:50 AM UTC 24
Finished Aug 27 08:52:53 AM UTC 24
Peak memory 213732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991875587 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.991875587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.900514763
Short name T792
Test name
Test status
Simulation time 34102775738 ps
CPU time 502.06 seconds
Started Aug 27 08:52:54 AM UTC 24
Finished Aug 27 09:01:22 AM UTC 24
Peak memory 213860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900514763 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_acce
ss_b2b.900514763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.1921029207
Short name T710
Test name
Test status
Simulation time 30378995 ps
CPU time 1.05 seconds
Started Aug 27 08:53:59 AM UTC 24
Finished Aug 27 08:54:01 AM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921029207 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1921029207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.834111498
Short name T860
Test name
Test status
Simulation time 10390000304 ps
CPU time 789.14 seconds
Started Aug 27 08:53:59 AM UTC 24
Finished Aug 27 09:07:17 AM UTC 24
Peak memory 381112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834111498 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.834111498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.1297645095
Short name T699
Test name
Test status
Simulation time 1194356796 ps
CPU time 14.84 seconds
Started Aug 27 08:52:17 AM UTC 24
Finished Aug 27 08:52:33 AM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297645095 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1297645095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2947801325
Short name T908
Test name
Test status
Simulation time 127630590536 ps
CPU time 1396.91 seconds
Started Aug 27 08:54:10 AM UTC 24
Finished Aug 27 09:17:42 AM UTC 24
Peak memory 388976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294780132
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.2947801325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.4089135940
Short name T741
Test name
Test status
Simulation time 4302241309 ps
CPU time 276.81 seconds
Started Aug 27 08:52:37 AM UTC 24
Finished Aug 27 08:57:18 AM UTC 24
Peak memory 213984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089135940 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.4089135940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.2351427413
Short name T709
Test name
Test status
Simulation time 838342294 ps
CPU time 16.43 seconds
Started Aug 27 08:53:40 AM UTC 24
Finished Aug 27 08:53:58 AM UTC 24
Peak memory 276584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2351427413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_t
hroughput_w_partial_write.2351427413
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.195287222
Short name T840
Test name
Test status
Simulation time 3407263552 ps
CPU time 586.53 seconds
Started Aug 27 08:55:12 AM UTC 24
Finished Aug 27 09:05:06 AM UTC 24
Peak memory 378728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195287222 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_during_
key_req.195287222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3319829826
Short name T732
Test name
Test status
Simulation time 88446187 ps
CPU time 0.87 seconds
Started Aug 27 08:55:39 AM UTC 24
Finished Aug 27 08:55:41 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319829826 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.3319829826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.303514969
Short name T726
Test name
Test status
Simulation time 2218841730 ps
CPU time 37.72 seconds
Started Aug 27 08:54:41 AM UTC 24
Finished Aug 27 08:55:20 AM UTC 24
Peak memory 213888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303514969 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.303514969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.1462906959
Short name T799
Test name
Test status
Simulation time 37791440157 ps
CPU time 381.26 seconds
Started Aug 27 08:55:16 AM UTC 24
Finished Aug 27 09:01:43 AM UTC 24
Peak memory 372932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462906959 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.1462906959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2428766679
Short name T725
Test name
Test status
Simulation time 1899889960 ps
CPU time 8.69 seconds
Started Aug 27 08:55:09 AM UTC 24
Finished Aug 27 08:55:20 AM UTC 24
Peak memory 224164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428766679 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.2428766679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.3285518072
Short name T737
Test name
Test status
Simulation time 543047096 ps
CPU time 107.92 seconds
Started Aug 27 08:55:04 AM UTC 24
Finished Aug 27 08:56:54 AM UTC 24
Peak memory 381040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
285518072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ma
x_throughput.3285518072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2443643238
Short name T729
Test name
Test status
Simulation time 169973412 ps
CPU time 3.41 seconds
Started Aug 27 08:55:24 AM UTC 24
Finished Aug 27 08:55:28 AM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443643238 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.2443643238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2950477316
Short name T730
Test name
Test status
Simulation time 361079583 ps
CPU time 6.76 seconds
Started Aug 27 08:55:24 AM UTC 24
Finished Aug 27 08:55:32 AM UTC 24
Peak memory 224084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950477316 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.2950477316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2123616876
Short name T874
Test name
Test status
Simulation time 51330410497 ps
CPU time 864.18 seconds
Started Aug 27 08:54:14 AM UTC 24
Finished Aug 27 09:08:48 AM UTC 24
Peak memory 386920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123616876 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2123616876
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1398425233
Short name T722
Test name
Test status
Simulation time 600308978 ps
CPU time 15.22 seconds
Started Aug 27 08:54:52 AM UTC 24
Finished Aug 27 08:55:08 AM UTC 24
Peak memory 214232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398425233 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.1398425233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2787940691
Short name T804
Test name
Test status
Simulation time 51095839209 ps
CPU time 419 seconds
Started Aug 27 08:54:59 AM UTC 24
Finished Aug 27 09:02:04 AM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787940691 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_acc
ess_b2b.2787940691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1335982001
Short name T727
Test name
Test status
Simulation time 26672317 ps
CPU time 1.09 seconds
Started Aug 27 08:55:21 AM UTC 24
Finished Aug 27 08:55:23 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335982001 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1335982001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.2447287782
Short name T909
Test name
Test status
Simulation time 16570354132 ps
CPU time 1375.81 seconds
Started Aug 27 08:55:21 AM UTC 24
Finished Aug 27 09:18:32 AM UTC 24
Peak memory 385148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447287782 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2447287782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.1177817468
Short name T724
Test name
Test status
Simulation time 3226523865 ps
CPU time 63.05 seconds
Started Aug 27 08:54:11 AM UTC 24
Finished Aug 27 08:55:16 AM UTC 24
Peak memory 327612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177817468 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1177817468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2871234074
Short name T919
Test name
Test status
Simulation time 69535167023 ps
CPU time 1637.32 seconds
Started Aug 27 08:55:33 AM UTC 24
Finished Aug 27 09:23:08 AM UTC 24
Peak memory 386996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287123407
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.2871234074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.913956715
Short name T116
Test name
Test status
Simulation time 6948459070 ps
CPU time 78.81 seconds
Started Aug 27 08:55:29 AM UTC 24
Finished Aug 27 08:56:50 AM UTC 24
Peak memory 315572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913956715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.913956715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3897393404
Short name T771
Test name
Test status
Simulation time 5184269416 ps
CPU time 274.13 seconds
Started Aug 27 08:54:46 AM UTC 24
Finished Aug 27 08:59:24 AM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897393404 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.3897393404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3253193176
Short name T731
Test name
Test status
Simulation time 427388031 ps
CPU time 33.27 seconds
Started Aug 27 08:55:04 AM UTC 24
Finished Aug 27 08:55:39 AM UTC 24
Peak memory 298860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3253193176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_t
hroughput_w_partial_write.3253193176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3210019417
Short name T819
Test name
Test status
Simulation time 14621758647 ps
CPU time 385.99 seconds
Started Aug 27 08:57:16 AM UTC 24
Finished Aug 27 09:03:47 AM UTC 24
Peak memory 376624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210019417 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_during
_key_req.3210019417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3624669812
Short name T749
Test name
Test status
Simulation time 15553065 ps
CPU time 0.86 seconds
Started Aug 27 08:57:32 AM UTC 24
Finished Aug 27 08:57:34 AM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624669812 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.3624669812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.1530853249
Short name T739
Test name
Test status
Simulation time 4242259131 ps
CPU time 76.32 seconds
Started Aug 27 08:55:57 AM UTC 24
Finished Aug 27 08:57:15 AM UTC 24
Peak memory 214164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530853249 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.1530853249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.3402649721
Short name T848
Test name
Test status
Simulation time 8634549957 ps
CPU time 516.41 seconds
Started Aug 27 08:57:18 AM UTC 24
Finished Aug 27 09:06:02 AM UTC 24
Peak memory 380864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402649721 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.3402649721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1028663628
Short name T743
Test name
Test status
Simulation time 3151452962 ps
CPU time 15.3 seconds
Started Aug 27 08:57:04 AM UTC 24
Finished Aug 27 08:57:20 AM UTC 24
Peak memory 213844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028663628 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.1028663628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1505220582
Short name T746
Test name
Test status
Simulation time 349863697 ps
CPU time 33.7 seconds
Started Aug 27 08:56:55 AM UTC 24
Finished Aug 27 08:57:30 AM UTC 24
Peak memory 300844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
505220582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ma
x_throughput.1505220582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.680972264
Short name T748
Test name
Test status
Simulation time 310853574 ps
CPU time 7.62 seconds
Started Aug 27 08:57:23 AM UTC 24
Finished Aug 27 08:57:32 AM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680972264 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.680972264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.27366923
Short name T745
Test name
Test status
Simulation time 407029149 ps
CPU time 5.96 seconds
Started Aug 27 08:57:21 AM UTC 24
Finished Aug 27 08:57:29 AM UTC 24
Peak memory 224024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27366923 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.27366923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3950473093
Short name T787
Test name
Test status
Simulation time 28301589779 ps
CPU time 319.14 seconds
Started Aug 27 08:55:42 AM UTC 24
Finished Aug 27 09:01:06 AM UTC 24
Peak memory 370680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950473093 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.3950473093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.597877499
Short name T740
Test name
Test status
Simulation time 2296329104 ps
CPU time 24.51 seconds
Started Aug 27 08:56:51 AM UTC 24
Finished Aug 27 08:57:17 AM UTC 24
Peak memory 213924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597877499 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.597877499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3338185652
Short name T801
Test name
Test status
Simulation time 46319479400 ps
CPU time 297.5 seconds
Started Aug 27 08:56:51 AM UTC 24
Finished Aug 27 09:01:53 AM UTC 24
Peak memory 213852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338185652 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_acc
ess_b2b.3338185652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1286059187
Short name T744
Test name
Test status
Simulation time 82083433 ps
CPU time 1.01 seconds
Started Aug 27 08:57:20 AM UTC 24
Finished Aug 27 08:57:22 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286059187 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1286059187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.886425919
Short name T831
Test name
Test status
Simulation time 19861659029 ps
CPU time 414.53 seconds
Started Aug 27 08:57:20 AM UTC 24
Finished Aug 27 09:04:20 AM UTC 24
Peak memory 385268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886425919 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.886425919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.1019482697
Short name T747
Test name
Test status
Simulation time 2679376155 ps
CPU time 106.07 seconds
Started Aug 27 08:55:42 AM UTC 24
Finished Aug 27 08:57:31 AM UTC 24
Peak memory 380804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019482697 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1019482697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3680781186
Short name T933
Test name
Test status
Simulation time 293480102680 ps
CPU time 3162.06 seconds
Started Aug 27 08:57:32 AM UTC 24
Finished Aug 27 09:50:45 AM UTC 24
Peak memory 388984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368078118
6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.3680781186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1279915290
Short name T759
Test name
Test status
Simulation time 6313075516 ps
CPU time 86.58 seconds
Started Aug 27 08:57:29 AM UTC 24
Finished Aug 27 08:58:58 AM UTC 24
Peak memory 339876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279915290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.1279915290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1816233992
Short name T764
Test name
Test status
Simulation time 2356536779 ps
CPU time 180.13 seconds
Started Aug 27 08:56:07 AM UTC 24
Finished Aug 27 08:59:10 AM UTC 24
Peak memory 213988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816233992 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.1816233992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3676867834
Short name T761
Test name
Test status
Simulation time 1625855093 ps
CPU time 120.49 seconds
Started Aug 27 08:57:01 AM UTC 24
Finished Aug 27 08:59:04 AM UTC 24
Peak memory 380704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3676867834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t
hroughput_w_partial_write.3676867834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2670984504
Short name T894
Test name
Test status
Simulation time 13215085819 ps
CPU time 841.04 seconds
Started Aug 27 08:58:54 AM UTC 24
Finished Aug 27 09:13:05 AM UTC 24
Peak memory 384868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670984504 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_during
_key_req.2670984504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2097657285
Short name T767
Test name
Test status
Simulation time 38518294 ps
CPU time 0.92 seconds
Started Aug 27 08:59:11 AM UTC 24
Finished Aug 27 08:59:13 AM UTC 24
Peak memory 212616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097657285 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2097657285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.2609213890
Short name T762
Test name
Test status
Simulation time 4770040708 ps
CPU time 87.26 seconds
Started Aug 27 08:57:36 AM UTC 24
Finished Aug 27 08:59:05 AM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609213890 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.2609213890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.1667129042
Short name T869
Test name
Test status
Simulation time 6309092249 ps
CPU time 578.8 seconds
Started Aug 27 08:58:54 AM UTC 24
Finished Aug 27 09:08:40 AM UTC 24
Peak memory 387012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667129042 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.1667129042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.2549987873
Short name T760
Test name
Test status
Simulation time 1838367831 ps
CPU time 8.69 seconds
Started Aug 27 08:58:53 AM UTC 24
Finished Aug 27 08:59:03 AM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549987873 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.2549987873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1413351433
Short name T772
Test name
Test status
Simulation time 169941233 ps
CPU time 75.72 seconds
Started Aug 27 08:58:12 AM UTC 24
Finished Aug 27 08:59:30 AM UTC 24
Peak memory 376688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
413351433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ma
x_throughput.1413351433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3776819359
Short name T766
Test name
Test status
Simulation time 220008656 ps
CPU time 3.91 seconds
Started Aug 27 08:59:07 AM UTC 24
Finished Aug 27 08:59:12 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776819359 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.3776819359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.1799329621
Short name T768
Test name
Test status
Simulation time 4628372763 ps
CPU time 11.43 seconds
Started Aug 27 08:59:05 AM UTC 24
Finished Aug 27 08:59:18 AM UTC 24
Peak memory 224276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799329621 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.1799329621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2545928337
Short name T905
Test name
Test status
Simulation time 42329931600 ps
CPU time 1113.26 seconds
Started Aug 27 08:57:35 AM UTC 24
Finished Aug 27 09:16:21 AM UTC 24
Peak memory 384936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545928337 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.2545928337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2935425833
Short name T773
Test name
Test status
Simulation time 771699289 ps
CPU time 103.25 seconds
Started Aug 27 08:57:51 AM UTC 24
Finished Aug 27 08:59:36 AM UTC 24
Peak memory 380736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935425833 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.2935425833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1688644381
Short name T817
Test name
Test status
Simulation time 14545284418 ps
CPU time 336.59 seconds
Started Aug 27 08:57:53 AM UTC 24
Finished Aug 27 09:03:34 AM UTC 24
Peak memory 213980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688644381 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_acc
ess_b2b.1688644381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.4092744894
Short name T763
Test name
Test status
Simulation time 52493672 ps
CPU time 1.22 seconds
Started Aug 27 08:59:03 AM UTC 24
Finished Aug 27 08:59:05 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092744894 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.4092744894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.1783903881
Short name T899
Test name
Test status
Simulation time 5529527767 ps
CPU time 922.46 seconds
Started Aug 27 08:58:59 AM UTC 24
Finished Aug 27 09:14:32 AM UTC 24
Peak memory 386928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783903881 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1783903881
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.3779770981
Short name T770
Test name
Test status
Simulation time 1501448401 ps
CPU time 108.12 seconds
Started Aug 27 08:57:33 AM UTC 24
Finished Aug 27 08:59:23 AM UTC 24
Peak memory 378740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779770981 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3779770981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1867805345
Short name T927
Test name
Test status
Simulation time 9133355410 ps
CPU time 1847.21 seconds
Started Aug 27 08:59:11 AM UTC 24
Finished Aug 27 09:30:17 AM UTC 24
Peak memory 388780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186780534
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.1867805345
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3536988070
Short name T813
Test name
Test status
Simulation time 13416702545 ps
CPU time 321.6 seconds
Started Aug 27 08:57:43 AM UTC 24
Finished Aug 27 09:03:09 AM UTC 24
Peak memory 213956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536988070 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.3536988070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2142753058
Short name T758
Test name
Test status
Simulation time 507212807 ps
CPU time 35.59 seconds
Started Aug 27 08:58:17 AM UTC 24
Finished Aug 27 08:58:53 AM UTC 24
Peak memory 305000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2142753058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_t
hroughput_w_partial_write.2142753058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2757984075
Short name T912
Test name
Test status
Simulation time 12701386720 ps
CPU time 1164.17 seconds
Started Aug 27 08:59:55 AM UTC 24
Finished Aug 27 09:19:32 AM UTC 24
Peak memory 384944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757984075 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_during
_key_req.2757984075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.202864325
Short name T784
Test name
Test status
Simulation time 108391614 ps
CPU time 1.02 seconds
Started Aug 27 09:00:54 AM UTC 24
Finished Aug 27 09:00:56 AM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202864325 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.202864325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1392544884
Short name T790
Test name
Test status
Simulation time 7402762737 ps
CPU time 106.73 seconds
Started Aug 27 08:59:19 AM UTC 24
Finished Aug 27 09:01:08 AM UTC 24
Peak memory 213944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392544884 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.1392544884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.1006225018
Short name T898
Test name
Test status
Simulation time 39400668973 ps
CPU time 841.42 seconds
Started Aug 27 09:00:14 AM UTC 24
Finished Aug 27 09:14:25 AM UTC 24
Peak memory 386920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006225018 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.1006225018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3954133867
Short name T775
Test name
Test status
Simulation time 183787884 ps
CPU time 4.56 seconds
Started Aug 27 08:59:49 AM UTC 24
Finished Aug 27 08:59:54 AM UTC 24
Peak memory 213724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954133867 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.3954133867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1198571455
Short name T788
Test name
Test status
Simulation time 144983545 ps
CPU time 93.14 seconds
Started Aug 27 08:59:31 AM UTC 24
Finished Aug 27 09:01:06 AM UTC 24
Peak memory 380784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
198571455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ma
x_throughput.1198571455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.906547355
Short name T782
Test name
Test status
Simulation time 308434837 ps
CPU time 6.71 seconds
Started Aug 27 09:00:45 AM UTC 24
Finished Aug 27 09:00:53 AM UTC 24
Peak memory 224092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906547355 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.906547355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3357389744
Short name T781
Test name
Test status
Simulation time 5474034177 ps
CPU time 14.66 seconds
Started Aug 27 09:00:34 AM UTC 24
Finished Aug 27 09:00:50 AM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357389744 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.3357389744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2197948815
Short name T842
Test name
Test status
Simulation time 2533989048 ps
CPU time 367.35 seconds
Started Aug 27 08:59:14 AM UTC 24
Finished Aug 27 09:05:26 AM UTC 24
Peak memory 378728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197948815 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.2197948815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1264164056
Short name T786
Test name
Test status
Simulation time 2992380288 ps
CPU time 94.37 seconds
Started Aug 27 08:59:24 AM UTC 24
Finished Aug 27 09:01:01 AM UTC 24
Peak memory 376708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264164056 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.1264164056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.1205488880
Short name T822
Test name
Test status
Simulation time 6807740043 ps
CPU time 263.78 seconds
Started Aug 27 08:59:25 AM UTC 24
Finished Aug 27 09:03:52 AM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205488880 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acc
ess_b2b.1205488880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3711230298
Short name T779
Test name
Test status
Simulation time 33826989 ps
CPU time 1.08 seconds
Started Aug 27 09:00:30 AM UTC 24
Finished Aug 27 09:00:32 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711230298 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3711230298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.3079126085
Short name T887
Test name
Test status
Simulation time 28559971151 ps
CPU time 682.64 seconds
Started Aug 27 09:00:23 AM UTC 24
Finished Aug 27 09:11:53 AM UTC 24
Peak memory 385208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079126085 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3079126085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.21666094
Short name T769
Test name
Test status
Simulation time 49716733 ps
CPU time 5.93 seconds
Started Aug 27 08:59:13 AM UTC 24
Finished Aug 27 08:59:20 AM UTC 24
Peak memory 227116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21666094 -assert nopostproc +UVM_TESTN
AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.21666094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3407464111
Short name T932
Test name
Test status
Simulation time 46371351845 ps
CPU time 2659.62 seconds
Started Aug 27 09:00:54 AM UTC 24
Finished Aug 27 09:45:39 AM UTC 24
Peak memory 396928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340746411
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all.3407464111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2689920864
Short name T841
Test name
Test status
Simulation time 1842538539 ps
CPU time 257.32 seconds
Started Aug 27 09:00:51 AM UTC 24
Finished Aug 27 09:05:12 AM UTC 24
Peak memory 397160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689920864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2689920864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.758980758
Short name T825
Test name
Test status
Simulation time 2365295461 ps
CPU time 282.87 seconds
Started Aug 27 08:59:21 AM UTC 24
Finished Aug 27 09:04:09 AM UTC 24
Peak memory 213956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758980758 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.758980758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3189882751
Short name T778
Test name
Test status
Simulation time 233667410 ps
CPU time 50.01 seconds
Started Aug 27 08:59:38 AM UTC 24
Finished Aug 27 09:00:29 AM UTC 24
Peak memory 335648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3189882751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_t
hroughput_w_partial_write.3189882751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.462243639
Short name T885
Test name
Test status
Simulation time 10037243546 ps
CPU time 585.32 seconds
Started Aug 27 09:01:25 AM UTC 24
Finished Aug 27 09:11:17 AM UTC 24
Peak memory 384872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462243639 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_during_
key_req.462243639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.635272697
Short name T803
Test name
Test status
Simulation time 16774007 ps
CPU time 0.85 seconds
Started Aug 27 09:01:53 AM UTC 24
Finished Aug 27 09:01:55 AM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635272697 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.635272697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2423099026
Short name T809
Test name
Test status
Simulation time 17661744232 ps
CPU time 95.34 seconds
Started Aug 27 09:01:01 AM UTC 24
Finished Aug 27 09:02:39 AM UTC 24
Peak memory 213864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423099026 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.2423099026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.384609870
Short name T872
Test name
Test status
Simulation time 1132102984 ps
CPU time 428.49 seconds
Started Aug 27 09:01:31 AM UTC 24
Finished Aug 27 09:08:45 AM UTC 24
Peak memory 384816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384609870 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.384609870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2745747252
Short name T795
Test name
Test status
Simulation time 709985172 ps
CPU time 7.71 seconds
Started Aug 27 09:01:23 AM UTC 24
Finished Aug 27 09:01:32 AM UTC 24
Peak memory 213796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745747252 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.2745747252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3648972914
Short name T797
Test name
Test status
Simulation time 91989165 ps
CPU time 29.45 seconds
Started Aug 27 09:01:09 AM UTC 24
Finished Aug 27 09:01:39 AM UTC 24
Peak memory 298864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
648972914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ma
x_throughput.3648972914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.4006288645
Short name T800
Test name
Test status
Simulation time 60921167 ps
CPU time 2.91 seconds
Started Aug 27 09:01:41 AM UTC 24
Finished Aug 27 09:01:45 AM UTC 24
Peak memory 223968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006288645 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.4006288645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1341357702
Short name T802
Test name
Test status
Simulation time 344362382 ps
CPU time 11.64 seconds
Started Aug 27 09:01:41 AM UTC 24
Finished Aug 27 09:01:54 AM UTC 24
Peak memory 224080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341357702 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.1341357702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.4204380758
Short name T823
Test name
Test status
Simulation time 4367914043 ps
CPU time 178.15 seconds
Started Aug 27 09:00:58 AM UTC 24
Finished Aug 27 09:03:59 AM UTC 24
Peak memory 333676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204380758 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.4204380758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.734999444
Short name T793
Test name
Test status
Simulation time 3556649038 ps
CPU time 16.11 seconds
Started Aug 27 09:01:07 AM UTC 24
Finished Aug 27 09:01:24 AM UTC 24
Peak memory 213900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734999444 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.734999444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.480063912
Short name T884
Test name
Test status
Simulation time 46998541561 ps
CPU time 600.54 seconds
Started Aug 27 09:01:08 AM UTC 24
Finished Aug 27 09:11:15 AM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480063912 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acce
ss_b2b.480063912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1686945893
Short name T798
Test name
Test status
Simulation time 79339880 ps
CPU time 1.08 seconds
Started Aug 27 09:01:38 AM UTC 24
Finished Aug 27 09:01:40 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686945893 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1686945893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.708303344
Short name T915
Test name
Test status
Simulation time 27529994606 ps
CPU time 1142.34 seconds
Started Aug 27 09:01:33 AM UTC 24
Finished Aug 27 09:20:47 AM UTC 24
Peak memory 384948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708303344 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.708303344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.900858351
Short name T791
Test name
Test status
Simulation time 560216508 ps
CPU time 10.26 seconds
Started Aug 27 09:00:57 AM UTC 24
Finished Aug 27 09:01:09 AM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900858351 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.900858351
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2988311375
Short name T917
Test name
Test status
Simulation time 61599248568 ps
CPU time 1217.68 seconds
Started Aug 27 09:01:46 AM UTC 24
Finished Aug 27 09:22:17 AM UTC 24
Peak memory 387000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298831137
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.2988311375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2436491844
Short name T810
Test name
Test status
Simulation time 335391632 ps
CPU time 61.27 seconds
Started Aug 27 09:01:44 AM UTC 24
Finished Aug 27 09:02:47 AM UTC 24
Peak memory 319332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436491844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.2436491844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1734574015
Short name T850
Test name
Test status
Simulation time 2513633684 ps
CPU time 302.27 seconds
Started Aug 27 09:01:07 AM UTC 24
Finished Aug 27 09:06:13 AM UTC 24
Peak memory 213896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734574015 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.1734574015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.1855796283
Short name T796
Test name
Test status
Simulation time 219207099 ps
CPU time 25.3 seconds
Started Aug 27 09:01:10 AM UTC 24
Finished Aug 27 09:01:37 AM UTC 24
Peak memory 317220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1855796283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_t
hroughput_w_partial_write.1855796283
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.388089930
Short name T910
Test name
Test status
Simulation time 49143959171 ps
CPU time 971.13 seconds
Started Aug 27 09:02:58 AM UTC 24
Finished Aug 27 09:19:19 AM UTC 24
Peak memory 386896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388089930 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_during_
key_req.388089930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1973965032
Short name T821
Test name
Test status
Simulation time 32661140 ps
CPU time 0.91 seconds
Started Aug 27 09:03:47 AM UTC 24
Finished Aug 27 09:03:49 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973965032 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1973965032
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.3051134969
Short name T816
Test name
Test status
Simulation time 3133704036 ps
CPU time 87.12 seconds
Started Aug 27 09:02:05 AM UTC 24
Finished Aug 27 09:03:34 AM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051134969 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.3051134969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.3261230790
Short name T923
Test name
Test status
Simulation time 16711318170 ps
CPU time 1395.95 seconds
Started Aug 27 09:03:10 AM UTC 24
Finished Aug 27 09:26:41 AM UTC 24
Peak memory 384888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261230790 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.3261230790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1993037591
Short name T811
Test name
Test status
Simulation time 533175408 ps
CPU time 7.95 seconds
Started Aug 27 09:02:47 AM UTC 24
Finished Aug 27 09:02:56 AM UTC 24
Peak memory 214076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993037591 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.1993037591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3931862321
Short name T827
Test name
Test status
Simulation time 135691811 ps
CPU time 98.3 seconds
Started Aug 27 09:02:33 AM UTC 24
Finished Aug 27 09:04:14 AM UTC 24
Peak memory 374640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
931862321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ma
x_throughput.3931862321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3417975471
Short name T818
Test name
Test status
Simulation time 119406687 ps
CPU time 6.31 seconds
Started Aug 27 09:03:35 AM UTC 24
Finished Aug 27 09:03:43 AM UTC 24
Peak memory 223956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417975471 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.3417975471
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.1367632862
Short name T820
Test name
Test status
Simulation time 711982378 ps
CPU time 13.22 seconds
Started Aug 27 09:03:34 AM UTC 24
Finished Aug 27 09:03:48 AM UTC 24
Peak memory 224336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367632862 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.1367632862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3538186271
Short name T891
Test name
Test status
Simulation time 12938895455 ps
CPU time 642.69 seconds
Started Aug 27 09:01:56 AM UTC 24
Finished Aug 27 09:12:45 AM UTC 24
Peak memory 382768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538186271 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.3538186271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3567217226
Short name T808
Test name
Test status
Simulation time 217863002 ps
CPU time 21.17 seconds
Started Aug 27 09:02:10 AM UTC 24
Finished Aug 27 09:02:33 AM UTC 24
Peak memory 282488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567217226 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.3567217226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.885449822
Short name T890
Test name
Test status
Simulation time 51319911130 ps
CPU time 618.31 seconds
Started Aug 27 09:02:15 AM UTC 24
Finished Aug 27 09:12:41 AM UTC 24
Peak memory 213928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885449822 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_acce
ss_b2b.885449822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.348129039
Short name T815
Test name
Test status
Simulation time 120896105 ps
CPU time 1.15 seconds
Started Aug 27 09:03:31 AM UTC 24
Finished Aug 27 09:03:33 AM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348129039 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.348129039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.200613439
Short name T806
Test name
Test status
Simulation time 1645602617 ps
CPU time 13.02 seconds
Started Aug 27 09:01:54 AM UTC 24
Finished Aug 27 09:02:09 AM UTC 24
Peak memory 213816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200613439 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.200613439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.2161772707
Short name T935
Test name
Test status
Simulation time 50967291107 ps
CPU time 3556.31 seconds
Started Aug 27 09:03:43 AM UTC 24
Finished Aug 27 10:03:35 AM UTC 24
Peak memory 397256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216177270
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.2161772707
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3676405797
Short name T828
Test name
Test status
Simulation time 1033421888 ps
CPU time 40.72 seconds
Started Aug 27 09:03:35 AM UTC 24
Finished Aug 27 09:04:17 AM UTC 24
Peak memory 288576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676405797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3676405797
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.571653263
Short name T856
Test name
Test status
Simulation time 12826296967 ps
CPU time 258.96 seconds
Started Aug 27 09:02:05 AM UTC 24
Finished Aug 27 09:06:27 AM UTC 24
Peak memory 214212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571653263 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.571653263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2266655653
Short name T812
Test name
Test status
Simulation time 94714192 ps
CPU time 27.97 seconds
Started Aug 27 09:02:39 AM UTC 24
Finished Aug 27 09:03:09 AM UTC 24
Peak memory 296812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2266655653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_t
hroughput_w_partial_write.2266655653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.1936251664
Short name T883
Test name
Test status
Simulation time 2006973133 ps
CPU time 401.24 seconds
Started Aug 27 09:04:20 AM UTC 24
Finished Aug 27 09:11:06 AM UTC 24
Peak memory 362504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936251664 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_during
_key_req.1936251664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3192821131
Short name T838
Test name
Test status
Simulation time 21455404 ps
CPU time 0.91 seconds
Started Aug 27 09:04:42 AM UTC 24
Finished Aug 27 09:04:43 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192821131 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3192821131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.4092272131
Short name T837
Test name
Test status
Simulation time 4819344405 ps
CPU time 46.39 seconds
Started Aug 27 09:03:53 AM UTC 24
Finished Aug 27 09:04:41 AM UTC 24
Peak memory 214248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092272131 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.4092272131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.2039873713
Short name T858
Test name
Test status
Simulation time 3041856767 ps
CPU time 133.4 seconds
Started Aug 27 09:04:21 AM UTC 24
Finished Aug 27 09:06:37 AM UTC 24
Peak memory 383172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039873713 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.2039873713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2301703485
Short name T833
Test name
Test status
Simulation time 4561965870 ps
CPU time 9.07 seconds
Started Aug 27 09:04:19 AM UTC 24
Finished Aug 27 09:04:29 AM UTC 24
Peak memory 224124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301703485 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.2301703485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2968101474
Short name T832
Test name
Test status
Simulation time 91437784 ps
CPU time 11.11 seconds
Started Aug 27 09:04:14 AM UTC 24
Finished Aug 27 09:04:27 AM UTC 24
Peak memory 253740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
968101474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ma
x_throughput.2968101474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3788715869
Short name T836
Test name
Test status
Simulation time 154537362 ps
CPU time 7.28 seconds
Started Aug 27 09:04:31 AM UTC 24
Finished Aug 27 09:04:40 AM UTC 24
Peak memory 224096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788715869 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.3788715869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.3550579726
Short name T835
Test name
Test status
Simulation time 1379264644 ps
CPU time 8.93 seconds
Started Aug 27 09:04:29 AM UTC 24
Finished Aug 27 09:04:39 AM UTC 24
Peak memory 224340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550579726 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.3550579726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1116126524
Short name T879
Test name
Test status
Simulation time 3417289475 ps
CPU time 392.68 seconds
Started Aug 27 09:03:51 AM UTC 24
Finished Aug 27 09:10:28 AM UTC 24
Peak memory 333668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116126524 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.1116126524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2093599834
Short name T826
Test name
Test status
Simulation time 102389728 ps
CPU time 6.93 seconds
Started Aug 27 09:04:05 AM UTC 24
Finished Aug 27 09:04:13 AM UTC 24
Peak memory 231188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093599834 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.2093599834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2255968349
Short name T886
Test name
Test status
Simulation time 83695000132 ps
CPU time 440.03 seconds
Started Aug 27 09:04:09 AM UTC 24
Finished Aug 27 09:11:35 AM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255968349 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_acc
ess_b2b.2255968349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1859956642
Short name T834
Test name
Test status
Simulation time 102132120 ps
CPU time 1.07 seconds
Started Aug 27 09:04:28 AM UTC 24
Finished Aug 27 09:04:30 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859956642 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1859956642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.572108841
Short name T901
Test name
Test status
Simulation time 12800529902 ps
CPU time 638.69 seconds
Started Aug 27 09:04:21 AM UTC 24
Finished Aug 27 09:15:07 AM UTC 24
Peak memory 386920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572108841 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.572108841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.2160446038
Short name T824
Test name
Test status
Simulation time 1665424113 ps
CPU time 13.58 seconds
Started Aug 27 09:03:50 AM UTC 24
Finished Aug 27 09:04:04 AM UTC 24
Peak memory 213884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160446038 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2160446038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.378404171
Short name T878
Test name
Test status
Simulation time 2335460954 ps
CPU time 293.47 seconds
Started Aug 27 09:04:40 AM UTC 24
Finished Aug 27 09:09:38 AM UTC 24
Peak memory 346044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378404171
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all.378404171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2818755943
Short name T844
Test name
Test status
Simulation time 9589991883 ps
CPU time 49.1 seconds
Started Aug 27 09:04:40 AM UTC 24
Finished Aug 27 09:05:31 AM UTC 24
Peak memory 231356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818755943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2818755943
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.4213060153
Short name T852
Test name
Test status
Simulation time 2300213553 ps
CPU time 134.64 seconds
Started Aug 27 09:04:00 AM UTC 24
Finished Aug 27 09:06:17 AM UTC 24
Peak memory 213892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213060153 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.4213060153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1054336663
Short name T829
Test name
Test status
Simulation time 168674529 ps
CPU time 3.03 seconds
Started Aug 27 09:04:14 AM UTC 24
Finished Aug 27 09:04:19 AM UTC 24
Peak memory 230632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1054336663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_t
hroughput_w_partial_write.1054336663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1725243661
Short name T904
Test name
Test status
Simulation time 2426812391 ps
CPU time 630.56 seconds
Started Aug 27 09:05:36 AM UTC 24
Finished Aug 27 09:16:14 AM UTC 24
Peak memory 385200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725243661 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_during
_key_req.1725243661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2541981746
Short name T855
Test name
Test status
Simulation time 35616993 ps
CPU time 0.9 seconds
Started Aug 27 09:06:25 AM UTC 24
Finished Aug 27 09:06:27 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541981746 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.2541981746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1666376205
Short name T843
Test name
Test status
Simulation time 1271639898 ps
CPU time 24.13 seconds
Started Aug 27 09:05:05 AM UTC 24
Finished Aug 27 09:05:30 AM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666376205 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.1666376205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.3763591024
Short name T922
Test name
Test status
Simulation time 2997091947 ps
CPU time 1215.81 seconds
Started Aug 27 09:05:49 AM UTC 24
Finished Aug 27 09:26:18 AM UTC 24
Peak memory 385284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763591024 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.3763591024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2860963818
Short name T847
Test name
Test status
Simulation time 3752568970 ps
CPU time 12.14 seconds
Started Aug 27 09:05:35 AM UTC 24
Finished Aug 27 09:05:48 AM UTC 24
Peak memory 213948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860963818 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.2860963818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.3806888569
Short name T846
Test name
Test status
Simulation time 122428070 ps
CPU time 2.18 seconds
Started Aug 27 09:05:32 AM UTC 24
Finished Aug 27 09:05:35 AM UTC 24
Peak memory 224120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
806888569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ma
x_throughput.3806888569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2464323980
Short name T854
Test name
Test status
Simulation time 208275292 ps
CPU time 6.95 seconds
Started Aug 27 09:06:15 AM UTC 24
Finished Aug 27 09:06:23 AM UTC 24
Peak memory 223984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464323980 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.2464323980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.645724244
Short name T857
Test name
Test status
Simulation time 565995222 ps
CPU time 16.46 seconds
Started Aug 27 09:06:14 AM UTC 24
Finished Aug 27 09:06:32 AM UTC 24
Peak memory 224156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645724244 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.645724244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3099864316
Short name T893
Test name
Test status
Simulation time 3408074434 ps
CPU time 487.3 seconds
Started Aug 27 09:04:50 AM UTC 24
Finished Aug 27 09:13:03 AM UTC 24
Peak memory 377008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099864316 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.3099864316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1818951277
Short name T845
Test name
Test status
Simulation time 1256104537 ps
CPU time 19.79 seconds
Started Aug 27 09:05:13 AM UTC 24
Finished Aug 27 09:05:34 AM UTC 24
Peak memory 213808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818951277 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.1818951277
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2750793452
Short name T880
Test name
Test status
Simulation time 11268817137 ps
CPU time 303.68 seconds
Started Aug 27 09:05:27 AM UTC 24
Finished Aug 27 09:10:35 AM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750793452 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_acc
ess_b2b.2750793452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2510722183
Short name T851
Test name
Test status
Simulation time 123527674 ps
CPU time 1.24 seconds
Started Aug 27 09:06:12 AM UTC 24
Finished Aug 27 09:06:15 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510722183 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2510722183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.3313226563
Short name T902
Test name
Test status
Simulation time 1671128010 ps
CPU time 545.3 seconds
Started Aug 27 09:06:03 AM UTC 24
Finished Aug 27 09:15:15 AM UTC 24
Peak memory 378680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313226563 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3313226563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.3853660423
Short name T839
Test name
Test status
Simulation time 151627291 ps
CPU time 3.55 seconds
Started Aug 27 09:04:45 AM UTC 24
Finished Aug 27 09:04:49 AM UTC 24
Peak memory 213788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853660423 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3853660423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.1457818582
Short name T897
Test name
Test status
Simulation time 8183634119 ps
CPU time 449.7 seconds
Started Aug 27 09:06:22 AM UTC 24
Finished Aug 27 09:13:57 AM UTC 24
Peak memory 395120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145781858
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all.1457818582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3377889013
Short name T865
Test name
Test status
Simulation time 5889388688 ps
CPU time 80.54 seconds
Started Aug 27 09:06:18 AM UTC 24
Finished Aug 27 09:07:40 AM UTC 24
Peak memory 342256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377889013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3377889013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2548900629
Short name T867
Test name
Test status
Simulation time 8439256730 ps
CPU time 199.11 seconds
Started Aug 27 09:05:06 AM UTC 24
Finished Aug 27 09:08:28 AM UTC 24
Peak memory 213900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548900629 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.2548900629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2557976802
Short name T849
Test name
Test status
Simulation time 1005237433 ps
CPU time 38.4 seconds
Started Aug 27 09:05:32 AM UTC 24
Finished Aug 27 09:06:12 AM UTC 24
Peak memory 325484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2557976802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_t
hroughput_w_partial_write.2557976802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1669274935
Short name T892
Test name
Test status
Simulation time 1556136213 ps
CPU time 321.74 seconds
Started Aug 27 09:07:34 AM UTC 24
Finished Aug 27 09:13:00 AM UTC 24
Peak memory 382832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669274935 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_during
_key_req.1669274935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.355587568
Short name T875
Test name
Test status
Simulation time 30076364 ps
CPU time 0.85 seconds
Started Aug 27 09:08:46 AM UTC 24
Finished Aug 27 09:08:48 AM UTC 24
Peak memory 212644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355587568 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.355587568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2795962523
Short name T864
Test name
Test status
Simulation time 5200041750 ps
CPU time 58.35 seconds
Started Aug 27 09:06:33 AM UTC 24
Finished Aug 27 09:07:33 AM UTC 24
Peak memory 214144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795962523 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.2795962523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.2221765496
Short name T896
Test name
Test status
Simulation time 7478553411 ps
CPU time 348.09 seconds
Started Aug 27 09:07:41 AM UTC 24
Finished Aug 27 09:13:34 AM UTC 24
Peak memory 374968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221765496 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.2221765496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.2410230320
Short name T866
Test name
Test status
Simulation time 630250552 ps
CPU time 14.35 seconds
Started Aug 27 09:07:32 AM UTC 24
Finished Aug 27 09:07:47 AM UTC 24
Peak memory 213820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410230320 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.2410230320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3911399517
Short name T862
Test name
Test status
Simulation time 374726968 ps
CPU time 3.85 seconds
Started Aug 27 09:07:22 AM UTC 24
Finished Aug 27 09:07:27 AM UTC 24
Peak memory 231600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
911399517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ma
x_throughput.3911399517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2147222112
Short name T873
Test name
Test status
Simulation time 100551751 ps
CPU time 4.05 seconds
Started Aug 27 09:08:41 AM UTC 24
Finished Aug 27 09:08:46 AM UTC 24
Peak memory 224088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147222112 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.2147222112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3544129253
Short name T870
Test name
Test status
Simulation time 220929244 ps
CPU time 6.52 seconds
Started Aug 27 09:08:33 AM UTC 24
Finished Aug 27 09:08:40 AM UTC 24
Peak memory 224004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544129253 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.3544129253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.335910410
Short name T900
Test name
Test status
Simulation time 14969405876 ps
CPU time 498.2 seconds
Started Aug 27 09:06:28 AM UTC 24
Finished Aug 27 09:14:52 AM UTC 24
Peak memory 377008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335910410 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.335910410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2843820986
Short name T861
Test name
Test status
Simulation time 279599271 ps
CPU time 20.08 seconds
Started Aug 27 09:06:59 AM UTC 24
Finished Aug 27 09:07:21 AM UTC 24
Peak memory 274616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843820986 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.2843820986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.335770168
Short name T906
Test name
Test status
Simulation time 69458687841 ps
CPU time 552.8 seconds
Started Aug 27 09:07:18 AM UTC 24
Finished Aug 27 09:16:38 AM UTC 24
Peak memory 213968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335770168 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_acce
ss_b2b.335770168
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.2634020719
Short name T868
Test name
Test status
Simulation time 28671475 ps
CPU time 0.94 seconds
Started Aug 27 09:08:30 AM UTC 24
Finished Aug 27 09:08:32 AM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634020719 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.2634020719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.1007555188
Short name T907
Test name
Test status
Simulation time 1548716707 ps
CPU time 584.27 seconds
Started Aug 27 09:07:48 AM UTC 24
Finished Aug 27 09:17:39 AM UTC 24
Peak memory 382768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007555188 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1007555188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.3320360249
Short name T859
Test name
Test status
Simulation time 414046600 ps
CPU time 29.26 seconds
Started Aug 27 09:06:28 AM UTC 24
Finished Aug 27 09:06:59 AM UTC 24
Peak memory 313428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320360249 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3320360249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.836537395
Short name T895
Test name
Test status
Simulation time 4139187330 ps
CPU time 267.32 seconds
Started Aug 27 09:08:43 AM UTC 24
Finished Aug 27 09:13:14 AM UTC 24
Peak memory 358328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836537395
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.836537395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1514643371
Short name T877
Test name
Test status
Simulation time 337346799 ps
CPU time 29.48 seconds
Started Aug 27 09:08:41 AM UTC 24
Finished Aug 27 09:09:12 AM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514643371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1514643371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.404382754
Short name T882
Test name
Test status
Simulation time 2263626151 ps
CPU time 255.54 seconds
Started Aug 27 09:06:37 AM UTC 24
Finished Aug 27 09:10:57 AM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404382754 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.404382754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3379542686
Short name T863
Test name
Test status
Simulation time 135525027 ps
CPU time 2.32 seconds
Started Aug 27 09:07:28 AM UTC 24
Finished Aug 27 09:07:31 AM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3379542686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_t
hroughput_w_partial_write.3379542686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2784666900
Short name T298
Test name
Test status
Simulation time 3250504392 ps
CPU time 1027.16 seconds
Started Aug 27 07:59:56 AM UTC 24
Finished Aug 27 08:17:14 AM UTC 24
Peak memory 384884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784666900 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_during_
key_req.2784666900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2248079497
Short name T164
Test name
Test status
Simulation time 11786534 ps
CPU time 0.97 seconds
Started Aug 27 08:00:11 AM UTC 24
Finished Aug 27 08:00:13 AM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248079497 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.2248079497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_bijection.2632093249
Short name T163
Test name
Test status
Simulation time 281994361 ps
CPU time 21.4 seconds
Started Aug 27 07:59:48 AM UTC 24
Finished Aug 27 08:00:10 AM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632093249 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.2632093249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.2700441231
Short name T306
Test name
Test status
Simulation time 62067414861 ps
CPU time 1044.22 seconds
Started Aug 27 07:59:56 AM UTC 24
Finished Aug 27 08:17:32 AM UTC 24
Peak memory 376744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700441231 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.2700441231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.931508104
Short name T156
Test name
Test status
Simulation time 3761868104 ps
CPU time 13.16 seconds
Started Aug 27 07:59:54 AM UTC 24
Finished Aug 27 08:00:08 AM UTC 24
Peak memory 213860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931508104 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.931508104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2691155178
Short name T161
Test name
Test status
Simulation time 232776393 ps
CPU time 7.95 seconds
Started Aug 27 07:59:52 AM UTC 24
Finished Aug 27 08:00:01 AM UTC 24
Peak memory 264036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
691155178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max
_throughput.2691155178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.621451527
Short name T87
Test name
Test status
Simulation time 134765225 ps
CPU time 6.81 seconds
Started Aug 27 08:00:06 AM UTC 24
Finished Aug 27 08:00:14 AM UTC 24
Peak memory 224036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621451527 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.621451527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2262199302
Short name T52
Test name
Test status
Simulation time 2941274199 ps
CPU time 14.59 seconds
Started Aug 27 08:00:02 AM UTC 24
Finished Aug 27 08:00:21 AM UTC 24
Peak memory 224112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262199302 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.2262199302
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.611702485
Short name T249
Test name
Test status
Simulation time 65873562311 ps
CPU time 751.52 seconds
Started Aug 27 07:59:47 AM UTC 24
Finished Aug 27 08:12:27 AM UTC 24
Peak memory 343984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611702485 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.611702485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1362747652
Short name T169
Test name
Test status
Simulation time 694396249 ps
CPU time 12.86 seconds
Started Aug 27 07:59:48 AM UTC 24
Finished Aug 27 08:00:02 AM UTC 24
Peak memory 213840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362747652 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.1362747652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.4057224850
Short name T245
Test name
Test status
Simulation time 53378240068 ps
CPU time 724.86 seconds
Started Aug 27 07:59:52 AM UTC 24
Finished Aug 27 08:12:05 AM UTC 24
Peak memory 214200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057224850 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acce
ss_b2b.4057224850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.339942216
Short name T166
Test name
Test status
Simulation time 75053609 ps
CPU time 1.11 seconds
Started Aug 27 08:00:02 AM UTC 24
Finished Aug 27 08:00:08 AM UTC 24
Peak memory 212540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339942216 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.339942216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_regwen.583188078
Short name T149
Test name
Test status
Simulation time 8906499019 ps
CPU time 437.57 seconds
Started Aug 27 07:59:56 AM UTC 24
Finished Aug 27 08:07:19 AM UTC 24
Peak memory 380784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583188078 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.583188078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_smoke.4256710266
Short name T167
Test name
Test status
Simulation time 163999220 ps
CPU time 9.16 seconds
Started Aug 27 07:59:43 AM UTC 24
Finished Aug 27 07:59:54 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256710266 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.4256710266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.116480096
Short name T634
Test name
Test status
Simulation time 38341439516 ps
CPU time 2718.92 seconds
Started Aug 27 08:00:11 AM UTC 24
Finished Aug 27 08:45:59 AM UTC 24
Peak memory 388716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116480096
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.116480096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.801027172
Short name T17
Test name
Test status
Simulation time 1047909458 ps
CPU time 109.65 seconds
Started Aug 27 08:00:08 AM UTC 24
Finished Aug 27 08:02:00 AM UTC 24
Peak memory 370864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801027172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.801027172
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3425328583
Short name T197
Test name
Test status
Simulation time 3015217144 ps
CPU time 321.02 seconds
Started Aug 27 07:59:48 AM UTC 24
Finished Aug 27 08:05:13 AM UTC 24
Peak memory 213836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425328583 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.3425328583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1488994398
Short name T158
Test name
Test status
Simulation time 1834648054 ps
CPU time 105.35 seconds
Started Aug 27 07:59:54 AM UTC 24
Finished Aug 27 08:01:41 AM UTC 24
Peak memory 380300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1488994398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_th
roughput_w_partial_write.1488994398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2719580482
Short name T288
Test name
Test status
Simulation time 3176824374 ps
CPU time 920.93 seconds
Started Aug 27 08:00:42 AM UTC 24
Finished Aug 27 08:16:13 AM UTC 24
Peak memory 384940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719580482 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during_
key_req.2719580482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3522841946
Short name T173
Test name
Test status
Simulation time 161850473 ps
CPU time 0.94 seconds
Started Aug 27 08:01:04 AM UTC 24
Finished Aug 27 08:01:07 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522841946 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3522841946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_bijection.1368122432
Short name T175
Test name
Test status
Simulation time 2508967967 ps
CPU time 71.84 seconds
Started Aug 27 08:00:15 AM UTC 24
Finished Aug 27 08:01:29 AM UTC 24
Peak memory 214184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368122432 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.1368122432
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_executable.369216642
Short name T148
Test name
Test status
Simulation time 13693018162 ps
CPU time 1104.61 seconds
Started Aug 27 08:00:47 AM UTC 24
Finished Aug 27 08:19:23 AM UTC 24
Peak memory 385264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369216642 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.369216642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.658341194
Short name T21
Test name
Test status
Simulation time 701918661 ps
CPU time 9.38 seconds
Started Aug 27 08:00:42 AM UTC 24
Finished Aug 27 08:00:52 AM UTC 24
Peak memory 224168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658341194 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.658341194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.27450782
Short name T174
Test name
Test status
Simulation time 192924556 ps
CPU time 32.34 seconds
Started Aug 27 08:00:35 AM UTC 24
Finished Aug 27 08:01:09 AM UTC 24
Peak memory 309108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
7450782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_max_t
hroughput.27450782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.933065141
Short name T88
Test name
Test status
Simulation time 362864902 ps
CPU time 3.09 seconds
Started Aug 27 08:00:58 AM UTC 24
Finished Aug 27 08:01:02 AM UTC 24
Peak memory 224104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933065141 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.933065141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.1590891015
Short name T44
Test name
Test status
Simulation time 1226055140 ps
CPU time 7.19 seconds
Started Aug 27 08:00:57 AM UTC 24
Finished Aug 27 08:01:05 AM UTC 24
Peak memory 224072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590891015 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.1590891015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2317318867
Short name T232
Test name
Test status
Simulation time 1905258726 ps
CPU time 622.03 seconds
Started Aug 27 08:00:15 AM UTC 24
Finished Aug 27 08:10:44 AM UTC 24
Peak memory 384876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317318867 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.2317318867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3275836433
Short name T172
Test name
Test status
Simulation time 1634194689 ps
CPU time 13.66 seconds
Started Aug 27 08:00:19 AM UTC 24
Finished Aug 27 08:00:34 AM UTC 24
Peak memory 214096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275836433 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.3275836433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3279006793
Short name T154
Test name
Test status
Simulation time 81353586074 ps
CPU time 492.24 seconds
Started Aug 27 08:00:23 AM UTC 24
Finished Aug 27 08:08:42 AM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279006793 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acce
ss_b2b.3279006793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1504928527
Short name T120
Test name
Test status
Simulation time 32380427 ps
CPU time 1.25 seconds
Started Aug 27 08:00:53 AM UTC 24
Finished Aug 27 08:00:55 AM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504928527 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1504928527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_regwen.3851898660
Short name T142
Test name
Test status
Simulation time 20119753264 ps
CPU time 1589.13 seconds
Started Aug 27 08:00:53 AM UTC 24
Finished Aug 27 08:27:39 AM UTC 24
Peak memory 384880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851898660 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3851898660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_smoke.1016202215
Short name T152
Test name
Test status
Simulation time 1288895949 ps
CPU time 51.26 seconds
Started Aug 27 08:00:15 AM UTC 24
Finished Aug 27 08:01:08 AM UTC 24
Peak memory 315316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016202215 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1016202215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3872075444
Short name T765
Test name
Test status
Simulation time 11262976264 ps
CPU time 3453.07 seconds
Started Aug 27 08:01:03 AM UTC 24
Finished Aug 27 08:59:10 AM UTC 24
Peak memory 388780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387207544
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.3872075444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1411476103
Short name T104
Test name
Test status
Simulation time 11676008620 ps
CPU time 183.54 seconds
Started Aug 27 08:00:17 AM UTC 24
Finished Aug 27 08:03:24 AM UTC 24
Peak memory 213844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411476103 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.1411476103
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.997593105
Short name T118
Test name
Test status
Simulation time 42842500 ps
CPU time 3 seconds
Started Aug 27 08:00:42 AM UTC 24
Finished Aug 27 08:00:46 AM UTC 24
Peak memory 224376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
997593105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_thr
oughput_w_partial_write.997593105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.156539083
Short name T358
Test name
Test status
Simulation time 17506575842 ps
CPU time 1213.16 seconds
Started Aug 27 08:02:01 AM UTC 24
Finished Aug 27 08:22:27 AM UTC 24
Peak memory 386916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156539083 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_during_k
ey_req.156539083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3367941818
Short name T181
Test name
Test status
Simulation time 21711938 ps
CPU time 0.99 seconds
Started Aug 27 08:02:40 AM UTC 24
Finished Aug 27 08:02:42 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367941818 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3367941818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_bijection.2681788946
Short name T160
Test name
Test status
Simulation time 7837519830 ps
CPU time 60.85 seconds
Started Aug 27 08:01:09 AM UTC 24
Finished Aug 27 08:02:11 AM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681788946 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.2681788946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_executable.409351548
Short name T146
Test name
Test status
Simulation time 10856591794 ps
CPU time 227.8 seconds
Started Aug 27 08:02:04 AM UTC 24
Finished Aug 27 08:05:56 AM UTC 24
Peak memory 372912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409351548 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.409351548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.579069727
Short name T178
Test name
Test status
Simulation time 830851611 ps
CPU time 7.49 seconds
Started Aug 27 08:01:58 AM UTC 24
Finished Aug 27 08:02:07 AM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579069727 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.579069727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.268880774
Short name T176
Test name
Test status
Simulation time 242327455 ps
CPU time 6.58 seconds
Started Aug 27 08:01:42 AM UTC 24
Finished Aug 27 08:01:50 AM UTC 24
Peak memory 237428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
68880774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_max_
throughput.268880774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2455996375
Short name T47
Test name
Test status
Simulation time 184951396 ps
CPU time 6.83 seconds
Started Aug 27 08:02:32 AM UTC 24
Finished Aug 27 08:02:40 AM UTC 24
Peak memory 224044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455996375 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.2455996375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3663284533
Short name T180
Test name
Test status
Simulation time 5517422979 ps
CPU time 14.51 seconds
Started Aug 27 08:02:16 AM UTC 24
Finished Aug 27 08:02:31 AM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663284533 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.3663284533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2233570159
Short name T194
Test name
Test status
Simulation time 382273962 ps
CPU time 225.46 seconds
Started Aug 27 08:01:07 AM UTC 24
Finished Aug 27 08:04:56 AM UTC 24
Peak memory 376684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233570159 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.2233570159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2579667576
Short name T177
Test name
Test status
Simulation time 2826852424 ps
CPU time 25.99 seconds
Started Aug 27 08:01:30 AM UTC 24
Finished Aug 27 08:01:57 AM UTC 24
Peak memory 213832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579667576 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.2579667576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2366763999
Short name T218
Test name
Test status
Simulation time 51344109634 ps
CPU time 382.28 seconds
Started Aug 27 08:01:35 AM UTC 24
Finished Aug 27 08:08:02 AM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366763999 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acce
ss_b2b.2366763999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3066057483
Short name T179
Test name
Test status
Simulation time 87809463 ps
CPU time 1.05 seconds
Started Aug 27 08:02:13 AM UTC 24
Finished Aug 27 08:02:15 AM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066057483 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3066057483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_regwen.841678306
Short name T135
Test name
Test status
Simulation time 6633080126 ps
CPU time 436.19 seconds
Started Aug 27 08:02:07 AM UTC 24
Finished Aug 27 08:09:29 AM UTC 24
Peak memory 381112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841678306 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.841678306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_smoke.260313054
Short name T157
Test name
Test status
Simulation time 431388702 ps
CPU time 55.72 seconds
Started Aug 27 08:01:06 AM UTC 24
Finished Aug 27 08:02:04 AM UTC 24
Peak memory 331900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260313054 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.260313054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2089446802
Short name T599
Test name
Test status
Simulation time 98656398888 ps
CPU time 2407.56 seconds
Started Aug 27 08:02:36 AM UTC 24
Finished Aug 27 08:43:08 AM UTC 24
Peak memory 395192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208944680
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.2089446802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1992597968
Short name T55
Test name
Test status
Simulation time 6529462884 ps
CPU time 100.36 seconds
Started Aug 27 08:02:34 AM UTC 24
Finished Aug 27 08:04:16 AM UTC 24
Peak memory 331764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992597968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1992597968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.690620945
Short name T216
Test name
Test status
Simulation time 3476803792 ps
CPU time 380.34 seconds
Started Aug 27 08:01:11 AM UTC 24
Finished Aug 27 08:07:36 AM UTC 24
Peak memory 214172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690620945 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.690620945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1435792748
Short name T183
Test name
Test status
Simulation time 150685507 ps
CPU time 97.06 seconds
Started Aug 27 08:01:50 AM UTC 24
Finished Aug 27 08:03:29 AM UTC 24
Peak memory 372588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1435792748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_th
roughput_w_partial_write.1435792748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3989035549
Short name T39
Test name
Test status
Simulation time 1884718996 ps
CPU time 491.4 seconds
Started Aug 27 08:03:59 AM UTC 24
Finished Aug 27 08:12:16 AM UTC 24
Peak memory 380776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989035549 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during_
key_req.3989035549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3826741536
Short name T190
Test name
Test status
Simulation time 95827516 ps
CPU time 1.05 seconds
Started Aug 27 08:04:21 AM UTC 24
Finished Aug 27 08:04:24 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826741536 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.3826741536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_bijection.2526478721
Short name T192
Test name
Test status
Simulation time 31780321053 ps
CPU time 88.66 seconds
Started Aug 27 08:03:13 AM UTC 24
Finished Aug 27 08:04:44 AM UTC 24
Peak memory 213864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526478721 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.2526478721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_executable.3533202075
Short name T337
Test name
Test status
Simulation time 13468957309 ps
CPU time 984.78 seconds
Started Aug 27 08:04:00 AM UTC 24
Finished Aug 27 08:20:35 AM UTC 24
Peak memory 385204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533202075 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.3533202075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1467573923
Short name T185
Test name
Test status
Simulation time 1237847180 ps
CPU time 5.98 seconds
Started Aug 27 08:03:51 AM UTC 24
Finished Aug 27 08:03:58 AM UTC 24
Peak memory 213916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467573923 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.1467573923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3811226766
Short name T188
Test name
Test status
Simulation time 431549532 ps
CPU time 37.64 seconds
Started Aug 27 08:03:41 AM UTC 24
Finished Aug 27 08:04:20 AM UTC 24
Peak memory 315188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
811226766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max
_throughput.3811226766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1550633364
Short name T56
Test name
Test status
Simulation time 98184695 ps
CPU time 6.65 seconds
Started Aug 27 08:04:17 AM UTC 24
Finished Aug 27 08:04:25 AM UTC 24
Peak memory 224128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550633364 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.1550633364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3261831976
Short name T189
Test name
Test status
Simulation time 343680285 ps
CPU time 8.47 seconds
Started Aug 27 08:04:11 AM UTC 24
Finished Aug 27 08:04:21 AM UTC 24
Peak memory 224116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261831976 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.3261831976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.105337412
Short name T336
Test name
Test status
Simulation time 2681349446 ps
CPU time 1047.17 seconds
Started Aug 27 08:02:48 AM UTC 24
Finished Aug 27 08:20:26 AM UTC 24
Peak memory 382900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105337412 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.105337412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access.1468327607
Short name T184
Test name
Test status
Simulation time 1665550258 ps
CPU time 14.27 seconds
Started Aug 27 08:03:24 AM UTC 24
Finished Aug 27 08:03:40 AM UTC 24
Peak memory 213748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468327607 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.1468327607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.422131388
Short name T253
Test name
Test status
Simulation time 17811132019 ps
CPU time 538.29 seconds
Started Aug 27 08:03:30 AM UTC 24
Finished Aug 27 08:12:36 AM UTC 24
Peak memory 213912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422131388 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_acces
s_b2b.422131388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3659801000
Short name T187
Test name
Test status
Simulation time 47204943 ps
CPU time 1.12 seconds
Started Aug 27 08:04:08 AM UTC 24
Finished Aug 27 08:04:10 AM UTC 24
Peak memory 212532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659801000 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3659801000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_regwen.2094927274
Short name T140
Test name
Test status
Simulation time 141344308701 ps
CPU time 626.76 seconds
Started Aug 27 08:04:06 AM UTC 24
Finished Aug 27 08:14:40 AM UTC 24
Peak memory 378808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094927274 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2094927274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_smoke.3364145241
Short name T182
Test name
Test status
Simulation time 207784839 ps
CPU time 2.64 seconds
Started Aug 27 08:02:43 AM UTC 24
Finished Aug 27 08:02:47 AM UTC 24
Peak memory 214144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364145241 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3364145241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all.3743891864
Short name T477
Test name
Test status
Simulation time 30632838508 ps
CPU time 1691.34 seconds
Started Aug 27 08:04:20 AM UTC 24
Finished Aug 27 08:32:49 AM UTC 24
Peak memory 378728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374389186
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.3743891864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3933588351
Short name T69
Test name
Test status
Simulation time 6193292874 ps
CPU time 98.04 seconds
Started Aug 27 08:04:19 AM UTC 24
Finished Aug 27 08:05:59 AM UTC 24
Peak memory 374640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933588351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3933588351
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.192484308
Short name T200
Test name
Test status
Simulation time 1710429512 ps
CPU time 154.72 seconds
Started Aug 27 08:03:18 AM UTC 24
Finished Aug 27 08:05:55 AM UTC 24
Peak memory 213876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192484308 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.192484308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3049122981
Short name T186
Test name
Test status
Simulation time 81528421 ps
CPU time 13.3 seconds
Started Aug 27 08:03:51 AM UTC 24
Finished Aug 27 08:04:05 AM UTC 24
Peak memory 263968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3049122981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_th
roughput_w_partial_write.3049122981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1386174278
Short name T270
Test name
Test status
Simulation time 3219690748 ps
CPU time 586.44 seconds
Started Aug 27 08:04:57 AM UTC 24
Finished Aug 27 08:14:51 AM UTC 24
Peak memory 360368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386174278 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_during_
key_req.1386174278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1733599664
Short name T202
Test name
Test status
Simulation time 11454921 ps
CPU time 1.01 seconds
Started Aug 27 08:05:58 AM UTC 24
Finished Aug 27 08:06:00 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733599664 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1733599664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_bijection.3784761531
Short name T198
Test name
Test status
Simulation time 4356354098 ps
CPU time 71.37 seconds
Started Aug 27 08:04:31 AM UTC 24
Finished Aug 27 08:05:44 AM UTC 24
Peak memory 213908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784761531 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.3784761531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_executable.2579832291
Short name T280
Test name
Test status
Simulation time 19526705610 ps
CPU time 628.35 seconds
Started Aug 27 08:05:09 AM UTC 24
Finished Aug 27 08:15:45 AM UTC 24
Peak memory 384888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579832291 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.2579832291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2540785213
Short name T196
Test name
Test status
Simulation time 806793388 ps
CPU time 9.88 seconds
Started Aug 27 08:04:57 AM UTC 24
Finished Aug 27 08:05:08 AM UTC 24
Peak memory 223260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540785213 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.2540785213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3856604692
Short name T193
Test name
Test status
Simulation time 187368742 ps
CPU time 5.13 seconds
Started Aug 27 08:04:45 AM UTC 24
Finished Aug 27 08:04:51 AM UTC 24
Peak memory 237284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
856604692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_max
_throughput.3856604692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3775416829
Short name T89
Test name
Test status
Simulation time 257922153 ps
CPU time 5.32 seconds
Started Aug 27 08:05:51 AM UTC 24
Finished Aug 27 08:05:57 AM UTC 24
Peak memory 224100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775416829 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.3775416829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1315676405
Short name T201
Test name
Test status
Simulation time 1332823057 ps
CPU time 7.95 seconds
Started Aug 27 08:05:48 AM UTC 24
Finished Aug 27 08:05:57 AM UTC 24
Peak memory 213792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315676405 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.1315676405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3904266682
Short name T303
Test name
Test status
Simulation time 2732024815 ps
CPU time 769.63 seconds
Started Aug 27 08:04:26 AM UTC 24
Finished Aug 27 08:17:25 AM UTC 24
Peak memory 382892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904266682 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.3904266682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1817021589
Short name T195
Test name
Test status
Simulation time 319450557 ps
CPU time 17.34 seconds
Started Aug 27 08:04:38 AM UTC 24
Finished Aug 27 08:04:56 AM UTC 24
Peak memory 214104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817021589 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.1817021589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.403937033
Short name T246
Test name
Test status
Simulation time 25984247660 ps
CPU time 442.82 seconds
Started Aug 27 08:04:39 AM UTC 24
Finished Aug 27 08:12:07 AM UTC 24
Peak memory 213848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumen
tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403937033 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acces
s_b2b.403937033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.610965476
Short name T199
Test name
Test status
Simulation time 47944032 ps
CPU time 1.05 seconds
Started Aug 27 08:05:45 AM UTC 24
Finished Aug 27 08:05:47 AM UTC 24
Peak memory 212528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610965476 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.610965476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2608274456
Short name T143
Test name
Test status
Simulation time 29713724594 ps
CPU time 774.36 seconds
Started Aug 27 08:05:13 AM UTC 24
Finished Aug 27 08:18:16 AM UTC 24
Peak memory 380776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608274456 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2608274456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_smoke.3860835979
Short name T204
Test name
Test status
Simulation time 2499764220 ps
CPU time 96.92 seconds
Started Aug 27 08:04:25 AM UTC 24
Finished Aug 27 08:06:04 AM UTC 24
Peak memory 356276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860835979 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3860835979
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.208067474
Short name T540
Test name
Test status
Simulation time 79487566256 ps
CPU time 1923.46 seconds
Started Aug 27 08:05:57 AM UTC 24
Finished Aug 27 08:38:21 AM UTC 24
Peak memory 386932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208067474
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.208067474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.685491928
Short name T70
Test name
Test status
Simulation time 550682449 ps
CPU time 11.87 seconds
Started Aug 27 08:05:56 AM UTC 24
Finished Aug 27 08:06:09 AM UTC 24
Peak memory 224440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685491928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.685491928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4044941713
Short name T231
Test name
Test status
Simulation time 3079552292 ps
CPU time 359.21 seconds
Started Aug 27 08:04:35 AM UTC 24
Finished Aug 27 08:10:39 AM UTC 24
Peak memory 213972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044941713 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.4044941713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2104771641
Short name T208
Test name
Test status
Simulation time 593998308 ps
CPU time 82.87 seconds
Started Aug 27 08:04:52 AM UTC 24
Finished Aug 27 08:06:17 AM UTC 24
Peak memory 370860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2104771641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_th
roughput_w_partial_write.2104771641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%