| T546 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2846979806 |
|
|
Aug 27 08:38:38 AM UTC 24 |
Aug 27 08:38:56 AM UTC 24 |
5414578835 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3416174407 |
|
|
Aug 27 08:37:26 AM UTC 24 |
Aug 27 08:38:56 AM UTC 24 |
130573956 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.546175976 |
|
|
Aug 27 08:36:57 AM UTC 24 |
Aug 27 08:39:06 AM UTC 24 |
2334362663 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_executable.1468652025 |
|
|
Aug 27 08:24:26 AM UTC 24 |
Aug 27 08:39:11 AM UTC 24 |
27605922716 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.539350078 |
|
|
Aug 27 08:33:53 AM UTC 24 |
Aug 27 08:39:11 AM UTC 24 |
18394908385 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2937294548 |
|
|
Aug 27 08:38:57 AM UTC 24 |
Aug 27 08:39:18 AM UTC 24 |
93369691 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.3823264396 |
|
|
Aug 27 08:39:07 AM UTC 24 |
Aug 27 08:39:20 AM UTC 24 |
1094400283 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3397271905 |
|
|
Aug 27 08:39:21 AM UTC 24 |
Aug 27 08:39:23 AM UTC 24 |
30784840 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.3158804871 |
|
|
Aug 27 08:28:22 AM UTC 24 |
Aug 27 08:39:25 AM UTC 24 |
26509606243 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1439549200 |
|
|
Aug 27 08:39:25 AM UTC 24 |
Aug 27 08:39:30 AM UTC 24 |
64097319 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.4204497273 |
|
|
Aug 27 08:39:24 AM UTC 24 |
Aug 27 08:39:34 AM UTC 24 |
840256000 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3919190465 |
|
|
Aug 27 08:17:05 AM UTC 24 |
Aug 27 08:39:50 AM UTC 24 |
22404023084 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2801327140 |
|
|
Aug 27 08:39:50 AM UTC 24 |
Aug 27 08:39:53 AM UTC 24 |
31747567 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.2685670059 |
|
|
Aug 27 08:34:22 AM UTC 24 |
Aug 27 08:39:55 AM UTC 24 |
8255839102 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_smoke.1005644638 |
|
|
Aug 27 08:39:54 AM UTC 24 |
Aug 27 08:39:59 AM UTC 24 |
157679886 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_bijection.1322406257 |
|
|
Aug 27 08:38:25 AM UTC 24 |
Aug 27 08:40:01 AM UTC 24 |
10403901615 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.3247741929 |
|
|
Aug 27 08:38:56 AM UTC 24 |
Aug 27 08:40:11 AM UTC 24 |
130753734 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1989016805 |
|
|
Aug 27 08:40:12 AM UTC 24 |
Aug 27 08:40:35 AM UTC 24 |
3469215929 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.886912218 |
|
|
Aug 27 08:40:36 AM UTC 24 |
Aug 27 08:40:45 AM UTC 24 |
61120843 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_executable.2783798197 |
|
|
Aug 27 08:31:50 AM UTC 24 |
Aug 27 08:40:56 AM UTC 24 |
2880786107 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1195774646 |
|
|
Aug 27 08:35:23 AM UTC 24 |
Aug 27 08:41:02 AM UTC 24 |
26575792131 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_executable.1634949126 |
|
|
Aug 27 08:37:44 AM UTC 24 |
Aug 27 08:41:03 AM UTC 24 |
2862796247 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_executable.399444210 |
|
|
Aug 27 08:36:09 AM UTC 24 |
Aug 27 08:41:03 AM UTC 24 |
1350466646 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_regwen.1293033192 |
|
|
Aug 27 08:33:22 AM UTC 24 |
Aug 27 08:41:07 AM UTC 24 |
4418673035 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_executable.2289958969 |
|
|
Aug 27 08:28:14 AM UTC 24 |
Aug 27 08:41:07 AM UTC 24 |
17182557196 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.357069462 |
|
|
Aug 27 08:40:56 AM UTC 24 |
Aug 27 08:41:07 AM UTC 24 |
828991338 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.3194629784 |
|
|
Aug 27 08:41:08 AM UTC 24 |
Aug 27 08:41:10 AM UTC 24 |
82583073 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.710417883 |
|
|
Aug 27 08:37:11 AM UTC 24 |
Aug 27 08:41:11 AM UTC 24 |
6274659128 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3741644517 |
|
|
Aug 27 08:41:08 AM UTC 24 |
Aug 27 08:41:14 AM UTC 24 |
102764972 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3306780045 |
|
|
Aug 27 08:41:08 AM UTC 24 |
Aug 27 08:41:15 AM UTC 24 |
76464255 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_alert_test.668701305 |
|
|
Aug 27 08:41:15 AM UTC 24 |
Aug 27 08:41:17 AM UTC 24 |
17201540 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_smoke.3186885671 |
|
|
Aug 27 08:41:16 AM UTC 24 |
Aug 27 08:41:19 AM UTC 24 |
36436937 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.2614124417 |
|
|
Aug 27 08:27:14 AM UTC 24 |
Aug 27 08:41:24 AM UTC 24 |
9718250473 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_bijection.1008589178 |
|
|
Aug 27 08:40:01 AM UTC 24 |
Aug 27 08:41:28 AM UTC 24 |
4448247424 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3140129281 |
|
|
Aug 27 08:41:28 AM UTC 24 |
Aug 27 08:41:37 AM UTC 24 |
390902342 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.1991485903 |
|
|
Aug 27 08:24:49 AM UTC 24 |
Aug 27 08:41:44 AM UTC 24 |
17709009913 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.3102836068 |
|
|
Aug 27 08:41:45 AM UTC 24 |
Aug 27 08:41:49 AM UTC 24 |
43456363 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2793091934 |
|
|
Aug 27 08:32:42 AM UTC 24 |
Aug 27 08:41:52 AM UTC 24 |
1382518693 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.352186678 |
|
|
Aug 27 08:41:50 AM UTC 24 |
Aug 27 08:41:59 AM UTC 24 |
1349088770 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_stress_all.293045538 |
|
|
Aug 27 08:06:56 AM UTC 24 |
Aug 27 08:42:09 AM UTC 24 |
43491113531 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1990177400 |
|
|
Aug 27 08:40:45 AM UTC 24 |
Aug 27 08:42:22 AM UTC 24 |
144212135 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3578037356 |
|
|
Aug 27 08:42:22 AM UTC 24 |
Aug 27 08:42:24 AM UTC 24 |
158866867 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3185969543 |
|
|
Aug 27 08:12:41 AM UTC 24 |
Aug 27 08:42:28 AM UTC 24 |
466137751228 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1145327843 |
|
|
Aug 27 08:42:25 AM UTC 24 |
Aug 27 08:42:33 AM UTC 24 |
173289272 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.889079299 |
|
|
Aug 27 08:32:50 AM UTC 24 |
Aug 27 08:42:36 AM UTC 24 |
74393175532 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1234536794 |
|
|
Aug 27 08:42:29 AM UTC 24 |
Aug 27 08:42:38 AM UTC 24 |
170036658 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_bijection.690328480 |
|
|
Aug 27 08:41:20 AM UTC 24 |
Aug 27 08:42:38 AM UTC 24 |
17021316473 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3580377256 |
|
|
Aug 27 08:42:39 AM UTC 24 |
Aug 27 08:42:41 AM UTC 24 |
19214752 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.2028947726 |
|
|
Aug 27 08:41:38 AM UTC 24 |
Aug 27 08:42:44 AM UTC 24 |
476354370 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3877693806 |
|
|
Aug 27 08:28:11 AM UTC 24 |
Aug 27 08:42:44 AM UTC 24 |
8180912888 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1699644001 |
|
|
Aug 27 08:38:38 AM UTC 24 |
Aug 27 08:42:50 AM UTC 24 |
11093295488 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3418069887 |
|
|
Aug 27 08:23:01 AM UTC 24 |
Aug 27 08:42:55 AM UTC 24 |
6768143447 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access.373108522 |
|
|
Aug 27 08:42:51 AM UTC 24 |
Aug 27 08:43:02 AM UTC 24 |
143199717 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_stress_all.2089446802 |
|
|
Aug 27 08:02:36 AM UTC 24 |
Aug 27 08:43:08 AM UTC 24 |
98656398888 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.2328208273 |
|
|
Aug 27 08:30:13 AM UTC 24 |
Aug 27 08:43:19 AM UTC 24 |
9498980097 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3926529646 |
|
|
Aug 27 08:40:28 AM UTC 24 |
Aug 27 08:43:26 AM UTC 24 |
8241485600 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1309974918 |
|
|
Aug 27 08:43:20 AM UTC 24 |
Aug 27 08:43:29 AM UTC 24 |
516807738 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_bijection.3677068091 |
|
|
Aug 27 08:42:45 AM UTC 24 |
Aug 27 08:43:39 AM UTC 24 |
2039736246 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_regwen.2419865637 |
|
|
Aug 27 08:41:04 AM UTC 24 |
Aug 27 08:43:48 AM UTC 24 |
2578935045 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2294264955 |
|
|
Aug 27 08:43:48 AM UTC 24 |
Aug 27 08:43:50 AM UTC 24 |
27662774 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3219756423 |
|
|
Aug 27 08:22:05 AM UTC 24 |
Aug 27 08:43:51 AM UTC 24 |
64900282935 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1812905875 |
|
|
Aug 27 07:59:32 AM UTC 24 |
Aug 27 08:43:54 AM UTC 24 |
71445550534 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2198624640 |
|
|
Aug 27 08:43:03 AM UTC 24 |
Aug 27 08:43:56 AM UTC 24 |
395376606 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.890988596 |
|
|
Aug 27 08:43:52 AM UTC 24 |
Aug 27 08:43:58 AM UTC 24 |
239583157 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_alert_test.1842196718 |
|
|
Aug 27 08:43:59 AM UTC 24 |
Aug 27 08:44:01 AM UTC 24 |
32564262 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.3860528145 |
|
|
Aug 27 08:42:00 AM UTC 24 |
Aug 27 08:44:02 AM UTC 24 |
13351962602 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2041219537 |
|
|
Aug 27 08:43:52 AM UTC 24 |
Aug 27 08:44:05 AM UTC 24 |
1429462117 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_smoke.120622333 |
|
|
Aug 27 08:42:39 AM UTC 24 |
Aug 27 08:44:09 AM UTC 24 |
2593323935 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.347777457 |
|
|
Aug 27 08:27:39 AM UTC 24 |
Aug 27 08:44:11 AM UTC 24 |
15767496066 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2178047007 |
|
|
Aug 27 08:43:10 AM UTC 24 |
Aug 27 08:44:12 AM UTC 24 |
155195308 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2183482950 |
|
|
Aug 27 08:42:34 AM UTC 24 |
Aug 27 08:44:12 AM UTC 24 |
2168130866 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2346214193 |
|
|
Aug 27 08:41:25 AM UTC 24 |
Aug 27 08:44:17 AM UTC 24 |
5810159946 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access.392240365 |
|
|
Aug 27 08:44:12 AM UTC 24 |
Aug 27 08:44:18 AM UTC 24 |
64776282 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.69895798 |
|
|
Aug 27 08:44:19 AM UTC 24 |
Aug 27 08:44:25 AM UTC 24 |
1160054770 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.3403154207 |
|
|
Aug 27 08:44:18 AM UTC 24 |
Aug 27 08:44:35 AM UTC 24 |
201309033 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1959620193 |
|
|
Aug 27 08:43:55 AM UTC 24 |
Aug 27 08:44:39 AM UTC 24 |
1807737056 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1847939190 |
|
|
Aug 27 08:41:18 AM UTC 24 |
Aug 27 08:44:40 AM UTC 24 |
4581553507 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_bijection.4035343278 |
|
|
Aug 27 08:44:06 AM UTC 24 |
Aug 27 08:44:42 AM UTC 24 |
1345767394 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2761175369 |
|
|
Aug 27 08:44:41 AM UTC 24 |
Aug 27 08:44:43 AM UTC 24 |
104854978 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1863870310 |
|
|
Aug 27 08:44:13 AM UTC 24 |
Aug 27 08:44:45 AM UTC 24 |
100170886 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.261777348 |
|
|
Aug 27 08:44:44 AM UTC 24 |
Aug 27 08:44:49 AM UTC 24 |
108108386 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.1791254904 |
|
|
Aug 27 08:44:43 AM UTC 24 |
Aug 27 08:44:51 AM UTC 24 |
140401096 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_alert_test.150024970 |
|
|
Aug 27 08:44:52 AM UTC 24 |
Aug 27 08:44:54 AM UTC 24 |
22711038 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1611581699 |
|
|
Aug 27 08:40:02 AM UTC 24 |
Aug 27 08:45:03 AM UTC 24 |
2640384284 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_smoke.327832968 |
|
|
Aug 27 08:44:55 AM UTC 24 |
Aug 27 08:45:16 AM UTC 24 |
96099377 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1139068469 |
|
|
Aug 27 08:33:42 AM UTC 24 |
Aug 27 08:45:31 AM UTC 24 |
12106996249 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_bijection.2157382951 |
|
|
Aug 27 08:45:18 AM UTC 24 |
Aug 27 08:45:46 AM UTC 24 |
2291143170 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_smoke.3777796314 |
|
|
Aug 27 08:44:02 AM UTC 24 |
Aug 27 08:45:52 AM UTC 24 |
655881766 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1090989717 |
|
|
Aug 27 08:34:42 AM UTC 24 |
Aug 27 08:45:56 AM UTC 24 |
3260199758 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.116480096 |
|
|
Aug 27 08:00:11 AM UTC 24 |
Aug 27 08:45:59 AM UTC 24 |
38341439516 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.3669557589 |
|
|
Aug 27 08:42:45 AM UTC 24 |
Aug 27 08:46:20 AM UTC 24 |
3407273610 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.2366725922 |
|
|
Aug 27 08:46:00 AM UTC 24 |
Aug 27 08:46:22 AM UTC 24 |
241231861 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2039974298 |
|
|
Aug 27 08:46:20 AM UTC 24 |
Aug 27 08:46:33 AM UTC 24 |
2642442334 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2040934267 |
|
|
Aug 27 08:28:37 AM UTC 24 |
Aug 27 08:46:56 AM UTC 24 |
12789015265 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.838349102 |
|
|
Aug 27 08:46:56 AM UTC 24 |
Aug 27 08:46:58 AM UTC 24 |
38217621 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3662537300 |
|
|
Aug 27 08:38:48 AM UTC 24 |
Aug 27 08:47:03 AM UTC 24 |
64380315868 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3376515528 |
|
|
Aug 27 08:46:59 AM UTC 24 |
Aug 27 08:47:07 AM UTC 24 |
146888613 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.3487896879 |
|
|
Aug 27 08:47:04 AM UTC 24 |
Aug 27 08:47:12 AM UTC 24 |
161817638 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3546774070 |
|
|
Aug 27 08:41:35 AM UTC 24 |
Aug 27 08:47:14 AM UTC 24 |
16940538177 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1735868021 |
|
|
Aug 27 08:47:14 AM UTC 24 |
Aug 27 08:47:16 AM UTC 24 |
40914052 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3182155850 |
|
|
Aug 27 08:42:57 AM UTC 24 |
Aug 27 08:47:20 AM UTC 24 |
15598414885 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_smoke.2273975241 |
|
|
Aug 27 08:47:18 AM UTC 24 |
Aug 27 08:47:34 AM UTC 24 |
702533637 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1455877129 |
|
|
Aug 27 08:45:57 AM UTC 24 |
Aug 27 08:47:36 AM UTC 24 |
512939259 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access.4018549799 |
|
|
Aug 27 08:45:47 AM UTC 24 |
Aug 27 08:47:37 AM UTC 24 |
659544102 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_executable.3583999942 |
|
|
Aug 27 08:33:21 AM UTC 24 |
Aug 27 08:47:45 AM UTC 24 |
16843971124 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access.644321598 |
|
|
Aug 27 08:47:38 AM UTC 24 |
Aug 27 08:47:49 AM UTC 24 |
191088977 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1271759613 |
|
|
Aug 27 08:47:07 AM UTC 24 |
Aug 27 08:48:18 AM UTC 24 |
5743083277 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4087718817 |
|
|
Aug 27 08:48:18 AM UTC 24 |
Aug 27 08:48:22 AM UTC 24 |
91251096 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.477715235 |
|
|
Aug 27 08:47:50 AM UTC 24 |
Aug 27 08:48:25 AM UTC 24 |
180717327 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3518492831 |
|
|
Aug 27 08:26:10 AM UTC 24 |
Aug 27 08:48:25 AM UTC 24 |
11024798976 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1934402814 |
|
|
Aug 27 08:48:24 AM UTC 24 |
Aug 27 08:48:32 AM UTC 24 |
3292497184 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_bijection.438646436 |
|
|
Aug 27 08:47:34 AM UTC 24 |
Aug 27 08:48:38 AM UTC 24 |
1458937497 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1462183015 |
|
|
Aug 27 08:48:39 AM UTC 24 |
Aug 27 08:48:41 AM UTC 24 |
31340208 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1563920477 |
|
|
Aug 27 08:48:42 AM UTC 24 |
Aug 27 08:48:49 AM UTC 24 |
92927592 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3330545622 |
|
|
Aug 27 08:45:32 AM UTC 24 |
Aug 27 08:48:58 AM UTC 24 |
1806990102 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2303100187 |
|
|
Aug 27 08:48:49 AM UTC 24 |
Aug 27 08:48:58 AM UTC 24 |
575583815 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_regwen.4124896732 |
|
|
Aug 27 08:48:33 AM UTC 24 |
Aug 27 08:49:00 AM UTC 24 |
1219340656 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1867479897 |
|
|
Aug 27 08:49:01 AM UTC 24 |
Aug 27 08:49:02 AM UTC 24 |
12072417 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.655565507 |
|
|
Aug 27 08:30:09 AM UTC 24 |
Aug 27 08:49:11 AM UTC 24 |
167577345809 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2540192832 |
|
|
Aug 27 08:31:48 AM UTC 24 |
Aug 27 08:49:30 AM UTC 24 |
4020965314 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.3851562134 |
|
|
Aug 27 08:48:26 AM UTC 24 |
Aug 27 08:49:44 AM UTC 24 |
1751540082 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.281021873 |
|
|
Aug 27 08:42:10 AM UTC 24 |
Aug 27 08:49:47 AM UTC 24 |
1756066203 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1353148559 |
|
|
Aug 27 08:38:23 AM UTC 24 |
Aug 27 08:49:51 AM UTC 24 |
9403856140 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_smoke.2637643685 |
|
|
Aug 27 08:49:04 AM UTC 24 |
Aug 27 08:49:55 AM UTC 24 |
306093251 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_regwen.22999619 |
|
|
Aug 27 08:31:51 AM UTC 24 |
Aug 27 08:49:58 AM UTC 24 |
28813617705 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access.57859267 |
|
|
Aug 27 08:49:47 AM UTC 24 |
Aug 27 08:49:58 AM UTC 24 |
151980517 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.793250445 |
|
|
Aug 27 08:49:59 AM UTC 24 |
Aug 27 08:50:02 AM UTC 24 |
47391362 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3289488727 |
|
|
Aug 27 08:47:13 AM UTC 24 |
Aug 27 08:50:02 AM UTC 24 |
13977654099 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.590061675 |
|
|
Aug 27 08:44:09 AM UTC 24 |
Aug 27 08:50:07 AM UTC 24 |
5819203726 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.621329505 |
|
|
Aug 27 08:49:59 AM UTC 24 |
Aug 27 08:50:07 AM UTC 24 |
1324806982 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.4220764928 |
|
|
Aug 27 08:50:08 AM UTC 24 |
Aug 27 08:50:10 AM UTC 24 |
165708591 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.339240376 |
|
|
Aug 27 08:33:19 AM UTC 24 |
Aug 27 08:50:14 AM UTC 24 |
15149779203 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.4262461573 |
|
|
Aug 27 08:50:14 AM UTC 24 |
Aug 27 08:50:22 AM UTC 24 |
699344080 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.275343552 |
|
|
Aug 27 08:50:11 AM UTC 24 |
Aug 27 08:50:23 AM UTC 24 |
1639856300 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1042311664 |
|
|
Aug 27 08:49:55 AM UTC 24 |
Aug 27 08:50:29 AM UTC 24 |
348063389 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_alert_test.3212378940 |
|
|
Aug 27 08:50:30 AM UTC 24 |
Aug 27 08:50:32 AM UTC 24 |
22013222 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.762309163 |
|
|
Aug 27 08:48:58 AM UTC 24 |
Aug 27 08:50:36 AM UTC 24 |
2244506398 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.3701663095 |
|
|
Aug 27 08:42:42 AM UTC 24 |
Aug 27 08:50:54 AM UTC 24 |
2686892000 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_smoke.1505597555 |
|
|
Aug 27 08:50:33 AM UTC 24 |
Aug 27 08:50:56 AM UTC 24 |
348155410 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3126887689 |
|
|
Aug 27 08:44:13 AM UTC 24 |
Aug 27 08:51:04 AM UTC 24 |
263557273111 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_bijection.949895938 |
|
|
Aug 27 08:50:55 AM UTC 24 |
Aug 27 08:51:20 AM UTC 24 |
1046734932 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_executable.2894891902 |
|
|
Aug 27 08:50:04 AM UTC 24 |
Aug 27 08:51:23 AM UTC 24 |
900634652 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access.655686915 |
|
|
Aug 27 08:51:04 AM UTC 24 |
Aug 27 08:51:28 AM UTC 24 |
4421720138 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.3460864646 |
|
|
Aug 27 08:46:39 AM UTC 24 |
Aug 27 08:51:31 AM UTC 24 |
3506844495 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.825806364 |
|
|
Aug 27 08:51:25 AM UTC 24 |
Aug 27 08:51:31 AM UTC 24 |
48622999 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_bijection.2057851796 |
|
|
Aug 27 08:49:30 AM UTC 24 |
Aug 27 08:51:31 AM UTC 24 |
13884770553 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1608345733 |
|
|
Aug 27 08:41:53 AM UTC 24 |
Aug 27 08:51:35 AM UTC 24 |
9518804363 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.4249440701 |
|
|
Aug 27 08:51:32 AM UTC 24 |
Aug 27 08:51:43 AM UTC 24 |
1774698157 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3676468691 |
|
|
Aug 27 08:51:44 AM UTC 24 |
Aug 27 08:51:46 AM UTC 24 |
34202536 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.528676897 |
|
|
Aug 27 08:51:47 AM UTC 24 |
Aug 27 08:52:04 AM UTC 24 |
1302812616 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2032615522 |
|
|
Aug 27 08:47:37 AM UTC 24 |
Aug 27 08:52:07 AM UTC 24 |
2181306659 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.1808713128 |
|
|
Aug 27 08:52:05 AM UTC 24 |
Aug 27 08:52:10 AM UTC 24 |
97535627 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.855476744 |
|
|
Aug 27 08:48:26 AM UTC 24 |
Aug 27 08:52:15 AM UTC 24 |
1896795481 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.454159070 |
|
|
Aug 27 08:37:43 AM UTC 24 |
Aug 27 08:52:16 AM UTC 24 |
47053065796 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_alert_test.751274540 |
|
|
Aug 27 08:52:16 AM UTC 24 |
Aug 27 08:52:18 AM UTC 24 |
39194940 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_smoke.1297645095 |
|
|
Aug 27 08:52:17 AM UTC 24 |
Aug 27 08:52:33 AM UTC 24 |
1194356796 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.237338657 |
|
|
Aug 27 07:59:33 AM UTC 24 |
Aug 27 08:52:37 AM UTC 24 |
223840536252 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.3821962661 |
|
|
Aug 27 08:50:08 AM UTC 24 |
Aug 27 08:52:49 AM UTC 24 |
1393167625 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access.991875587 |
|
|
Aug 27 08:52:50 AM UTC 24 |
Aug 27 08:52:53 AM UTC 24 |
74279976 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.2419013347 |
|
|
Aug 27 08:51:29 AM UTC 24 |
Aug 27 08:52:59 AM UTC 24 |
615300179 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.806799938 |
|
|
Aug 27 08:50:57 AM UTC 24 |
Aug 27 08:53:39 AM UTC 24 |
1403569773 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.453352233 |
|
|
Aug 27 08:43:27 AM UTC 24 |
Aug 27 08:53:49 AM UTC 24 |
3772098373 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.801638666 |
|
|
Aug 27 08:36:10 AM UTC 24 |
Aug 27 08:53:51 AM UTC 24 |
21909858528 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.3181290857 |
|
|
Aug 27 08:39:12 AM UTC 24 |
Aug 27 08:53:53 AM UTC 24 |
3080953805 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.4209294686 |
|
|
Aug 27 08:53:50 AM UTC 24 |
Aug 27 08:53:57 AM UTC 24 |
468980547 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.2351427413 |
|
|
Aug 27 08:53:40 AM UTC 24 |
Aug 27 08:53:58 AM UTC 24 |
838342294 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.1921029207 |
|
|
Aug 27 08:53:59 AM UTC 24 |
Aug 27 08:54:01 AM UTC 24 |
30378995 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.826997833 |
|
|
Aug 27 08:41:11 AM UTC 24 |
Aug 27 08:54:02 AM UTC 24 |
54284806093 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_bijection.3158163165 |
|
|
Aug 27 08:52:34 AM UTC 24 |
Aug 27 08:54:07 AM UTC 24 |
3099821898 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2421923407 |
|
|
Aug 27 08:54:02 AM UTC 24 |
Aug 27 08:54:09 AM UTC 24 |
96323043 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2293668267 |
|
|
Aug 27 08:50:23 AM UTC 24 |
Aug 27 08:54:10 AM UTC 24 |
8964415243 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1514775861 |
|
|
Aug 27 08:54:03 AM UTC 24 |
Aug 27 08:54:10 AM UTC 24 |
156138923 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_alert_test.42711780 |
|
|
Aug 27 08:54:11 AM UTC 24 |
Aug 27 08:54:13 AM UTC 24 |
24757889 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.410046423 |
|
|
Aug 27 08:53:00 AM UTC 24 |
Aug 27 08:54:39 AM UTC 24 |
139354983 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_regwen.1204113743 |
|
|
Aug 27 08:44:39 AM UTC 24 |
Aug 27 08:54:45 AM UTC 24 |
2332546765 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2961535248 |
|
|
Aug 27 08:49:45 AM UTC 24 |
Aug 27 08:54:51 AM UTC 24 |
3070764600 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.4119002476 |
|
|
Aug 27 08:47:46 AM UTC 24 |
Aug 27 08:54:58 AM UTC 24 |
52267180516 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.501533315 |
|
|
Aug 27 08:50:03 AM UTC 24 |
Aug 27 08:55:02 AM UTC 24 |
6759038275 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.4112710938 |
|
|
Aug 27 08:36:38 AM UTC 24 |
Aug 27 08:55:03 AM UTC 24 |
72894598884 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1398425233 |
|
|
Aug 27 08:54:52 AM UTC 24 |
Aug 27 08:55:08 AM UTC 24 |
600308978 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.253369230 |
|
|
Aug 27 08:52:08 AM UTC 24 |
Aug 27 08:55:11 AM UTC 24 |
4301990698 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_smoke.1177817468 |
|
|
Aug 27 08:54:11 AM UTC 24 |
Aug 27 08:55:16 AM UTC 24 |
3226523865 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2428766679 |
|
|
Aug 27 08:55:09 AM UTC 24 |
Aug 27 08:55:20 AM UTC 24 |
1899889960 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_bijection.303514969 |
|
|
Aug 27 08:54:41 AM UTC 24 |
Aug 27 08:55:20 AM UTC 24 |
2218841730 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1335982001 |
|
|
Aug 27 08:55:21 AM UTC 24 |
Aug 27 08:55:23 AM UTC 24 |
26672317 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_executable.540681602 |
|
|
Aug 27 08:39:12 AM UTC 24 |
Aug 27 08:55:23 AM UTC 24 |
3033839593 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2443643238 |
|
|
Aug 27 08:55:24 AM UTC 24 |
Aug 27 08:55:28 AM UTC 24 |
169973412 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2950477316 |
|
|
Aug 27 08:55:24 AM UTC 24 |
Aug 27 08:55:32 AM UTC 24 |
361079583 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3253193176 |
|
|
Aug 27 08:55:04 AM UTC 24 |
Aug 27 08:55:39 AM UTC 24 |
427388031 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3319829826 |
|
|
Aug 27 08:55:39 AM UTC 24 |
Aug 27 08:55:41 AM UTC 24 |
88446187 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3896122280 |
|
|
Aug 27 08:52:19 AM UTC 24 |
Aug 27 08:55:41 AM UTC 24 |
5030452874 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3926088737 |
|
|
Aug 27 08:47:21 AM UTC 24 |
Aug 27 08:55:56 AM UTC 24 |
7650159251 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_executable.1162721752 |
|
|
Aug 27 08:43:30 AM UTC 24 |
Aug 27 08:56:05 AM UTC 24 |
48317920291 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.913956715 |
|
|
Aug 27 08:55:29 AM UTC 24 |
Aug 27 08:56:50 AM UTC 24 |
6948459070 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1153773728 |
|
|
Aug 27 08:46:22 AM UTC 24 |
Aug 27 08:56:50 AM UTC 24 |
9415703282 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.3285518072 |
|
|
Aug 27 08:55:04 AM UTC 24 |
Aug 27 08:56:54 AM UTC 24 |
543047096 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2231727028 |
|
|
Aug 27 08:45:53 AM UTC 24 |
Aug 27 08:57:03 AM UTC 24 |
78069569464 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_bijection.1530853249 |
|
|
Aug 27 08:55:57 AM UTC 24 |
Aug 27 08:57:15 AM UTC 24 |
4242259131 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access.597877499 |
|
|
Aug 27 08:56:51 AM UTC 24 |
Aug 27 08:57:17 AM UTC 24 |
2296329104 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.4089135940 |
|
|
Aug 27 08:52:37 AM UTC 24 |
Aug 27 08:57:18 AM UTC 24 |
4302241309 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.54622475 |
|
|
Aug 27 08:24:45 AM UTC 24 |
Aug 27 08:57:19 AM UTC 24 |
127561515051 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1028663628 |
|
|
Aug 27 08:57:04 AM UTC 24 |
Aug 27 08:57:20 AM UTC 24 |
3151452962 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1286059187 |
|
|
Aug 27 08:57:20 AM UTC 24 |
Aug 27 08:57:22 AM UTC 24 |
82083433 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.27366923 |
|
|
Aug 27 08:57:21 AM UTC 24 |
Aug 27 08:57:29 AM UTC 24 |
407029149 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1505220582 |
|
|
Aug 27 08:56:55 AM UTC 24 |
Aug 27 08:57:30 AM UTC 24 |
349863697 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_smoke.1019482697 |
|
|
Aug 27 08:55:42 AM UTC 24 |
Aug 27 08:57:31 AM UTC 24 |
2679376155 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.680972264 |
|
|
Aug 27 08:57:23 AM UTC 24 |
Aug 27 08:57:32 AM UTC 24 |
310853574 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3624669812 |
|
|
Aug 27 08:57:32 AM UTC 24 |
Aug 27 08:57:34 AM UTC 24 |
15553065 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.538125651 |
|
|
Aug 27 08:45:03 AM UTC 24 |
Aug 27 08:57:35 AM UTC 24 |
16382561052 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.2918231298 |
|
|
Aug 27 08:44:26 AM UTC 24 |
Aug 27 08:57:42 AM UTC 24 |
3916846312 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.1676353507 |
|
|
Aug 27 08:41:03 AM UTC 24 |
Aug 27 08:57:51 AM UTC 24 |
13422666853 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.2319855953 |
|
|
Aug 27 08:49:51 AM UTC 24 |
Aug 27 08:57:53 AM UTC 24 |
78616130643 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2209692089 |
|
|
Aug 27 08:51:21 AM UTC 24 |
Aug 27 08:58:11 AM UTC 24 |
4696668236 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_regwen.451266934 |
|
|
Aug 27 08:43:39 AM UTC 24 |
Aug 27 08:58:15 AM UTC 24 |
17074164524 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.4101725303 |
|
|
Aug 27 08:14:41 AM UTC 24 |
Aug 27 08:58:52 AM UTC 24 |
42913363582 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1841517415 |
|
|
Aug 27 08:49:12 AM UTC 24 |
Aug 27 08:58:53 AM UTC 24 |
20648690758 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2142753058 |
|
|
Aug 27 08:58:17 AM UTC 24 |
Aug 27 08:58:53 AM UTC 24 |
507212807 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1279915290 |
|
|
Aug 27 08:57:29 AM UTC 24 |
Aug 27 08:58:58 AM UTC 24 |
6313075516 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.2549987873 |
|
|
Aug 27 08:58:53 AM UTC 24 |
Aug 27 08:59:03 AM UTC 24 |
1838367831 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3676867834 |
|
|
Aug 27 08:57:01 AM UTC 24 |
Aug 27 08:59:04 AM UTC 24 |
1625855093 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_bijection.2609213890 |
|
|
Aug 27 08:57:36 AM UTC 24 |
Aug 27 08:59:05 AM UTC 24 |
4770040708 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.4092744894 |
|
|
Aug 27 08:59:03 AM UTC 24 |
Aug 27 08:59:05 AM UTC 24 |
52493672 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1816233992 |
|
|
Aug 27 08:56:07 AM UTC 24 |
Aug 27 08:59:10 AM UTC 24 |
2356536779 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3872075444 |
|
|
Aug 27 08:01:03 AM UTC 24 |
Aug 27 08:59:10 AM UTC 24 |
11262976264 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3776819359 |
|
|
Aug 27 08:59:07 AM UTC 24 |
Aug 27 08:59:12 AM UTC 24 |
220008656 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2097657285 |
|
|
Aug 27 08:59:11 AM UTC 24 |
Aug 27 08:59:13 AM UTC 24 |
38518294 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.1799329621 |
|
|
Aug 27 08:59:05 AM UTC 24 |
Aug 27 08:59:18 AM UTC 24 |
4628372763 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_smoke.21666094 |
|
|
Aug 27 08:59:13 AM UTC 24 |
Aug 27 08:59:20 AM UTC 24 |
49716733 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_smoke.3779770981 |
|
|
Aug 27 08:57:33 AM UTC 24 |
Aug 27 08:59:23 AM UTC 24 |
1501448401 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3897393404 |
|
|
Aug 27 08:54:46 AM UTC 24 |
Aug 27 08:59:24 AM UTC 24 |
5184269416 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1413351433 |
|
|
Aug 27 08:58:12 AM UTC 24 |
Aug 27 08:59:30 AM UTC 24 |
169941233 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access.2935425833 |
|
|
Aug 27 08:57:51 AM UTC 24 |
Aug 27 08:59:36 AM UTC 24 |
771699289 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.3249479789 |
|
|
Aug 27 08:51:32 AM UTC 24 |
Aug 27 08:59:48 AM UTC 24 |
16913897076 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3954133867 |
|
|
Aug 27 08:59:49 AM UTC 24 |
Aug 27 08:59:54 AM UTC 24 |
183787884 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3650111880 |
|
|
Aug 27 08:20:22 AM UTC 24 |
Aug 27 09:00:13 AM UTC 24 |
39215997710 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_executable.2216521223 |
|
|
Aug 27 08:41:04 AM UTC 24 |
Aug 27 09:00:22 AM UTC 24 |
16806744225 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3189882751 |
|
|
Aug 27 08:59:38 AM UTC 24 |
Aug 27 09:00:29 AM UTC 24 |
233667410 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3711230298 |
|
|
Aug 27 09:00:30 AM UTC 24 |
Aug 27 09:00:32 AM UTC 24 |
33826989 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.4077866369 |
|
|
Aug 27 08:11:25 AM UTC 24 |
Aug 27 09:00:44 AM UTC 24 |
8872690829 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3357389744 |
|
|
Aug 27 09:00:34 AM UTC 24 |
Aug 27 09:00:50 AM UTC 24 |
5474034177 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.906547355 |
|
|
Aug 27 09:00:45 AM UTC 24 |
Aug 27 09:00:53 AM UTC 24 |
308434837 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_executable.1246712503 |
|
|
Aug 27 08:46:34 AM UTC 24 |
Aug 27 09:00:53 AM UTC 24 |
11918308345 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_alert_test.202864325 |
|
|
Aug 27 09:00:54 AM UTC 24 |
Aug 27 09:00:56 AM UTC 24 |
108391614 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_regwen.604522694 |
|
|
Aug 27 08:37:50 AM UTC 24 |
Aug 27 09:00:57 AM UTC 24 |
13285471183 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1264164056 |
|
|
Aug 27 08:59:24 AM UTC 24 |
Aug 27 09:01:01 AM UTC 24 |
2992380288 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3950473093 |
|
|
Aug 27 08:55:42 AM UTC 24 |
Aug 27 09:01:06 AM UTC 24 |
28301589779 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1198571455 |
|
|
Aug 27 08:59:31 AM UTC 24 |
Aug 27 09:01:06 AM UTC 24 |
144983545 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.479579299 |
|
|
Aug 27 08:50:37 AM UTC 24 |
Aug 27 09:01:07 AM UTC 24 |
55425236014 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_bijection.1392544884 |
|
|
Aug 27 08:59:19 AM UTC 24 |
Aug 27 09:01:08 AM UTC 24 |
7402762737 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.900858351 |
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|
Aug 27 09:00:57 AM UTC 24 |
Aug 27 09:01:09 AM UTC 24 |
560216508 ps |