| T792 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.900514763 |
|
|
Aug 27 08:52:54 AM UTC 24 |
Aug 27 09:01:22 AM UTC 24 |
34102775738 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access.734999444 |
|
|
Aug 27 09:01:07 AM UTC 24 |
Aug 27 09:01:24 AM UTC 24 |
3556649038 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_executable.2909975156 |
|
|
Aug 27 08:44:35 AM UTC 24 |
Aug 27 09:01:30 AM UTC 24 |
12311990015 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2745747252 |
|
|
Aug 27 09:01:23 AM UTC 24 |
Aug 27 09:01:32 AM UTC 24 |
709985172 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.1855796283 |
|
|
Aug 27 09:01:10 AM UTC 24 |
Aug 27 09:01:37 AM UTC 24 |
219207099 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3648972914 |
|
|
Aug 27 09:01:09 AM UTC 24 |
Aug 27 09:01:39 AM UTC 24 |
91989165 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1686945893 |
|
|
Aug 27 09:01:38 AM UTC 24 |
Aug 27 09:01:40 AM UTC 24 |
79339880 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.1462906959 |
|
|
Aug 27 08:55:16 AM UTC 24 |
Aug 27 09:01:43 AM UTC 24 |
37791440157 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.4006288645 |
|
|
Aug 27 09:01:41 AM UTC 24 |
Aug 27 09:01:45 AM UTC 24 |
60921167 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3338185652 |
|
|
Aug 27 08:56:51 AM UTC 24 |
Aug 27 09:01:53 AM UTC 24 |
46319479400 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1341357702 |
|
|
Aug 27 09:01:41 AM UTC 24 |
Aug 27 09:01:54 AM UTC 24 |
344362382 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.635272697 |
|
|
Aug 27 09:01:53 AM UTC 24 |
Aug 27 09:01:55 AM UTC 24 |
16774007 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2787940691 |
|
|
Aug 27 08:54:59 AM UTC 24 |
Aug 27 09:02:04 AM UTC 24 |
51095839209 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_executable.2823662898 |
|
|
Aug 27 08:53:53 AM UTC 24 |
Aug 27 09:02:04 AM UTC 24 |
5701519714 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_smoke.200613439 |
|
|
Aug 27 09:01:54 AM UTC 24 |
Aug 27 09:02:09 AM UTC 24 |
1645602617 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3691555805 |
|
|
Aug 27 08:51:32 AM UTC 24 |
Aug 27 09:02:14 AM UTC 24 |
3293555081 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3567217226 |
|
|
Aug 27 09:02:10 AM UTC 24 |
Aug 27 09:02:33 AM UTC 24 |
217863002 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_bijection.2423099026 |
|
|
Aug 27 09:01:01 AM UTC 24 |
Aug 27 09:02:39 AM UTC 24 |
17661744232 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2436491844 |
|
|
Aug 27 09:01:44 AM UTC 24 |
Aug 27 09:02:47 AM UTC 24 |
335391632 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1993037591 |
|
|
Aug 27 09:02:47 AM UTC 24 |
Aug 27 09:02:56 AM UTC 24 |
533175408 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2266655653 |
|
|
Aug 27 09:02:39 AM UTC 24 |
Aug 27 09:03:09 AM UTC 24 |
94714192 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3536988070 |
|
|
Aug 27 08:57:43 AM UTC 24 |
Aug 27 09:03:09 AM UTC 24 |
13416702545 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.2579600777 |
|
|
Aug 27 08:53:51 AM UTC 24 |
Aug 27 09:03:30 AM UTC 24 |
3935081217 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.348129039 |
|
|
Aug 27 09:03:31 AM UTC 24 |
Aug 27 09:03:33 AM UTC 24 |
120896105 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.3051134969 |
|
|
Aug 27 09:02:05 AM UTC 24 |
Aug 27 09:03:34 AM UTC 24 |
3133704036 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.1688644381 |
|
|
Aug 27 08:57:53 AM UTC 24 |
Aug 27 09:03:34 AM UTC 24 |
14545284418 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3417975471 |
|
|
Aug 27 09:03:35 AM UTC 24 |
Aug 27 09:03:43 AM UTC 24 |
119406687 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.3210019417 |
|
|
Aug 27 08:57:16 AM UTC 24 |
Aug 27 09:03:47 AM UTC 24 |
14621758647 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.1367632862 |
|
|
Aug 27 09:03:34 AM UTC 24 |
Aug 27 09:03:48 AM UTC 24 |
711982378 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1973965032 |
|
|
Aug 27 09:03:47 AM UTC 24 |
Aug 27 09:03:49 AM UTC 24 |
32661140 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.1205488880 |
|
|
Aug 27 08:59:25 AM UTC 24 |
Aug 27 09:03:52 AM UTC 24 |
6807740043 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.4204380758 |
|
|
Aug 27 09:00:58 AM UTC 24 |
Aug 27 09:03:59 AM UTC 24 |
4367914043 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.2160446038 |
|
|
Aug 27 09:03:50 AM UTC 24 |
Aug 27 09:04:04 AM UTC 24 |
1665424113 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.758980758 |
|
|
Aug 27 08:59:21 AM UTC 24 |
Aug 27 09:04:09 AM UTC 24 |
2365295461 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2093599834 |
|
|
Aug 27 09:04:05 AM UTC 24 |
Aug 27 09:04:13 AM UTC 24 |
102389728 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3931862321 |
|
|
Aug 27 09:02:33 AM UTC 24 |
Aug 27 09:04:14 AM UTC 24 |
135691811 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3676405797 |
|
|
Aug 27 09:03:35 AM UTC 24 |
Aug 27 09:04:17 AM UTC 24 |
1033421888 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.1054336663 |
|
|
Aug 27 09:04:14 AM UTC 24 |
Aug 27 09:04:19 AM UTC 24 |
168674529 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3086947787 |
|
|
Aug 27 08:23:41 AM UTC 24 |
Aug 27 09:04:19 AM UTC 24 |
41040849679 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_regwen.886425919 |
|
|
Aug 27 08:57:20 AM UTC 24 |
Aug 27 09:04:20 AM UTC 24 |
19861659029 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2968101474 |
|
|
Aug 27 09:04:14 AM UTC 24 |
Aug 27 09:04:27 AM UTC 24 |
91437784 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2301703485 |
|
|
Aug 27 09:04:19 AM UTC 24 |
Aug 27 09:04:29 AM UTC 24 |
4561965870 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1859956642 |
|
|
Aug 27 09:04:28 AM UTC 24 |
Aug 27 09:04:30 AM UTC 24 |
102132120 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.3550579726 |
|
|
Aug 27 09:04:29 AM UTC 24 |
Aug 27 09:04:39 AM UTC 24 |
1379264644 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3788715869 |
|
|
Aug 27 09:04:31 AM UTC 24 |
Aug 27 09:04:40 AM UTC 24 |
154537362 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.4092272131 |
|
|
Aug 27 09:03:53 AM UTC 24 |
Aug 27 09:04:41 AM UTC 24 |
4819344405 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3192821131 |
|
|
Aug 27 09:04:42 AM UTC 24 |
Aug 27 09:04:43 AM UTC 24 |
21455404 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.3853660423 |
|
|
Aug 27 09:04:45 AM UTC 24 |
Aug 27 09:04:49 AM UTC 24 |
151627291 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.195287222 |
|
|
Aug 27 08:55:12 AM UTC 24 |
Aug 27 09:05:06 AM UTC 24 |
3407263552 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2689920864 |
|
|
Aug 27 09:00:51 AM UTC 24 |
Aug 27 09:05:12 AM UTC 24 |
1842538539 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2197948815 |
|
|
Aug 27 08:59:14 AM UTC 24 |
Aug 27 09:05:26 AM UTC 24 |
2533989048 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1666376205 |
|
|
Aug 27 09:05:05 AM UTC 24 |
Aug 27 09:05:30 AM UTC 24 |
1271639898 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2818755943 |
|
|
Aug 27 09:04:40 AM UTC 24 |
Aug 27 09:05:31 AM UTC 24 |
9589991883 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1818951277 |
|
|
Aug 27 09:05:13 AM UTC 24 |
Aug 27 09:05:34 AM UTC 24 |
1256104537 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.3806888569 |
|
|
Aug 27 09:05:32 AM UTC 24 |
Aug 27 09:05:35 AM UTC 24 |
122428070 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2860963818 |
|
|
Aug 27 09:05:35 AM UTC 24 |
Aug 27 09:05:48 AM UTC 24 |
3752568970 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.3402649721 |
|
|
Aug 27 08:57:18 AM UTC 24 |
Aug 27 09:06:02 AM UTC 24 |
8634549957 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2557976802 |
|
|
Aug 27 09:05:32 AM UTC 24 |
Aug 27 09:06:12 AM UTC 24 |
1005237433 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1734574015 |
|
|
Aug 27 09:01:07 AM UTC 24 |
Aug 27 09:06:13 AM UTC 24 |
2513633684 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2510722183 |
|
|
Aug 27 09:06:12 AM UTC 24 |
Aug 27 09:06:15 AM UTC 24 |
123527674 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.4213060153 |
|
|
Aug 27 09:04:00 AM UTC 24 |
Aug 27 09:06:17 AM UTC 24 |
2300213553 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.4103948358 |
|
|
Aug 27 08:39:57 AM UTC 24 |
Aug 27 09:06:21 AM UTC 24 |
21314976101 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2464323980 |
|
|
Aug 27 09:06:15 AM UTC 24 |
Aug 27 09:06:23 AM UTC 24 |
208275292 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2541981746 |
|
|
Aug 27 09:06:25 AM UTC 24 |
Aug 27 09:06:27 AM UTC 24 |
35616993 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.571653263 |
|
|
Aug 27 09:02:05 AM UTC 24 |
Aug 27 09:06:27 AM UTC 24 |
12826296967 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.645724244 |
|
|
Aug 27 09:06:14 AM UTC 24 |
Aug 27 09:06:32 AM UTC 24 |
565995222 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.2039873713 |
|
|
Aug 27 09:04:21 AM UTC 24 |
Aug 27 09:06:37 AM UTC 24 |
3041856767 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.3320360249 |
|
|
Aug 27 09:06:28 AM UTC 24 |
Aug 27 09:06:59 AM UTC 24 |
414046600 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_regwen.834111498 |
|
|
Aug 27 08:53:59 AM UTC 24 |
Aug 27 09:07:17 AM UTC 24 |
10390000304 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2843820986 |
|
|
Aug 27 09:06:59 AM UTC 24 |
Aug 27 09:07:21 AM UTC 24 |
279599271 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3911399517 |
|
|
Aug 27 09:07:22 AM UTC 24 |
Aug 27 09:07:27 AM UTC 24 |
374726968 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3379542686 |
|
|
Aug 27 09:07:28 AM UTC 24 |
Aug 27 09:07:31 AM UTC 24 |
135525027 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2795962523 |
|
|
Aug 27 09:06:33 AM UTC 24 |
Aug 27 09:07:33 AM UTC 24 |
5200041750 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3377889013 |
|
|
Aug 27 09:06:18 AM UTC 24 |
Aug 27 09:07:40 AM UTC 24 |
5889388688 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.2410230320 |
|
|
Aug 27 09:07:32 AM UTC 24 |
Aug 27 09:07:47 AM UTC 24 |
630250552 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2548900629 |
|
|
Aug 27 09:05:06 AM UTC 24 |
Aug 27 09:08:28 AM UTC 24 |
8439256730 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.2634020719 |
|
|
Aug 27 09:08:30 AM UTC 24 |
Aug 27 09:08:32 AM UTC 24 |
28671475 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_executable.1667129042 |
|
|
Aug 27 08:58:54 AM UTC 24 |
Aug 27 09:08:40 AM UTC 24 |
6309092249 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3544129253 |
|
|
Aug 27 09:08:33 AM UTC 24 |
Aug 27 09:08:40 AM UTC 24 |
220929244 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3884330472 |
|
|
Aug 27 08:32:33 AM UTC 24 |
Aug 27 09:08:42 AM UTC 24 |
10272733070 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.384609870 |
|
|
Aug 27 09:01:31 AM UTC 24 |
Aug 27 09:08:45 AM UTC 24 |
1132102984 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2147222112 |
|
|
Aug 27 09:08:41 AM UTC 24 |
Aug 27 09:08:46 AM UTC 24 |
100551751 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2123616876 |
|
|
Aug 27 08:54:14 AM UTC 24 |
Aug 27 09:08:48 AM UTC 24 |
51330410497 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.355587568 |
|
|
Aug 27 09:08:46 AM UTC 24 |
Aug 27 09:08:48 AM UTC 24 |
30076364 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2986081306 |
|
|
Aug 27 08:34:33 AM UTC 24 |
Aug 27 09:09:00 AM UTC 24 |
159953857780 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1514643371 |
|
|
Aug 27 09:08:41 AM UTC 24 |
Aug 27 09:09:12 AM UTC 24 |
337346799 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.378404171 |
|
|
Aug 27 09:04:40 AM UTC 24 |
Aug 27 09:09:38 AM UTC 24 |
2335460954 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1116126524 |
|
|
Aug 27 09:03:51 AM UTC 24 |
Aug 27 09:10:28 AM UTC 24 |
3417289475 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2750793452 |
|
|
Aug 27 09:05:27 AM UTC 24 |
Aug 27 09:10:35 AM UTC 24 |
11268817137 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.4150037042 |
|
|
Aug 27 08:26:04 AM UTC 24 |
Aug 27 09:10:43 AM UTC 24 |
50097457411 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.404382754 |
|
|
Aug 27 09:06:37 AM UTC 24 |
Aug 27 09:10:57 AM UTC 24 |
2263626151 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.1936251664 |
|
|
Aug 27 09:04:20 AM UTC 24 |
Aug 27 09:11:06 AM UTC 24 |
2006973133 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.480063912 |
|
|
Aug 27 09:01:08 AM UTC 24 |
Aug 27 09:11:15 AM UTC 24 |
46998541561 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.462243639 |
|
|
Aug 27 09:01:25 AM UTC 24 |
Aug 27 09:11:17 AM UTC 24 |
10037243546 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2255968349 |
|
|
Aug 27 09:04:09 AM UTC 24 |
Aug 27 09:11:35 AM UTC 24 |
83695000132 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.3079126085 |
|
|
Aug 27 09:00:23 AM UTC 24 |
Aug 27 09:11:53 AM UTC 24 |
28559971151 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.2168655508 |
|
|
Aug 27 08:51:36 AM UTC 24 |
Aug 27 09:12:02 AM UTC 24 |
31976608616 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3561473674 |
|
|
Aug 27 08:44:03 AM UTC 24 |
Aug 27 09:12:28 AM UTC 24 |
37685331213 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.885449822 |
|
|
Aug 27 09:02:15 AM UTC 24 |
Aug 27 09:12:41 AM UTC 24 |
51319911130 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3538186271 |
|
|
Aug 27 09:01:56 AM UTC 24 |
Aug 27 09:12:45 AM UTC 24 |
12938895455 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1669274935 |
|
|
Aug 27 09:07:34 AM UTC 24 |
Aug 27 09:13:00 AM UTC 24 |
1556136213 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3099864316 |
|
|
Aug 27 09:04:50 AM UTC 24 |
Aug 27 09:13:03 AM UTC 24 |
3408074434 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2670984504 |
|
|
Aug 27 08:58:54 AM UTC 24 |
Aug 27 09:13:05 AM UTC 24 |
13215085819 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.836537395 |
|
|
Aug 27 09:08:43 AM UTC 24 |
Aug 27 09:13:14 AM UTC 24 |
4139187330 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.2221765496 |
|
|
Aug 27 09:07:41 AM UTC 24 |
Aug 27 09:13:34 AM UTC 24 |
7478553411 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.1457818582 |
|
|
Aug 27 09:06:22 AM UTC 24 |
Aug 27 09:13:57 AM UTC 24 |
8183634119 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.1006225018 |
|
|
Aug 27 09:00:14 AM UTC 24 |
Aug 27 09:14:25 AM UTC 24 |
39400668973 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.1783903881 |
|
|
Aug 27 08:58:59 AM UTC 24 |
Aug 27 09:14:32 AM UTC 24 |
5529527767 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.335910410 |
|
|
Aug 27 09:06:28 AM UTC 24 |
Aug 27 09:14:52 AM UTC 24 |
14969405876 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.572108841 |
|
|
Aug 27 09:04:21 AM UTC 24 |
Aug 27 09:15:07 AM UTC 24 |
12800529902 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.3313226563 |
|
|
Aug 27 09:06:03 AM UTC 24 |
Aug 27 09:15:15 AM UTC 24 |
1671128010 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3289689292 |
|
|
Aug 27 08:44:50 AM UTC 24 |
Aug 27 09:15:26 AM UTC 24 |
39223800405 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1725243661 |
|
|
Aug 27 09:05:36 AM UTC 24 |
Aug 27 09:16:14 AM UTC 24 |
2426812391 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.2545928337 |
|
|
Aug 27 08:57:35 AM UTC 24 |
Aug 27 09:16:21 AM UTC 24 |
42329931600 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.335770168 |
|
|
Aug 27 09:07:18 AM UTC 24 |
Aug 27 09:16:38 AM UTC 24 |
69458687841 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.1007555188 |
|
|
Aug 27 09:07:48 AM UTC 24 |
Aug 27 09:17:39 AM UTC 24 |
1548716707 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2947801325 |
|
|
Aug 27 08:54:10 AM UTC 24 |
Aug 27 09:17:42 AM UTC 24 |
127630590536 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_regwen.2447287782 |
|
|
Aug 27 08:55:21 AM UTC 24 |
Aug 27 09:18:32 AM UTC 24 |
16570354132 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.388089930 |
|
|
Aug 27 09:02:58 AM UTC 24 |
Aug 27 09:19:19 AM UTC 24 |
49143959171 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2446150208 |
|
|
Aug 27 08:21:55 AM UTC 24 |
Aug 27 09:19:24 AM UTC 24 |
226685462447 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2757984075 |
|
|
Aug 27 08:59:55 AM UTC 24 |
Aug 27 09:19:32 AM UTC 24 |
12701386720 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1298097691 |
|
|
Aug 27 08:30:36 AM UTC 24 |
Aug 27 09:20:08 AM UTC 24 |
246178308474 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1723867120 |
|
|
Aug 27 08:41:12 AM UTC 24 |
Aug 27 09:20:38 AM UTC 24 |
91675786399 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.708303344 |
|
|
Aug 27 09:01:33 AM UTC 24 |
Aug 27 09:20:47 AM UTC 24 |
27529994606 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3338711934 |
|
|
Aug 27 08:48:59 AM UTC 24 |
Aug 27 09:21:26 AM UTC 24 |
33122721256 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2988311375 |
|
|
Aug 27 09:01:46 AM UTC 24 |
Aug 27 09:22:17 AM UTC 24 |
61599248568 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.4207621901 |
|
|
Aug 27 08:52:11 AM UTC 24 |
Aug 27 09:22:51 AM UTC 24 |
17502263330 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2871234074 |
|
|
Aug 27 08:55:33 AM UTC 24 |
Aug 27 09:23:08 AM UTC 24 |
69535167023 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.4279577050 |
|
|
Aug 27 08:43:57 AM UTC 24 |
Aug 27 09:23:20 AM UTC 24 |
128745857336 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.840286348 |
|
|
Aug 27 08:50:24 AM UTC 24 |
Aug 27 09:23:24 AM UTC 24 |
46797607306 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.3763591024 |
|
|
Aug 27 09:05:49 AM UTC 24 |
Aug 27 09:26:18 AM UTC 24 |
2997091947 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.3261230790 |
|
|
Aug 27 09:03:10 AM UTC 24 |
Aug 27 09:26:41 AM UTC 24 |
16711318170 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.812958519 |
|
|
Aug 27 08:38:17 AM UTC 24 |
Aug 27 09:26:56 AM UTC 24 |
8449488941 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.899171218 |
|
|
Aug 27 08:33:36 AM UTC 24 |
Aug 27 09:27:18 AM UTC 24 |
64910274631 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2856514698 |
|
|
Aug 27 07:59:41 AM UTC 24 |
Aug 27 09:28:52 AM UTC 24 |
296833611572 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1867805345 |
|
|
Aug 27 08:59:11 AM UTC 24 |
Aug 27 09:30:17 AM UTC 24 |
9133355410 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2561026496 |
|
|
Aug 27 08:18:40 AM UTC 24 |
Aug 27 09:30:27 AM UTC 24 |
276502918008 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.2066504351 |
|
|
Aug 27 08:36:29 AM UTC 24 |
Aug 27 09:35:31 AM UTC 24 |
302904697344 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_stress_all.211291363 |
|
|
Aug 27 08:42:37 AM UTC 24 |
Aug 27 09:39:47 AM UTC 24 |
265945744051 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.1626211784 |
|
|
Aug 27 08:27:31 AM UTC 24 |
Aug 27 09:42:29 AM UTC 24 |
158844498899 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3407464111 |
|
|
Aug 27 09:00:54 AM UTC 24 |
Aug 27 09:45:39 AM UTC 24 |
46371351845 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3680781186 |
|
|
Aug 27 08:57:32 AM UTC 24 |
Aug 27 09:50:45 AM UTC 24 |
293480102680 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_stress_all.1748232703 |
|
|
Aug 27 08:39:34 AM UTC 24 |
Aug 27 09:57:53 AM UTC 24 |
210376229874 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.2161772707 |
|
|
Aug 27 09:03:43 AM UTC 24 |
Aug 27 10:03:35 AM UTC 24 |
50967291107 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.382671452 |
|
|
Aug 27 09:08:47 AM UTC 24 |
Aug 27 09:08:51 AM UTC 24 |
203666072 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.459541127 |
|
|
Aug 27 09:08:49 AM UTC 24 |
Aug 27 09:08:53 AM UTC 24 |
244304398 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1143797083 |
|
|
Aug 27 09:08:52 AM UTC 24 |
Aug 27 09:08:53 AM UTC 24 |
38543020 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3763877391 |
|
|
Aug 27 09:08:48 AM UTC 24 |
Aug 27 09:08:54 AM UTC 24 |
339822639 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3319105223 |
|
|
Aug 27 09:08:54 AM UTC 24 |
Aug 27 09:08:55 AM UTC 24 |
33198936 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2481788362 |
|
|
Aug 27 09:08:55 AM UTC 24 |
Aug 27 09:08:57 AM UTC 24 |
21368213 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3173572728 |
|
|
Aug 27 09:08:55 AM UTC 24 |
Aug 27 09:08:57 AM UTC 24 |
29576564 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3778775123 |
|
|
Aug 27 09:08:56 AM UTC 24 |
Aug 27 09:08:58 AM UTC 24 |
60892539 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1998673776 |
|
|
Aug 27 09:08:58 AM UTC 24 |
Aug 27 09:09:02 AM UTC 24 |
102827775 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4154674617 |
|
|
Aug 27 09:08:58 AM UTC 24 |
Aug 27 09:09:03 AM UTC 24 |
358412804 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.242489477 |
|
|
Aug 27 09:08:59 AM UTC 24 |
Aug 27 09:09:04 AM UTC 24 |
137784012 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2030106931 |
|
|
Aug 27 09:09:03 AM UTC 24 |
Aug 27 09:09:05 AM UTC 24 |
196096880 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.305797188 |
|
|
Aug 27 09:09:00 AM UTC 24 |
Aug 27 09:09:06 AM UTC 24 |
392085011 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.261143156 |
|
|
Aug 27 09:09:04 AM UTC 24 |
Aug 27 09:09:06 AM UTC 24 |
12606579 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.374322062 |
|
|
Aug 27 09:09:05 AM UTC 24 |
Aug 27 09:09:07 AM UTC 24 |
47053400 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.61528599 |
|
|
Aug 27 09:09:06 AM UTC 24 |
Aug 27 09:09:08 AM UTC 24 |
21366382 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.799262402 |
|
|
Aug 27 09:09:05 AM UTC 24 |
Aug 27 09:09:09 AM UTC 24 |
244188139 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1696279365 |
|
|
Aug 27 09:09:06 AM UTC 24 |
Aug 27 09:09:10 AM UTC 24 |
67311356 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3907686820 |
|
|
Aug 27 09:09:08 AM UTC 24 |
Aug 27 09:09:11 AM UTC 24 |
826251620 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3044607445 |
|
|
Aug 27 09:09:11 AM UTC 24 |
Aug 27 09:09:13 AM UTC 24 |
62889710 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.455298443 |
|
|
Aug 27 09:09:11 AM UTC 24 |
Aug 27 09:09:13 AM UTC 24 |
17896974 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3915420242 |
|
|
Aug 27 09:09:10 AM UTC 24 |
Aug 27 09:09:13 AM UTC 24 |
322743601 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2861636408 |
|
|
Aug 27 09:09:10 AM UTC 24 |
Aug 27 09:09:13 AM UTC 24 |
21704556 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.390379970 |
|
|
Aug 27 09:09:14 AM UTC 24 |
Aug 27 09:09:16 AM UTC 24 |
20315552 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1020836821 |
|
|
Aug 27 09:09:14 AM UTC 24 |
Aug 27 09:09:16 AM UTC 24 |
38813743 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.510426726 |
|
|
Aug 27 09:09:13 AM UTC 24 |
Aug 27 09:09:16 AM UTC 24 |
298119953 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.685767712 |
|
|
Aug 27 09:09:17 AM UTC 24 |
Aug 27 09:09:19 AM UTC 24 |
128988984 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1835682321 |
|
|
Aug 27 09:09:15 AM UTC 24 |
Aug 27 09:09:19 AM UTC 24 |
137401669 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.70523511 |
|
|
Aug 27 09:09:15 AM UTC 24 |
Aug 27 09:09:21 AM UTC 24 |
3350732453 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2046789968 |
|
|
Aug 27 09:09:17 AM UTC 24 |
Aug 27 09:09:21 AM UTC 24 |
526436499 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1552558931 |
|
|
Aug 27 09:09:20 AM UTC 24 |
Aug 27 09:09:22 AM UTC 24 |
15714245 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2317035636 |
|
|
Aug 27 09:09:21 AM UTC 24 |
Aug 27 09:09:23 AM UTC 24 |
21850098 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.297844981 |
|
|
Aug 27 09:09:20 AM UTC 24 |
Aug 27 09:09:23 AM UTC 24 |
92251116 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1307098695 |
|
|
Aug 27 09:09:17 AM UTC 24 |
Aug 27 09:09:25 AM UTC 24 |
483401966 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2796987243 |
|
|
Aug 27 09:09:23 AM UTC 24 |
Aug 27 09:09:25 AM UTC 24 |
237925372 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.783019142 |
|
|
Aug 27 09:09:23 AM UTC 24 |
Aug 27 09:09:27 AM UTC 24 |
35932355 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.126678393 |
|
|
Aug 27 09:09:26 AM UTC 24 |
Aug 27 09:09:28 AM UTC 24 |
15855957 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.321143463 |
|
|
Aug 27 09:09:24 AM UTC 24 |
Aug 27 09:09:29 AM UTC 24 |
890920572 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2641646980 |
|
|
Aug 27 09:09:26 AM UTC 24 |
Aug 27 09:09:29 AM UTC 24 |
159877099 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1500606692 |
|
|
Aug 27 09:09:29 AM UTC 24 |
Aug 27 09:09:31 AM UTC 24 |
44834618 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.37904863 |
|
|
Aug 27 09:09:24 AM UTC 24 |
Aug 27 09:09:32 AM UTC 24 |
471840250 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2382576929 |
|
|
Aug 27 09:09:29 AM UTC 24 |
Aug 27 09:09:32 AM UTC 24 |
70282567 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4032367440 |
|
|
Aug 27 09:09:31 AM UTC 24 |
Aug 27 09:09:33 AM UTC 24 |
16597340 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1765089525 |
|
|
Aug 27 09:09:31 AM UTC 24 |
Aug 27 09:09:33 AM UTC 24 |
84530366 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1770523454 |
|
|
Aug 27 09:09:34 AM UTC 24 |
Aug 27 09:09:36 AM UTC 24 |
14227916 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3772317475 |
|
|
Aug 27 09:09:34 AM UTC 24 |
Aug 27 09:09:36 AM UTC 24 |
17144564 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1840871833 |
|
|
Aug 27 09:09:33 AM UTC 24 |
Aug 27 09:09:37 AM UTC 24 |
69996922 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4247322543 |
|
|
Aug 27 09:09:33 AM UTC 24 |
Aug 27 09:09:37 AM UTC 24 |
141774384 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3350997815 |
|
|
Aug 27 09:09:34 AM UTC 24 |
Aug 27 09:09:38 AM UTC 24 |
182315744 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4290777801 |
|
|
Aug 27 09:09:33 AM UTC 24 |
Aug 27 09:09:39 AM UTC 24 |
1365347816 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1761416583 |
|
|
Aug 27 09:09:38 AM UTC 24 |
Aug 27 09:09:42 AM UTC 24 |
116645589 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.429128482 |
|
|
Aug 27 09:09:39 AM UTC 24 |
Aug 27 09:09:43 AM UTC 24 |
326289808 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3077243925 |
|
|
Aug 27 09:09:41 AM UTC 24 |
Aug 27 09:09:43 AM UTC 24 |
14483050 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2792477742 |
|
|
Aug 27 09:09:42 AM UTC 24 |
Aug 27 09:09:44 AM UTC 24 |
77088109 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3293485793 |
|
|
Aug 27 09:09:39 AM UTC 24 |
Aug 27 09:09:44 AM UTC 24 |
137177521 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2214207147 |
|
|
Aug 27 09:09:41 AM UTC 24 |
Aug 27 09:09:45 AM UTC 24 |
101384931 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.224990446 |
|
|
Aug 27 09:09:42 AM UTC 24 |
Aug 27 09:09:45 AM UTC 24 |
56432877 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2438885241 |
|
|
Aug 27 09:09:45 AM UTC 24 |
Aug 27 09:09:47 AM UTC 24 |
22504867 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3044143258 |
|
|
Aug 27 09:09:45 AM UTC 24 |
Aug 27 09:09:48 AM UTC 24 |
133177208 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3617727097 |
|
|
Aug 27 09:09:43 AM UTC 24 |
Aug 27 09:09:48 AM UTC 24 |
803998921 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.723939826 |
|
|
Aug 27 09:09:47 AM UTC 24 |
Aug 27 09:09:49 AM UTC 24 |
39943485 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2626066474 |
|
|
Aug 27 09:09:47 AM UTC 24 |
Aug 27 09:09:49 AM UTC 24 |
59307532 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3147577361 |
|
|
Aug 27 09:09:45 AM UTC 24 |
Aug 27 09:09:50 AM UTC 24 |
141436338 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2756114944 |
|
|
Aug 27 09:09:47 AM UTC 24 |
Aug 27 09:09:51 AM UTC 24 |
241705145 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4237582179 |
|
|
Aug 27 09:09:50 AM UTC 24 |
Aug 27 09:09:52 AM UTC 24 |
14735045 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4072958386 |
|
|
Aug 27 09:09:50 AM UTC 24 |
Aug 27 09:09:52 AM UTC 24 |
79052535 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.299452716 |
|
|
Aug 27 09:09:48 AM UTC 24 |
Aug 27 09:09:54 AM UTC 24 |
74358313 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2013767055 |
|
|
Aug 27 09:09:50 AM UTC 24 |
Aug 27 09:09:54 AM UTC 24 |
167676013 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3680422645 |
|
|
Aug 27 09:09:50 AM UTC 24 |
Aug 27 09:09:55 AM UTC 24 |
359906546 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1496525295 |
|
|
Aug 27 09:09:53 AM UTC 24 |
Aug 27 09:09:55 AM UTC 24 |
54709973 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2564054216 |
|
|
Aug 27 09:09:52 AM UTC 24 |
Aug 27 09:09:56 AM UTC 24 |
32619844 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.545553135 |
|
|
Aug 27 09:09:55 AM UTC 24 |
Aug 27 09:09:57 AM UTC 24 |
82593293 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.968512487 |
|
|
Aug 27 09:09:52 AM UTC 24 |
Aug 27 09:09:57 AM UTC 24 |
1591409293 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1500092360 |
|
|
Aug 27 09:09:53 AM UTC 24 |
Aug 27 09:09:58 AM UTC 24 |
334329365 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3635026896 |
|
|
Aug 27 09:09:55 AM UTC 24 |
Aug 27 09:09:58 AM UTC 24 |
60022206 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2863456651 |
|
|
Aug 27 09:09:57 AM UTC 24 |
Aug 27 09:10:00 AM UTC 24 |
110805371 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4180837680 |
|
|
Aug 27 09:09:59 AM UTC 24 |
Aug 27 09:10:01 AM UTC 24 |
13991457 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3017087189 |
|
|
Aug 27 09:09:57 AM UTC 24 |
Aug 27 09:10:01 AM UTC 24 |
230904642 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4119768308 |
|
|
Aug 27 09:09:59 AM UTC 24 |
Aug 27 09:10:01 AM UTC 24 |
56976505 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3255408108 |
|
|
Aug 27 09:09:59 AM UTC 24 |
Aug 27 09:10:03 AM UTC 24 |
38415225 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1163564048 |
|
|
Aug 27 09:09:57 AM UTC 24 |
Aug 27 09:10:04 AM UTC 24 |
624268661 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1286635858 |
|
|
Aug 27 09:10:02 AM UTC 24 |
Aug 27 09:10:04 AM UTC 24 |
15447223 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4088703478 |
|
|
Aug 27 09:10:03 AM UTC 24 |
Aug 27 09:10:06 AM UTC 24 |
16707752 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2158952077 |
|
|
Aug 27 09:09:59 AM UTC 24 |
Aug 27 09:10:07 AM UTC 24 |
2768597011 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1953695812 |
|
|
Aug 27 09:10:02 AM UTC 24 |
Aug 27 09:10:07 AM UTC 24 |
79764804 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.961964101 |
|
|
Aug 27 09:10:02 AM UTC 24 |
Aug 27 09:10:08 AM UTC 24 |
538445613 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2399138064 |
|
|
Aug 27 09:10:05 AM UTC 24 |
Aug 27 09:10:08 AM UTC 24 |
24522689 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.481405798 |
|
|
Aug 27 09:10:08 AM UTC 24 |
Aug 27 09:10:11 AM UTC 24 |
11311814 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1086454218 |
|
|
Aug 27 09:10:08 AM UTC 24 |
Aug 27 09:10:11 AM UTC 24 |
66991849 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1910013481 |
|
|
Aug 27 09:10:07 AM UTC 24 |
Aug 27 09:10:11 AM UTC 24 |
275409266 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1375046231 |
|
|
Aug 27 09:10:05 AM UTC 24 |
Aug 27 09:10:12 AM UTC 24 |
485721400 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3216987655 |
|
|
Aug 27 09:10:10 AM UTC 24 |
Aug 27 09:10:13 AM UTC 24 |
139106868 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.507065215 |
|
|
Aug 27 09:10:13 AM UTC 24 |
Aug 27 09:10:15 AM UTC 24 |
31690246 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3829034867 |
|
|
Aug 27 09:10:06 AM UTC 24 |
Aug 27 09:10:15 AM UTC 24 |
713857202 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2420259504 |
|
|
Aug 27 09:10:10 AM UTC 24 |
Aug 27 09:10:15 AM UTC 24 |
234317695 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1516451142 |
|
|
Aug 27 09:10:14 AM UTC 24 |
Aug 27 09:10:16 AM UTC 24 |
36336060 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1714242422 |
|
|
Aug 27 09:10:14 AM UTC 24 |
Aug 27 09:10:17 AM UTC 24 |
39847906 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3677706177 |
|
|
Aug 27 09:10:13 AM UTC 24 |
Aug 27 09:10:18 AM UTC 24 |
255884483 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2107097594 |
|
|
Aug 27 09:10:13 AM UTC 24 |
Aug 27 09:10:19 AM UTC 24 |
62274361 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.881800758 |
|
|
Aug 27 09:10:16 AM UTC 24 |
Aug 27 09:10:19 AM UTC 24 |
355245955 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1128196128 |
|
|
Aug 27 09:10:18 AM UTC 24 |
Aug 27 09:10:20 AM UTC 24 |
35361831 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1148088135 |
|
|
Aug 27 09:10:18 AM UTC 24 |
Aug 27 09:10:20 AM UTC 24 |
53057355 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3162867376 |
|
|
Aug 27 09:10:16 AM UTC 24 |
Aug 27 09:10:22 AM UTC 24 |
5309750292 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2718604255 |
|
|
Aug 27 09:10:19 AM UTC 24 |
Aug 27 09:10:23 AM UTC 24 |
141334451 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2888803559 |
|
|
Aug 27 09:10:21 AM UTC 24 |
Aug 27 09:10:23 AM UTC 24 |
16747027 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2000230538 |
|
|
Aug 27 09:10:22 AM UTC 24 |
Aug 27 09:10:25 AM UTC 24 |
58375647 ps |