| T308 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1074791031 |
|
|
Sep 01 10:13:47 PM UTC 24 |
Sep 01 10:13:49 PM UTC 24 |
33705296 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2587667215 |
|
|
Sep 01 10:09:50 PM UTC 24 |
Sep 01 10:13:57 PM UTC 24 |
9947755036 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.1649694111 |
|
|
Sep 01 10:08:20 PM UTC 24 |
Sep 01 10:13:58 PM UTC 24 |
48791155668 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1911815833 |
|
|
Sep 01 10:13:08 PM UTC 24 |
Sep 01 10:14:01 PM UTC 24 |
444636359 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.4004783290 |
|
|
Sep 01 09:54:13 PM UTC 24 |
Sep 01 10:14:16 PM UTC 24 |
2404453478 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2032721273 |
|
|
Sep 01 10:14:16 PM UTC 24 |
Sep 01 10:14:24 PM UTC 24 |
632147690 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3074865629 |
|
|
Sep 01 09:51:47 PM UTC 24 |
Sep 01 10:14:36 PM UTC 24 |
29133045383 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2203553438 |
|
|
Sep 01 10:12:36 PM UTC 24 |
Sep 01 10:14:40 PM UTC 24 |
2313490468 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2794032108 |
|
|
Sep 01 10:14:41 PM UTC 24 |
Sep 01 10:14:48 PM UTC 24 |
258796886 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_bijection.999900650 |
|
|
Sep 01 10:13:58 PM UTC 24 |
Sep 01 10:14:53 PM UTC 24 |
3515119157 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.96419727 |
|
|
Sep 01 09:48:56 PM UTC 24 |
Sep 01 10:14:53 PM UTC 24 |
17170497432 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1108381238 |
|
|
Sep 01 10:11:04 PM UTC 24 |
Sep 01 10:15:05 PM UTC 24 |
1150129396 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3335771809 |
|
|
Sep 01 10:15:06 PM UTC 24 |
Sep 01 10:15:08 PM UTC 24 |
75230714 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1982840489 |
|
|
Sep 01 10:14:36 PM UTC 24 |
Sep 01 10:15:11 PM UTC 24 |
361963255 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.1010572808 |
|
|
Sep 01 10:14:25 PM UTC 24 |
Sep 01 10:15:13 PM UTC 24 |
97975708 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_smoke.3734824010 |
|
|
Sep 01 10:13:50 PM UTC 24 |
Sep 01 10:15:15 PM UTC 24 |
1421766006 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.1107279590 |
|
|
Sep 01 10:15:12 PM UTC 24 |
Sep 01 10:15:20 PM UTC 24 |
229026173 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1053743518 |
|
|
Sep 01 10:15:21 PM UTC 24 |
Sep 01 10:15:23 PM UTC 24 |
14880183 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.4268973511 |
|
|
Sep 01 10:15:09 PM UTC 24 |
Sep 01 10:15:24 PM UTC 24 |
457615779 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.339585732 |
|
|
Sep 01 09:59:52 PM UTC 24 |
Sep 01 10:15:27 PM UTC 24 |
12816321529 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_executable.874484869 |
|
|
Sep 01 09:52:57 PM UTC 24 |
Sep 01 10:15:30 PM UTC 24 |
23918120948 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2827064436 |
|
|
Sep 01 10:15:13 PM UTC 24 |
Sep 01 10:15:39 PM UTC 24 |
639006787 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3821157159 |
|
|
Sep 01 09:58:46 PM UTC 24 |
Sep 01 10:15:55 PM UTC 24 |
26934968752 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_bijection.1559110467 |
|
|
Sep 01 10:15:28 PM UTC 24 |
Sep 01 10:16:10 PM UTC 24 |
2916744900 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.957899421 |
|
|
Sep 01 10:10:14 PM UTC 24 |
Sep 01 10:16:15 PM UTC 24 |
25407603363 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_smoke.3888518331 |
|
|
Sep 01 10:15:24 PM UTC 24 |
Sep 01 10:16:19 PM UTC 24 |
111040989 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.123237129 |
|
|
Sep 01 10:07:08 PM UTC 24 |
Sep 01 10:16:19 PM UTC 24 |
70932286721 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.80948108 |
|
|
Sep 01 09:56:51 PM UTC 24 |
Sep 01 10:16:30 PM UTC 24 |
25078993763 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3477831544 |
|
|
Sep 01 10:16:20 PM UTC 24 |
Sep 01 10:16:30 PM UTC 24 |
2159611507 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.3217819402 |
|
|
Sep 01 10:16:11 PM UTC 24 |
Sep 01 10:16:32 PM UTC 24 |
138681048 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2829210397 |
|
|
Sep 01 10:16:33 PM UTC 24 |
Sep 01 10:16:35 PM UTC 24 |
69046513 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access.42762532 |
|
|
Sep 01 10:15:40 PM UTC 24 |
Sep 01 10:16:42 PM UTC 24 |
237399607 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1156717553 |
|
|
Sep 01 10:08:06 PM UTC 24 |
Sep 01 10:16:43 PM UTC 24 |
70401257906 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.4056782306 |
|
|
Sep 01 10:16:36 PM UTC 24 |
Sep 01 10:16:45 PM UTC 24 |
457436376 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3253517139 |
|
|
Sep 01 10:16:43 PM UTC 24 |
Sep 01 10:16:54 PM UTC 24 |
174441710 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2189529707 |
|
|
Sep 01 10:16:55 PM UTC 24 |
Sep 01 10:16:57 PM UTC 24 |
18645953 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.732198599 |
|
|
Sep 01 10:06:06 PM UTC 24 |
Sep 01 10:16:59 PM UTC 24 |
5689420485 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1095266744 |
|
|
Sep 01 10:14:01 PM UTC 24 |
Sep 01 10:17:10 PM UTC 24 |
1839898576 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3845607143 |
|
|
Sep 01 10:11:31 PM UTC 24 |
Sep 01 10:17:14 PM UTC 24 |
72097352682 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_smoke.2370087457 |
|
|
Sep 01 10:16:58 PM UTC 24 |
Sep 01 10:17:30 PM UTC 24 |
667734917 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.4216880784 |
|
|
Sep 01 10:11:17 PM UTC 24 |
Sep 01 10:17:33 PM UTC 24 |
22323734814 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2066047904 |
|
|
Sep 01 10:16:16 PM UTC 24 |
Sep 01 10:17:44 PM UTC 24 |
632204861 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.970157276 |
|
|
Sep 01 10:16:43 PM UTC 24 |
Sep 01 10:17:49 PM UTC 24 |
1183167027 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3965343967 |
|
|
Sep 01 10:17:30 PM UTC 24 |
Sep 01 10:17:50 PM UTC 24 |
936464558 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_regwen.1810733716 |
|
|
Sep 01 10:06:20 PM UTC 24 |
Sep 01 10:17:53 PM UTC 24 |
6522829292 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.2232687516 |
|
|
Sep 01 10:17:51 PM UTC 24 |
Sep 01 10:17:58 PM UTC 24 |
1337035067 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1036362234 |
|
|
Sep 01 10:14:17 PM UTC 24 |
Sep 01 10:18:08 PM UTC 24 |
34431662521 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.202327074 |
|
|
Sep 01 09:52:47 PM UTC 24 |
Sep 01 10:18:15 PM UTC 24 |
20764172272 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.1394486683 |
|
|
Sep 01 10:18:15 PM UTC 24 |
Sep 01 10:18:17 PM UTC 24 |
48396916 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.290741714 |
|
|
Sep 01 10:12:54 PM UTC 24 |
Sep 01 10:18:27 PM UTC 24 |
50039521275 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.4154431571 |
|
|
Sep 01 10:15:31 PM UTC 24 |
Sep 01 10:18:27 PM UTC 24 |
1525426248 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.4247186869 |
|
|
Sep 01 10:12:27 PM UTC 24 |
Sep 01 10:18:35 PM UTC 24 |
5472811326 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.2812478 |
|
|
Sep 01 10:18:18 PM UTC 24 |
Sep 01 10:18:36 PM UTC 24 |
516132636 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1486221851 |
|
|
Sep 01 10:18:27 PM UTC 24 |
Sep 01 10:18:37 PM UTC 24 |
785365842 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_regwen.3885283954 |
|
|
Sep 01 10:07:36 PM UTC 24 |
Sep 01 10:18:37 PM UTC 24 |
40781840790 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3847073769 |
|
|
Sep 01 10:18:37 PM UTC 24 |
Sep 01 10:18:39 PM UTC 24 |
23173090 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1321695701 |
|
|
Sep 01 10:17:46 PM UTC 24 |
Sep 01 10:18:43 PM UTC 24 |
112099622 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_bijection.1454862259 |
|
|
Sep 01 10:17:11 PM UTC 24 |
Sep 01 10:18:48 PM UTC 24 |
3651294782 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2476556850 |
|
|
Sep 01 10:02:04 PM UTC 24 |
Sep 01 10:18:51 PM UTC 24 |
4367613156 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2952011678 |
|
|
Sep 01 10:18:49 PM UTC 24 |
Sep 01 10:19:11 PM UTC 24 |
2759232469 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_bijection.1190927841 |
|
|
Sep 01 10:18:39 PM UTC 24 |
Sep 01 10:19:24 PM UTC 24 |
2196568507 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.796553903 |
|
|
Sep 01 10:17:51 PM UTC 24 |
Sep 01 10:19:24 PM UTC 24 |
563897929 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2638224950 |
|
|
Sep 01 10:19:25 PM UTC 24 |
Sep 01 10:19:33 PM UTC 24 |
754512615 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_smoke.2557537602 |
|
|
Sep 01 10:18:38 PM UTC 24 |
Sep 01 10:19:35 PM UTC 24 |
117536290 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.246917422 |
|
|
Sep 01 09:57:53 PM UTC 24 |
Sep 01 10:19:49 PM UTC 24 |
19713388458 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3100743900 |
|
|
Sep 01 10:19:51 PM UTC 24 |
Sep 01 10:19:53 PM UTC 24 |
28877917 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.234214971 |
|
|
Sep 01 10:18:56 PM UTC 24 |
Sep 01 10:20:00 PM UTC 24 |
106764096 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2198401737 |
|
|
Sep 01 10:15:56 PM UTC 24 |
Sep 01 10:20:01 PM UTC 24 |
6372737484 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.63393661 |
|
|
Sep 01 10:19:54 PM UTC 24 |
Sep 01 10:20:02 PM UTC 24 |
975645757 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3549790322 |
|
|
Sep 01 10:12:35 PM UTC 24 |
Sep 01 10:20:04 PM UTC 24 |
16783376542 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3196018378 |
|
|
Sep 01 10:20:01 PM UTC 24 |
Sep 01 10:20:06 PM UTC 24 |
215832692 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1085717298 |
|
|
Sep 01 10:20:05 PM UTC 24 |
Sep 01 10:20:07 PM UTC 24 |
36154062 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_smoke.1878990950 |
|
|
Sep 01 10:20:07 PM UTC 24 |
Sep 01 10:20:12 PM UTC 24 |
111554703 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.161886491 |
|
|
Sep 01 10:13:46 PM UTC 24 |
Sep 01 10:20:24 PM UTC 24 |
18753842303 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_bijection.3712580237 |
|
|
Sep 01 10:20:14 PM UTC 24 |
Sep 01 10:20:54 PM UTC 24 |
20540100331 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1560188756 |
|
|
Sep 01 10:20:55 PM UTC 24 |
Sep 01 10:20:58 PM UTC 24 |
106037535 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2205406021 |
|
|
Sep 01 10:19:12 PM UTC 24 |
Sep 01 10:21:18 PM UTC 24 |
583570252 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.297181717 |
|
|
Sep 01 10:04:00 PM UTC 24 |
Sep 01 10:22:09 PM UTC 24 |
15767219957 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2072040897 |
|
|
Sep 01 10:17:15 PM UTC 24 |
Sep 01 10:22:11 PM UTC 24 |
26123658389 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.90089245 |
|
|
Sep 01 10:22:12 PM UTC 24 |
Sep 01 10:22:16 PM UTC 24 |
3196341678 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1434585792 |
|
|
Sep 01 10:22:38 PM UTC 24 |
Sep 01 10:22:41 PM UTC 24 |
32001464 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2846932534 |
|
|
Sep 01 09:47:50 PM UTC 24 |
Sep 01 10:22:55 PM UTC 24 |
14449127772 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.2022251184 |
|
|
Sep 01 10:21:19 PM UTC 24 |
Sep 01 10:22:59 PM UTC 24 |
128781345 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1297616051 |
|
|
Sep 01 10:22:42 PM UTC 24 |
Sep 01 10:23:00 PM UTC 24 |
2508424183 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.408992026 |
|
|
Sep 01 10:22:56 PM UTC 24 |
Sep 01 10:23:03 PM UTC 24 |
117563694 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_alert_test.3956182322 |
|
|
Sep 01 10:23:04 PM UTC 24 |
Sep 01 10:23:06 PM UTC 24 |
40588838 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_executable.2943812268 |
|
|
Sep 01 10:06:15 PM UTC 24 |
Sep 01 10:23:26 PM UTC 24 |
13097581009 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_smoke.896578948 |
|
|
Sep 01 10:23:07 PM UTC 24 |
Sep 01 10:23:26 PM UTC 24 |
1255281690 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_regwen.176345873 |
|
|
Sep 01 10:10:53 PM UTC 24 |
Sep 01 10:23:31 PM UTC 24 |
53586854120 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2892024901 |
|
|
Sep 01 10:22:10 PM UTC 24 |
Sep 01 10:23:44 PM UTC 24 |
264435457 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/13.sram_ctrl_executable.3352083975 |
|
|
Sep 01 10:08:41 PM UTC 24 |
Sep 01 10:23:45 PM UTC 24 |
97519642403 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3046642333 |
|
|
Sep 01 10:18:29 PM UTC 24 |
Sep 01 10:23:53 PM UTC 24 |
6457292449 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_bijection.3879798040 |
|
|
Sep 01 10:23:27 PM UTC 24 |
Sep 01 10:23:56 PM UTC 24 |
15877087107 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3404923593 |
|
|
Sep 01 10:11:58 PM UTC 24 |
Sep 01 10:24:07 PM UTC 24 |
1926599252 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3361751521 |
|
|
Sep 01 10:24:08 PM UTC 24 |
Sep 01 10:24:14 PM UTC 24 |
235550795 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.1771465050 |
|
|
Sep 01 10:18:43 PM UTC 24 |
Sep 01 10:24:24 PM UTC 24 |
13369934565 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1750006150 |
|
|
Sep 01 10:20:02 PM UTC 24 |
Sep 01 10:24:28 PM UTC 24 |
4222459089 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.2976240543 |
|
|
Sep 01 10:24:29 PM UTC 24 |
Sep 01 10:24:31 PM UTC 24 |
167662751 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.3323552279 |
|
|
Sep 01 10:23:54 PM UTC 24 |
Sep 01 10:24:35 PM UTC 24 |
218721974 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.747028746 |
|
|
Sep 01 10:13:24 PM UTC 24 |
Sep 01 10:24:39 PM UTC 24 |
3449684554 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3664109516 |
|
|
Sep 01 10:24:32 PM UTC 24 |
Sep 01 10:24:40 PM UTC 24 |
466186904 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.2532941151 |
|
|
Sep 01 10:24:36 PM UTC 24 |
Sep 01 10:24:41 PM UTC 24 |
122136504 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_regwen.2385608596 |
|
|
Sep 01 10:22:35 PM UTC 24 |
Sep 01 10:24:43 PM UTC 24 |
4146028775 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1234028979 |
|
|
Sep 01 10:24:42 PM UTC 24 |
Sep 01 10:24:44 PM UTC 24 |
13412519 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_regwen.2202648433 |
|
|
Sep 01 10:02:08 PM UTC 24 |
Sep 01 10:24:45 PM UTC 24 |
28042323666 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.512566003 |
|
|
Sep 01 10:26:40 PM UTC 24 |
Sep 01 10:26:48 PM UTC 24 |
1728993252 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1348928089 |
|
|
Sep 01 10:08:00 PM UTC 24 |
Sep 01 10:24:46 PM UTC 24 |
70030713491 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3116354313 |
|
|
Sep 01 10:23:57 PM UTC 24 |
Sep 01 10:24:50 PM UTC 24 |
117675394 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access.1961476989 |
|
|
Sep 01 10:24:47 PM UTC 24 |
Sep 01 10:25:05 PM UTC 24 |
858590997 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3399238201 |
|
|
Sep 01 10:23:46 PM UTC 24 |
Sep 01 10:25:05 PM UTC 24 |
2610552460 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_smoke.1987812812 |
|
|
Sep 01 10:24:44 PM UTC 24 |
Sep 01 10:25:11 PM UTC 24 |
778019193 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_executable.1044119593 |
|
|
Sep 01 10:17:59 PM UTC 24 |
Sep 01 10:25:12 PM UTC 24 |
9054775250 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/3.sram_ctrl_stress_all.2671179524 |
|
|
Sep 01 09:49:37 PM UTC 24 |
Sep 01 10:25:18 PM UTC 24 |
119412432020 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_regwen.3031658702 |
|
|
Sep 01 10:14:54 PM UTC 24 |
Sep 01 10:25:21 PM UTC 24 |
37898033099 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.681232122 |
|
|
Sep 01 10:25:11 PM UTC 24 |
Sep 01 10:25:22 PM UTC 24 |
5200574612 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.1255253103 |
|
|
Sep 01 10:25:23 PM UTC 24 |
Sep 01 10:25:25 PM UTC 24 |
51900217 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2808123510 |
|
|
Sep 01 10:25:26 PM UTC 24 |
Sep 01 10:25:35 PM UTC 24 |
880633153 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_bijection.301324019 |
|
|
Sep 01 10:24:47 PM UTC 24 |
Sep 01 10:25:37 PM UTC 24 |
1960252880 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.291361864 |
|
|
Sep 01 10:25:36 PM UTC 24 |
Sep 01 10:25:45 PM UTC 24 |
328238484 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.892864989 |
|
|
Sep 01 10:17:00 PM UTC 24 |
Sep 01 10:25:47 PM UTC 24 |
2128209060 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.4114078503 |
|
|
Sep 01 10:20:59 PM UTC 24 |
Sep 01 10:25:47 PM UTC 24 |
7528413454 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.166870580 |
|
|
Sep 01 10:25:06 PM UTC 24 |
Sep 01 10:25:49 PM UTC 24 |
478429314 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3621152984 |
|
|
Sep 01 10:25:48 PM UTC 24 |
Sep 01 10:25:50 PM UTC 24 |
21148179 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2345729502 |
|
|
Sep 01 09:46:22 PM UTC 24 |
Sep 01 10:25:52 PM UTC 24 |
27296588887 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_executable.2762190694 |
|
|
Sep 01 10:13:32 PM UTC 24 |
Sep 01 10:25:52 PM UTC 24 |
19656045646 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access.2127693366 |
|
|
Sep 01 10:25:53 PM UTC 24 |
Sep 01 10:26:00 PM UTC 24 |
126419315 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2888770706 |
|
|
Sep 01 10:18:53 PM UTC 24 |
Sep 01 10:26:10 PM UTC 24 |
15894807598 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1941170895 |
|
|
Sep 01 10:25:05 PM UTC 24 |
Sep 01 10:26:10 PM UTC 24 |
440323586 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2564479293 |
|
|
Sep 01 10:23:00 PM UTC 24 |
Sep 01 10:26:19 PM UTC 24 |
1730294525 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.3022050618 |
|
|
Sep 01 10:26:11 PM UTC 24 |
Sep 01 10:26:27 PM UTC 24 |
9044105089 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1771378219 |
|
|
Sep 01 10:14:49 PM UTC 24 |
Sep 01 10:26:31 PM UTC 24 |
13924223738 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3050865605 |
|
|
Sep 01 10:11:05 PM UTC 24 |
Sep 01 10:26:36 PM UTC 24 |
14533624588 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1126455829 |
|
|
Sep 01 10:26:37 PM UTC 24 |
Sep 01 10:26:39 PM UTC 24 |
43066585 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1960354917 |
|
|
Sep 01 10:26:49 PM UTC 24 |
Sep 01 10:26:55 PM UTC 24 |
199452158 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.589304385 |
|
|
Sep 01 10:26:11 PM UTC 24 |
Sep 01 10:27:03 PM UTC 24 |
462301160 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.3640304878 |
|
|
Sep 01 10:02:33 PM UTC 24 |
Sep 01 10:27:11 PM UTC 24 |
3941738879 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3916605081 |
|
|
Sep 01 10:27:12 PM UTC 24 |
Sep 01 10:27:14 PM UTC 24 |
12259704 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_bijection.3770345361 |
|
|
Sep 01 10:25:51 PM UTC 24 |
Sep 01 10:27:23 PM UTC 24 |
5067574278 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.1927067268 |
|
|
Sep 01 10:20:25 PM UTC 24 |
Sep 01 10:27:33 PM UTC 24 |
3686402077 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_smoke.3426920344 |
|
|
Sep 01 10:27:15 PM UTC 24 |
Sep 01 10:27:35 PM UTC 24 |
319907851 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_smoke.1942793225 |
|
|
Sep 01 10:25:48 PM UTC 24 |
Sep 01 10:27:36 PM UTC 24 |
581927192 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.3576142274 |
|
|
Sep 01 10:23:33 PM UTC 24 |
Sep 01 10:27:44 PM UTC 24 |
4786996340 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1715901317 |
|
|
Sep 01 10:26:21 PM UTC 24 |
Sep 01 10:27:57 PM UTC 24 |
686104654 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2690021217 |
|
|
Sep 01 09:53:42 PM UTC 24 |
Sep 01 10:27:58 PM UTC 24 |
35349024124 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access.1699360916 |
|
|
Sep 01 10:27:37 PM UTC 24 |
Sep 01 10:28:01 PM UTC 24 |
1145052309 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1230256915 |
|
|
Sep 01 10:27:59 PM UTC 24 |
Sep 01 10:28:04 PM UTC 24 |
82805580 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_regwen.1948971260 |
|
|
Sep 01 10:12:06 PM UTC 24 |
Sep 01 10:28:04 PM UTC 24 |
28031172603 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.821756065 |
|
|
Sep 01 10:26:07 PM UTC 24 |
Sep 01 10:28:06 PM UTC 24 |
562049859 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3793188848 |
|
|
Sep 01 10:28:02 PM UTC 24 |
Sep 01 10:28:08 PM UTC 24 |
583365794 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3570320858 |
|
|
Sep 01 10:28:09 PM UTC 24 |
Sep 01 10:28:12 PM UTC 24 |
51248774 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.120731618 |
|
|
Sep 01 10:18:38 PM UTC 24 |
Sep 01 10:28:16 PM UTC 24 |
12041895144 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_regwen.846455334 |
|
|
Sep 01 10:16:31 PM UTC 24 |
Sep 01 10:28:18 PM UTC 24 |
7305745500 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1815289767 |
|
|
Sep 01 10:28:18 PM UTC 24 |
Sep 01 10:28:22 PM UTC 24 |
155013914 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.3543501935 |
|
|
Sep 01 10:28:13 PM UTC 24 |
Sep 01 10:28:29 PM UTC 24 |
481096896 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1921905275 |
|
|
Sep 01 10:28:30 PM UTC 24 |
Sep 01 10:28:32 PM UTC 24 |
75576585 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_bijection.1468199772 |
|
|
Sep 01 10:27:34 PM UTC 24 |
Sep 01 10:28:37 PM UTC 24 |
2880434259 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3675073882 |
|
|
Sep 01 10:27:59 PM UTC 24 |
Sep 01 10:28:42 PM UTC 24 |
483045140 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3648831920 |
|
|
Sep 01 10:28:49 PM UTC 24 |
Sep 01 10:34:29 PM UTC 24 |
11389415473 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_smoke.766045809 |
|
|
Sep 01 10:28:33 PM UTC 24 |
Sep 01 10:28:48 PM UTC 24 |
320951468 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.254019528 |
|
|
Sep 01 10:25:38 PM UTC 24 |
Sep 01 10:28:48 PM UTC 24 |
5917471182 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3196164564 |
|
|
Sep 01 10:28:49 PM UTC 24 |
Sep 01 10:28:54 PM UTC 24 |
262744422 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_regwen.1940881926 |
|
|
Sep 01 10:18:08 PM UTC 24 |
Sep 01 10:29:10 PM UTC 24 |
4579746915 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2566807579 |
|
|
Sep 01 10:17:34 PM UTC 24 |
Sep 01 10:29:24 PM UTC 24 |
21443582919 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_executable.3680382698 |
|
|
Sep 01 10:24:17 PM UTC 24 |
Sep 01 10:29:26 PM UTC 24 |
10296943697 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.1808669874 |
|
|
Sep 01 10:29:24 PM UTC 24 |
Sep 01 10:29:36 PM UTC 24 |
2154580125 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.724305176 |
|
|
Sep 01 10:24:45 PM UTC 24 |
Sep 01 10:29:46 PM UTC 24 |
6883314579 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2353235534 |
|
|
Sep 01 10:28:05 PM UTC 24 |
Sep 01 10:30:05 PM UTC 24 |
1549236936 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3352797370 |
|
|
Sep 01 10:30:06 PM UTC 24 |
Sep 01 10:30:08 PM UTC 24 |
45878638 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_bijection.1120158272 |
|
|
Sep 01 10:28:43 PM UTC 24 |
Sep 01 10:30:16 PM UTC 24 |
4756974554 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.2068929060 |
|
|
Sep 01 10:30:09 PM UTC 24 |
Sep 01 10:30:24 PM UTC 24 |
1454260477 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1003910494 |
|
|
Sep 01 10:30:17 PM UTC 24 |
Sep 01 10:30:24 PM UTC 24 |
123828692 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3231266717 |
|
|
Sep 01 10:29:11 PM UTC 24 |
Sep 01 10:30:47 PM UTC 24 |
582195138 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_alert_test.3189036040 |
|
|
Sep 01 10:30:47 PM UTC 24 |
Sep 01 10:30:49 PM UTC 24 |
44065538 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2836311460 |
|
|
Sep 01 10:28:55 PM UTC 24 |
Sep 01 10:31:00 PM UTC 24 |
897290435 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1211690702 |
|
|
Sep 01 10:23:46 PM UTC 24 |
Sep 01 10:31:00 PM UTC 24 |
5014003423 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.21456925 |
|
|
Sep 01 10:24:47 PM UTC 24 |
Sep 01 10:31:06 PM UTC 24 |
3943873018 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_smoke.278599392 |
|
|
Sep 01 10:30:50 PM UTC 24 |
Sep 01 10:31:07 PM UTC 24 |
2391913249 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_bijection.3720691982 |
|
|
Sep 01 10:31:01 PM UTC 24 |
Sep 01 10:31:20 PM UTC 24 |
933203214 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_partial_access.425651507 |
|
|
Sep 01 10:31:09 PM UTC 24 |
Sep 01 10:31:24 PM UTC 24 |
741529887 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2011968521 |
|
|
Sep 01 10:25:53 PM UTC 24 |
Sep 01 10:31:39 PM UTC 24 |
3025546865 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.2934916737 |
|
|
Sep 01 10:23:27 PM UTC 24 |
Sep 01 10:31:39 PM UTC 24 |
698262000 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/6.sram_ctrl_stress_all.3854167831 |
|
|
Sep 01 09:56:24 PM UTC 24 |
Sep 01 10:31:41 PM UTC 24 |
51904157379 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1761359379 |
|
|
Sep 01 10:31:41 PM UTC 24 |
Sep 01 10:31:53 PM UTC 24 |
8270882845 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2700493509 |
|
|
Sep 01 10:30:25 PM UTC 24 |
Sep 01 10:32:11 PM UTC 24 |
368772110 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.1655584560 |
|
|
Sep 01 10:32:12 PM UTC 24 |
Sep 01 10:32:15 PM UTC 24 |
29492914 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2123302534 |
|
|
Sep 01 10:15:16 PM UTC 24 |
Sep 01 10:32:18 PM UTC 24 |
17927798147 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/10.sram_ctrl_executable.2861981711 |
|
|
Sep 01 10:04:04 PM UTC 24 |
Sep 01 10:32:21 PM UTC 24 |
106304837496 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3166590043 |
|
|
Sep 01 10:32:19 PM UTC 24 |
Sep 01 10:32:25 PM UTC 24 |
102998110 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1200619819 |
|
|
Sep 01 10:32:15 PM UTC 24 |
Sep 01 10:32:27 PM UTC 24 |
635471391 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_alert_test.697565638 |
|
|
Sep 01 10:32:28 PM UTC 24 |
Sep 01 10:32:30 PM UTC 24 |
38184580 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1171522410 |
|
|
Sep 01 10:05:02 PM UTC 24 |
Sep 01 10:32:33 PM UTC 24 |
30379393359 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_smoke.3784889147 |
|
|
Sep 01 10:32:31 PM UTC 24 |
Sep 01 10:32:35 PM UTC 24 |
40840032 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_executable.662961363 |
|
|
Sep 01 10:25:19 PM UTC 24 |
Sep 01 10:32:49 PM UTC 24 |
5469525724 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1817016853 |
|
|
Sep 01 10:09:24 PM UTC 24 |
Sep 01 10:33:02 PM UTC 24 |
15005196153 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_bijection.315055868 |
|
|
Sep 01 10:32:35 PM UTC 24 |
Sep 01 10:33:03 PM UTC 24 |
4901936032 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3351220818 |
|
|
Sep 01 10:32:23 PM UTC 24 |
Sep 01 10:33:04 PM UTC 24 |
918327938 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.3690516969 |
|
|
Sep 01 10:31:25 PM UTC 24 |
Sep 01 10:33:06 PM UTC 24 |
274960995 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3644524888 |
|
|
Sep 01 10:25:50 PM UTC 24 |
Sep 01 10:33:25 PM UTC 24 |
26384820431 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2468939731 |
|
|
Sep 01 10:33:03 PM UTC 24 |
Sep 01 10:33:26 PM UTC 24 |
287509661 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.1743606535 |
|
|
Sep 01 10:24:51 PM UTC 24 |
Sep 01 10:33:30 PM UTC 24 |
9721995095 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.319615866 |
|
|
Sep 01 10:31:39 PM UTC 24 |
Sep 01 10:33:35 PM UTC 24 |
616295169 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.1291631218 |
|
|
Sep 01 10:33:26 PM UTC 24 |
Sep 01 10:33:39 PM UTC 24 |
3382637396 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.1351503205 |
|
|
Sep 01 10:33:39 PM UTC 24 |
Sep 01 10:33:41 PM UTC 24 |
32890075 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1326534552 |
|
|
Sep 01 10:16:21 PM UTC 24 |
Sep 01 10:33:49 PM UTC 24 |
23757298265 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.986030069 |
|
|
Sep 01 10:33:42 PM UTC 24 |
Sep 01 10:33:54 PM UTC 24 |
693816535 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3416215152 |
|
|
Sep 01 10:33:50 PM UTC 24 |
Sep 01 10:33:57 PM UTC 24 |
67637977 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1100347914 |
|
|
Sep 01 10:33:57 PM UTC 24 |
Sep 01 10:33:59 PM UTC 24 |
36798885 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_smoke.61370040 |
|
|
Sep 01 10:34:00 PM UTC 24 |
Sep 01 10:34:11 PM UTC 24 |
889552524 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_executable.3374599048 |
|
|
Sep 01 10:28:05 PM UTC 24 |
Sep 01 10:35:05 PM UTC 24 |
5420594430 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2287817063 |
|
|
Sep 01 10:27:36 PM UTC 24 |
Sep 01 10:34:36 PM UTC 24 |
4350902954 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2253892360 |
|
|
Sep 01 10:19:25 PM UTC 24 |
Sep 01 10:34:36 PM UTC 24 |
5070292635 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.446312444 |
|
|
Sep 01 10:33:05 PM UTC 24 |
Sep 01 10:34:38 PM UTC 24 |
246256886 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.3884045252 |
|
|
Sep 01 10:33:07 PM UTC 24 |
Sep 01 10:34:40 PM UTC 24 |
1066438860 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.3001205138 |
|
|
Sep 01 10:20:08 PM UTC 24 |
Sep 01 10:34:44 PM UTC 24 |
11019225370 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.1044734307 |
|
|
Sep 01 10:15:25 PM UTC 24 |
Sep 01 10:34:52 PM UTC 24 |
2715971132 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_partial_access.842291020 |
|
|
Sep 01 10:34:38 PM UTC 24 |
Sep 01 10:34:53 PM UTC 24 |
1194040727 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.4049870899 |
|
|
Sep 01 10:34:53 PM UTC 24 |
Sep 01 10:35:02 PM UTC 24 |
1554454964 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_bijection.222912176 |
|
|
Sep 01 10:34:29 PM UTC 24 |
Sep 01 10:35:15 PM UTC 24 |
655925883 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3276500212 |
|
|
Sep 01 10:35:17 PM UTC 24 |
Sep 01 10:35:19 PM UTC 24 |
28748924 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.4217524295 |
|
|
Sep 01 10:34:41 PM UTC 24 |
Sep 01 10:35:27 PM UTC 24 |
149458995 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.4086129191 |
|
|
Sep 01 10:26:01 PM UTC 24 |
Sep 01 10:35:30 PM UTC 24 |
18783918690 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1403082358 |
|
|
Sep 01 10:35:21 PM UTC 24 |
Sep 01 10:35:30 PM UTC 24 |
395777997 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_alert_test.427872829 |
|
|
Sep 01 10:35:31 PM UTC 24 |
Sep 01 10:35:33 PM UTC 24 |
16908917 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3117908901 |
|
|
Sep 01 10:35:20 PM UTC 24 |
Sep 01 10:35:33 PM UTC 24 |
363254633 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.1216649363 |
|
|
Sep 01 10:34:45 PM UTC 24 |
Sep 01 10:35:42 PM UTC 24 |
577199455 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_regwen.2890893578 |
|
|
Sep 01 10:25:23 PM UTC 24 |
Sep 01 10:35:45 PM UTC 24 |
1809432721 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_regwen.1917830252 |
|
|
Sep 01 10:28:06 PM UTC 24 |
Sep 01 10:35:49 PM UTC 24 |
22073980002 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2381077612 |
|
|
Sep 01 10:25:46 PM UTC 24 |
Sep 01 10:36:09 PM UTC 24 |
4421448268 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3033641937 |
|
|
Sep 01 10:36:10 PM UTC 24 |
Sep 01 10:36:25 PM UTC 24 |
230786950 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/24.sram_ctrl_regwen.650088413 |
|
|
Sep 01 10:26:32 PM UTC 24 |
Sep 01 10:36:33 PM UTC 24 |
8056912339 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.277386591 |
|
|
Sep 01 10:36:33 PM UTC 24 |
Sep 01 10:36:44 PM UTC 24 |
1463841389 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2587522795 |
|
|
Sep 01 10:35:46 PM UTC 24 |
Sep 01 10:36:44 PM UTC 24 |
4882471219 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.2812178935 |
|
|
Sep 01 10:27:45 PM UTC 24 |
Sep 01 10:36:45 PM UTC 24 |
73603607333 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_regwen.1658962681 |
|
|
Sep 01 10:19:35 PM UTC 24 |
Sep 01 10:36:46 PM UTC 24 |
4628157855 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_bijection.3684339029 |
|
|
Sep 01 10:35:43 PM UTC 24 |
Sep 01 10:36:47 PM UTC 24 |
772729531 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.1476335051 |
|
|
Sep 01 10:36:46 PM UTC 24 |
Sep 01 10:36:48 PM UTC 24 |
213990844 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.3864928641 |
|
|
Sep 01 10:28:50 PM UTC 24 |
Sep 01 10:36:49 PM UTC 24 |
133226459539 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_regwen.1342322645 |
|
|
Sep 01 10:33:36 PM UTC 24 |
Sep 01 10:36:49 PM UTC 24 |
7088484548 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.425025106 |
|
|
Sep 01 10:36:26 PM UTC 24 |
Sep 01 10:36:52 PM UTC 24 |
1089014427 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2416299802 |
|
|
Sep 01 10:36:50 PM UTC 24 |
Sep 01 10:36:52 PM UTC 24 |
10931135 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1688265525 |
|
|
Sep 01 10:36:47 PM UTC 24 |
Sep 01 10:36:55 PM UTC 24 |
152327170 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.172631392 |
|
|
Sep 01 10:31:08 PM UTC 24 |
Sep 01 10:36:56 PM UTC 24 |
28999034754 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2956922934 |
|
|
Sep 01 10:36:48 PM UTC 24 |
Sep 01 10:37:00 PM UTC 24 |
226865186 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_executable.2204927231 |
|
|
Sep 01 10:16:31 PM UTC 24 |
Sep 01 10:37:00 PM UTC 24 |
23661663645 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1025274644 |
|
|
Sep 01 10:36:46 PM UTC 24 |
Sep 01 10:37:04 PM UTC 24 |
4366294439 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/15.sram_ctrl_executable.4007658808 |
|
|
Sep 01 10:12:00 PM UTC 24 |
Sep 01 10:37:10 PM UTC 24 |
11634236435 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2463377757 |
|
|
Sep 01 10:37:01 PM UTC 24 |
Sep 01 10:37:15 PM UTC 24 |
142786813 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_smoke.2542630170 |
|
|
Sep 01 10:36:51 PM UTC 24 |
Sep 01 10:37:19 PM UTC 24 |
76898957 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1677296247 |
|
|
Sep 01 10:36:57 PM UTC 24 |
Sep 01 10:37:19 PM UTC 24 |
492216651 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1140421683 |
|
|
Sep 01 10:24:40 PM UTC 24 |
Sep 01 10:37:21 PM UTC 24 |
9957986690 ps |