| T798 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1897502042 |
|
|
Sep 01 10:59:49 PM UTC 24 |
Sep 01 11:00:03 PM UTC 24 |
1830056676 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.792179418 |
|
|
Sep 01 10:59:59 PM UTC 24 |
Sep 01 11:00:05 PM UTC 24 |
310130282 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3461010385 |
|
|
Sep 01 10:59:11 PM UTC 24 |
Sep 01 11:00:13 PM UTC 24 |
112255453 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_alert_test.1867355697 |
|
|
Sep 01 11:00:15 PM UTC 24 |
Sep 01 11:00:17 PM UTC 24 |
17624856 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_smoke.3402060667 |
|
|
Sep 01 10:58:14 PM UTC 24 |
Sep 01 11:00:21 PM UTC 24 |
134495849 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_regwen.3163612137 |
|
|
Sep 01 10:55:53 PM UTC 24 |
Sep 01 11:00:32 PM UTC 24 |
51889725336 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_regwen.2167832218 |
|
|
Sep 01 10:40:23 PM UTC 24 |
Sep 01 11:00:33 PM UTC 24 |
64944629322 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3723074057 |
|
|
Sep 01 10:49:05 PM UTC 24 |
Sep 01 11:00:33 PM UTC 24 |
49194632492 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2590726275 |
|
|
Sep 01 10:50:04 PM UTC 24 |
Sep 01 11:00:58 PM UTC 24 |
15091044683 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.956947441 |
|
|
Sep 01 11:01:00 PM UTC 24 |
Sep 01 11:01:23 PM UTC 24 |
87557496 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1837809997 |
|
|
Sep 01 10:51:31 PM UTC 24 |
Sep 01 11:01:24 PM UTC 24 |
6519675731 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.4082281389 |
|
|
Sep 01 11:01:25 PM UTC 24 |
Sep 01 11:01:33 PM UTC 24 |
252471639 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2611514942 |
|
|
Sep 01 11:01:24 PM UTC 24 |
Sep 01 11:01:50 PM UTC 24 |
157189355 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3192404630 |
|
|
Sep 01 10:55:22 PM UTC 24 |
Sep 01 11:01:57 PM UTC 24 |
9908350342 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3368419706 |
|
|
Sep 01 11:00:33 PM UTC 24 |
Sep 01 11:01:58 PM UTC 24 |
847032391 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.444759047 |
|
|
Sep 01 11:01:59 PM UTC 24 |
Sep 01 11:02:01 PM UTC 24 |
95389231 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_bijection.4055216705 |
|
|
Sep 01 11:00:32 PM UTC 24 |
Sep 01 11:02:07 PM UTC 24 |
8051185922 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3262763831 |
|
|
Sep 01 11:02:02 PM UTC 24 |
Sep 01 11:02:11 PM UTC 24 |
281775347 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.4281160295 |
|
|
Sep 01 11:02:08 PM UTC 24 |
Sep 01 11:02:17 PM UTC 24 |
645533546 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3763164330 |
|
|
Sep 01 11:00:07 PM UTC 24 |
Sep 01 11:02:21 PM UTC 24 |
5788150878 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_alert_test.707900744 |
|
|
Sep 01 11:02:21 PM UTC 24 |
Sep 01 11:02:23 PM UTC 24 |
15603346 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3020424525 |
|
|
Sep 01 10:45:02 PM UTC 24 |
Sep 01 11:02:30 PM UTC 24 |
7685293214 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_smoke.3036889366 |
|
|
Sep 01 11:02:24 PM UTC 24 |
Sep 01 11:02:51 PM UTC 24 |
1360199935 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2685196273 |
|
|
Sep 01 10:56:52 PM UTC 24 |
Sep 01 11:02:55 PM UTC 24 |
2596974435 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.2755061238 |
|
|
Sep 01 10:54:42 PM UTC 24 |
Sep 01 11:02:58 PM UTC 24 |
1428954548 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_regwen.3313181732 |
|
|
Sep 01 10:59:42 PM UTC 24 |
Sep 01 11:03:00 PM UTC 24 |
1808627785 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_regwen.2594301841 |
|
|
Sep 01 10:57:54 PM UTC 24 |
Sep 01 11:03:04 PM UTC 24 |
31395869043 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.1300317433 |
|
|
Sep 01 11:00:33 PM UTC 24 |
Sep 01 11:03:10 PM UTC 24 |
4126902596 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3778798076 |
|
|
Sep 01 11:02:59 PM UTC 24 |
Sep 01 11:03:12 PM UTC 24 |
651101610 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_executable.773697616 |
|
|
Sep 01 11:01:51 PM UTC 24 |
Sep 01 11:03:18 PM UTC 24 |
1061107196 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1290819511 |
|
|
Sep 01 11:03:13 PM UTC 24 |
Sep 01 11:03:19 PM UTC 24 |
402184407 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.3708220733 |
|
|
Sep 01 10:59:04 PM UTC 24 |
Sep 01 11:03:27 PM UTC 24 |
2605121715 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.4184178325 |
|
|
Sep 01 11:03:11 PM UTC 24 |
Sep 01 11:03:30 PM UTC 24 |
85296421 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1644302273 |
|
|
Sep 01 11:03:31 PM UTC 24 |
Sep 01 11:03:33 PM UTC 24 |
120727826 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_regwen.1212174919 |
|
|
Sep 01 10:47:35 PM UTC 24 |
Sep 01 11:03:36 PM UTC 24 |
48852728099 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4241195354 |
|
|
Sep 01 11:03:05 PM UTC 24 |
Sep 01 11:03:42 PM UTC 24 |
98711002 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3237881200 |
|
|
Sep 01 11:03:36 PM UTC 24 |
Sep 01 11:03:44 PM UTC 24 |
473442249 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.444818156 |
|
|
Sep 01 11:02:12 PM UTC 24 |
Sep 01 11:03:45 PM UTC 24 |
6877661843 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3317183819 |
|
|
Sep 01 10:55:42 PM UTC 24 |
Sep 01 11:03:47 PM UTC 24 |
10015399376 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_alert_test.1494091815 |
|
|
Sep 01 11:03:47 PM UTC 24 |
Sep 01 11:03:49 PM UTC 24 |
42486681 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3719740757 |
|
|
Sep 01 10:56:56 PM UTC 24 |
Sep 01 11:03:51 PM UTC 24 |
92862176954 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/4.sram_ctrl_stress_all.412707591 |
|
|
Sep 01 09:51:18 PM UTC 24 |
Sep 01 11:03:52 PM UTC 24 |
41873906052 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.1813916747 |
|
|
Sep 01 11:03:34 PM UTC 24 |
Sep 01 11:03:53 PM UTC 24 |
5457905542 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_regwen.2745455629 |
|
|
Sep 01 10:35:06 PM UTC 24 |
Sep 01 11:03:53 PM UTC 24 |
67978765642 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access.385475731 |
|
|
Sep 01 11:03:55 PM UTC 24 |
Sep 01 11:04:02 PM UTC 24 |
555715062 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4098174580 |
|
|
Sep 01 11:03:45 PM UTC 24 |
Sep 01 11:04:06 PM UTC 24 |
769811786 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.4106307214 |
|
|
Sep 01 11:04:04 PM UTC 24 |
Sep 01 11:04:07 PM UTC 24 |
40993745 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_bijection.1578381155 |
|
|
Sep 01 11:03:53 PM UTC 24 |
Sep 01 11:04:14 PM UTC 24 |
1824697672 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3701154666 |
|
|
Sep 01 11:04:08 PM UTC 24 |
Sep 01 11:04:20 PM UTC 24 |
2290654010 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_smoke.337395233 |
|
|
Sep 01 11:03:49 PM UTC 24 |
Sep 01 11:04:21 PM UTC 24 |
1430566071 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2078038929 |
|
|
Sep 01 11:04:22 PM UTC 24 |
Sep 01 11:04:24 PM UTC 24 |
45249703 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_bijection.231437483 |
|
|
Sep 01 11:02:53 PM UTC 24 |
Sep 01 11:04:25 PM UTC 24 |
16466056495 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.19325543 |
|
|
Sep 01 10:54:59 PM UTC 24 |
Sep 01 11:04:30 PM UTC 24 |
1220793382 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3681893428 |
|
|
Sep 01 11:04:25 PM UTC 24 |
Sep 01 11:04:31 PM UTC 24 |
105390304 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.644885272 |
|
|
Sep 01 11:04:25 PM UTC 24 |
Sep 01 11:04:37 PM UTC 24 |
525491491 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3877916289 |
|
|
Sep 01 11:04:38 PM UTC 24 |
Sep 01 11:04:40 PM UTC 24 |
84612164 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.4057792998 |
|
|
Sep 01 11:01:34 PM UTC 24 |
Sep 01 11:04:42 PM UTC 24 |
1115449317 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_executable.3425565105 |
|
|
Sep 01 10:57:44 PM UTC 24 |
Sep 01 11:04:51 PM UTC 24 |
1496314981 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3543325438 |
|
|
Sep 01 11:04:07 PM UTC 24 |
Sep 01 11:04:51 PM UTC 24 |
114074614 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1383426065 |
|
|
Sep 01 10:34:12 PM UTC 24 |
Sep 01 11:04:53 PM UTC 24 |
188692919062 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_smoke.2452309563 |
|
|
Sep 01 11:04:41 PM UTC 24 |
Sep 01 11:04:58 PM UTC 24 |
742903009 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.863827114 |
|
|
Sep 01 10:54:04 PM UTC 24 |
Sep 01 11:05:00 PM UTC 24 |
17504002448 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_bijection.2539587829 |
|
|
Sep 01 11:04:52 PM UTC 24 |
Sep 01 11:05:30 PM UTC 24 |
405842212 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3693055898 |
|
|
Sep 01 11:05:01 PM UTC 24 |
Sep 01 11:05:33 PM UTC 24 |
96184034 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.425678090 |
|
|
Sep 01 11:04:08 PM UTC 24 |
Sep 01 11:05:34 PM UTC 24 |
303775179 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1146163853 |
|
|
Sep 01 10:58:55 PM UTC 24 |
Sep 01 11:05:35 PM UTC 24 |
3274756649 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3871034133 |
|
|
Sep 01 11:05:31 PM UTC 24 |
Sep 01 11:05:36 PM UTC 24 |
453073144 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_executable.1859411946 |
|
|
Sep 01 11:04:15 PM UTC 24 |
Sep 01 11:05:37 PM UTC 24 |
1526234806 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.971129371 |
|
|
Sep 01 11:05:37 PM UTC 24 |
Sep 01 11:05:40 PM UTC 24 |
28431133 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3063076891 |
|
|
Sep 01 11:04:54 PM UTC 24 |
Sep 01 11:05:42 PM UTC 24 |
3137349313 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3932270622 |
|
|
Sep 01 10:58:18 PM UTC 24 |
Sep 01 11:05:42 PM UTC 24 |
5494844729 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.890165452 |
|
|
Sep 01 11:05:40 PM UTC 24 |
Sep 01 11:05:47 PM UTC 24 |
149618255 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2123847171 |
|
|
Sep 01 11:05:43 PM UTC 24 |
Sep 01 11:05:48 PM UTC 24 |
47512535 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_alert_test.1308002160 |
|
|
Sep 01 11:05:49 PM UTC 24 |
Sep 01 11:05:51 PM UTC 24 |
26095633 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.92003668 |
|
|
Sep 01 11:05:34 PM UTC 24 |
Sep 01 11:05:54 PM UTC 24 |
7586094369 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.589510348 |
|
|
Sep 01 10:56:34 PM UTC 24 |
Sep 01 11:06:01 PM UTC 24 |
27618386264 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1233050718 |
|
|
Sep 01 11:00:59 PM UTC 24 |
Sep 01 11:06:29 PM UTC 24 |
12758620521 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_executable.3719668094 |
|
|
Sep 01 10:54:44 PM UTC 24 |
Sep 01 11:06:59 PM UTC 24 |
10129344368 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.800823176 |
|
|
Sep 01 10:47:18 PM UTC 24 |
Sep 01 11:07:14 PM UTC 24 |
7559813808 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.3648406526 |
|
|
Sep 01 10:48:12 PM UTC 24 |
Sep 01 11:07:25 PM UTC 24 |
165801642404 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3845328029 |
|
|
Sep 01 11:03:19 PM UTC 24 |
Sep 01 11:07:28 PM UTC 24 |
3194610212 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_executable.3744340627 |
|
|
Sep 01 10:46:00 PM UTC 24 |
Sep 01 11:07:32 PM UTC 24 |
24017058479 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_regwen.2520229619 |
|
|
Sep 01 10:44:22 PM UTC 24 |
Sep 01 11:07:39 PM UTC 24 |
9487471305 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2534550397 |
|
|
Sep 01 11:02:56 PM UTC 24 |
Sep 01 11:08:07 PM UTC 24 |
11419731589 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1742329829 |
|
|
Sep 01 10:13:47 PM UTC 24 |
Sep 01 11:08:13 PM UTC 24 |
38407227751 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.2144545800 |
|
|
Sep 01 11:04:59 PM UTC 24 |
Sep 01 11:09:12 PM UTC 24 |
15250288464 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1173415104 |
|
|
Sep 01 10:46:28 PM UTC 24 |
Sep 01 11:09:14 PM UTC 24 |
63152456309 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/28.sram_ctrl_stress_all.4890105 |
|
|
Sep 01 10:33:55 PM UTC 24 |
Sep 01 11:09:31 PM UTC 24 |
41079254255 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1969450849 |
|
|
Sep 01 11:03:01 PM UTC 24 |
Sep 01 11:09:55 PM UTC 24 |
4541715352 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_executable.2389065801 |
|
|
Sep 01 10:49:26 PM UTC 24 |
Sep 01 11:10:00 PM UTC 24 |
54992589208 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3004524685 |
|
|
Sep 01 11:04:31 PM UTC 24 |
Sep 01 11:10:24 PM UTC 24 |
3507875657 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2458788045 |
|
|
Sep 01 11:04:52 PM UTC 24 |
Sep 01 11:10:30 PM UTC 24 |
11654919446 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_regwen.3646923501 |
|
|
Sep 01 10:49:34 PM UTC 24 |
Sep 01 11:10:44 PM UTC 24 |
23330186763 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.2898366994 |
|
|
Sep 01 11:02:30 PM UTC 24 |
Sep 01 11:10:45 PM UTC 24 |
2284101530 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.4017247507 |
|
|
Sep 01 11:00:22 PM UTC 24 |
Sep 01 11:10:45 PM UTC 24 |
85497765272 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1922414824 |
|
|
Sep 01 10:53:53 PM UTC 24 |
Sep 01 11:11:00 PM UTC 24 |
13749846506 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.3465264555 |
|
|
Sep 01 10:57:35 PM UTC 24 |
Sep 01 11:11:05 PM UTC 24 |
8541248412 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3550452847 |
|
|
Sep 01 10:51:00 PM UTC 24 |
Sep 01 11:11:30 PM UTC 24 |
3693572449 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2209809831 |
|
|
Sep 01 10:53:44 PM UTC 24 |
Sep 01 11:11:32 PM UTC 24 |
12579222142 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3167861290 |
|
|
Sep 01 11:03:55 PM UTC 24 |
Sep 01 11:12:08 PM UTC 24 |
16676092629 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2432519544 |
|
|
Sep 01 11:03:53 PM UTC 24 |
Sep 01 11:12:20 PM UTC 24 |
4151796689 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.829258830 |
|
|
Sep 01 11:05:44 PM UTC 24 |
Sep 01 11:12:23 PM UTC 24 |
1594688386 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3749783969 |
|
|
Sep 01 11:03:51 PM UTC 24 |
Sep 01 11:13:08 PM UTC 24 |
2959642276 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.425647876 |
|
|
Sep 01 10:58:08 PM UTC 24 |
Sep 01 11:13:45 PM UTC 24 |
1662262232 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.295439953 |
|
|
Sep 01 10:59:31 PM UTC 24 |
Sep 01 11:14:05 PM UTC 24 |
61354915594 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.1952012288 |
|
|
Sep 01 10:53:00 PM UTC 24 |
Sep 01 11:14:05 PM UTC 24 |
8759285250 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3050860185 |
|
|
Sep 01 11:04:43 PM UTC 24 |
Sep 01 11:14:33 PM UTC 24 |
8765743689 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/33.sram_ctrl_executable.122031264 |
|
|
Sep 01 10:40:22 PM UTC 24 |
Sep 01 11:14:35 PM UTC 24 |
61281889791 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/38.sram_ctrl_stress_all.2809478894 |
|
|
Sep 01 10:48:05 PM UTC 24 |
Sep 01 11:16:19 PM UTC 24 |
84421375680 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3912963776 |
|
|
Sep 01 11:05:34 PM UTC 24 |
Sep 01 11:16:25 PM UTC 24 |
20835257287 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_regwen.4112588140 |
|
|
Sep 01 11:01:59 PM UTC 24 |
Sep 01 11:16:27 PM UTC 24 |
1575893741 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_regwen.819979775 |
|
|
Sep 01 11:05:36 PM UTC 24 |
Sep 01 11:16:30 PM UTC 24 |
6864536484 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1448336921 |
|
|
Sep 01 10:51:53 PM UTC 24 |
Sep 01 11:17:20 PM UTC 24 |
12222687209 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_regwen.3763220441 |
|
|
Sep 01 11:04:21 PM UTC 24 |
Sep 01 11:17:27 PM UTC 24 |
2183339853 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.4230147084 |
|
|
Sep 01 10:55:11 PM UTC 24 |
Sep 01 11:17:29 PM UTC 24 |
88163347151 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1820116380 |
|
|
Sep 01 10:44:46 PM UTC 24 |
Sep 01 11:18:03 PM UTC 24 |
44924476123 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/27.sram_ctrl_stress_all.4206763856 |
|
|
Sep 01 10:32:26 PM UTC 24 |
Sep 01 11:18:11 PM UTC 24 |
9155947413 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/41.sram_ctrl_executable.264668009 |
|
|
Sep 01 10:53:15 PM UTC 24 |
Sep 01 11:19:07 PM UTC 24 |
16712156385 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_executable.3901014869 |
|
|
Sep 01 10:59:40 PM UTC 24 |
Sep 01 11:19:47 PM UTC 24 |
17933121079 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1551090812 |
|
|
Sep 01 10:28:22 PM UTC 24 |
Sep 01 11:19:56 PM UTC 24 |
142399986187 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_regwen.757844745 |
|
|
Sep 01 11:03:28 PM UTC 24 |
Sep 01 11:20:26 PM UTC 24 |
3929752919 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1072453971 |
|
|
Sep 01 10:02:28 PM UTC 24 |
Sep 01 11:21:48 PM UTC 24 |
587980958827 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1845748433 |
|
|
Sep 01 10:36:49 PM UTC 24 |
Sep 01 11:22:05 PM UTC 24 |
133066424966 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/39.sram_ctrl_stress_all.3915278023 |
|
|
Sep 01 10:49:59 PM UTC 24 |
Sep 01 11:25:16 PM UTC 24 |
7715232461 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_executable.3446075052 |
|
|
Sep 01 11:03:21 PM UTC 24 |
Sep 01 11:26:10 PM UTC 24 |
3939814090 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3497970608 |
|
|
Sep 01 10:30:25 PM UTC 24 |
Sep 01 11:27:34 PM UTC 24 |
60864775829 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/22.sram_ctrl_stress_all.764465069 |
|
|
Sep 01 10:24:41 PM UTC 24 |
Sep 01 11:28:04 PM UTC 24 |
368172160926 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2888820458 |
|
|
Sep 01 11:00:07 PM UTC 24 |
Sep 01 11:28:52 PM UTC 24 |
41732733692 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_executable.931465184 |
|
|
Sep 01 11:05:35 PM UTC 24 |
Sep 01 11:29:51 PM UTC 24 |
4808588744 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/18.sram_ctrl_stress_all.525459082 |
|
|
Sep 01 10:16:45 PM UTC 24 |
Sep 01 11:31:42 PM UTC 24 |
52678417284 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/35.sram_ctrl_stress_all.178582826 |
|
|
Sep 01 10:43:07 PM UTC 24 |
Sep 01 11:33:04 PM UTC 24 |
11086220084 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/29.sram_ctrl_stress_all.559980429 |
|
|
Sep 01 10:35:31 PM UTC 24 |
Sep 01 11:34:18 PM UTC 24 |
87024476653 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/48.sram_ctrl_stress_all.569439490 |
|
|
Sep 01 11:04:32 PM UTC 24 |
Sep 01 11:37:10 PM UTC 24 |
30729888558 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1400327517 |
|
|
Sep 01 10:23:01 PM UTC 24 |
Sep 01 11:40:41 PM UTC 24 |
53813083208 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1710054490 |
|
|
Sep 01 10:58:09 PM UTC 24 |
Sep 01 11:50:13 PM UTC 24 |
45267524395 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/37.sram_ctrl_stress_all.368690264 |
|
|
Sep 01 10:46:15 PM UTC 24 |
Sep 01 11:54:55 PM UTC 24 |
133944369216 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3835307964 |
|
|
Sep 01 11:03:45 PM UTC 24 |
Sep 01 11:56:39 PM UTC 24 |
274858778232 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/42.sram_ctrl_stress_all.763618927 |
|
|
Sep 01 10:55:01 PM UTC 24 |
Sep 02 12:02:19 AM UTC 24 |
154462155289 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/34.sram_ctrl_stress_all.3756849954 |
|
|
Sep 01 10:41:51 PM UTC 24 |
Sep 02 12:06:22 AM UTC 24 |
281319616189 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/49.sram_ctrl_stress_all.522756743 |
|
|
Sep 01 11:05:48 PM UTC 24 |
Sep 02 12:08:55 AM UTC 24 |
9218195147 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3286062602 |
|
|
Sep 01 10:56:32 PM UTC 24 |
Sep 02 12:15:07 AM UTC 24 |
64383923310 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1975474643 |
|
|
Sep 01 11:02:18 PM UTC 24 |
Sep 02 12:18:38 AM UTC 24 |
172028552919 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/default/20.sram_ctrl_stress_all.4142412250 |
|
|
Sep 01 10:20:02 PM UTC 24 |
Sep 02 12:37:03 AM UTC 24 |
92278059950 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1708920909 |
|
|
Sep 01 11:05:52 PM UTC 24 |
Sep 01 11:05:57 PM UTC 24 |
1914573468 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1645257386 |
|
|
Sep 01 11:05:55 PM UTC 24 |
Sep 01 11:05:59 PM UTC 24 |
59893933 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2690082768 |
|
|
Sep 01 11:05:58 PM UTC 24 |
Sep 01 11:06:03 PM UTC 24 |
147869451 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.310627567 |
|
|
Sep 01 11:06:00 PM UTC 24 |
Sep 01 11:06:03 PM UTC 24 |
27223514 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1297174811 |
|
|
Sep 01 11:06:02 PM UTC 24 |
Sep 01 11:06:04 PM UTC 24 |
19886030 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2332939532 |
|
|
Sep 01 11:06:04 PM UTC 24 |
Sep 01 11:06:06 PM UTC 24 |
17395395 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3287391630 |
|
|
Sep 01 11:06:05 PM UTC 24 |
Sep 01 11:06:07 PM UTC 24 |
145618671 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2007805605 |
|
|
Sep 01 11:06:04 PM UTC 24 |
Sep 01 11:06:08 PM UTC 24 |
625270988 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.674401016 |
|
|
Sep 01 11:06:07 PM UTC 24 |
Sep 01 11:06:10 PM UTC 24 |
31572163 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1988677232 |
|
|
Sep 01 11:06:08 PM UTC 24 |
Sep 01 11:06:14 PM UTC 24 |
443418926 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2719391563 |
|
|
Sep 01 11:06:11 PM UTC 24 |
Sep 01 11:06:14 PM UTC 24 |
77882863 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1444873784 |
|
|
Sep 01 11:06:15 PM UTC 24 |
Sep 01 11:06:16 PM UTC 24 |
13273746 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.966291220 |
|
|
Sep 01 11:06:09 PM UTC 24 |
Sep 01 11:06:17 PM UTC 24 |
541280959 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3376430225 |
|
|
Sep 01 11:06:16 PM UTC 24 |
Sep 01 11:06:18 PM UTC 24 |
22276799 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.736255890 |
|
|
Sep 01 11:06:18 PM UTC 24 |
Sep 01 11:06:20 PM UTC 24 |
35506302 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1896364497 |
|
|
Sep 01 11:06:18 PM UTC 24 |
Sep 01 11:06:20 PM UTC 24 |
29804993 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3858817368 |
|
|
Sep 01 11:06:17 PM UTC 24 |
Sep 01 11:06:21 PM UTC 24 |
485221707 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2557288339 |
|
|
Sep 01 11:06:22 PM UTC 24 |
Sep 01 11:06:24 PM UTC 24 |
40608353 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4272186937 |
|
|
Sep 01 11:06:22 PM UTC 24 |
Sep 01 11:06:26 PM UTC 24 |
917260328 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2140619306 |
|
|
Sep 01 11:06:23 PM UTC 24 |
Sep 01 11:06:27 PM UTC 24 |
107683965 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2078067784 |
|
|
Sep 01 11:06:25 PM UTC 24 |
Sep 01 11:06:28 PM UTC 24 |
193963922 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2052725053 |
|
|
Sep 01 11:06:26 PM UTC 24 |
Sep 01 11:06:29 PM UTC 24 |
56931501 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1951929982 |
|
|
Sep 01 11:06:28 PM UTC 24 |
Sep 01 11:06:30 PM UTC 24 |
32744611 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2854158846 |
|
|
Sep 01 11:06:29 PM UTC 24 |
Sep 01 11:06:31 PM UTC 24 |
43574050 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2777388868 |
|
|
Sep 01 11:06:29 PM UTC 24 |
Sep 01 11:06:32 PM UTC 24 |
241794654 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3931472775 |
|
|
Sep 01 11:06:30 PM UTC 24 |
Sep 01 11:06:33 PM UTC 24 |
31425769 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1562415759 |
|
|
Sep 01 11:06:30 PM UTC 24 |
Sep 01 11:06:33 PM UTC 24 |
129329993 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3795048796 |
|
|
Sep 01 11:06:34 PM UTC 24 |
Sep 01 11:06:36 PM UTC 24 |
17896523 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2606871305 |
|
|
Sep 01 11:06:33 PM UTC 24 |
Sep 01 11:06:39 PM UTC 24 |
478275371 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3797197411 |
|
|
Sep 01 11:06:34 PM UTC 24 |
Sep 01 11:06:39 PM UTC 24 |
249508021 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1748890443 |
|
|
Sep 01 11:06:38 PM UTC 24 |
Sep 01 11:06:40 PM UTC 24 |
33449278 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.771659731 |
|
|
Sep 01 11:06:34 PM UTC 24 |
Sep 01 11:06:41 PM UTC 24 |
141020718 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3063022786 |
|
|
Sep 01 11:06:40 PM UTC 24 |
Sep 01 11:06:42 PM UTC 24 |
57880479 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3311195271 |
|
|
Sep 01 11:06:40 PM UTC 24 |
Sep 01 11:06:43 PM UTC 24 |
30927507 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1447646306 |
|
|
Sep 01 11:06:41 PM UTC 24 |
Sep 01 11:06:43 PM UTC 24 |
13964697 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1767599276 |
|
|
Sep 01 11:06:44 PM UTC 24 |
Sep 01 11:06:47 PM UTC 24 |
1670018524 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1492598865 |
|
|
Sep 01 11:06:46 PM UTC 24 |
Sep 01 11:06:48 PM UTC 24 |
18658008 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3990918364 |
|
|
Sep 01 11:06:42 PM UTC 24 |
Sep 01 11:06:49 PM UTC 24 |
1081964121 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2501952970 |
|
|
Sep 01 11:06:44 PM UTC 24 |
Sep 01 11:06:49 PM UTC 24 |
144072635 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.730262199 |
|
|
Sep 01 11:06:49 PM UTC 24 |
Sep 01 11:06:51 PM UTC 24 |
30818708 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1910092206 |
|
|
Sep 01 11:06:50 PM UTC 24 |
Sep 01 11:06:52 PM UTC 24 |
27707303 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.906136080 |
|
|
Sep 01 11:06:50 PM UTC 24 |
Sep 01 11:06:52 PM UTC 24 |
202886681 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.119507266 |
|
|
Sep 01 11:06:49 PM UTC 24 |
Sep 01 11:06:53 PM UTC 24 |
375108218 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2732655257 |
|
|
Sep 01 11:06:52 PM UTC 24 |
Sep 01 11:06:55 PM UTC 24 |
56300663 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2005153337 |
|
|
Sep 01 11:06:54 PM UTC 24 |
Sep 01 11:06:58 PM UTC 24 |
713004958 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1384827989 |
|
|
Sep 01 11:06:57 PM UTC 24 |
Sep 01 11:06:59 PM UTC 24 |
36386325 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1314226925 |
|
|
Sep 01 11:06:53 PM UTC 24 |
Sep 01 11:06:59 PM UTC 24 |
1577839542 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.464469785 |
|
|
Sep 01 11:06:59 PM UTC 24 |
Sep 01 11:07:02 PM UTC 24 |
46758258 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1478347379 |
|
|
Sep 01 11:06:59 PM UTC 24 |
Sep 01 11:07:02 PM UTC 24 |
57245501 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.862660310 |
|
|
Sep 01 11:06:53 PM UTC 24 |
Sep 01 11:07:02 PM UTC 24 |
144062488 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.90480050 |
|
|
Sep 01 11:07:02 PM UTC 24 |
Sep 01 11:07:04 PM UTC 24 |
59438487 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4282019513 |
|
|
Sep 01 11:07:03 PM UTC 24 |
Sep 01 11:07:06 PM UTC 24 |
26600714 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3402575676 |
|
|
Sep 01 11:07:01 PM UTC 24 |
Sep 01 11:07:06 PM UTC 24 |
1867730714 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3756050647 |
|
|
Sep 01 11:07:02 PM UTC 24 |
Sep 01 11:07:06 PM UTC 24 |
142108566 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1531633979 |
|
|
Sep 01 11:07:01 PM UTC 24 |
Sep 01 11:07:07 PM UTC 24 |
585791647 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1884104346 |
|
|
Sep 01 11:07:05 PM UTC 24 |
Sep 01 11:07:08 PM UTC 24 |
127628899 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4116324622 |
|
|
Sep 01 11:07:08 PM UTC 24 |
Sep 01 11:07:11 PM UTC 24 |
12499663 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.948316358 |
|
|
Sep 01 11:07:09 PM UTC 24 |
Sep 01 11:07:11 PM UTC 24 |
48666229 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.113212570 |
|
|
Sep 01 11:07:07 PM UTC 24 |
Sep 01 11:07:11 PM UTC 24 |
754698550 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1038767082 |
|
|
Sep 01 11:07:07 PM UTC 24 |
Sep 01 11:07:12 PM UTC 24 |
708972814 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2297082343 |
|
|
Sep 01 11:07:15 PM UTC 24 |
Sep 01 11:07:17 PM UTC 24 |
64428185 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1649373443 |
|
|
Sep 01 11:07:07 PM UTC 24 |
Sep 01 11:07:14 PM UTC 24 |
116405622 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3004286067 |
|
|
Sep 01 11:07:12 PM UTC 24 |
Sep 01 11:07:15 PM UTC 24 |
98630854 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1761833883 |
|
|
Sep 01 11:07:12 PM UTC 24 |
Sep 01 11:07:16 PM UTC 24 |
428432751 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3783957827 |
|
|
Sep 01 11:07:15 PM UTC 24 |
Sep 01 11:07:17 PM UTC 24 |
14648654 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.902205349 |
|
|
Sep 01 11:07:14 PM UTC 24 |
Sep 01 11:07:18 PM UTC 24 |
776141092 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3013991178 |
|
|
Sep 01 11:07:16 PM UTC 24 |
Sep 01 11:07:19 PM UTC 24 |
74865426 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1132226335 |
|
|
Sep 01 11:07:18 PM UTC 24 |
Sep 01 11:07:21 PM UTC 24 |
141645509 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2928027387 |
|
|
Sep 01 11:07:19 PM UTC 24 |
Sep 01 11:07:21 PM UTC 24 |
15420542 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1095014714 |
|
|
Sep 01 11:07:12 PM UTC 24 |
Sep 01 11:07:21 PM UTC 24 |
161705879 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1036515845 |
|
|
Sep 01 11:07:18 PM UTC 24 |
Sep 01 11:07:22 PM UTC 24 |
217313883 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3489193768 |
|
|
Sep 01 11:07:20 PM UTC 24 |
Sep 01 11:07:23 PM UTC 24 |
156876888 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3507048662 |
|
|
Sep 01 11:07:22 PM UTC 24 |
Sep 01 11:07:24 PM UTC 24 |
86526303 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3675312247 |
|
|
Sep 01 11:07:18 PM UTC 24 |
Sep 01 11:07:25 PM UTC 24 |
146199328 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2634597805 |
|
|
Sep 01 11:07:23 PM UTC 24 |
Sep 01 11:07:25 PM UTC 24 |
17489307 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2286355607 |
|
|
Sep 01 11:07:22 PM UTC 24 |
Sep 01 11:07:26 PM UTC 24 |
875659617 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.478463563 |
|
|
Sep 01 11:07:23 PM UTC 24 |
Sep 01 11:07:27 PM UTC 24 |
805109263 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2418589126 |
|
|
Sep 01 11:07:26 PM UTC 24 |
Sep 01 11:07:28 PM UTC 24 |
77078637 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3774065118 |
|
|
Sep 01 11:07:26 PM UTC 24 |
Sep 01 11:07:29 PM UTC 24 |
94309172 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.511883239 |
|
|
Sep 01 11:07:23 PM UTC 24 |
Sep 01 11:07:30 PM UTC 24 |
220050215 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1470958329 |
|
|
Sep 01 11:07:29 PM UTC 24 |
Sep 01 11:07:31 PM UTC 24 |
15468519 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1648029540 |
|
|
Sep 01 11:07:29 PM UTC 24 |
Sep 01 11:07:31 PM UTC 24 |
40727516 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1112907335 |
|
|
Sep 01 11:07:26 PM UTC 24 |
Sep 01 11:07:32 PM UTC 24 |
394108818 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.446179853 |
|
|
Sep 01 11:07:27 PM UTC 24 |
Sep 01 11:07:33 PM UTC 24 |
285404669 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1216476186 |
|
|
Sep 01 11:07:30 PM UTC 24 |
Sep 01 11:07:34 PM UTC 24 |
54655468 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4117547332 |
|
|
Sep 01 11:07:32 PM UTC 24 |
Sep 01 11:07:34 PM UTC 24 |
18323433 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4253213896 |
|
|
Sep 01 11:07:27 PM UTC 24 |
Sep 01 11:07:35 PM UTC 24 |
128524151 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2589366637 |
|
|
Sep 01 11:07:33 PM UTC 24 |
Sep 01 11:07:36 PM UTC 24 |
24703526 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3261738386 |
|
|
Sep 01 11:07:32 PM UTC 24 |
Sep 01 11:07:36 PM UTC 24 |
686062291 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2311272988 |
|
|
Sep 01 11:07:34 PM UTC 24 |
Sep 01 11:07:37 PM UTC 24 |
370057291 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3378315312 |
|
|
Sep 01 11:07:34 PM UTC 24 |
Sep 01 11:07:38 PM UTC 24 |
430467196 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.217502843 |
|
|
Sep 01 11:07:30 PM UTC 24 |
Sep 01 11:07:38 PM UTC 24 |
1285490423 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2686027596 |
|
|
Sep 01 11:07:32 PM UTC 24 |
Sep 01 11:07:38 PM UTC 24 |
47102962 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4197373517 |
|
|
Sep 01 11:07:36 PM UTC 24 |
Sep 01 11:07:39 PM UTC 24 |
362211121 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4080721694 |
|
|
Sep 01 11:07:38 PM UTC 24 |
Sep 01 11:07:40 PM UTC 24 |
13262318 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3724458280 |
|
|
Sep 01 11:07:38 PM UTC 24 |
Sep 01 11:07:40 PM UTC 24 |
65265354 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1641115353 |
|
|
Sep 01 11:07:38 PM UTC 24 |
Sep 01 11:07:41 PM UTC 24 |
124944817 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2820058501 |
|
|
Sep 01 11:07:40 PM UTC 24 |
Sep 01 11:07:42 PM UTC 24 |
21274536 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2519896972 |
|
|
Sep 01 11:07:36 PM UTC 24 |
Sep 01 11:07:42 PM UTC 24 |
215557510 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3309487572 |
|
|
Sep 01 11:07:40 PM UTC 24 |
Sep 01 11:07:43 PM UTC 24 |
36520398 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4182984595 |
|
|
Sep 01 11:07:38 PM UTC 24 |
Sep 01 11:07:44 PM UTC 24 |
79769186 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3164106751 |
|
|
Sep 01 11:07:42 PM UTC 24 |
Sep 01 11:07:44 PM UTC 24 |
95836660 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.297439431 |
|
|
Sep 01 11:07:40 PM UTC 24 |
Sep 01 11:07:44 PM UTC 24 |
360084928 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1703885267 |
|
|
Sep 01 11:07:44 PM UTC 24 |
Sep 01 11:07:46 PM UTC 24 |
23518188 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3558674722 |
|
|
Sep 01 11:07:38 PM UTC 24 |
Sep 01 11:07:46 PM UTC 24 |
2778011902 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2350145374 |
|
|
Sep 01 11:07:44 PM UTC 24 |
Sep 01 11:07:46 PM UTC 24 |
18376375 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_ret-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.179269027 |
|
|
Sep 01 11:07:42 PM UTC 24 |
Sep 01 11:07:46 PM UTC 24 |
653265949 ps |